CA1147015A - Inductive load actuating circuit using higher current levels for pull-in and two alternating lower current levels for hold-in - Google Patents

Abstract

ABSTRACT
Comparator means respond to the current levels through an inductive load to generate HIGH and LOW level outputs causing first switch means to connect and dis-connect power to the load. When the load current initially exceeds a peak load actuation level flip-flop means responsive to the corresponding change In comparator output levels change the current through an auxilliary sense resistor coupled to the sense input of the com-parator means. In one embodiment a one-shot multi-vibarator prevents a change in the current to the auxil-liary sense resistor for a fixed period after the com-mencement of a load actuation signal. The subseguent HIGH end LOW comparator output levels are fed back to the comparator reference input to switch the reference voltage thereat so as to represent first and second levels of the current sufficient to maintain actuation of the load.

Description

This invention relates generally to circuits for driving inductive loads such as solenoids and, more particularly, to circuits wherein power consumption is minimized by operating a power stage in a switching mode.
This application is related to the subject matter of applicant's United States Patent to Reddy 3,725,678 issued April 3, 1973. This application is also related to the subject matter of applicant's co-pending application Serial No. 321,335, filed February 13, ]979.
Description of the Prior Art.
The above-identified Reddy patent discloses injector drive circuits wherein the current is controlled to first regulate the voltage across the injector coil until after the current has built up enough to open or pull in the injector armature and to thereafter regulate the current at a holding level in excess of a closing or drop out current but considerably less than the pull in--current. These drive circuits render the injector opening `~ and closing times, and therefore the fuel supplied therebetween, substantially independent of variations in the power supply and variations in the unit-to-unit ?~ s mb/~lD

voltage drops across the power stage.
However, in regulating first the voltage and then the hold current, the power stage experiences a voltage drop thereacross corresponding to the difference between the voltage of the power supply and the voltage - at the injectors. The power stage therefore consumes and must dissipate power at a level increasing with the number of injeetors being driven at one time and the current required to operate each injector. The heat dissipation and therefore the heat sink and tem-perature ranges associated with these power stages also increase accordingly to the point that the heat sink is often larger than all of the other elements of the electronic control unit leading up to the injectors.
Moreover, the temperature cycles produced by the dis-sipation decrease the life while increasing the mounting costs of the semi-conductor elements comprising the power stage. It is therefore desirable to reduce the power dissipated by the power stage.
The United States patent to Paine 3,549,955 discloses a circuit for minimizing power consumption by operating the power stage fully ON so that there is a very small voltage drop thereacross until a pull-in current level is detected and thereafter operating the power stage in a switching mode where it is either fully ON or OFF to maintain a hold-in current level in excess of the drop out level. More specifically, the current is alternately increased to an upper hold-in level in excess of the drop out level and is then allowed to decay slowly through the solenoid coil to ~lower hold-in level still in excess of the drop-out level. Thereafter, the power stage is switched fully GN again until the upper hold-in level is again de-tected.
The United States patent to Ule 3,896,3~
discloses an inductive load driver circuit of the type .~ s ~isclosed in the Paine patent but wherein power con-sumption ls further Minimized by returning -the energy ln the collapsing solenoid field -to energy storage means in the form of the power supply or a second solenoid.
Citing the Paine patent, the United States patent to Stewart 4,041,546 discloses a solenoid drive circuit including capacitor timing means for discon-necting the driving voltage for fixed intervals between eaeh application of hold current.
To minimize power consumption, switching-mode decay rates effected by circuits of the type disclosed in Paine, Ule, and Stewart patents must be sufficiently slow to maintain the current above the drop-out level while the power stage is OFF. Using such circuits to 'control the fuel injector would -ender the turn off time of the injector, and therefore the fuel delivered there-by, subject to when in the decay cycle it is desired to close the injector. For example, if the end of the injeetor actuation command coincided with the instant ao that the eurrent exceeded the upper hold-in level, then the elosing time would be the time rec~uired to deeay to the lowex hold-in level plus the time required to deeay, therefrom to the drop-out, level. If the end of the aetuation eommand eoineidec~ with the instant that the eurrent fell below the low~3r hold in level/ then the closing time would be just the time required for the current to deeay to the drop out level.
Use of circuits of the type disclosed in the Paine, Ule, and Stewart patents to eontrol a fueI in-jeetion valve would therefore incur not only the varia-tions in opening times eliminated by the eircuits of the above-identified Reddy cases but would also intro-duee variations in closing times that would offset a substan-tial portion o~ all the variations eliminated by the Reddy eircuits.

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' ~4 ~ 5 It is therefore desirable to provide an im-proved circuit wherein the solenoid current is held above a drop-out level by switching the power stage between fully ON and OFF conditions to reduce power consumption and then rendering the closing time inde-pendent of decay rates associated with such hold level switching.
OBJECTS
It is an object of the present invention to provide a new and useful method and dr apparatus for controlling the current drive to the solenoid coil of an electromagnetically-actuated device.
It is another object of the present invention to provide a method and apparatus of the foregoing type that minimizes the power consumed after the electro-magnetic device has been actuated from one position to another and thflt minimizes the time required to re-turn the electromagnetic device from the second position to the first.
It is another primary object of the present invention to provide a method and apparatus for activat-ing and deactivating a solenoid operated electromagnetic device wherein current is allowed to flow to the coil of the solenoid through a slow current decay path when - 25 it is desired to maintain the devi~e in its activated position and through a fast decay path when it is de-sired to allow the device to return to its unactivated position.
It is another object of the present invention 3~ to provide a method and apparatus of the foregoing type wherein the slow dec&y path comprises an SCR disabled by a final momentary turn ON of the power switch nor-mally building up the load current.
It is another primary object of the present invention to provide Q method and apparatus for con-0~5 trolling the current through an inductive load wherein comparator means respond to sensed levels of load cur-rent to generate HIG~ and LOW output levels that are fed back to the reference input of the comparator to S generate reference voltages representative of first and second levels of load current and that are also applied to switch means to connect and disconnect power to the load so as to maintain the load current between the first and second current levels.
~It is another object of the present invention ,;~ro v;~e to ~m~e a method and apparatus of the foregoing type wherein flip-flop means cause variable current source means to change the magnitude of current through a sense resistor coupled to the comparator sense input lS when the load current first exceeds a peak actuation level.
SUMMARY OF INVENTION
An inductive load driver circuit comprises first and second switch means and high and low impedance load current decay means. For the duration of a load actuation signal the first switch means are responsive to the magnitude of the load current to complete and interrupt a first current path to the load to cycle the load current between first and second levels. The second switch means are enabled for the duration of the load actuation signal to complete a second current path to the load when the first switch means interrupts the first current path. When completed the second cur-~ rent path comprises the low impedance decay means al-- 3~ lowing the load current to decay slowly from the first current level to the second level to provide during ;- such slow decay a loa,d current sufficient to maintain ~ e actuation of the i~rt~to~ load.
The end of the load actuation signal disables the seooni switch means to interrupt the seconù current ,, path and thereby require the load current to decay rapidly through the high impedance decay means. In one embodiment of the invention, the second switch means comprise a SCR disabled by a final momentary turn ON
of the first switch means.
Comparator means respond to the current levels through an inductive load to generate HIGH and LOW level outputs causing first switch means to connect and dis-connect power to the load. When the load current ini-tially exceeds a peak load actuation level, flip-flop means responsive to the corresponding change in com-parator output levels change the current through an auxilliary sense resistor coupled to the sense input of the comparator means. In one embodiment, ~ one-shot multivibrator prevents a change in the currentto the auxilliary sense resistor for a fixed period after the commencement of a load actuation signal.
The subsequent HIGH and LOW comparator output levels are fed back to the comparator reference input to switch the reference voltage thereat so as to represent first and second levels of the current sufficient to maintain actuation of the load.
These and other objects and features of the present invention will become more apparent from the following written description taken in conjunction with the following figures wherein FIGURES
FIGURE 1 illustrates in block diagram form an engine control system in the form of a fuel injection control system utilizing one or more transduced engine dependent parameters to control the pulse duration of fuel injected into an internal combustion engine;
FIGURE 2 illustrates in circuit schematic form one embodiment of the present invention;

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FIGURE 3 illustrates in time coordinated form certain waveforms illustrative of the operation of the Figure 2 embodiment; and FIG~RE 4 illustrates in circuit schematic form a second embodiment of the present invention.
FIGURE l The circuit of the present application may be utilized in combination with any inductive device requiring the precise control of actuation thereof with minimum expenditure of power. One such application is to control one or more electromagnetically-actuatable fuel injection valves to provide single, simultaneous, or grouped fuel pulses of controllable duration to certain solenoid controlled fuel inlet passages of an internal combustion engine.
One such fuel injection system may be of the type shown in the block diagram of Figure 1. Therein, an injector drive circuit 10 of the present invention responds to injector actuation signals provided by a fuel injection control system 12 to control one or more injectors 14 to inject a precise quantity of fuel into a suitable fuel intake passage of internal combustion engine 16. The injector actuation signals are computed in response to one or more engine-dependent parameters communicated from engine 16 to fuel injection control system 12 by one or more engine trans~ucers, such as RPM transducer 18, an intake manifold pressure transducer 20, an engine temperature transducer 22~ or an engine roughness sensor 24.

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Fuel injection control system 12 may be of the type disclosed in commonly-assigned U.S. Patents 3,734,068 and RE 29,060 issued to Reddy respectively on May 22, 1973 and December 7, 1976. As disclosed more fully therein, during one portion o-E an engine cycle, a capacitor is initiali~ed to a starting value in accordance with one engine-dependent parameter such as the magnitude of a speed-dependent trigger signal as developed by RPM
transducer 22. In the next portion of the engine cycle the capacitor is charged with a ramp voltage, the slope of which may be modified in accordance with a temperature signal as developed by temperature transducer 22.
Comparator means then compare the resulting magnitude of this ramp voltage with a reference signal in the form of a pressure signal, as developed by a pressure transducer 20 which may be of the type disclosed in applicant1s U.S.
Patent No. 4,131,088, issued December 26, 1978. The comparator means generates an injector actuation signal Tp having a duration beginning at the start of the second portion of the engine cycle and ending when the ramp voltage exceeds the pressure reference. The injector actuation ~:: signal may be further modified as disclosed in the commonly-assigned patent to Taplin et al. 3,789,816 using a roughness signal as developed by a roughness sensor which may be of the type shown in applicantls U.S~ Patent No.
4,092,955, issued June 6, 1978.
The fuel injection valve 14 may be of the type disclosed in commonly-assigned U.S. patent 4,030,668 issued mb~ - 8 -s on June 21, 1977 to Kiwior. The fuel injection valve described comprises electromagnetic coil means operative when suitably energized to apply a motion-imparting magneto-motive force to armature means of a movable actuator means. The actuator means are moved against the bias of a closing spring from a closed position whereat valve head means carried by the actuator means seat on valve seal means to an open position whereat a radial shoulder element of the actuator means abuts a radial surface ~b/J~ - 8a -.

L7'0:~5 fixed with respect -to the val~e body in which the actua-tor means reciprocate.

Figure 2 shows one embodiment of the present invention, the operation of which is explained in con-junction with the waveforms shown in Figure 3.
In Figure 3, waveform 3a represents an in-jector actuation signal Tp, the width of which is gen-erated to control the opening and closing of one or more fuel injectors. Waveform 3b illustrates the ap-plication of either a regulated voltage or an unregulated voltage s+ to one side of the solenoid coil of an injector. Waveform 3c illustrates the current through tne solenoid coil, Io being the current at which the injector armature begins to move ~rom its closed to its open position, Ip being a current slightly in excess of the current at which the in~ector always fully opens, IHL being a lower level of holding current slightly in excess of the current level at which the injector armature begins to drop out, and IHH being a h~igher level of holding current in excess of the lower holding level. rl is the efective decay constant associated with the decay of current from IHH and IHL and l2 is the effective decay constant associated with the return of the injector armature from its open to its closed position.
In the Figure 2 embodiment, inductor Ll repre-.
sents the solenoid coils of one or more electromagnetic-cally-actuated fuel injection valves 14. First switch means in the form of a suitable NPN power transistor ` Ql couples one side of A of coil Ll and a load conductor 30, here connected to the high or B-~ side of a suitable power supply. Coil sensing means in the form of a small ohmage current sensing resistor Rl couples the other side B of coil Ll and a second load conductor 32, here ms/~

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connected to -the ground side of the power supply, Connected in series between ground conductor 32 and coil side A are controlLable coil current decay means' here in the form of an NPN transistor Q2 and unidirec-tional current conducting means in the form of diode Dl~
When rendered conductive as will be discussed shor~-ly, power transistor Ql completes a first current path to and through coil ~1 and sensing resistor Rl~
such path comprising B+ conductor 30 and the emitter-to-collector junction of ~1. When rendered non-con-ductive, power transistor Ql interrupts this first, current path. Transistor Q2 when rendered conductive 'completes a second'current path to and through coil Ll and sensing resistor Rl, such second path comprising the ground conductor 32, the collector-to-emitter j,unc-tion of transistor Q2, and anode-to-cathode junction of diode Dl. And when rendered non-conductive~ tran-sistor Q2 interrupts this second current path.
~ To enable both powe:r transistor Ql and decay 20, transistor Q2 during the presence of an injector actuation signal TP, at terminal C, the terminal is coupled respectivel~v to thè base of an NPN input transistor Q3 by an input resistor R2 and to the base of another NPN
,input transistor Q4 by another input resistor R3.' The Q3 coilector is coupled to B+ by series-connected res'istors : R8 and R9 and, at a node D therebetween, is coupled by resistor R10 to the non-inverting input of a comparator - CPl. A Zener diode ~1 having its anode connected to node -~ D and its cathode coupled to B+ conductor 30 is operative, for the duration of an injector actuation signal TP at the ~3 base, to clamp the voltage at node D at a reference voltage of B+ less the breakdown voltage of the Zener ~1.
' The Q4 emitter is ~rounded at conductor 32, ``~ and tlle Q4 collector is coupled to B+ conductor 30 by series-connected resistors R4, R5 and at a node E there-between is coupled to the base of a PNP transistor Q5.

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7~ 5 The Q5 emitter is coupled to B-l~ conductor 30~ and the Q5 collector is coupled by resistor R6 to the base of transistor Q2 and therefrom by resistor R7 to point A.
An injector actuation signal TP saturates transistor Q4 and through transistor Q4 enables transistors Q2 and Q5 to saturate whenever the potential at coil side A is suf~iciently beLow that o~ coil side B~
Comparator CPl may be a conventional oper~-tional amplifier such as a 2901 quad comparator of the type that Produces HIGH and LOW ouput levels, here of B+ and zero volts, when the voltage at its non-in-verting input is respectively greater and less thàn the voltage at its inverting input. In the Figure 2 embodiment, the voltages at the inverting input and non-inverting input are both referenced to that of B+ conductor 30 and respectively comprise'a sense voltage and a reference voltage. As will be explained more fully shortly,'the voltage at the inverting CPl input drops below B+ with increasi.ng current`through'coil L1.
' The output of comparator CPl is coupled by a feedback resistor Rll back to the non-inverting input and is cou,pled by another resistor R12 to the,base of a first PNP drive control transistor Q6. The Q6 collector is connected to ground conductor 32, and the Q6 emitter is coupled to B+ conductor 30 by series-connected resistors R13 and R14 to suitably bias, at a node F
therebetween, the base o~ a second PNY drive control transistor Q7. The Q7 emitter is coupled to B~ conductor 30, and the Q7 collector is connected to the Ql base.
~ Zener diode ~2 having`its anode coupled to the Ql emitter at coil side A and its cathode coupled to the B-~ conductor 30 through resistor R14 protects both transistors Ql.and Q7 against the possibly-damaging , -- 11 --~ ms ~

~l~7a~s reverse voltages effected by the inductive kicks produced when transistor Ql interrupts the first current path to coil Ll.
Representative of a one circuit location responsive to the attainment of the peak current the output of comparator CPl is also connected to the reset input R of a flip-flop FFl. The set input S of flip-flop FFl is coupled by a capacitor Cl to the injector actùation terminal C and in response to a positive-going set input produces both a HIGH level output at one output terminal Q and a LOW
level output at another output terminal Q*. The LOW level output Q* is connected to the base of a PNP transistor Q8, the emitter of which is connected to B-~ conductor 30. The Q8 collector is coupled to the inverting input of comparator CPl by series-connected resistorc; R15 and R16, and the node G therebetween is coupled by a resistor R17 to B+ conductor 30.
The exact values of voltage drop across resistors R15 and R17 needed to cause comparator CPl to switch from one of its output levels to the other are determined by the relative values of resistors R10 and Rll and the voltage thereacross. These points may be computed assuming a B+
of 14 volts, Rl0 and Rll values of 10K and 100K respectively, and a 5.6 volt breakdown voltage for Zener ~.1.
With a zero output level from comparator CPl, as exists to complete the first current path to coil Ll, the voltage across resistors R10 and Rll is B+ less the breakdown voltage of Zener Zl. The reference voltage resulting at the non-inverting input of comparator CPl is therefore mb/~ 12 -.

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equal to [B+ - VZ] -R10~+ Rll' or (14-5.6) 0.9 = 7.6.
With a HIGH output ~i mb/~)b - 12a-. .

, s level ~rom comparator CPl of 1~ volts as exits to interrupt ~he first current path, the voltage across resistors R10 and ~11 decreases to 5.6 volts which when multiplied by the 0.9 ratio of resistance R10/R10 +
Rll results in a second reference voltage at the non-inverting CPl input terminal of about S.l volts below B+.
In other words, the ma~nitude of feedback re-sistor Rll cooperates with the magnitude of input re-sistor R10 and the magnitudes of the two different CPl output levels ~here Zero and B+~ to vary reference voltage at the non-inverting CPl input between 6.4 volts below B+ when the CPl output is ~ero volts and 5~1 volts below B+ when the CPl output is 14 volts. As will be discussed shortly~ when resistor R15 is connected in parallel with resistor R17 to set the current dropping the voltage from B-~, these reference voltages and the "hysteresis" between them, determine the peak opening current level Ip, Figure 3c, and the lower level of the hold current IHL and the difference between them.
These reference voltages also determined the higher level of the hold current level IHH and lower hold current level IHL, and the difference between them, when resistor R15 is not used to set the current drop-ping volta~e from B+.
To generate a voltage corresponding to that produced across sensing resistor Rl, node G is also coupled to the collector of an NPN transistor Q9, the emitter of which is coupled by a variable resistor R18 to ground conductor 32. The Q9 base is coupled to B+
conductor 30 by resistor R19 and also to the emitter of a PNP transistor Q10, the collector of which is grounded at conductor 32. The Q10 base is coupled to the current sensing resistor Rl at coil side B and the QlO base--~ to-emitter voltage drop is selected to negate the-Q9 base-to-emitter drop.

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70~l5 As will be discussed shortly, when the injectors are being opened, ~ransistors ~9 and Q10 co-operate with resistors Rl5 and Rl7 to develop a very small current that produces across resistor Rl8 a vol-tage representing that developed across current sense resistor Rl at the much larger injector opening drive current. After the injectors have opened and the cur~
rent thereto is reduced to just hold them open, tran-sistors Q9 and Ql0 cooperate with resistors R17 and Rl8 to produce a second very small current that produces across resistor R18 a voltage representing that produced across resistor Rl at the much larger injector holding current. Thus, assuming each injector requires a peak current of 1.5 amps to open and current of 0.4 amps to hold it open, a voltage drop of 0.15 volts would be produced across a sensing resistor Rl of 0.1 ohms by the 1.5 amp peak opening current lp and 0.04 volts would be produced by the 0.4 amp holding currentO
Assuming the circuit of Figure 2 drives eight injectors ak a time, the required total opening current of 12 amps and total holding current of 3.2 amps would produce respective volt drops across sensing resistor Rl of about 1.2 and 0.32 volts and corresponding voltage drops would be produced across resistor R18.
The magnitude o~ the ~18 resistance is ad-justed so that, with transistor Q8 biased ON, the peak current through resistance Rl8 produces a voltage drop across resistance R15 in parallel with a resistance Rl7 just exceeding the 6.4 volt drop to the non-inverting input of comparator CPl. Assuming values of resistances R15 and R17 respectively of 5K ohms and 10k ohms and a 5.6 volt breakdown for Zener ~1~ this 6.4 vo.lt drop-to the non-inverting CPl input when divided by the 3.3K parallel resistance of R15 and R17 would produce therethrough a current of about l.93 milliamps Then to match the .. csm/,~
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1.2 volt drop produced across resistor Rl by the 12 amp peak opening current with these 1.93 milliamps across R18, the value of R18 would be set at about 625 ohms.
As will be explained more fully shortly, after the peak opening current is detected by comparator CPl, the resulting HIGH output therefrom resets flip-flop FFl. The HIGH Q* output stops current flow through resistor R15 and causes just resistor R17 to determine both the sense voltage at the inverting input of comparator CPl and the magnitude of the current through resistor R18 associated with the higher and lower levels of the hold currentO Resistance R17 reduces to 0.51 milliamps the current required to exceed the now 5.1 volt drop to - the non-inverting input of comparator CPl and these 0.51 milliamps in turn produce about a 0.32 volt drop across resistor R18 corresp.)nding to a lower level of hold current of about 3.2 ampsO
In the operation of the embodiment illustrated in Figure 2, prior to the beginning of an injector actuation signal TP, transistors Q3 and Q~, and through Q4 transistors Q2 and Q5, are biased OFF. Until set by the beginning of an injector actuation signal TP, flip-flop FFl produces a HIGH voltage at its Q* output, thereby biasing Q8 OFF. With B-~ voltage coupled to - - the non-inverting input of comparator CPl by resistors R9 and R10, that input controls and comparator CPl produces a HIGH level output, thereby biasing OFF transistors Q6 ana in turn Q7 and Ql. With no current flowing through sensing resistor Rl, transistor Ql~ and therefore tran-sistor Q9 are biased OFF and essentially no current is drawn aaross resistor Rl70 Concurrent with the beginning of an injec-tor actuation signal TP, the leading positive-going edge thereof is differentiated by capacitor Cl to pro-vide a set pulse to the set input S of flip-flop FFl.
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The resulting LOW level produced at the Q* output of flip-flop FFl biases ON transistor Q8 so that the vol~
tage at node G to inverting input o~ comparator CPl i9 then that on B+ conductor 30 less that developed across the parallel combination of resistors R15 and R17. However, immediately after the beginning of a TP signal, the voltage at the inverting input is still close to B-~ while the voltage at the non-inverting CPl input is dropped to B+ less the Zener breakdown. The higher voltage at the inverting CPl input then causes the comparator CPl to produce a LOW output to bias ON
transistor Ql through transistors Q6 and Q7.
As the current to coil Ll builds up toward the 12 amp peak opening current lp, the current through ~ resistors Rl and RlB also builds. When the R18 current ; exceeds 1.93 milliamps, this current produces a voltage drop of greater than 6.4 volts across resistors R15 and R17, thereby lowering the voltage at node G to the inverting input below that at the non-inverting input. With a greater voltage resulting at its non-inverting input, comparator CPl produces a HIGH level output, biasing OFF transistor Q6 and therethrough tran~
sistors Q7 and Ql.
When output of comparator CPl switches to a HIGH
level output, this output resets flip-flop FFl to produce a HIGH level output at its Q* terminal and in turn to bias OFF transistor Q8. With transistor Q8 OFF, just re-sistor R17 develops the volta~e drop from B+ to the inverting input of comparator CPl and does so with less current since the resistor R15 no longer is in parallel with resistor R17-.
- With transistor Q1 biased OFF, the first cu~-rent path to coil Ll is interrupted to allow the current therethrough to decay and to thereb~ reverse the voltage induced thereacross so that side B is positive with respect to side A. With its collector now at a lower voltage csm/~ -than its base~ previously enabled transistor Q5 completes a biasing circuit to -the 02 base across R7. With its emitter now at a lower potential than its base, pre-viously enabled transistor Q2 now completes the second current path to provide replenishment current from ground conductor 32 through diode Dl, coil Ll, and sensing resistor Rl.
The ef~ective impedance to the current de-caying through this second path comprises approximately 0.3 ohms representing the parallel equivalent of an internal resistance of 2.3 ohms for each of eight parallelly-connected injectors plus .016 ohms produced by 12 amps across the 0.2 volt drop of 0.1 volt each across transistor Q2 and diode Dl. Dividing this ef-fective 0.316 ohm impedance into the 1.67 millihenry equivalent of an inductance of eight parallelly-con-nected injectors of 13.25 millihenries each fixes the L/R decay time constant T 1 of this circuit at about 5.3 milliseconds and thereby fixes the perio~d rec~uired to decay from one known level to another.
Thus, the coil current decays at essentially this rate from 12 amps to the lower holding level IHL
of about 3.2 amps where the volt:age across resistor R17 at the inverting input o~ the comparator CPl is less than the now 5.1 volt drop to the non-inverting CPl input.
To develop S.l volts across the lOK resistor R17 requires about 0.51 milliamps which produces a 0.32 volt drop across R18.
~hen the injector current decays just below - 30 3.2 amps, the voltage drop across R17 to the inverting CPl input decreases below the 5.1 volts dropped to the noninverting CPl input so that the voltage at the in-verting input of the comparator CPl is greater than at the non-inverting input. With the inverting input then controlling, comparator CPl again produces a ~ero level output biasing ON transistor Ql through transistors 06 and Q7 and increasing the reference voltage at the CPl non-inverting input to a 6.4 volt drop from B+.
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The injector current then increases agaln until 6.4 volts is again effected to the inverting input across now just resistor R17. This drop is effected by 0.~4 milliamps across resistor R17 which produces a drop of about 0.~ volts across resistor R18.
A drop of 0.4 volts across resistor R18 corresponds to a similar drop across resistor Rl and therefore to an injector current of 4 amps thereacross.
The injector current thereafter is cycled between the lower and the higher levels of holding current of 3.2 and 4 amps respectively until the end of the injector actuation signal TPo At that instant the injector current would be at some unknown value between 3.2 and 4 amps. If the second current path were still enabled, the coil current would require some unknown time up to one millisecond to decay below the low holding level of 3.2 amps. Since an uncertainty of up to a millisecond in the closing time of the in-jector would detract from the precision required for fuel injection, the second current path is thus imme-.diately disabled with the end of the injector actuation pulse to require the.coil replenishment current to be supplied through a much faster decay circuit comprising Zener ~2. Assuming a breakdown voltage o 33 volts for Zener ~2 r an effective resistance of about 8 ohms is presented by this Zener to a 4 amp holding level ` ~ current. Com~ining these effective resistances with`
the 0.3 ohm the equivalent internal resistance of the : eight 2.3 ohm injector coils results in a total efféc~
,` 30 tive resistance of 8.3 ohmsO Dividing the 1~67 milli~
henry effective inductance of eight 13.25 millihenry injector coils results in a L/R decay time constant

2 of about 0.2 milliseconds. This 0.2 millisecond de-cay constant ~2 is. more than 20 times faster than the decay constant Tl effected ~y the second current path and effectively eliminates variations in closing times as a factor degrading precision of fuel injection.
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~7~5 In the alte~native embodiment of the invention illustrated in Figure 4, the current sense resistor Rl is located on the B-~ side of each injector so that the voltage across the sense resistor is measured with respect to s+ rather than with respect to ground. Also, -to reduce the power loss and added heating associated with driving the decay transistor Q2, this device is replaced by a silicon controlled rectifier SCR 1, which does not require a continuous drive but does require `additional control circuitry to effect turn on and turn off. Also, to assure that the injectors pull-in in the presence of increases in the supply voltages to levels where the .rise time of current might be faster than the mechanical response time of the injectors, the Figure 4 embodiment also comprises circuitry for holding the peak opening current Ip for at least a minimum fixed period.
Again, inductor Coil Ll represents the sole-noid coils of one or more electromagnetically-actuated fuel injector valves 14 to be d~.iven singly, simultane-ously, or in groups with pbwer supplied between a B+
conductor 30 and a ground conductor 32. First switch means in the form o Darlington connected NPN transis-tors Qll, such as a RCA expitaxial TA 8997, couples.
-:: one side A of coil Ll and ground conductor 32, and a small ohmage-current sensing resistor Rl couples the other side B of coil Ll to the B+ conductor 30. Coil side A is also coupled directly to the anode of a siIicon controlled rectifier SCR l, the cathode of which is coupled to the B+ conductor ~0. Coil side A is also . coupled to the gate o~ SCR l by a pair of series con-nected capacitors C2 and C3 and to ground 32 by a re-sistor 21.
Whenever transistor Qll is biased OFF, during a TP signal the resulting back-emf-induced voltage rise at coil side A is communicated by capacitors C2 and ~ .. csm/~

0~5 C3 -to the gate o~ SCR 1 to turn ON SCR 1 un~ll reverse biased OFF again by a subsequent turn ON of Qll. To insure that SCR 1 does not come ON when an injector actuation signal TP is not present, the node H between capacitors C2 and C3 is coupled to the collector of an NPN transistor Q12 and is grounded therethrough during a TP* signal, the complement of the TP signal~
To be able to alternately-complete and in-terrupt a first current path from coil side A through transistor Qll to ground 32, the Qll base is coupled to ground 32 by a resistor 22 and also to B+ 30 by a resistor 23 connected in series to the Qll base by the emitter-to-col].ector junction of a PNP transistor Q13.
The Q13 base is connected to the emitter of a PNP tran-sistor Ql~ and to B+ 30 by a resistor R24. The Q14 collector is grounded at 32, and the Q14 base is coupled by a resistor R25 to B+ conductor 30 and by a resistor R26 to the output of a comparator CP2.
Comparator CP2 has an inverting input and a non-inverting input, here comprising the reference and sense inputs, respectively. The CP2 output is coupled by a resistor R27 to the CP2 non-inverting input, which is coupled to grour~d 32 by series connected resistors R28 and R29 having a rlode J therebet~een.
Coupled to the node J are the collectors of a pair of PNP current source transistors Q15 and Q16 each of which comprise an emitter follower circuit with an NPN tran-sistorO ~he Q15 emittex is coupled to B+ R30 by a fixed ` resistor R30 and a variable resistor R31, and similarly the Q16 emitter is coupled to B~ 30 by a fixed resistor R32 and a variable resistor R33. The Q15 and Q16, bases are both coupled by a resistor R34 to ground 32 and by the emitter-to-base junction of transistor Q17 to coil side B. The Q17 collector is coupled to B+ conductor 30. With the base-to-emitter drop of transistor Q17 `~ matching the base-to-emitter rises of transistor Q15 and ., . _ ~o _ csm/~
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Q16, the Q15 and Q16 emi-tters therefore follow the voltage at poin-t B to provide currents through resistors R30-R31 and R32-R33, each varying directly wi-th the current through sensing resistor Rl. Summed at node J, these Q15 and Q16 currents develop a voltage across resistor R29 varying with the injector currentO To selectively bias OFF transistor Q15 and stop current therethrough to resistor R29 after the pull-in level Ip of injector current is attained, the Q15 emitter is coupled to ground conductor 32 by the series connection of a resistor R35 and the emitter-to-collector junction of an NPN tran-sistor Q18.
The output of comparator CP2 is also coupled by a capacitor C4 and a diode D2 to the base of an NPN
transistor Ql9 of a flip-flop FF2 also comprising a second NPN transistor Q20. (Another circuit location responsive to the attainment of the peak current to which flip-flop FF2 might be coupled by capacitor C4 and Diode D2 is the emitter of Darlington transistor Q13. This circuit location provides more current`and power than the uncommitted emitter in the 2901 quad comparator CP2.) The Ql9 collector is coupled by a resistor R36 to the Q18 base, and the Ql9 and Q20 col-lectors are coupled by respecti~ve resistors R37 and R38 to B+ conductor 30 and by resistors R39 and R43 to the Q20 and Ql9 bases respectively. The Ql9 and Q20 emitters are grounded at 320 Injector actuation terminal C is coupled by a capacitor C5 to the node between diodes D4 and D5 connected ~orwardly in series from ground 32 to the Q20 base. Terminal C is also coupled by resistors R40 and R41 to the bases of NPN transistors Q21 and Q22 respectivelyO The Q21 collector is series-connected to ground 32 by a capacitor C6 and a resistor R42 having a node K therebetween coupled by a resistor R43 to the inverting CP2 input. The Q22 collector is coupled to csm/~

' s+ conductor 30 by a resistor R4~ and by a resistor R~5 to the Q12 base. An injector actuation signal TP biases ON
transistor Q22 and biases OFF transistor Q12 through the Q22 collector-to-emitter junction. When an injector actuation signal Tp is not present, the resulting HIGH
Q22 collector voltage produces the TP* signal biasing ON transistor Q12.
Also coupled to the Q22 collector is the base of an NPN transistor Q23, the collector of which is coupled by a resistor R47 to B~ conductor 30 and the emitter of which is coupled to capacitor C6 and the collector of a transistor Q21. ,When the TP signal is present, resistor R46 and the Q22 collector-to-emitter junction are coupled within the base of a PNP transistor , Q24 to ground 32, thereby biasing ON transistor ~24 and coupling the breakdown voltage of a Zener diode ~4 to the inverting input of comparator CP2.
Even though the SCR 1 gate signal is effectively grounded by transistor Q12 by the fall of the TP signal, ~ 20 the SCR 1 is not cut off until reverse biasedO To pro-``' vide a short (approximately 50 microsecond) reverse bias toSCR 1 upon the fall of the TP signal, the Q21'collector voltage rising with the fall of the TP signal is coupled by capacit~r C6 and resistor R~3 to the inverting CP2 input causing a positive spike thereat producing a momentary - LOW level output turning ON transistor Qllo The momen-tary turn ON of transistor Qll quickly diverts the current through SCR 1 to quickly turn it OFF.
An additional feature afforded by the Figure , 30 ~ embodiment are means to assure that the coil current is not dropped below the peak pull-in current before a minimum time has elapsed from the beginning of an injector actuator signal. ~uch protection is desirable where the combination of a higher-than-normal B+ supply and/or a slower responding injector would otherwise cause the coil current to exceed the peak pull-in-current csm/~

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and then drop back to the holding level before the injectors have in fact opened. To avoid this pos-sibility, the comparator CP2 is caused to maintain a LOW level output for at least a minimum period such as 1.5 milliseconds after the beginning of an injector actuation command. This minimum period is generated by timing means in the form of a one-shot monostable comprising a resistor R50 coupling B~ conductor 30 to a node N between a capacitor C7 and a diode D6 connected in series between the collector of flip-flop transistor Q20 and the base of an NPN transistor Q25~ The Q25 collector is coupled by a resistor R51 to B+ conductor 30 and by a resistor R52 to the base of an NPN transistor Q26, the em tter of which.is grounded at 32. The Q26 col-lector is cou~led to the output of comparator CP2 by capacitor C4 and to the node between diodes D2 and D3 connected in series between ground 32 and the base of flip-flop transistor Ql9.
.As will be discused more fully shortly, the beginning of an injector actuat:ion signal TP causes flip-flop transistor Q20 to ground one side of capacitor C7. This momentarily biases OFF one-shot transistor Q25 and biases ON transistor Q26 to ground the CP2 out-put. If, auring the short l.S millisecond period that one-shot capacitor C7 charges through resistor R50, the sense voltage at the non-inverting CP2 input exceeds the reference voltage at the inverting CP2 input, the resulting HIGH level output o comparator CP2 would be diverted to ground through transistor Q26 and would not be communicated to the Ql9 base until after the short one-shot period~ Thus inhibited for the one-shot period, transistor Ql9 would therefore not bias OFF transistor Q18 to downshift the reference voltage to the non inverting comparator CP2 until both the one-shot period had elapsed and the coil current exceeded the peak opening current , ,, .

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level.
In operation o~ the Figure 4 embodiment, prior to the receipt of terminal C of an injector actuation signal TP, all transistors are biased OFF with the exception of flip-flop transistor Ql9, the one-shot transistor Q25 and transistor Q12 which is biased ON
by the Q22 collector voltage TP* thereby grounding the SCR 1 gate. With the Q24 base coupled to B+ conductor 30 by resistors R44 and R46, transistor Q24 is biased OFF
so that the inverting input of comparator CP2 is clamped to ground 32 by resistors R42 and R43. The non-inverting CP2 input there~ore controls to produce a HIGH CP2 output biasing OFF power transistor Qll through control transistors Q13 and Q14~ No current therefore flows through Coil Ll.
- With the presence of an injector actuation : pulse TP, the rise thereof is communicated to the Q21 and Q22 bases by resistors R40 and R41, biasing ON
transistors Q21 and Q22. The Q12 base is grounded through transistors Q22 and resistor R45 to bias OFF
transistor Q12, thereby enabling SCR 1 by removing the ground to the SCR 1 gate. The rise of the TP actuation signal is also communicated by capacitor C5 and diode D4 to the base of flip-flop transistor Q20, biasing ON transistor Q20 and therethrough grounding the bias to flip-flop transistor Ql9. The B+ voltage at the Ql9 :~ collector biases ON shunt transistor Q18 to reverse bias : . current source transistor Q15 and through transistor Q18 and resistor R35 the current that would otherwise flow through current souxce transistor Q15~
With its base now grounded through resistor R46 and transistor Q22, transistor Q24 is biased ON
- to communicate the breakdown voltage of Zener ~4 to the inverting input of comparator CP2. With no voltage : drop.develop:ed. across resistor R29 until current begins to flow through coil Ll~ the Zener breakdown voltage at the inverting CP2 input produces a LOW level output of comparator CP2 biasing ON control transistor Q13 and Q14 to develop a voltage across resistor R22 biasing ON power - ~ 24 -csm/"~

7~5 transistor Qll.
As the coil current begins to build up, the voltage across sensing resistor Rl increases lowering the potential at coil side B. The Q16-Q17 current source-emitter follower circuit causes the voltage drop across resistors R32-R33 to correspond closely to that across sensing resistor Rl. Thus, increasing with the current through sensing resistor Rl, coil Ll, and tran-sistor Qll, the Q16 current at node J develops a voltage across resistor R29 increasing with that across sensing resistor Rl.
Variable resistor R33 was previously set so that the QlG current caused the voltage across resistor R29 to just exceed the breakdown voltage of Zener ~4 at a value of coil current slightly in excess of the solenoid pull-in current Ip under worst-case conditions.
Representative switching points may be computing as-suming representative circuit values shown in the Table - o~ Component Values below. That is, a minimum pull-in cur~ !
rent Ip of 12 amps, a low level of hold current IHL
o~ 3.2 amps, and HIGH and LOW level CP2 outputs corresponding respectively to 14 volts and zero volts.
Then, when the CP2 output is LOW, as is ini-tiall~ the case until the 12 amp pull-in current is exceeded, the sense voltage at the non-inverting CP2 - input is that developed across resistor R29 multiplied by the 0.9 ratio of R27/R27 + R28 (i.e., 0.9 = 100/
(100`+ 10). Thus, to exceed the 4.3 volts re~erence at the inverting CP2 input, about 4.8 volts must be developed across the 3.6K resistance of R29, requiring `~ about 1.33 milliamps thereacross. To provide this 1.33 milliamps current when the minimum pull-in current o~
12 amps is just exceeded, resistors R32-R33 must be set to develop the same-1.2 volts developed across sense resistor Rl. To develop 1.2 volts with 1.33 milliamps, ` the resistance of resistors R32 and R33 must be set at ` 900 ohms.

csm/~-~'70~l5 If more than the 1.5 millisecond delay of the one-shot has elapsed when the 4.3 volt reference at the inverting input of comparator CP2 is exceeded for the first time, the resulting 14 volt HIGH output is communicated by capacitor C4 and diode D2 to the base of flip-flop transistor Ql9, thereby biasing ON
. transistor Ql9 and therethrough biasing OFF shunt . transistor Q18. The voltage at the non-inverting sense ; input of comparator CP2 is now the voltage developed across resistor R29 the 14 volt CP2 output less the voltage developed across resistor R29 multiplied by 0.9. Thus, to fall below the 4.3 volt reference at the inverting CP2 reference input when the CP2 output is 14 volts~
. about 3.3 volts must be de~eloped across R29, requiring about 0.9 milliamps therethrough. These 0.9 milliamps are provided through current sources transistors Q15 and Q16 in developing a 0.32 volt drop across resistors R30-R31 and R32-R33, corresponding to the lower hold level current of about 3.2 amps. This requires that the resistors R30-31-32-33 provide an èquivalent resistance of about 350 ohms, meaning that R30 and R31 be about 570 ohms since resistors R32 and R33 were previously ~ set at: 900 ohms O
: TABLE OF REPRESENTATIVE VALUES
The following is a table of representative values and designations of components that may be used to embody the cireu1ts 111ustrated ln Figures 2 and 4 .
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TABLE OF COMPON~NTS

RESISTORS (Ohms) Zener (Breakdown Voltage) Rl 0 1 R21 4.7K R41 10K ~1 S.6 IN4734A
5 R2 10K R22 100 R42 10K ~2 27 IN4750A
R3 10K R23 58 R43 10K ~3 43 IN4755A
R4 560 R24 2.2K R44 6.8K ~4 4.3 IN4731A
R5 10K R25 4.7K R45 10K
R6 33 R26 l.lK R46 22K Capacitors (Microfarads) R7 50K R27 100K R47 2.2 R8 2.2K R28 lOK R48 22K Cl 0.001 R9 6.8K R29 3.6K R49 C2 0.0068 10 R10 10K R30 330 R50 50K C3 0.0068 C4 0.05 Rll 100K R31 0-lK R51 10K C5 0.05 R12 6.8K R32 330 R52 10K C6 0.05 R13 560 R33 0-lK C7 0.05 R14 lK R34 3.3K
R15 5K R35 2.2K Transistors and Diodes 15 R16 10K R36 22K All NPNs - MPSA05-Motorola R17 10K R37 4.7K All PNPs - MPSA55-Motorola R18 0-lK R38 4.7K Qll 2N6387-RCA
Rl9 33K R39 22K SCR 1 - C122D - G.E.
R20 R40 10K Diode Dl - MR754 - Motorola 2C Other Diodes IN4004 CONCLUSION
Having described several embodiments of the invention, it is understood that the specific terms and examples are employed herein in a descriptive sense only and not for the purpose of limitation. Other em-bodiments of the invention, modification thereof, and alternatives thereof will be obvious to those skilled in the art and may be made without departing from our invention. We therefore aim in the appended claims to cover the modifications and changes as we would in the true scope and spirit of our invention.
WHAT WE CLAIM IS:

Claims (14)

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:

Claims:

1. In a current control circuit enabled by a load actuation signal, comprising:
a) switch means operative to actuate an inductive load by increasing the current thereto above a first current level and to thereafter alternately connect and disconnect a power supply to said load to maintain load actuation with current in a range between a second current level and a third current level, each less than said first current level, b) load current sense means comprising a first sense resistor in series with said inductive load and second sense resistor connected in parallel with said first sense resistor;
c) reference means providing at least two reference voltages representing two of said first, second, and third current levels;
d) comparator means having a sense input coupled to said second sense resistor, a reference input coupled to said reference means, and an output coupled to the said switch means, said comparator means adapted to generate a first comparator output level when a sense voltage at said sense input is a greater magnitude than a reference voltage at said reference input and a second comparator output level when said sense voltage is less than the magnitude of the reference voltage at said reference input; and e) time delay means for delaying a downshift of said load current from said first level to said range of said second and third levels when said load current increases to said first level at a rate too fast to actuate said inductive load.

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2. The current control circuit of Claim 1 further including flip-flop means coupled to said second sense resistor and to circuit means responsive to the attainment of said first current level, said flip-flop means comprising variable current source means coupled in series with said second sense resistor and operative to change the current therethrough in response to said attainment of said first current level.

3. The current control circuit of Claim 2 wherein said time delay means is coupled to said flip-flop means and is operative to delay the generation of the second of said flip-flop outputs for a predetermined period after the commencement of said load actuation signal.

4. The current control circuit of Claim 2 wherein said circuit means responsive to the attainment of said first current level comprises one of said comparator means output and said switch means.

5. The current control circuit of Claim 3 wherein said flip-flop means is operative to generate a first flip-flop output level in response to the commencement of the load actuation signal and a second flip-flop output level in response to the attainment of said first current level.

- ?

6. The current control circuit of Claim 1 wherein said reference means comprise a feedback resistor coupling said comparator means output to said comparator means reference input and operative to generate thereat one of said two reference voltages when said comparator means generates one of said comparator means output levels and the other of said two reference voltages when said comparator means generates the other of said comparator means output levels.

7. A current control circuit enabled by a load actuation signal, comprising:
a) switch means operable to actuate an inductive load by increasing the current therethrough above a first level of load current and operable thereafter to alternately connect and disconnect a power supply to said load to maintain load actuation with holding current ranging between second and third levels of current, wherein said second and third levels of current are downshifted from and less than said first level, said control circuit further including:
b) load current sense means, comprising a sense impedance in series with said inductive load, for generating a sense signal representative of the current drawn through said inductive load;
c) reference means for providing reference signals representative of said first, second and third current levels, respectively;

- ? -d) comparator means, having a sense input coupled to said sense means, a reference input coupled to said reference means, and an output coupled to said switch means, for comparing said sense signal and said reference signal and for generating a first comparator output level causing said switch means to disconnect said power supply and a second compartor output level causing said switch means to connect said power supply, said first output level being generated after the beginning of said actuation signal when initially said comparison indicates the current through said inductive load exceeds said first current level and thereafter until the end of said actuation signal when said comparison indicates the current through said inductive load exceeds said second current level, said second output level being generated when said comparison indicates the current through said inductive load is less than said third current level; and e) time delay means for delaying the downshift of said load current from said first level to the range between said second and third levels when said load current increases to said first level at a rate too fast to actuate said inductive load.

8. The current control circuit of Claim 7 wherein:
said reference means generates a first reference signal and second reference signal representative of said first and third current levels respectively; and flip-flop means, responsive to the attainment of said first current level, for modifying the sense signal such that said second current level produces a sense signal to the sense input of said comparator means equivalent to that produced by said first current level, said flip-flop means producing said downshift in current levels by causing said first comparator output level to be generated when said load current exceeds said second current level.

9. In a current control circuit enabled by a load actuation signal, comprising:
a) switch means operative to actuate an inductive load by incrasing the current thereto above a first current level and to thereafter alternatively connect and disconnect a power supply to the load to maintain load acutation with current in a range between a second current level and a third current level, each less than said first current level, b) load current sense means comprising a first sense resistor in series with said inductive load and second sense resistor connected in parallel with said first sense resistor;
c) reference means providing at least two reference voltages representing two of said first, second, and third current levels;
d) comparator means having a sense input coupled to said second sense resistor, a reference input coupled to said reference means, and an output coupled to said switch means, said comparator means adapted to genreate a first comparator output level when a sense voltage at said sense input is a greater magnitude than a reference voltage at said reference input and a second comparator output level when said sense voltage is a less magnitude than a reference voltage at said reference input; and e) flip-flop means coupled to said comparator means and to circuit means responsive to the attainment of said first current level, said flip-flop means comprising variable current source means coupled in series with said second sense resistor and operative to change the current therethrough in response to said attainment of said first current level.

- ? -

10. The current control circuit of Claim 9 wherein said circuit means responsive to the attainment of said first current level comprises one of said comparator means output and said switch means.

11. The current control circuit of Claim 8 or 9 wherein said flip-flop means is operative to generate a first flip-flop output level in response to the commencement of the load actuation signal and a second flip-flop output level in response to the attainment of said first current level.

12. The current control circuit of Claim 8 or 9 wherein said reference means comprises a feedback resistor coupling said comparator means output to said comparator means reference input and operative to generate thereat one of said two reference voltages when said comparator means generates one of said comparator output levels and the other of said two reference voltage when said comparator means generates the other of said comparator output levels.

- ? -

13. A current control circuit for controlling current from a power supply to the solenoid coil of an electro-magnetically activated armature in response to a command pulse having a beginning and an end bounding an actuating portion and a holding portion, the current in the actuating portion increasing to an actuating current level sufficient to overcome a bias causing the armature to move from a first position to a second position and the current in the holding portion decreasing to a range of holding current sufficient to maintain the armature in the second position, said current control circuit comprising:
a) power switch means coupled to the power supply and adapted to be coupled to one side of the solenoid coil, said power switch means responsive to first and second inputs thereto to alternately complete and interrupt a charging current path between the power supply and the solenoid coil;
b) reference means for generating a lower and higher reference value representing respectively a lower level and a higher level of holding current;
c) comparator means coupled to said reference means, said power switch means, and the solenoid coil for comparing a representation of the current through the solenoid coil with said lower and higher reference values and generating said first input to said power switch means when the current through said solenoid is less than said lower holding level and generating said second input when said current through the solenoid coil is greater than said higher holding level;

?-d) solenoid current decay means comprising low impedance means and high impedance means, said low impedance means having a low impedance value coupled across both sides of the solenoid coil and being enabled by the presence of the command pulse to establish a low impedance current path through the solenoid coil when the charging current path is interrupted, said low impedance means comprising silicon controlled rectifier means, and said high impedance means coupled across both sides of the solenoid coil and having an impedance value higher than said low impedance means to establish a high impedance current path through the solenoid coil;
e) silicon controlled rectifier turn off means coupled to said power switch means and responsive to the termination of the command pulse to momentarily cause said power switch means to complete said charging current path so as to rapidly turn off said silicon controlled rectifier means by diverting current therefrom; and said low and high impedance means cooperating with the inductance of the solenoid coil to establish respective slow and fast L/R decay rates for the current through the coil so that said slow L/R decay rate allows the holding current to flow through the solenoid coil prior to the end of the command pulse even though said power switch interrupts the path between said power supply and the solenoid coil and so that said fast L/R
decay allows the armature to be rapidly biased back to its first position after the end of the command pulse.

14. The current control circuit of Claim 13 wherein said silicon controlled rectifier turn off means comprises timing means generating a fixed pulse coupled to said comparator means causing said comparator means to switch from one of said first and second comparator means output levels for the duration of said fixed pulse and to immediately thereafter switch back to the other of said first and second comparator means output levels.