CA1145019A - Arrangement of interactive telephone switching processors for control of ports - Google Patents

Abstract

ABSTRACT
A telephone switching system in which a call process-or and port event processor interact to control call progress-ion and switching. The port event processor and the call processor communicate through a port storage means which stores information concerning the status of each port and its connected telephone line. The port event processing means connects to the port storage means and alters certain items of port status information in response to other items of port status information. Switching means are provided con-nected to the port means and to the port storage means to effect actual switching of intelligent signals among the var-ious port means. Supervisory signals representing telephone line conditions are transferred to the port means and the port storage means by the switching means while receiver su-pervisory signals are transferred from the port means and the port storage means. The call processing means in connected to the switching means and to the port storage means and uses information in the port storage means to control call progression. The call processing means at various times ex-changes information with the switching means to establish the paths for intelligent signals through the switching means as well as altering information in the port storage means to control the operation of the port event processing means.

Description

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BACKGROUND OF THE INVENTION
Field of the Invention:
;1 This invention relates to a community office (C.O.) switch-,''' 10 ing system in which the uppermost element of its common c,ontrol ' I
l hierarchy~is a stored program processor. More particularly, it re~
,'! ~ ' ;~ lates to the portions of such a system which are involved in the ' function of sensing or transmitting supervisory events.
Descri~tion of the Prior Art: ;
~i 15 In known prior art C.O. switching systems, the uppermost ' element of the common control hierarchy have been stored program I processors which operate in an interrupt mode.
Following is an example of what is meant by the interrupt mode in sensing or transmitting 100 millisecond wink or 100 milli-second hookflash supervisory events, the processor responds to 10 consecutive interrupts from a 10 millisecond clock, For each of .. ..
these responses, the processor must test the state of the super-¦ vision signal. Such operation is an interrupt mode results in a ! number of limitations and disadvantages as,~ollows:
' a. The processor spends considerable of its time in the ,ioverhead function of servicing the interrupts.

b. ,The stored program is complex and requi~es considerable memory space, and in turn dictates that the stored program pro-cessor be of large enough capacity to handle the more complex larger programs. This is particularly true where the stored pro-, gram is designed for modularity.

, 2 ~5~i9 ¦11 c. C~O. switching systems must be monitored for automatic I
fault detectionO A stored program processor operating in the interrupt mode is quite difficult to monitor for automatic fault detection.
One prior art approach to lessening -the effect of these lim-itations and disadvantages has been to employ a second processor as an automatic scan advice for detecting seizures and abandonments ¦of seizures. However, this approach merely allows the uppermost (in hierarchy) processor to operate with a reduced number of in-terrupts.
The other mode of operation of a stored program processor is called the "polling mode" in which the processor polls the status of an external device (such as a queueing register) to receive its next processing task. The foregoing limitations and disadvantages are not present in the case of a processor employed in a polling Illmode. The polling mode can be used only if the processing load jlpresented to the processor (particularly the maximum rate at ,,which processing tasks are received) can be "worked off" by the processor in time to obtain results within the "real time" con- j ~straints of the system.
Heretofore, there has been no known case of a C-O. switching ¦Isystem in which the uppermost element of the common control is a stored program processor which totally operates in the polling mode. The frequency with which processing tasks present them-selves to the processor depends upon both the number of lines and trunks o~ the switching system, and the busy hour call rate througj the switching system. Frior to the present invention, the quantit~
- of lines and trunks and the busy hour call rate capacity which are normal by commercial standards, have presented processing loads which have required the use of the interrupt mode.

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Accordingly, the invention provides a telephone switc.hing system for interconnecting plural telephone lines, said system comprising: a pluralit~ of port means each of which connects to a telephone line, each said pGrt means transferring, to and from its corresponding telephone line, information in the form of supervisory signals representing telephone line conditions and other signals representing intelligence, port storage means for storing a plurality of port status information items representing different condi- ~, 10tions for each said port means and its corresponding telephone line 7 port event processing means connected to said port stor-age means fox altering certain of said port status information items in said port storage means in response to other port status information items, switching means connected to each said port means and to said port storage means for selectively establishing, (i) signal paths that transfer the supervisory signals between said port storage means and each said port means thereby to control the operation of each said port means and, (ii) signal paths that transfer the other signals repxe-20senting intelligence between selected ones of said port means,and call processing means connected to (i) said switching means to control the operation of said switching means and, (ii) said port storage means for altering port status infor-mation in said port storage means in response to other port status information in accordance with a predetermined sequence of call progression steps thereby to control the operation of said port event processing means.
BRIEF DESCRIPTION OF THE DRAWING
. . . _ Figure lA is a block diagram of a community office 30 ~C.O.) switching system which embodies the present invention;

Fig. lB is an enlargement of a portion of the system of Fig. lA; 4 ~s~
Fig. 2 i5 a layout representing a port data memory ~;- field associated with each port equipment position of the system of Fig. lA;
Fig. 3 depicts the timeslot format of a time-divi-sion multiplex ~TDM) sense/control data communication network in the system of Fig. lA;
Fig. 4 is a diagrammatic illustrating the sequence of presence of binary data channels in the timeslot positions of Fig. 3;
Fig. 5 is a block diagram of circuit elements of ; the system of Fig. 1~ which comprise the TDM sense/control data communication ,'' , , -4a-,,., ~

1~L45'`~19 1 .
I

network which provides the timeslot format of Fig~ ~;
Fig. 6 is a detailed block diagram of certain components of the TDM sense/control data communication network of Fig. 5;
Fig. 7 is another more detailed block diagram of certain ~¦components of the TDM communication network of Fig. 5;
Figso 8A, 8B, and 8C together comprise a wave diagram and ¦timing diagram depicting certain timing relationships involved in the operations of the TDM sense/control da-ta communication subsystem of Fig. 5, and also depicting certain timing relation-~ships involved in the operation of the parallel-serial binary data signal converter circuit of Fig, 10;
Fig. 9 is a timing diagram of certain operations of a time-slot interchange (TSI) matrix switch network of Fig. 12;~
.
Fig. 10 is a detailed block diagram of a portion of a par-allel-serial binary data signal converter circuit (component of the system of Fig. lA);
I Fig. 11 is a detailed block diagram of another portion of the parallel~serial converter circuit;
Fig. 12 is a block diagram of a certain portion of the TSI
circuit of Fig. 55 (the TSI circuit is a component of the TSI
matrix switch network, and the portion thereof in Fig. 12 esp-ecially shows the stripping out of sense data and the insertion o~ control data from and to the port group highway TDM frame;
Fig. 13 is a timing diagram depicting certain operations of the TSI matrix switch network;
Figs. 14A, 14B, and 14C together comprise a wave diagram and timing diagram depicting certain timing relationships involved in the operations of the TDM sense/control data communication network of E'ig. 5, and also depicting certain timing relation-ships involved in the operation of the parallel-serial binary data signal converter circuit of Figs. 10 and 11;

1~L45~L9 Fig. 15 is a detailed block diagram of certain components of the TDM sense/control data communication network of Fig. 5;
j Fig. 16 is a table of functions performed by the channels liof the TDM sense/control data communication network of Fig~ 5, ¦¦broken down by the various types of equip~ent present in a port equipment position;
Fig. 17 is a flow chart of certain operations which implement the updating of certain bit areas and bit locations of the port data field of Fig. 2;
Fig. 18 is a diagrammatic (similar to, but not a true block diagram) of a combinatorial logic organization of a port event ; processor component of the system of Fig. lA;
Fig. 19 is a detailed block diagram of a timing and control circuit (component of the system of Fig. lA);
Figs. 20A, 20B, 20C, 20D~ and 20~ are tables depicting the ~formats of the command and event codes ~hich become recorded in the port data field of Fig. 3, and which are involved in the oper-ation of the combinatorial logic organization of Fig. 18, when port event processor is functioning to sense supervisory e~ents;
Fig. 21 is a wave diagram depicting timing relationships during the detection of seizure under control of the combinatorial logic organization of Fig. 189 Fig. 22 is a wave diagram depicting timing relationships ¦during the recognition of wink-type supervision signals under ¦control of the combinatorial logic organization of Fig. 18;
Fig. 23 is a wave diagram depicting timing relationships during the sensing of the end of a stop dial-type of supervision signal under control of the combinatorial logic organization of Fig. 18;
Fig. 24 is a wave diagram depicting timing relationships during the sensing of the end of a delay dial supervisory signal I under control of the combinatorial logic organization of Fig. 18;
Figs. 25A, 25B, 25C9 25D and 25E are tables depicting the ,formats of command and evant codes (which become rècorded in the ! port da~a field of Figg 3) and which are involved in the operation ¦¦of the ~ombinatorial logic organization of Fig~ 18, when t~e port l event processor transmits supervisory events;
Fig. 26 is a wave diagram depicting timing relationships ' during the transmission of wink-off type supervisory signalling ;under control of the combinatorial logic organization of Fig. 18;
Fig. 27 is a wave diagram depicting timing relationships during the transmission of wink type supervisory events under con-trol of the combinatorial logic organization of Fig. 18;
, .
Fig. 28 is a wave diagram depicting the timing relationships during the transmission of delay dial type supervisory events under control of the combinatorial logic organization of Fig. 18;
Figs. 29A9 29B, 29C, ~nd 29D are tables depicting the formats of command codes and event codes (which become recorded in the port data field of Fig. 3) and which are involved in -the operation o~ the combinatorial logic organization of Fig. 18, when the port event processor operates in its "ring line" mode of operation;
Figs. 30A9 30B, ~OC, 30D and 30E are tables depicting the formats of command codes and event codes (which become recorded in the port data field of Fig. 3) which are involved in the loPeration of the combinatorial logic organization of Fig. 18, ¦when t~ port event processor operates in its "send digits" ~ode ¦of operation;
Fig. 31 is a wave diagram depicting timing relationships during the transmission of dial pulse signals under control of the combinatorial logic organization of Fig. 18;
Fig. 32 is a wave diagram depicting timing relationships during the transmission of tome dialing signals under control of a5'~9 1l ~
Ij ~lthe combinatorial logic organization of Fig. 18;
Figs. 3~A, 33B, 33Cs and 33D are tables depicti~g the formats ;of command codes and event codes (which become recorded in the ¦ port data field of Fig. 3) and which are involved in the operation ¦¦of the combinatorial logic organization of Fig. 18, when the port levent processor operates in its "receive digits" mode of operation;
Fig. 34 is a flow chart of a sequence of operation occurring within the combinatorial logic organization of Fig. 18, when the port event processor is in its "receive digits" mode of operation;
Fig. 35 is a detailed block diagram of a timing and control circuit (component of the system of Fig. l);
Fig. 36 is a diagrammatic depicting the hierarchical relation-~ship of various tiers and clusters of the stored program modules, which are part of the call control processor, whose functions include call progression, control marking of matrix switch paths5 and translations;
Fig. 37 is an electrical schematic of a line interface ; ~
circuit (component of the system of Fig. l);
Fig. 38 is a table showing the various states of operation of a line interface circuit of Fig. 37, Fig. l);
Fig. 39 is an electrical schematic of an ~&M trunk interface circuit;
Fig. 40 is a table of the states of operation of the ~M
¦ interface circuit of Fig. 39;
Fig. 41 is a block diagram of a COD~C/filter circuit assembly (component of the system of Fig. lA);
Fig. 42 is a block diagram of a COD~C/filter unit of the ¦clrcuit assemblyof Fig. 41;
I Fig. 43 is partially a block diagram and partially a diagram-jmatic of the CODEC portion of ths COD~C/filter unit of Fig. 42;

Fig. 44 is a family of wave forms and timing charts depicting ~ ` " ~
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¦the operation of the single CODEC/filter unit of Fig. 42;
i~ Fig. 45 is a detailed block diagram of the single COD~C/filter ¦¦unit of Figo 42, showing a certain component thereof in greater detail;
li Fig. 46 is a block diagram of voice data multiplexer/demulti-¦jplexer (component of the system of Fig. lA);
! Figo 47 is a detailed block diagram of a voice data multi-~¦plexer/demultiplexer (component of the system of Fig. lA);
I Fig. 48 is a block diagram of a sense/control data multiplex-~er/demultiplexer (component of the system of Fig. lA);
, Fig. 49 is partially a block diagram and partially an elect-l~rical schema-tic of a port group common utility circuit (component of the system of Fig. lA);
Fig. 50 is a table providing information concerning the re-`llays of the circuit of Fig. 49, and concerning the associated data channels of the TDM sense/control communication network (of ~Fig. 5);
~ Fig. 51 is a block diagram of the high level ringing signal ',subsystem of the system of Fig. lA;
Figs. 52 and 53 together comprise an electrical schematic of ¦
,the ringing interrupter circuit in the subsystem of Fig. 51;
Fig. 53A is a family of signal waves depicting the operation ¦lof the ringing interrupter circuit of Figs. 52 and 53;
Fig. 54 is an electrical schematic of the ringing monitor circuit of the subsystem of Fig. 51;
Fig. 55 is a block diagram of a single timeslot interchange (TSI) circuit of the TSI matrix switch network (component of the system of Fig. lA);
Fig. 56 is a diagrammatic depicting the TDM timeslot format of the cross-office high~ys which are p~rt of the TSI matrix switch networ of the system oi Fig. lA;

i Fig. 57 is a detailed block diagram of the TSI circuit o~
Fig. 55;
Fig. 57A is a detailed block diagram of a portion of the TSI
circuit of Fig. 57 (especially the portion which provides the ¦mechanism for stripping out binary sense data and inserting broad-¦cast tone data in the emptied timeslots);
Fig. 58 is a detailed block diagram of a portion of the TSI
circuit of Figo 55 (especially showing the portion which provides ,the mechanism for inserting binary control data in the output timeslot frames of the TSI circuit);
Fig. 59 is a detailed block diagram of another portion of - the TSI circuit of Fig~ 55 (especially showing the portion which provides control and mapping of matrix switch paths);
, ~Fig. 60 is a table showing binary control codes involved in the operation of a TSI circuit of Fig. 57;
Fig~ 61 is another detailed block diagram of the TSI circuit of Fig. 55;
Fig~ 62 is still another detailed block diagram of the TSI
circuit of Fig. 55;
Fig. 63 is a block diagram of a precise tone generator circuit (component of the system of Fig. lA);
Fig. 64 is a detailed block diagram of a detail of Fig. 63;
Fig. 65 is a graph depicting the operation of the precise tone generator circuit of Fig. 63;
Fig. 66 is a family of wave forms associated with the oper- ¦
ation of the precise tone generator circuit of Fig. 63;
Fig. 67 is a detailed block diagram of a tone buffer circuit (component of -the system of Fig. lA);
Fig. 68 is another block diagram of the tone buffer circuit of Fig. 67;
Fig. 69 is a wave diagram depicting certain timing relation-ships involved in the operation of the tone buffer circuit of Fig.
67; -10-~5~9 , ! Fig. 70 is another family of wave forms depicting certain ,Itiming relationships involved in the operation of the tone buf~er ~,circuit of Fig. 67;
~ Fig. 71 is a block diagram showing input and output connec-¦'tions to and ~rom the timing and control circuit of Fig. l9;
Fig. 72 is a timing diagram depicting the basic cycle of ¦access to a port data circuit (component of the system of Fig. lA), which cycle is generated by the timing and control circuit of Fig.
, 19;
Fig. 73 is a family of wave forms depicting certain timing relationships involved in the operation of the timing and control circuit of Fig. l9;
Fig. 74 is a block diagram of a parallel-serial converter control circuit (component of the system of Fig. lA);
~ Fig. 75 is a detailed block diagram of the parallel~serial converter con-trol circuit of Fig. 74;
Figs. 76 and 78 together comprise an electrical schematic of a portion of the parallel-serial converter control circuit of Figo 74;
Fig. 77 is an electrical schema-tic of a portion o~ the !l .
parallel-serial converter control circuit of Fig. 74;
~ There are no Fig. 79 or 80);
¦¦ Fig. 81 is an electrical schematic of another portion of the parallel-serial converter control circuit of Fig. 74;
Fig. 82 contains a family of wave forms depicting certain timing relationships involved in the operation of the parallel-serial converter control circuit of Fig. 74;
Fig. 83 contains a family of wave forms depicting timing relationships involved in the operation o~ the parallel-serial binary data signal converter circuit of Figs, lO and ll;
Fig~ 84 is a block diagram of the port data store (which is il :
~ 53~

¦ a memory organization that provides the port data fields o~ Fig.

2);
Fig. 85 is a detailed block diagram of the port data store ~of Fig. 84;
Fig. 86 is a detailed block diagram of a "common logic"
functional unit, which is a component of the combinatorial logic organization of Fig. 18;
Figo 87 is a table presenting the formats of code of certain of the bit areas of a port data field (of Fig~ 3) which are gen-erated by the common logic functional unit of Fig. 86 in response to the detection of various events at the port by the port event process in various port command code states;
Fig. 88 is a block diagram of a portion of a "sense super-visory event/transmit supervisory event functional" logic unit, ;~which is a component of the combinatGrial logic organization of Fig. 18;
Figs. 89~ 90 and 91 together comprise a block diagram of another portion of the "sense supervisory event/transmit super-visory event functional logic" unit which is a component of the combinatorial logic organization of Fig. 18;
Fig. 92 is a block diagram of a portion of a "ring line~' functional unit, which is a component of the combinatorial logic ¦organization of Fig. 18;
Fig. 93 is a block diagram of another portion of the ring line ~unctional unit, which is a component of the combinatorial logic organization of Fig. 18;
Fig. 94 is a block diagram of a "send digits" functional ¦logic unit, which is a component of the combinatorial logic organ-ization of Fig. 18;
Fig. 95 is a detailed block diagram of a '7receive digits"
functional logic unit, which is a component of the combinatorial logic organization of Fig. 18;

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IFig. 96 is a detailed block diagram of a ~receive digits/send digits" functional logic unit, which is a component of the combin-iatorial logic organization of Fig. 18;
Fig. 97 is a block diagram showing inputs and outputs of a ¦¦call control processor interface controller (component of the l~system of Fig. lA);
1~ Fig. 98 is another broad block diagram of the call control l'processor interfaces controller of Fig. 97;
Fig. 99 is a detailed block diagram of the call control processor interfaces controller of Fig. 97;
Fig. 100 is a detailed block diagram of a portion of the call control processor interfaces controller of Fig. 97;
Fig. 101 is a diagrammatic depicting a format of an address , code associated with 'che operation of the call control processor interfaces controller of Fig. 97;
Fig. 102 is a table depicting another format of an address code associated wlth the operation of the call control processor ,interfaces controller;
I Fig. 103 is a table depicting the format of addresses of certain registers in the call control processor interfaces con-troller of Fig. 97;
Fig. 104 is a diagrammatic depicting the format of data which is written into certain registers of the call control processor linterfaces controller of Fig. 97;
¦ Fig. 105 is a diagrammatic depicting the format o~ data which I
may be read from certain registers in the call control processor ¦interfaces controller of Fig. 97;
¦ Fig. 106 is a table depicting relationships of components of the call control processor interfaces controller (of Fig. 97) in the presence of certain command signals related to controlling the TSI matrix switch network;
Fig. 107 is a detailed block diagram of another portion of 5`~9 !Ithe call control processor interfaces controller of Fig. 97;
I Figs.108 through 122 are detailed flow charts of an "exec-utive cluster" of the stored program of the call control processor, Figs. 113 and 114 are flow charts of an "originations and j¦dial tone cluster" of stored program modules from the stored pro-¦!gram of the call control processor;
Figs. 115 through 118 are detailed flow charts of certain ~modules of a "receiving digits cluster of the stored program of iIthe call control ~rocessor;
Figs~ 119 through 123 are detailed flow charts of certain mcdules of a "data base utilities cluster" of the stored program of the call control processor;
Fig. 124 is a diagrammatic depicting the layout of a data -table of the system data base of the stored program of the call jcon-trol processor;
i Fig. 125 is a flow chart of a module of the "equipment connect subroutines cluster" of the storecL program of the call control pro-cessor;
Figs. 126 through 128 are flow charts o~ certain modules of the "network utilities" cluster of the stored program of the call control processor; Z
Fig. 129 is a module o~ the "translations subroutines cluster"
ilof the stored program of the call control processor;
j', Figs. 130 and 131 are flow charts of certain modules employed ¦¦in processing tables of the systems data base of the call control ¦ ¦processor; ZZ
! Fig. 132 (located on the same sheet with Fig. 127) is a ¦Idetailed flow chart of a module of the "translation subroutines cluster" of the stored program of the call control processor.
j Fig. 1~3 is a diagrammatic depicting the layout of a table of ¦!the system data base of the stored program of the call control pro cessor;

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Fig. 134 is a flow chart of a module of the "translation sub-Iroutines cluster" of the stored program of the call control pro-¦cessor;
Figs. 135 through 137 are flow charts of certain modules of ¦the "data base u-tilities cluster1' of the stored program of the ¦call control processor;
¦ Figs. 138 through 141 are diagrammatics depicting the memory layout of certain data tables of the system da-ta base of the stored program of t~.ecall control processor;
Fig. 142 is a flow chart of a module in the "translations ~subroutine cluster" of the stored pr~gram of the call control ,processor;
Figs. 143 and 144 are flow charts of certain modules in the l,"equipment connect subroutines cluster" of the stored program of ¦~the call control processor;
¦~ Fig. 145 is a flow chart of a module in the "line-to-line cluster" of the stored program of the call control processor;
Fig. 146 is a module of the "equipment release subroutines ~¦cluster" of the stored program o~ the call control processor;
Figs. 147 through 150 are flow charts of modules in the "network utilities clus-ter" of the stored program of the call l,control processor;
¦, Figs. 151 and 152 are flow charts of modules in the "equipment release subroutines cluster" of the stored program of the call con-trol processor;
Fig. 153 is a module in the "network utilities cluster" of the~
stored program of the call control processor;
Figs. 154, 155, 156, 156A, 157, 1589 159, 160, 161 and 162 are flow charts of modules of the "port data store utilities cluster" of the stored program of the call control processor;
Fig. 163 is a flow chart of a module in the "equipment connect subroutines cluster" of the stored program of the call control processor;

1145~19 ¦ E'ig. 164 is a flow chart of a certain module in the "receive t ,Idigits cluster" of the stored program of the call control process-jjor;
¦I Fig. 165 is a flow chart of a certain module i~ an "incoming Itrunk cluster" of the stored program of the call control process-or;
Fig. 166 is a diagrammatic for use in explaining a system OI
block diagram-like and flow chart-like diagrams for describing the progression of a call;
Figs. 166 through 175 are diagrammatics which employ the ,form of diagrams e}~plained in connection with Fig. 166 to illus-trate several of the principle call progressions occurring in the operation of the system of Fig. 1A;
Fig. 176 is a flow chart of a certain sequence performed by 'the logic unit of Fig. 86;
Figo I77 is an electrical schematic of a portion of the logic unit OI Fig. ~6;
Fig. 178 is a detailed flow chart of a certain sequence Iperformed by the logic unit of Fig. 86;
Fig. 179 is an electrical schematic of a portion of Fig. 86;
Fig. 180 is a detailed flow chart of a certain logic sequence ~erformed by the logic unit of Fig. 86;
Figs. 181 and 182 are electrical schematics of certain portion o~ the logic unit of Fig. 86;
Figs. 183-185 are flow charts of a certain logical sequence performed by the logic unit of Fig. 86;
Figs, 186 and 187 are electrical schematics of a portion of : the logic unit of Fig. 86;
Fil3. 18~ is a detailed ilow chart OI a certain logical sequence performed by the logic unit oî Fig. 86;

~L~.45~h9 ¦i Figs. 189-193 are electrical schematics of the logic unit of ~ig. 86;
Fig. 194 is a state diagram representing the various combina-torial logic States of the logic unit of Fig. 86;
Fig. 195 is a flow chart of a certain logical-sequence perform-ed by the logic unit of Figs. 88-91;
¦I Figs. 196-200 are electrical schematics of portions of the ~¦logic unit of Figs. 88-91;
Fig. 201 is a flow chart of a certain logical sequence per-formed by the logic unit of Figs. 88-91;
Fig. 202 is an electrical schematic of a portion of the logic iunits of Figs. 88-91;
Fig. 203 is a flow chart of a logical sequence performed by ~the logic unit of Figs. 88-91;
; Fig. 204 is a state transition diagram depicting the various ¦!combinatorial logic states involved in the performance of SSE
IIcommands by the logic unit of Figs. 88-91;
Fig. 205 iS a flow chart of a certain logical sequence per-formed by the logic unit of Figs. 88-91;
Fig. 206 is a flow chart of a certain logical sequence perform-ed by the logic unit of Figs. 88-91;
Figo 207 is an electrical schematic of a portion of a logic unit of FigS. 88-91;
Fig. 208 is a flow chart of a certain logical sequence per-formed by the logic unit of Figs. 88-91;
Fig. 209 is a state transition diagram depictlng various combinatorial logic states involved in the perform~nce of TSE

commands by the logic unit of Figs. 88-91;
Fig. 210 is a flow chart of the operation of a Timer 1 com-ponent of the l.ogic unit of Figs. 88-91;

~16A-Fig. 211 is an electrical schematic showing a portion of the logic unit of Figs. 88-91;
Figs. 212 and 213 are flow charts of certain logical sequences performed by the logic unit of Fig. 94;
Figso 214-219 are electrical schematics of poI~tions of the ,logic unit of Fig. 94;
i Fig. 220 is a flow chart of a certain logical sequence per-formed by the logic unit of Fig~ 94;
Fig. 221 is an electrical schematic of a portion of the logic unit of Fig. 94;
Fig. 222 is a flow chart of a certain logical sequence per-formed by the logic unit of Fig. 94;
Fig. 223 is an electrical schematic of a portion of the logic unit of Fig. 94;
Figs. 224-226 are flow charts of certain logical sequences performed by the logic unit of Fig. 94;
Figs. 227 and 228 are electrical schematics of portions of the logic unit of Fig. 94;
Fig. 229 is a state transition diagram depicting the various combinatorial logic states of logic unit 94;
Fig. 230 is a flow chart of a certain logical sequence per-formed by the logic unit of Fig. 95;
Fig. 231 is an electrical schematic of a portion of the logic junit of Fig. 95;
Figs. 232-234 are electrical schematics of portions of the unit of Fig, 95;
Figs. 235-237 are flow charts of certain logical sequences '~erformed by the logic unit of Fig. 95;
i I Fig. 238 is an electrical schematic of a portion of the logic unit of Fig. 95;

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Fig. 239 is an electrical schematic of a certain portion of the logic : unit of Fig. 96;
Fig. 24Q is a flow chart of a certain logical sequence performed by the logic u~it of Fig. 95;
Fig. 241 is an electrical schematic of a portion of the logic unit of :
Fig. 95;
Figs. 242 and 243 are flow charts of certain logical sequences per-formed by the logic unit of Fig. 95;
Fig. 244 is an electrical schematic of a portion of the logic unit of Fig. 96;
Figs. 245 and 246 are flow charts of certain logical sequences of the.
logic unit of Fig. 95;
Figs. 247-250 are electrical schematics of certain portions of the logic unit of Fig. 95;
Figs. 251-255 are electrical schematics of certain portions of the logic unit of Fig. 96;
Fig. 256 is a state transition diagram depicting the various combina-torial log;c st`ates involved ;n the operat;on of the logic unit of Fig. 9S;

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Referring now to Fig. 1A, the major subdivisions of an end ,office switching system 400 comprise a plurality of port group ¦lunits 402; a timeslot interchange (TSI) matrix switCh network 403;
~ia port data storage network 405; a port event (PEP) processor 406;
sense/control time division multiplex ~TDM) network 407, and a call control processor (CCP) subsystem 408. TSI matrix network ~403 establishes the line-to-line connec-tions, the -trunk-line connections, and other equipment to line/trunk connections which constitute the basic function of end office switching system 4000 ~As is apparent from the block diagram of Fig. 1A, overlap exists between these subdivisions~ This is because many of the units ;represented by individual blocks are circuit assembli2s of circuits that perform a number of functions. The aforementioned major sub-divisions are defined along functional lines, and therefore the overlap exists due to the basic block diagram unitS performing - l~functions associated with more than one of the functionally ,idefined subdivisions.

B . PORT GROUP UNITS ( 402 ) ; Referring now to Fig. 1B, each port group unit 402 contains the various circuitry which provides the analog-digital trans-formation and the multiplexing-demultiplexing operation to the jconverSions between the analog signals of thirty ports and a single serial TDM stream of binary data which connects unit 402 and TSI
network 403. The grouping of the signals of all the port,s into a Isingle stream of bits facilities: (i) the Communication of Voice ~data between the ports and network 403; and (ii) the communication of sense/con-trol data between the portS and other subdivisions of system 400.

1, i~

The sense data which is communicated in the direction from 'the port positions to other subdivisions of system 400 includes ~data representing the status of incoming line or trunk supervision I ,jsignals, or data representing incoming dialing signals, or signals jlrepresenting the state of relays in circuits installed in the port ¦¦equipment positions. Data of this type is collectively referred ~!to as "sense" dataO
i~
The control data which is communicated in the direction toward ~the ports from various subdivisions of system 400 includes low I level signal intelligence for generating outgoing supervision si~nals on trunks, low level signal intelligence for generating outgoing dialing signals along trunks, and signals for controlling ~' relays in the circuits installed in the port positions. Data of I this type is collectively referred to as "control" data.
' me functions and circuits of port group unit 402 which l~involve sense and control will also be discussed in connection with 'the description of the sense/control data TDM network 407 in sub-division N, following.
, C. PORT EQUIPMENT POSITIONS
Referring now to Fig. 1B, each port group unit 402 has thirty (30) port equipment positions and two (2) virtual port positions.
e port equipment positions are designated 00 through 29. The block diagram of Fig. 1B shows that there are five groups of six (6) port positions each; namely, 00 through 05, 06 through 11, 12 through 17, 18 through 23, and 24 through 29. (The reason that the port positions have been illustrated in such groupings of six (6) is that each group ~eeds a common PCM CODEC/filter 3500, as will be discussed in subdivision E, following.) The 30th and ~1st ¦port equipment positions are virtual port positions. They do not exist as a physical equipment position into which a circuit may be l~installed. Instead they are a virtual position permitting TDM
~streams of binary data which have timeslot designations other-than-voice data timeslots~ These extra timeslots are used for the 'transmission of sense and control data from and to port group unit ¦¦common circuitry.
The thirty port equipment positions 00...29 are universal.
That is to say, any of the various types of port equipment used with system 400 may be installed in each port equipment position.
To illustrate this universalityg the block diagram of Fig. 1B
shows five different types of circuits installed in the various ~groups of positions. Positions 00...05 contain a single party line interface circuit 2000. Positions 06...11 contain a multi-party line interface circuit 2000'. Circuit 2000' is shown as a ~ broken line box indicating that it is optional. Circuits 2000 and 1~ ,2000' are connected with the outside telephone facilities through a conventional main distribution frame 3400.
Positions 12...17 contain multifrequency signal detector l~interfaces ~2009 also optional. Interfaces 3200 serve to either ,interface a dual tone multiple frequency (DTMF) detector through TSI matrix switch network 403, or interface a toll multifrequency (TMF) detector with a toll port via the TSI matrix switch network ,403. This is shown by the connection of interfaces 3200 to blocks 3230 which diagramatically represent either a DTMF detector or a TMF detector.
Positions 18...23 contain toll multifrequency senders 3250, also optional. Senders 3250 receive tones from a tone plant inter-face 3270, which in turn receives the tones from a tone buffer ¦25100 (introduced later in subdivision K). Tone buffer 25100 is the output of the tone plant for system 400.
Positions 24...29 contain E~M trunk interface circuits 3000, which connect to the interoffice trunk facility through main dis-I' tribution ~rame ~400.
It will be appreciated that the variety of inter~ace or ,service circuits shown as installed in port group unit 402-00 is a hypothetical situation which has been depicted in order to illustrate the universality of the port positions. In actual practice, the individual port group units are likely to contain a lsingle type of interface or service circuitO

.: ' .

; Do INTERFACE_CIRCUITS/SERVICE CIRCUITS
Each line interface circuit 2000 is a controlled interface for conversion between the two-way analog signal on the subscriber , I side of the circuit and the 2 one-way (4-wire) signal paths-on the side connected to TSI matrix switch 403. It also provides control led conversions between metallic path circuit conditions (high level signal conditions in the subscriber line) and the low level lbinary signal system of sense/control data TDM network 407. The signals of the latter are strobed onto and o~f of sense and control ,;buses 402"' via latches within circuit 2000.
Each multiple party line interface circuit 2000' is sub-stantially the same as a single party line interface, except that ,a muItiple frequency ringing bus having the various parties ring-ing frequencies thereon at particular time phases provides the ringing signal. The ringing relay is then selectively controlled jto operate during the phase which corresponds -to a party's ringing llfrequency.
¦¦ E&M trunk inter~ace circuit 3000 provides a controlled inter- i lface between system 400 and an interoffice trunk. It provides the analog 2-to-4 wire conversion circuitry and the necessary signal-ling interfaces for conversions between metallic path circuit conditions (high level signal conditions in the lines of the trunk facility), and the low level binary signal system of sense/control ~ 5~

data TDM network 407.
, Each MFSD interface circuit 3200 is an interface circuit to a llservice circuit. Circuit 3200 is itself universal in that it operates with either a toll multifrequency (TMF) detector or a dual ¦tone multifrequency (DTMF) detector which provides the digital ¦outputs for two-out-of-six and two-out-of-seven, respectively, ¦tone signal detections. The incoming MF tones are switched through ITSI network 403 to MFSD interface circuit 3200 where they appear las an analog tone. One detector is connected to each circuit ~200.
The TMF or DI~ tones present at the input to a detector enable the corresponding decoded outputs to be active. MFSD interface Icircuit 3200 interfaces the outputs of the detector with sense/
control data DTM network 407.
Toll multifrequency sender 3250 is a service circuit which gates tone pulses to the PCM CODEC circuitry for transfe~ through TSI network 403 to a toll MF port. Binary control signals from ~Isense/control data TDM network 403 select two tones out of six ¦jcoming from tone plant interface 3270 and gate these two tones through a summing network to the PCM CODEC/filter circuit 3500-3.
¦ Tone plant interface 3270 serves as a receiver and buffer between tone buffer circuit 25100 and TMF sender 3250.

I
E. PCM CODEC_FILTERS (3500) A set of five PCM CODEC/filter circuit assemblies 3500 provide the analog/digital conversions ~etween the line and ~runk inter-~ace circuits, service circuits or service circuit in-terfaces and the digital stream form of signals employed in transmission to and from the TSI matrix switch network 403. Also voice band pass filtering is performed upon the analog signal before coding into the digital stream, and a filtering to remove high frequencies performed upon the regenerated analog signal before it is received ¦,at the port circuit.
Each circuit assembly 3500 operates in connection with the ,~three successive pairs of port circuits, providing three code/
decode operations associated with respective successive pairs of ¦~orts. Thus, the circuit assembly ~500 connected to port position ¦inumber 00-05 provides three code/decode operations connected with ¦IPort position numbers 00 and 01, 02 and 03, and 04 and 05, respectively. Thus, for the thirty port positions, the set of ,five circuit assemblies 3500 provide fi teen digital streams in 'the direction of network 403. Conversely, the five circuit '~assemblies 3500 operate upon fifteen digital streams received from network 403 to provide thirty analog inputs to the port circuits.
~Turning now to the details of the conversion of the analog '~signal to a digital stream, each operation affecting two successive `ports samples quantizes the analog signal inputs by the conven-;tional successive approximation mode. This produces an 8 bit serial binary word representing the value of a sample. The serial '~'value words from each of the successive pairs of ports are format-~'~ed into a single output frame consisting of two s~rial PCM output bits in tandem. The sampling is done at the 8 KHz rate conven-tional for telephony pulse code modulations. Two sample words are llprovided within the 125 microsecond sample period. Accordingly, '~Ijthe data rate of the output is 128 KHz. (Since 16 bits must be transmitted in the 125 microsecond period.) The decoding operation for regenerating an analog signal from the digital stream is essentially the converse of the coding operation.

F. VOICE DATA MUX/DMUX (16000) A voice data multiplexer/demultiplexer circuit 16000 performs ¦
transformations between the voice data format at the digital sides I

S'`l9 ;of the CODEC circuit assemblies 3500, and the voice data format in the port group highway (PGH) frame. As previously described, the format in the CODEC ~rame consists of two successive 8 bit words llrepresenting PCM words from a successive pair of ports in a 125 jmicrosecond frame. The PGH frame consists of thirty-two O.488 ¦microsecond timeslots in a 15.62 microsecond frame, with the voice data from the thirty ports assigned to timeslot 00-29~ (As will be later discussed, timeslots 30 and 31 provide binary sense and control channels). MUX/DMUX provides the 16:1 concentration factor~
to yield the thirty-two timeslots and the reformating to cause the transformation between the formats of digital streams. The specific bits of the PCM words of the series of ports 00-29 are carried in timeslots 00-29 of a PGH frame. A-t this point, time-slots 30 and 31 do exist as though virtual port positions 30 and i31 existed. The concentration ratio and the reformating are per-~; 'formed by random access memory circuitry.
., G. ~ ATA MUX/DMUX (18000~
A sense/control data multiplexer/demul-tiplexer circuit 18000 provides the other portion of the MUX/DMUX operation by which grouping of the individual port circuits signals to a port group highway is effected. The partial MUX/DMUX performed by circuit 18000 involves the mergence and separation of sense and control data into and from the voice data. Binary sense data is strobed from the thirty ports via the sense buses and control buses 402 "' , and separated into two fast sense channels SF0 and SF1 which are carried by timeslot 30 of the PGH frame, and into slow sense bits SS0-SS7 which are carried by the 31st timeslot of the PGH frame.
me fast control channels CF0 and CF1 (carried by TS 30) and the slow control channels CS0-CS7 (via TS 30) are converted into signals on the four control buses of sense and control buses 402" '~

1145~319 ilTS 30 and 31 and the sense and control buses are time shared in ~obtaining these ten binary sense channels and ten binary control channels. Circuit 18000 generates the port strobes that read the supervisory sense data from the port circuits, or clock the llsupervisory control data into the port circuits.

,H. PORT GROUP COMMON UTILITY CIRCUIT
Port group common utility circuit 20000 comprises a circuit assembly which provides the following functions which are common to the port group. It provides interconnections of the line ~; interface circuits to the single and multifrequency ringing buses.
Also, the interconnections between line and trunk interface circuits and test access circuits are provided. Included is an arrangement of relays for selectively interconnecting one of several test access buses to the test access connections to the interface circuit. This relay arrangement also connects a receiver off-hook (ROH) signal generator to the circuits using the same connection to the por-t inter~ace circuits as used for the test access buses. A transfer path (including a receiver driver) for the binary serial voice data and control data in the port group highway (PGH) format is provided ~rom the associated ! TSI circuit 24000 to sense/control data multiplexer/demultiplexer l~circuit 16000.
i, i I. RINGING GENERATORS AND THE LIKE
A small group of circuits is associated with the port group units 402 in order to provide the high level ringing signals and the like. These consist of a ringing generator 21000, an inter- !
rupter-serializer 21100, and a receiver off-hook (ROH) generator 21200.
A conventional ringing generator 21000 provides a normal 4_ i~ 9 4 frequency series of ringing signals.
~ inging monitor and serializer 21100 provides the appropriate 1~ interrupted ringing for single frequency, called-party ringing and ¦Iphasing for 4-frequency called-party ringing. The output for single ~requency ringing produces output cadences consisting of two 1.28-second periods of ringing alternating with two 1.79-second Il periods of silence and a 6.144-second cycle. me output in i, connection with 4-frequency ringing produces four outputs with the "
same cadence, but shifted in phase with respect to each other.
Each of these 4~frequency outputs comprises four 1.28-second periods of ringing alternating with four 0~25-second periods of silence in a 6.144~second cycle~ The in-terrupter is driven by an output of port event processor (PEP) 406.
Receiver off-hook (ROH) tone generator 21200 produces a distinctive tone signal, designed to get the attention of a sub-scriber who has left a receiver off-hook.

J. TSI MATRIX SWITCH NETWORK (403) 10 Structure And Operation Of Buffer 24002 And Buffer Unit 2400~
~ !
Timeslot interchange (TSI) matrix switch network 403 is a TDM network which provides for the switching of PCM voice or tone, data between selected pairs of port equipment positions. It com- ¦
prises eight TSI circuits 24000-0...27000-70 (Only three of these are shown in the 3-dimensional drawing of network 403 in Fig. 1B~), Each TSI circuit 24000 receives bit streams from eight port group ¦
units 402 via their respective transmit port group highways (PGHs) 402' and transmits a stream of binary data signals back to the eight TSI circuits via their respective receive PGHs 4021'. The PGHs have a 2.048 MHz bil; rate so that each timeslot i5 0.488 microseconds in duration. Each 32 bit frame has a duration of .45~
l!
I
15.62 microseconds~ The frame rate is 64 KHz. Each port group 1l unit 402 contains 30 ports, thus a TSI circuit can service 240 ! port equipment positions, and the eight TSI circuits of network 1 403 can service 1920 ports.
I Each TSI circuit 24000 has a transmit cross-office highway ¦, (XOH) that is used to make a connection to any of the port equip-ment positions associated with any of the TSI circuits. The XOH
i has a serial TDM frame containing 128 timeslots with an 8.192 MHz bit rate so that each timeslot is 122 nanoseconds in duration.
- Each 128 bit frame has a duration of 15.62 microseconds. The frame rate is 64 KHz.
The binary data streams from eight port group units 402 enter a single TSI circuit (e.g.) the data streams of PGHs 402-00'...402-07" enter TSI circuit 24000-0). These data streams are received by a multiplexer and sense data/tone data exchange buffer 24002 and a receive buffer unit 24003 which are connected serially together. Multiplexer and exchange buf~er 24002 and li buf~er unit 24003 together operate to multiplex select ~rames of the eight data streams onto a single line.
Call progrèssion (CCP) subsystem 408 determines what TSI
circuit 24000 and what port equipment position of that circuit is !
, the calling terminus of a duplex connection through the matrix switch port and what TSI circuit 24000 and port equipment positioni thereof is the call terminus of the duplex connection. Subsystem ¦
l408 then assigns one timeslot on the XOH eminating from the TSI
¦circuit 24000 of the calling terminus and one timeslot of the XOH !
of the TSI circuit 24000 of the called terminus to provide a path ;to carry the voice data in each direction.
Within TSI circuit 24000 the binary data streams from the eight port group units first pass through multiplexer and buffer 24002. The operation of multiplexer and buffer 24002 in strip out ¦Isense binary data and in inserting PCM tone data is described in ¦ the following Section 2~ Details of the construction and ¦¦operation o~ multiplexer and buffer 24002 are described in the subsequent divisions of this specification. The data streams then enter send buffer unit 24003. me data bits of the selected PGH frames are buffered until the correct timeslot on the associated transmit XOH is being transmitted. Stated another way, send buffer unit 24003 stores sense binary data bits during the interval of time conversion between PGH timeslots and the selected XOH timeslot.
The timeslot which is the one into which the stored binary f data bit is gated is the timeslot which CCP subsystem 408 has set up to transmit the voice or tone data to the particular TSI
circuit and port equipment position thereof associated with the ' other terminus of the duplex paths~ It will be appreciated that there is a 50% blockage that can occur in this process. A 15.62 microsecond frame interval of the eight PGHs contains 8 x 32 =
256 bit. The same 15.62 microsecond frame interval of the XOH
I frame contains only ~28 bits.
: , 2. Multiplexer And Buffer 24002 Strips Out Sense Data And Inserts PCM Tone Data j me last two timeslot positions (i.e. #30 and #31) of the 32 timeslot PGH frame of the stream of binary data entering a TSI ¦
circuit along transmit port group highway 402' contain the binary ¦
information of the sense channels of sense/control data TDM network 4070 Multiplexer and exchange buffer 24002 functions to remove the binary information from timeslots #30 and #31, and ~end it in the form of a serial data stream -to port data storage network 405.
It will be appreciated that eight PGHs enter each TSI circuit 24000, with each PGH having two binary bits of sense data in time-s~i9 slots #30 and #31 o~ each PGH frame. Thus the eight PGHssimultaneously coming into TSI circuit 24000 have 16 bits of sense data which are shifted out of the demultiplexer and data exchange buffer 24002 to port data storage network 405. (Within ne-twork 402, this sense data goes to a parallel-serial converter 32000, to be discussed later.) i Multiplexer and exchange buffer 24002 also performs the insertion of pulse code encoded (PCM) tone signals in the other-.
wise vacant timeslots #30 and #31 at its output side. The broad-cast tones include dial tone, busy tone, and ringback tone. The binary data signals of these individual tones are introduced into each TSI circuit 24000 from a tone buffer 25100 in a synchronously timed relation such that the timeslots #30 and ~31 of certain port group highway frames effectively operate as if they came from broadcast ports. Multiplexer and sense data/tone data exchange buffer 24002 provide the tone binary signals in its binary data output. Under control of CCP subsystem 408, send buffer unit , :
24003 time buffers the tone data until a selected transmit XOH
timeslot comes along, permitting the binary data tone signal to be sent or "broadcast" to a selected port equipment position. It will be appreciated that the PGH frame which contains the binary tone data signal ln its format is effectively a port equipment position containLng broadcast tone plant equipment.

3. Network Of Transmlt XOHs ¦ As previously stated, the binary data bits arrive at a TSI
circuit 24000 in a port group highway timeslot reserved exclu-sively for a specific port, and leave in a transmit XOH timeslot arbitrarily set up for the desired port-to-port switching connection.

A transmit XOH originates in each TSI circuit. Referring now to the three-dimensional block diagram of TSI network 403 of Fig. 1A, -the TSI circuit from which a transmit XOH originates may be identified as the circuit 24000 in which the arrow feeding the XOH is pointing in an outgoing direction from the TSI circuit li24000. Thus XOH-O originates in TSI circuit 24000 0; XOH~1 in circuit 24000-1; and XOH-7 in circuit 24000~7 (the intermediate XOHs and the intermediate TSI circuits are not shown in the three-dimensional block diagram, as indicated by dashed lines).
The origin of the data stream on each XOH is the send buffer unit 24003 of the associated TSI circuit. In addition to the output of the buffer unit 24003 being directed externally (from the TSI circuit 24000 of which it is part) to the transmit XOH, it is also directed inwardly to the XOH selector 24004 within the same TSI circuit. Another relationship which can be seen from the drawing is that all the XOHs of the other TSI circuits 24000 are coming relative to a given TSI circuit. Thus, the data from a send buffer unit is distributed to all the TSI circuits. (i.e. 9 the seven other TSI circuits connect to its tra~smit XOH and to itself.) In summary, each TSI circuit has a send buffer unit 24003 which transmits a 128 timeslot XOH frame to any of the TSI
circuits including itself. The XOH has 128 timeslots used for data sending. Any one of the free timeslots may be used in making a connection to any of the other seven TSI circuits 24000 via connection to those circuits, or to any other of its own ports via an internal connection to its own XOH selector 24004. The time-slots are used to establish a full duplex link through TSI network 403. The output o~ a TSI circuit comprises binary bit signals in an XOH frame containing 128 timeslots.

!1 , .

4. Space-Division XOH Selector_2L,004 ,I The next opera-tion is the switching of the XOH timeslot ' which carries the binary data of the transmitting port equipment I'position into the XOH selector 24004 of the TSI circuit having the port which is to receive the data. Again, this is done under control of CCP interfaces controller 54000. XOH selector 24006 comprises a space-divided switching device which effects this Iswitching as a space-divided g~ting operation each time the ; selected XOH timeslot of a selected -transmit XOH comes around.

5. XOH Selector And Tone Si~als I

As previously stated, the tone signals inserted by send buffer unit 24003 are contained in predetermined XOH timeslots.
The XOH selector 24004 of each TSI circuit gates tones to a TSI
circuit 24000 under control o~ CCP subsystem 408 when their transmission to a selected receiving port equipment position is desired.
; .
' 60 Structure And Operation Of Buffer Demultiplexer And Buffer Unit 24005 And 24006 Those binary data signals which are passed by an XOH selector 24004 of a TSI circuit 24000 enter a receive buffer unit 24005 where they are stored until the correct time for passing through I
idemultiplexer and control data buffer 24006 into the correct ¦outgoing timeslot in a selected one of the receive PGH lines ¦402" connected to the TSI circuit. Then the data is sen-t to ¦, selected port group uni-t 402 where it is sent to the selected port.
i. I
ll 7. Insertion Of Control Data By ! Demultiplexer And Buff_r 24006 j Supervisory control bits from port data storage network 405 ¦(and more particularly from the parallel-serial converter 32000 ~ L5~

itherein, to be later described) are inserted into timeslots #30 and #31 of the serial data stream going back to port group unit 402. This is done within demultiplexer and control data in~ection ibuffer 24010.
I' ll 8. Description_Of Operation ¦! .
I The operation of TSI matrix switch network 403 is as follows.
''The eight port group highways 402~ coming into a given TSI circuit 24000 carry serially multiplexed voice ard sense data from up to 240 ports. Multiplexer and data exchange buffer 24002 and send . .
buffer unit 2400~ selectively converts this data to a further multiplexed (sometimes called "super-multiplexed") form of serially multiplexed data in predetermined timeslot on the transmit cross-office highway XOH originating from the TSI circuit. The selection of the data and of the predetermined timeslots is per-formed under control of CCP subsystem 408 via control/map RAMs 24007~ Within the TSI circuit 24000 for the port equipment position which is to receive the data, the XOH selector 24004 gates the data in the predetermined timeslot into the receive buffer " unit 24004. XOH selector 24004 also operates under control of CCP~
subsystem 408. (Note that the TSI circuit to receive the data may be the same as the TSI circuit in which the data originates.) This is done by means of space-divided switching performed by the XOH.
IReceive buffer unit 24005 and demultiplexer and injection buffer ¦24006 performed the time-divided selection of the data (also ¦under control of CCP subsystem 408) and switch the data to the lappropriate receive port group highway 402" and timeslot therein ¦for the port equipment position which is to receive the data.
¦ At the same time that the foregoing operations of switching ¦voice data takes place, the binary data corresponding to the sense channels of other-than-voice TDM network 407 are stripped 5r~19 ', o~f from the incoming serial data streams within multiplexer and jldata exchange bu~er 24002. In some instances PCM tone data is ' ' introduced in the timeslots vacated by the sense channel data.
- !iWithin demultiplexer and injection buf~er 24005, binary control , ¦Idata from port data storage network 405 is inserted into the serial data stream going back to port group unit 402.
'~ , 9. Control/Map RAMs 2400 Control/map RAMs 24007 proved memories for storing the call-, ing equipment number, the cross-office highway timeslot (XOH), and called equipment number for every path or connection set up ~;, through TSI network 403~ RAMs 24007 also ac-t as real and reserve ' ' map-in-memories of the actual and "reserved'1 paths through TSI
~,,network 403~ In the latter capacity the RAMs serve as a part of , the memory for recording the state of the call. If this addition ;~, al map-in-memory capacity did not exist, CCP subsystem 408 would require additional memory to record actual and reserved paths through TSI network 403. CCP subsystem 408 has access to the map-in-memories through bus 54001 between the CCP inter~aces control-ler 54000 and RAMs 24007 10. ~ o^~9:
It will be appreciated that TSI matrix switch network 403 is a TDM matrix switch for establishing voice data paths between ¦various port equipment positions of system 400 via the transmit ¦XOHS of the various TSI circuits. The paths between port equip-jment positions which are established by network 403 are selected ,by CCP subsystem 408 acting through controller 54000 and control/
¦map RAMs 24007. TSI network 24000 also serves as a buffer for ¦binary sense data and binary control data between port group units 402 and parallel-serial, converter 32000.

1145F~119 11. Signal Bit Rate Il It will be appreciated that overall, the switching of the ¦'serial data stream from one port equipment position to another is ¦ performed by TSI matrix network 403 at a rate of 64 Kbits/second.
Sense/control data multiplexer/demultiplexer 18000 operates with a 16:1 concentration ratio upon the 128 KHz bit rate of the serial da-ta stream emerging from CODEC 3500, providing serial binary data stream at the output thereof at a 2 MHz bit rateO Multi-~plexer and data exchange buffer 24002 and buffer unit 24003 con-centrate this further into an 8 MHz bit rate data stream on the XOH. This is subsequently expanded by receive buffer unit 24005 ' and demultiplexer and injection buffer 24006 back to a 2 MHz bit rate data stream, which is subsequently expanded to the 128 KHz bit rate of the CODEC frame. Overall, this is equivalent to a 64 KHz bit rate at the port. Thus, TSI network 403 provldes port ! to port data swi-tching at a 64 Kbit/second rate.
, K. TONE PLANT
A group of circuits are associated with the input port positions and TSI matrix switch network 403 to introduce low level;
~ tone signals. This group consists of a precise tone generator ! 25000, a toll multifrequency generator 25070 (optional) and a tone buffer circuit 25100. Precise tone generator 25000 and toll MF
generator 25070 are an operatively associated pair in which the tone signals are generated digitally.
Precise tone generator 25000 produces the following precise tone frequencies: 1004 Hz, 620 Hz, 480 Hz, 40 Hz and 350 Hz.
¦These are used for dial tone, high tone, low tone, busy tone, and ¦ringback tone. In addition, generator 25000 produces the follow-ing non-precise tones which are forwarded to TMF generator 25070:

11.2 KHz, 230~4 KHz, 235 KHz, 281.6 KHz, 332~8 KHz, 435.2 KHz, and - - ~ }

5~19 ¦,1.024 MHz~
TMF generator 25070 provides six frequencies for use in MF
pulsing. These comprise 700 Hz, 900 Hz; 1100 Hz9 ~300 Hz; 1500 Hz, and 1700 Hz frequencies. They are generated in pulse-rate-modulat-~ed square wave form for subsequent conversion to a sign-wave form in toll MF sender circuit 3250.
, Tone buffer 25100 is a formating and distributing circuit for ¦'precise tones and toll MF tones. The broadcast tones are inserted directly into TSI network 403, and are distributed therein by a "broadcast" technique which negates the need for use of input ports for a tone plant source.
'' ' '.
; L. PORT DATA STORAGE NETWORK 405 ~; ~ The primary function of port data storage network 405 is to provide an individual data memory field for each port. These data fields are the only paths of communication between the two inter-~- j active processors of system 400. mey also constitute a buffer j store between the processors and sense/control data TDM network 407, which in turn is the communication path for binary supervisory data to the port circuits. Thus, a port data field is an essentia~
link in the communication between the processors and the port ,circuits.
The circuits included in network 405 are: a timing and contro circuit 28000 (which is also a part of PEP processor 406) a con-verter control circuit 30000, a set of parallel-serial binary signal converters 32000 (which is also a part o~ internal super visory data TDM network 407), and a set of port data store circuit~
33000.
The port data store circuits 33000 comprise the storage medium for the individual port data fields for the individual ports. A circuit 33000 stores a 256 bit word for each of the 1920 1145~19 ¦~ports of system 400.
Reference is now made to Fig. 2, for the format of each 256 bit port data field 33500. Field 33500 is broken down into ten subfields. Some of the subfields which have important roles in the interaction between PEP 406 and CCP subsystem 408 will be described in subdivision M, O, and P, following.

¦I M. PORT EVENT PROCESSOR (406) Port event processor (PEP) 406 is one of the two interactive processors of system 400. It comprises a combinatorial logic ; organization 34000 and timing and control circuit 28000 (which also provides certain functions within port data storage network (405). PEP 406 scans the port circuits for status change by way ~of scanning certain subfields of the port data field 33500 for ~1~ that port. More particularly, E'EP scans the indicators of port supervision conditions and/or other indicators of the detection of port conditions in accordance with a logic sequence which is ¦ defined by a command generated by call control processor (CCP) subsystem 408. (This command is recorded in a port command sub~
I field 3~502, Fig. 2.3 Based upon the information which is the subject of the interrogation, PEP 406 may generate changes to ~outgoing supervision or other controlled at the port interface or ¦service circuit and/or communicate with the other interactive processor; namely, CCP subsystem 408~ i This interaction between PEP 406 and CCP subsystem 408 may be characterized as a command and response type mode. CCP subsystem 408 generates a command code which is communicated to PEP 406 via , subfield 33502, which presets the sequence o~ logical operations , performed by PEP 406 to pro~ide impulse analysis or other pro-cessing for detection of specific port conditions. The command ¦ ode also presets the processing to be performed upon a deteot~on I!

,of a specific event. The normal mode of processing which PEP 406 'l performs upon the detection of a port condition anticipated by the !i command9 includes communicating a coded response representing the Il port condition (i.e., an event code, EVC) to CCP subsystem 408.
!i Subsystem 408 is constantly scanning for the coded responses ¦Irepresenting a port condition, and in response thereto performs !~ processing which results in the generation of the next coded command for PEP 406. Several such stimulus and response type cycles take place durLng the progression of a call.
PEP 406 performs the scanning of each port over a repetitive 4 millisecond scan cycle in which PEP 406 has a 1.953 nanosecond scan interval for each port. During this scan interval, PE~ 406 has access to -the port data field 3~500 associated with the port.
In this manner, PEP 406 performs processing upon each of the 2048 port positions in system 400.
Combinatorial logic organization 34000 comprises basically ~ five different combinatorial functional units. One of them pro-; vides logical functions which are common to each type of operation ; performed by the processor. The other four arc for specific types of operation which the processor may be commanded to perform by the coding in port command subfleld 33502.
The functions common to each type of processor operation is performed by a common logic unit 36000. This ~mit is enabled Iduring all scan intervals, in contrast to the other functional ¦logic units which are only enabled when the appropriate port ¦command (given by CCP subsystem 408) is recorded in subfield 33502.
! Descriptions of the functional logic units which are enabled ¦only during presence of certain port commands follow.
i Sense supervisory event (SSE)/transmit supervisory event ~(TSE)/supplement to common logic unit 38000 provides impulse analysis to detect such supervisory events as seizure/release, ~L14~'~19 , ,, I wink/hookflash, stop dial, and delay dial~ It also generates out-¦¦going supervision signals such as wink9 hookflash, wink off and delay dial.
A ring line (RGL) functional logic unit 40000 applies ring-¦¦ing to lines and senses occurrence of a ring trip~
ll A send digits (SD) functional logic unit 42000 sends dialing ! digits to the port equipment interface circuit for outpulsing in dial pulse or multifrequency tone pulse form. A receive digits (RD) functional logic unit 44000 collects and racks the digits introduced at a port equipment interface circuit. SD unit 42000 and RD unit 44000 have an associated circuits assembly unit, call-¦
ed the receive digits (RD)/send digits (SD) unit 45000. It per-forms processing as though it were a part of either SD unit 42000 or RD unit 44000 when either of the latter are enabled.
i,', 1 N. C~ ATA T M NETW RK 407 Sense/control data TDM network 407 is comprised of~
sense/control data multiplexer/demultiplexer (18000); supervisory buffer 32000; (ii) those certain portions interface circuits and service circuits 2000, 2000', 3000, 3200, and 3250 which form input/output connections to sense and control buses 402 "'; (iii) ¦
portions of port group common utility circuit 20000 and TSI
circuit 24000; and (iv) portions of port data store 33000~
The flmction of network 407 is to provide paths for the com-munication of binary data between PEP 406 and the interface and service circuits in the port equipment positions. Control data from PEP 406, consisting of the outputs from the functional logic units on the CF0, CF1, and CS0-CS7 leads of the tri-state bus are communicated to an equipment interface circuit or service circuit and to subfield 33502. Sense data from the interface circuits or service circuits, which represents the status of relay contacts or ~ LSq~
~ '' l l ~of electronic latches therein, is in general communicated to and recorded in an assigned bit location of port communication subfield 33501. Once sense data is recorded in subfield 33501, PEP 406 has ~access to it during the scan interval for the port position.
(There is arbitration circuitry which sometimes operates to com- i municate the data directly to PEP 406.) Ten different binary sense functions from each interface circuit or service circuit may !
be sampled in a 4 millisecond period. Similarly, PEP 406 can transmit 10 control functions to each port position in a 4 milli-second period.
` Referring now to Fig. 2, in subfield 33501 bit areas CFO
¦land ~, and bit locations CSO ~7 serve to record the 10 binary control data outputs from PEP 406; and bit areas SFO and ~ and bit locations SSO-SS7 serve to record the 10 binary sense function~
; ~Ifrom -the interface or service circuit.
; !, Network 407 provides the 10 binary channels in each direction ¦!between the interface/service circuits and PEP 406. It does this !l in a way which takes advantage of the port group time divided ¦ highways between port group units 402 and TSI matrix switch 403.
Briefly, the time division highways have a frame which multiplexes !
.. i l PCM voice data for 30 ports using 30 timeslots of the frame. The Ij circuitry for formating the PGH frame provides 2 timeslots in addition to those needed for the 30 ports. The presence of these 2 timeslots in each PG~ ~rame is time divided over a period of 4 milliseconds to provide 2 fast channels (with strobe or sampling rates at 1 millisecond intervals) and 8 slow channels (with strobe or sampling rates at 4 millisecond rates).
¦ Throughout this specification, the channels o~ TDM network 407 are desi~nated by a scheme which assigns the channels the same alphanumeric designation a~ the bit areas or bit locations of port subfield 33501 with which the channel communicates. However, the ~ 5~9 designation of the channel further bearing a l'prime symbol" (') ¦as a suf~ix. For example, the fast control data channel com-I municating with bit area CF0 is designated CF0~o O, CCP SUBSYSTEM 408 ; 1. Ma,jor Com~onents Of CCP Subsystem 408 CCP subsystem 408, which is a microprocessor-based, stored program system~ comprises a processor unit 50000, the processor bus BCCP, a call control interfaces controller circuit 54000 and a 32K memory 56000 for holding a call control stored program 56002. All communications between CCP subsystem 408 and either ¦! port data store 33000 or TSI matrix switch network 403 must go ijthrough controller 54000.

~; 1, 2. Data Stored In Other-Than-Conventional Memor~
¦ While memory 56000 contains processing logic and some of ¦the data base for the processing performed by subsystem 408, it ~i' . does not contain an internal map-in-memory of the TSI matrix paths, nor a data base storing specific call state information such as on-off hook status, dial-tone requests, ring-line requests, etc. Instead TSI matrix network 403 is itself used as the recording media for TSI paths, and the port data field 33500 contains the specific call state data. This externally stored information in network 403 and data store 33000 is contained in random access memories (RAMs) therein, which are addressable through normal memory access instructions along bus BCCP via con-troller 54000. Stated another way, controller 54000 manipulates the binary information contents of network 403 and store 33000 to ¦
give process~r 50000 access to this information.

5~
:

3. Overview Of Call Control Stored Pro~ram ~6002 !
il CC stored program 56002 is the primary instrumentality for controlling the advancement of a call through its various stages, ' and for controlling PEP 406. By controlling PEP 406 program ¦¦ 56002 controls the logical sequence by which PEP 406 processes ¦ sense data from the ports, and the logical sequence by which PEP
!1 406 controls the supervisory signal output and other ~unctions of 1, the port interface circuits/service circuits. Further, by con-' trolling PEP 406, it controls the logical sequence by which an event code (representing occurrence of a port condition) is generated and communicated to CCP subsystem 408.
Exemplary of the stages through which a call is advanced are the following stages associated with a si~ple line-to-line (local) call through switching system 400.
~ 1. Idle-to-dial tone (origination) 1 2. Dial tone-to-~irst pulse 3. First digit tran~lation (digit analysis) 4. Third digit translation ' 5. Final translation

6. Answer 7r Disconnect The mode o~ processor interaction by which CCP subsystem 408 ' controls PEP 406 has been previously described; namely, CCP sub-system 408 places a coded command in subfield 33502.

4. Stored Program 56002 And "State Transitions"
Program 56002 advances a call through its stages by l'state transition" modes. The logic of program 56002 is organized to have up to 256 fundamental states, which generally correspond to the logical sequence needed for at specific call stages. Call -40~

s~l9 state transition is the process of making a transition from the present state of a call to the next state, based upon interaction with PEP 406~
~; ! In the course of performing state transitions, program 56002 ¦performs the following common control functions normally found in an office switching system:
1 1. Translator functions, including: class of ¦i service checks and associated restrictions and routings; identification number trans-lations; code translations; and route trans-lations.
2. Switching matrix control functions including:
recovery of linkage information of existing paths; path selection; path setup and dis-connection (i.e., marking or unmarking of TSI matrix switch paths); reservation o~
path; and busy checks.
3. Control of ringback tones.
Finally, stored program 56002 also functions to record the fact of itself being in a new state by entering this information in subfield 33503, Fig. 2.

; 4. The Tiered Structure Of _Stored Pro~am 56002 _ Functionally, CCP stored program 56000 may be regarded as having 4 tiers.
Executive Tier 56004. An executive tier 56004 has the primary function of scanning information communicated to CCP
subsystem 408 to detect ports which require processing. Based upon information recorded in the port data field 33500 for the port, including the call state, a module in executive tier 56004 vectors the logic to perform a particular state transition. The 11~5~19 ';
Il .
~'call state transition is performed by a call state transition routine which takes system 400 from its existing call state to the next.
State Transition Tier 56006. A state transition tier 56006 ¦~contains stored program modules which provide the logic to l,formulate such a transition routine. The logic within tier 56006 ¦! cannot perform a complete call state transition. Logic in the tiers to be next described are necessary to constitute a complete transition routine.
Shared Subroutine Tier ~6008. A shared su~routine tier 56008 contains modules of common shared subroutines such as equipment connection subroutines, equipment release subroutines and translation subroutines. These again require the services of the next lower level tier to be described next.
i Shared InE_t/Output Utiliti _ Tier 56010. A shared input/
i output utilities tier 56010 contains the stored program logic for accessing port data store 33000, accessing TSI matrix switch ' network 40~, and accessing certain stored program system data bases.
' 5. Access Cycle To Port Data Store 33000 , Although for purposes of internal operation, CCP subsystem 408 is a synchronous computer, it operates asynchronously in obtaining access to specific port data fields 33500 of store 33000.
The RAM control circuitry of store 33000 operates in a way in which the read access by PEP 406 during a 1.953 microsecond scan interval is split between a first read period and a second read periodO During the first read period PEP 406 has access to the first 8 words (128 bits) of the field, and during the second read period it has access to the second 8 words of the field. The format of field 33500 is so chosen that for purposes of most of 1145~19 ¦ -the processing task which PEP 406 performs, only the first 8 words ¦lare used. Thus, the amount of time needed by PEP 406 for a second , "second read" is minimized. Upon completion of the "first read"
¦,a logical determination is made of whether a "second read" is 'going to be required. If not, CCP subsystem 408 is given access l~to a field 33500 during a second read period not neededO It will !¦be appreciated that this availability of a second read scan " interval to subsystem 408, together with the asynchronous access mode of subfield 408 virtually eliminates the "idle time" of waiting for a scanning interval (such as would exist with a synchronous mode of access).

.
PO BRIEF DESCRIPTION OF OPERATION
Following is a brief description of the operation of system 400 which illustrates the nature of interaction of PEP 406 and CCP subsystem 408. The status of various functions of port interface/service circuits (e.g., status of incoming supervision of lines and trunks) are communicated to subfield 33501 of store 33000 via binary sense channels SFO', SF1' and SSO'-SS7i. This information is then processed by the time shared combinatorial logic organization 34000 of port event processor (PEP) 406, during the 1.953 microsecond scan interval (out of the total 4 milli-¦,second scan cycle) for the particular port equipment positionsinvolved. The processing of this by PEP 406 is performed in accordance with a loglc sequence defined by a coded command recorded in port co~mand subfield 33502. When the logical sequence detects a condition to which it is to respond at the port, jit may generate binary output con-trol signals to control various ¦binary control func-tions associated with the interface circuit in the port eguipment position (e.g., the outgoing super~isory control signal for along a trunk). I-t may communicate (via 1~45~19 ¦,response subfield 33506) to CCP subsystem 408 an indicia that a ~'port event has occurred. The control function for the line ¦'circuit9 trunk circuit, or other interface/service circuit is , communicated to the same binary control channels CFO', CF1' and j¦CSQ'-CS7'. The current control data is recorded in the correspond-¦iing bit areas and bit locations in port communication subfield ¦33501. The communication of an indicia of occurrence of event to ¦~CCP subsystem 408 is accompanied by placing the equipment (EN#) of the port equipment position in a queue of a set of priority ; related queues registers. These queues are accessible to CCP
subsystem 408. CCP subsystem 408 scans the queues and is responsive to the indicated event to effect a transition to a different call state by invoking a particular state transition routine. Once the transition routine has completed the transition, CCP subsystem 408 changes the coded command in port command subfield 33502, thereby defining the new logical sequence with which PEP 406 will interrogate the status of the port circuit. CCP subsystem 408 also records in subfield 33502 the fact that a transition to a new call state has been made.

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1,~

II. DESCRIPTION AT sYsr~v I_,~L
A. LINE INTERFACE CIRCUIT (2000, or 2000' WHEN MULTIPARTY2 1 Line inter~ace circuit 2000 is a controlled interface : between switching system 400 and a subscriber line. Two-way ~ llanalog signals on the subscriber line are converted to so-called : ' "four wire" signals consisting of l-way transmit and l-way receive analog pathsO Binary control signals received over . the CFl1 and CSA' channels of other-than-voice data TDM network 407 are stored in flip-flops. These signals control relays concerned with ringing and linè/port testing, respectively. The off-hook state of a line operates a relay, which controls the status of the latter relay, is converted -to standard TTL levels and provided as an output overfast binary sense channel SF01 of ; . TDM network 407. When connected to a multiple party line the circuit is designated 2000'.
:
B. ~ ~ M TRUNK INTERFACE CIRCUIT ~3000) . E&M trunk interface circuit 3000 provides a controlled interface for use between switching system 400 and E&M type ; interoffice trunk facilitiesO Two-way analog signals on the tip and ring leads are transformed into a four-wire path (i.e. two ~one way analog paths for digital conversion). The signals on ¦~these paths are converted to/from pulse code modulation (PCM) ¦!digital bit streams by the PCM CODEC circuit 3500.
The binary control signals received over channels CF0, and ¦¦CSA' of other~than voice data TDM Network 407, which have been j!generate~ by port event processor (PEP) 406, control a PL
l,(pulsing) relay and a pair of test access relay (TA and TB
j!respectively)~ Incoming ~-lead signals are converted to standard TTL levels and than provided as an output on fast binary sense channel SF0 of TDM network 407.
Relay circuitry is provided to enable test access of the ~1~5~19 !i , ~ tip, ring, E, and M leads.
' C. PCM CODEC CIRCUIT~FILTERJ3500 ~ A pulse code modulation (PCM) coder-decoder (CODEC) and jjfilter circuit 3500 circuit assembly has six (6~ separate codec-I filters along with associated circuitry common to all six (6) j !
codecs. ~ach- co~ec-filter has a transmit filter, a receive filter, a sample and hold circuit and a hybrid circuit containing the coding and decoding circults. The common circuitry includes a timing generator.
From the CLK and SYNC pulses supplied to circuit assembly l~ 3500, are generated the Encode/Decode (E) pulses, odd and even;
;~ the S (Start) pulse~ odd and even; and the S/H (Sample and Hold) pulses, odd and even.
. ~.
The transmit outputs (DO) of two (2) codecs, odd and even, are multiplexed together by gating under control of the E pulses.
The receive is demultiplexed by the CODECs under control of the ; ~ pulses. Thus there are three (3) receive inputs and three (3) transmit outputs (DO) to and from circuit assembly 3500.
.
D. VOIC~ DATA MULTIPLEXER/DEMULTIPLEXER 16000 ; i Voice data Multiplexer/Demultiplexer circuit 16000 multi- i plexes the 15 parallel 128 KHz data streams from five (5) pulse- !
code modulation (PCM) COD~C/filter circuit assemblies 3500 into a single 2.048 MHz serial data stream for transmission to the sense/control data multiplexer/demultiplexer circuit 18000.
Simultaneously, the card demultiplexes the 2.048 MHz serial data from multiplexer/demultiplexer 18000 into sets of 15-bit parallel data and transfers this data to the CODEC circuit assemblies 3500 at 128 KHz. Whether multiplexing or demulti-¦plexing data, circuit 16000 reformats the data to match the ~ 9 I
.
~requirements of the CODECs to those of the TDM timeslot frame of l,the port group highways 402' and 402ll.
I Each of these data streams receive and transmit carries data for two channels. One is an odd numbered channel and the other ~¦an even numbered channel.

E. SENSE/CONTROL DATA MULTIPLEX~R LD~MULTIPLEXER (1800Q~
I Sense/control data multiplexer circuit 18000 provides the ¦jpath for "receive voice data" ~i.e., voice data which is received by the port circuit from TSI circuit 24000) between port group common utility circuit 20000 and the demultiplexer portion of multiplexer/demultiplexer 16000. It also provides the path ~or "transmit voice data" (i.e., voice data which is transmitted by the port circuit to TSI circuit 24000) from the multiplexer i~portion of multiplexer/demultiplexer 16000 to circuit 20000.
Circuit 18000 also provides signal paths for control data of Network 407 from the circuit 20000 to the port circuits and ~,for sense data from the port circuits to circuit 20000.
Circuit 18000 also generates the port strobes that read the ~ supervisory sense data from the port circuit and clock the control !
¦~idata into the port circuits.
Il ~
¦ I F . ~ ~ L ~ ~ i Sense/Control data network 407 between the port equipment positions and port data store 33000 and/or CL organization 34000 provides 10 binary da-~ channels control information 'Icontrol bits" per port, and up to 10 binary data channels of sense in~or-mation per port. The sample rate for either set of 10 channels is 1 ms. for 2 "fast channels" and 4 ms. for the remaining 8 "slow channels". The availability of a 1 ms. sample rate channel makes it possible to perform filtering in CL organization 34000 rather than require filtering circuitry in the port. In system 400, the 1145~19 filtering of the supervisory signal is done digitally in receive digits (RD) functional logic unit 42000.
The lO channels of sense information are communicated between any port and port data store 33000 and/or CL organization 34000 in jitime division multiplexed fashion. The port group highway TDM
¦Iframe is 15.625 microseconds long and contains 32 timeslots of 488 ns. in duration. The last two timeslots, namely numbers 30 and 319 carry binary sense data. Two consecutive port group highway ;constitute a port sense data frame, containing four/4 bit of ; binary sense data.
Referring now to Fig. 3, four timeslots consisting of time-slots number 30 and 31 of each two consecutive PGH frames (PGH
couplet) are transmitted every l ms. The logic is such that the four timeslots carry data from the 2 fast channels, and data from 2 ~of the 8 slow channels every millisecond. The timeslots carrying slow channel data are time shared so that a bit of binary data from the slow channels is transmitted every 4 milliseconds.
The fast binary data channels consist of fast control channels CF0' and C~l' and fast sense channels SF0' and SF1'. Each fast channel comprises a continuous stream occurring at timeslot 30 of i each port group frame with a period of recurrence of 1 ms. (i.e., every fast bit frame, Fig. 4) for the bit of a given port.
The slow binary data channels consist of 8 slow control channels (CS~' to CS7') for which subfield 33501/CL organization 34000 is the transmit end and a port is the receive end, and 8 slow sense bits (SS0' to SS7') for which a port is the transmit end and subfield 33501/CL organization 34000 is the receive end.
The 8 channels in a set of lO port channels represent functions.
The binary data bits of a slow channel will at timeslot 31 of each port ~roup frame with a period of repetition of each channel recurring every 4 milliseconds (i.e., every slow bit frame, Fig. 4) -~8-I! .
L~5~

! ' .

The control cha~nels respond to CL organization 34000 or call ¦Icontrol processor (CCP) subsystem 408 to provide control intelli-gence for operating relays or electronic latches in the port l~equipment. The supervisory sense channels respond to relays or ¦lelectronic latches in the port equipment to transmit data to subfield 33501 or CL organization 34000.
Referring again to Fig. 3, a port group highway (PGH) 402J or ,40?' carries voice and control or sense information for 30 ports, except that in the case of the last two PG~ couplets in each ast bit frame (Nos. 62 ~ 63) maintenance information and port group control information are carried in place of the control or sense ., information. Referring to Fig. 3, there are 32 timeslots in a PGH frame, out of which timeslots 00 through 29 carry voice data ;~for ports 00 through 29 respectively, and timeslots 30 and 31 are . .
, time shared to carry control or sense information for ports 00 through 29 and also to carry maintenance information and port group control information in the case of timeslots 30 and 31 of ~;
virtual ports 30 and 31. Over the period of 4 fast bit frames timeslots 30 and 31 are time shared to carry information relating to different functions. Stated a different way, the four #30 and #31 timeslots of two successive port group highway frames (i.e., a PGH Couplet Frame) are assigned to carry the sense or control data for an individual ports or maintenance and port group control information~ The bit rate of the PGH signals is 2~048 MHz. There are 32 timeslots in a PGH frame which makes the PGH frame duration 15.625 microsecond.
In summary, for each port 2 PGH frames (or a PGH couplet) are required for the other-than-voice data binary data channels. It will be appreciated that the sample interval for a fast channel is 1 millisecond, and the sample interval for a slow channel is 4 milliseconds for a given port.

~ 5~9 il ¦I P.eferring again to Figo 4, the channel carried by timeslot 30 l,of a PGH frame is designated a fast channel "F0" for an even ; jlnumbered PGH frame. The timeslot 31 of a PGH frame is designated I lla fast channel F1" for an odd numbered PGH frame. me timeslot ¦l31 of the PGH is designated a slow channel "SA~' (not shown in ¦!Fig. 4, since "SA" is the collective designation for channels S~, ¦~S2', S4', and S6,as will be presently described) for an even-¦numbered PGH frame. Channel 1'SA"' bit is slow channel "S0"' j, .during the first one millisecond fast bit frame of a 4 millisecond slow bit frame, channel S2' during the 2nd fast bit frame, channel S41 during the 3rd fast bit frame, and channel S61 during the 4th fast bit frame. The timeslot 31 of the PGH is called a slow "SB~' (not shown in Fig. 4) for an odd numbered PGH frame. me slow channel "SB'1' is slow channel S1' during the 1st fast bit frame, channel S3 t during the 2nd fast bit frame, channel S5' during the 3rd fast bit frame, and channel S7' during the 4th fast bit frame.
Each millisecond period constitutes a ~ast channel ~rame.
The four fast channel frames constitute a slow channel frame. A
slow channel frame of 4 milliseconds contains 10 channels for carrying control and sense information for each of 30 port lequipment positions, and additionally for carrying information for maintenance information, and port group control information iduring the two addition virtual port positions. The arrangement I of fast channel frames within a slow channel frame is best shown in Fig. 4.
Reference is now made to Fig. 5, which is a generalized block diagram of the total sense/control data TDM network 407 of system 400. There are 30 ports (designated ports 00-29) per port group unit 402.
Eight port group units are served by a TSI circuit 24000.
The following description will first cover the usage of the other- ~

5~- i ~4~19 ~ than-voice channels for a line circuit, and then their usage for !11 a trunk or other port equipment.
Reference is now made to Fig. 6, which is a generalized block diagram of line interface circuit 2000, to Fig. 7, which is ¦¦a generalized block diagram of sense/control data Multiplexer/
! Demultiplexer 18000 and to Figs. 8A, 8B, and 8C, which collect-ively constitute a supervisory information timing diagram.
¦IReferring to Fig. 6, four parallel bits of supervisory information jappearing on bus leads SBF~, SBFl, SBSA, SBSA sense bus 18002 from the line interface circuit 2000 are enabled by the port strobe signals PS 00 through PS-29 on a port strobe line 18003.
Referring to Fig. 7, the sense bus data are clocked into latches 18004 (e.g. positive going edge 18004a, Fig. 8C) by a clock !
signal on 18005 generated by a PGC control counter and a decoder 18006. A 4 input to 2 output multiplexer 18008 multiplexes ¦~latch the states of sense bus leads SBF0 and SBFl into timeslot ','30 and the states of sense bus leads SSA and SSB into timeslot 31 for each port group frame couplet. For even-numbered port group frame counts the states of leads SBF~ and SBSA become binary data bits on channels SF0' and SFA', and for odd numbered ¦iport group frame counts these states become bits on channels SFl~, and SSB'. Multiplexer 18008 is controlled by a select signal ¦provided by port group counter and decoder 18006 via select leads 18010. The multiplexed data at the output of multiplexer 18008 are inserted into the port group highway at timeslots 30 (e.g., pulse 18008a, Fig. 8A) and 31 by a salector 18012. The transmit voice data for the ports 00 to 29 and the sense data are multi-plexed to form a transmit port group highway (PGH) 402' going ¦to TSI circuit assembly 24000.
Reference is now made to Fig. 12, which is a generalized block diagram of the portions of a TSI circuit assembly 24000 that 5f~
Il 1 .
are involved in the sense/control data TDM network 407. In the ¦¦TSI circuit assembly 24000 the binary data carried during PGH
Itimeslots 30 and 31 (e.g., pulses 24009~ and 24009" Fig. 8B) are jstripped and loaded into a 16 bit supervisory sense bit shift ~register 24009. During the period of the next P&H timeslots O
¦to 29, the 16 sense supervisory bits from eight port group controls ¦are shifted out from the register 24009 and stored in supervisory buffer 32000. This is depicted by pulse waveforms 32000' and 32000 " , Figs. 8A, 8B, and 8C, and by time periods 32000 " ", Fig. 9. Reference i5 now made to Fig. lO,which is a generalized i block diagram of supervisory buffer 32000 depicting the sense channel paths. The sense channels SF0', SFl, SSA' and SSB' from each of the two TSI circuit assemblies 24000-0 and 24000-1 are stored in corresponding RAMs 32002a and 32002b for each port ~levery millisecond. After 4 milliseconds, each of the RAMs has ,laccumulated 16 bits of sense supervisory information per port.
¦IIt is to be appreciated that the number of accumulated bits, namely 16, includes four samples of channel SF~', and ~our samples of channel SFl'. This is done in order to enable the 1 millisecond sampling of the function communicated by these ¦!channels under the circumstances of combinatorial logic (CL) lorganization 34000 scanning a port data field 33500 at a 4 ¦millisecond rate. In other words, 1 millisecond samplings must ;
be s-tored. This is the reason SF0' and SFl' channels are fanned o into leads SF0A,SF~B, SFOC, SF0D, SFlA, SFlB, SFlC, and SFlD. me status of the fanned out channels are stored in the corresponding port data store field 33500 and transferred to the CL organization ~4000 when scanned by same.
¦ Referencc is now made to Fig. 11, which is a generalized ¦block di~gram of supervisory buffer 32000 depictingthe control channel paths. Sixteen (16) leads carrying bits of binary data s~

~from -the associated port communication subfield ~3501, or from CL organization 34000, are stored into RAMs 32004a and 32004b every 4 milliseconds. Data read out from the RhMs are stored ' in dual ~ bit shift registers 32006a and 32006b under control ¦lof suitable clocking signals 32006', Figs. 14A, 14B, and 14C.
!! There they are strobed (by signals 32006 ") in strings of 16 bits l,to TSI circuit assembly 24000.
I Referring again to Fig. 12, each TSI circuit 24000 has a supervisory bit shift register circuit 24010 from which the supervisory bits are inserted into the port group highway via a 4 input to 2 output multiplexer selector 24011, and a demulti-plexer 24012. (See time periods 24004' and 24004 ", Fig. 13, and time interval diagram 24004" ', Figs. 14 A, 14B, and 14C).
Register 24010 stores 16 bits of control information for 8 port groups in 16 bit serial input, serial output fashion. The demultiplexer 24012 Fig. 12 converts the 8.192 MHz multiplexed data Lnto 8 port group highways.
Referring again to Fig. 7, a receive selector 18014a splits off timeslots 30 and 31 from the 30 voice timeslots~ and sends timeslot 30 and 31 to reformatting logic 18014b. (See time interval diagram 18014', Figs. 14A, 14B, and 14C, for the timed ~relationship of the timeslots received at the port group control ~¦latch~) ¦I The control bits for two PGH frames are stored into reformatting logic 18014b and enabled onto the control bus 18016 Referring now to Fig. 6, the data lines CBF0, CBFl, CBSA, and CBSB
of control bus 18016 are received by a latch 2004 under control of a port strobe signal PC (N) from port strobe line 18003. For S!
example, the data will be received in latch 2004 at the positive going edge of the port strobe zero 2004', Fig. 14A.

1~ 45~:1 9 I Reference is now made to Fig. 15, which is a generalized , .
¦Iblock diagram representing the input/output communication aspects o~ either a trunk interface circuit or other form o~ port equipment interface circuit. The various relay and sense logic ~ifunctions of a trunk or port equipment circuit are connected to ¦¦leads corresponding to fast supervisory channels SF0' and SFl' and slow sense channels S0'-SS7l. A pair o~ 4-line to l-line ~multiplexers 3002a and 3002b multiplex the individual slow sense ;channel states to the slow sense channel signals SSA and SSB, Multiplexers 30~2a, 3002b 9 are controlled by a select 1 millisecond signal and a select 2 millisecond signal carried by lines 18018 ~and 18020 from sense/control data multiplexer/demultiplexer circuit 18000, Fig. 7, where they are generated by PG control counter and decoder 18006. During each one millisecond period ,the signals on lines 18018 and 18020 select 1 of the 4 inputs to each of multiplexers 3002a and 3002b~ The port strobe signal ~controls a bus driver 3004 to strobe the ~ast and slow sense bits I 'lonto sense bus 18002 in the same manner as previously described !in connection with the line circuit, Fig. 6.
; Fast control channels CF0' and CF1 and slow control channelbus signals CSA and CSB are communicated from port data store llcircuit 33000 or CL organization 34000 to control bus 18016 via ¦~parallel-serial binary signal converter 32000 and sense/control data multiplexer/demultiplexer circuit 18000 in the same manner as previously described in connection with the line circuits.
The binary signals of fast control channels CF0' and CFl' are clocked into a latch 3006 each millisecond when a port strobe signal is generated for the port. The binary signals of slow 'i control channels CS0' and CSl' are clocked into a latch 3008 when a l-line to 4-line demultiplexer 3010 selects one port strobe out of a four port strobe cycle to clock latch 3008.

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l ~
I
In a similar manner the binary signals of slow control channels CS2' and SC3' are clocked into latch 3012; the binary signals of slow control channels CS4' and CS5' are clocked into a latch ~014;
I,,and CS6~ and CS7~ are clocked into a latch 3016. Multiplexer ¦¦~010 is controlled by the select 1 millisecond and select 2 ¦Imillisecond signals from lines 18018 and 18020.
¦l It will be appreciated that in system 400 the port strobe at each port simultaneously clocks both the control binary bits l~received and the sense binary bits sent. This has been achieved 1: .
by time alignment of the bits on these buses being adjusted in the design of parallel serial circuit 32000 to bring this a~out.
Reference is now made to Fig. 14B and 8C to illustrate the ~ore-going, and using Port Number 00 strobe as an example. Control data is received as shown at positive going wave transition 20041. , Sense data is enabled during the low active portion of the por-t strobe, preparing it to be clocked into the Port Group Control ~circuit at positive going wave transition 18004a, Fig~ 8C.

I , G. PORT GROUP COMMON UTILITY CIRCUIT (20000~ i :
Port Group Common Utility Circuit 2COOO has the function of routing accessed tip and ring leads from the port circuits to one of three test access buses. Accessed ~ and M lines are ¦switched to a single ~ and M test access bus. Switching is accomplished by five relays controlled by a slow control channel carried by timeslot 31.

Ho INTERRUPT R-SERIA_IZER h RINGING MO_I OR (21100 me interrupter-serializer and ringing monitor 21100 receives the continious ringing signal from the ringing generator transfer circuit. The in-terrupter then provides interrupted ringing : !.
signals on two buses for single-frequency ringing, and on four .buses for 4-frequency ringing. ~ach 4-frequency bus supplies four frequencies in sequence. Each frequency is of 1.28 seconds duration, with 0.220 seconds of silence or open circuit, and with a different frequency on each bus during each of the four ringing phases. The single-frequency bus SFRB0 provides the single frequency ringing signal during the first and third of the four phases, and bus SFRBl provides this ringing signal during the second and fourth phases. The interrupter is driven ,.
by the RGL functional logic unit 40000 of combinatorial logic (CL) organization 34000.
The ringing monitor function of circuit 21100 serves to monitor interrupted ringing signals on all six ringing buses and initiates a failure signal if the interrupter fails to supply interrupted ringing signals.

I~ TSI CIRCUITS (24000 Eight TSI circuits 24000 performs the switching function for switching system 400. Each operates under the direction of the CCP interfaces controller 54000. ~ach TSI circuit may be connected to up to eight port group units 402 via port group highways (PGHs) 402' and up to seven other matrix switches via cross-office highways XOH. In addition the TSI circuit receives broadcast tone bits from the tone buffer circuit 25100, separates the sense data from the serial data stream of the transmit PGHs for transmission to parallel-serial binary signal converter 32000, and injects control data from converter 32000 onto the receive IPGHS for. and switches pulse-code modulated (PCM) voice data bits been selected pairs of port equipment positions. Data bits received from other TSI circuits 24000 are received via XOHs in a system containing up to 1920 ports.

i l TSI circuit 24000 serves four main functions. It serves as ¦la buffer for the control or sense binary data between the port 'group units and converter 3~000. lt maintains a store of data that controls the availability of paths through the TSI matrix switch network 403 including the performance of limited processing o~ the data. It gates the pulse code modulated (PCM) data from the port equipment position or the PCM broadcast precise tones !from the tone buffer 25100 to the proper time slot on the XOH
associated with that TSI circuit containing the transmitting port.
When the TSI circuit contains the receiving port, it gates the PCM data from the transmitting XOH and timeslot to the recelving port.

J. PRECISE TONE GENERATOR 25000 The precise tone generator develops the following precise tone frequencies from the 2.048 MHz system clock:
1004 Hz ~ 350 Hz ;~ 4L~o Hz~ , 480 Hz , 620 Hz il The 2~048 MHz clock is first divided by eight and gated to ¦produce a 256 KHz two-phase clock. The two phases of the clock ~; drive decade rate multipliers. Outputs of the rate multipliers are combined with each other and/or the opposite phase of the clock and further divided by binary counters to produce outputs at sixteen times the desired audio frequency.
Sine conversion (conversion of the digital outputs of the ~requency synthesizer to sine waves) is accomplished using non-frequency-dependent digital techniques. Each frequency synthe-1145;1~L9 sizer output drives a sixteen-step up/down counter. The ~our-bit ioutput of the up/down counter is modified to produce sine values corresponding to the steps o~ the up/down counter using the following algorithm:
.4) B=(2.~) + (1.~.4) C=~-4 i D~2.4 where, 1. 1,2, and 4 are the LSB to MSB outputs o~ the up/down counter respectively.
2. A, B, C, and D are the LSB to MSB programming inputs to the decade rate multiplier (D/A conv.), respèct-ively.
'I Mixing is provided for the precise tones produced by the circuit. The outputs from the digital to sine con~erts are filter-~ed via a simple R/C-T section to remove the 1.024 MHz component and provide some smoothing of the sinewave peaks.
Adjustable ampli~iers for each frequency provide isolation ~rom the digital circuitry and a low impedance source for mixing and signal distribution. Mixing is done using relatively high value resistor networks for the actual mixing with unity gain l¦ampli~iers to provide an impedance transformation from the high mixer input impedance to a relatively low source impedance for signal distribution. Signal distribution is via twisted pairs with one side grounded.

K. TONE BUFFER (2510~
~ Tone Buf~er circuit 25100 provides interrupted pulse-code-¦modulated (PCM) digital ringing and broadcast tones to the TSI
circuits 24000 in TSI matrix network 403. Circuit 25100 also provides uninterrupted PCM digital precise tones to the tone plant 1145~

interface circuit (optional). Pulse-rate-modulated (PRM) digital imulti~requency (MF) tones received from Toll MF Tone Generator circuit 25070 (optional) are buf~ered by circuit 25100 and sent Ito tone plant interXace 3270. The tones provided by circui-t ¦25100 are derived from the output of precise tone generator 25000 or the output of a toll MF generator 25070.
.' L. TIMING AND CONTROL CIRCUIT ~0 ~
The timing and control circuit 28000 provides signals required by port data store ~3000 to per~orm read, read-modify-write, and write cycles for combinatorial logic ~CL) organization 34000 and .!accesses with call control processor (CCP) interfaces controller 54000. It also provides clock signals for the timing of sequential ~ ''operations in CL organization 34000. In addition, three priority ;: lqueues are located in circuit 28000 for storage of equipment numbers of port equipment positions having active event codes.
Circuit 28000 can be divided into five interfaces described ,below:
1. An interface with CL organization 34000 receives inputs from CL 34000 which indicate when the event code field is zero (no event code stored) and when CL 34000 requires a second read of port data store 33000 to complete the processing of a port.
¦Outputs to CL 34000 serve to gate the first and second (if necessary) reads into the registers in CL 34000 and serve to enable the CL 34000 to send data to data store 33000. In addition, six clock pulses are provided to enable sequential operations in CL organization 3400.
2. A clock distribution and maintenance interface receives the 8-MHz clock. The 4-ms synchronization pulse enables a check for synchronization errors and resets internal counters within circuit ~L4s0~

~128000. Access is provided to reset the error signals and the priority queues.
3. An interface with port data store 33000 provides inputs to enable the storage, in the appropriate queue, o~ the equipment number (EN#) of a port equipment position with an event code waiting to be ac-ted upon by CCP subsystem 408. Parity error Iinputs are also received from data store 33000. Ou~puts to data store 33000 include the 12 bit address bus, row and column :address strobes, an address multiplex control, parity controls, and a signal which indicates whether ths access is being made by CL organization 34000 or by con-troller 54000. A control line is provided which determines whether the trans~er o~ sense bits of other-than-void TDM network 407 will be from data store 33000 or from the parallel-serial binary signal converter ~2000. Enables to gate data to the CL organization 34000 or to controller 54000 from data store 33000 are provided.
4. An interface with CCP inter:faces controller 54000 includes twelve bi-directional lines which either are used to send the address of a desired memory access to circuit 280~0 or are used by circuit 28000 to transfer an equipment number from the queue to the controller 54000O Signals are provided by controller 54000 to indicate that it either requires a memory access or ¦Iwants to read the next entry from an indicated queue. Signals are provided by circuit 28000 to inform controller 54000 of the queue status or of the completion of a memory cycle and to gate ¦data into and out of the controller.
5. A bu~fer control interface provided control signals for the Imemory units in converter control 30000, These include row and ¦column address strobes, address multiplex controls, write enable control, and data transfer enables.

l l M. ~
I The converter control circuit 3000 generates and supplies I,the clock and control signals needed by the parallel-serial ¦binary signal converter 32000 to route other-than-voice sense ¦and control signals between TSI matrix network 403 and the ,combinatorial logic organization 34,000.
Ii I` :
: , N. ~
! Parallel-serial binary signal converter 32000 interfaces . ~ .
between TSI circuits 24000, and port communication subfield '33501 of port data store 33000. Each set of two TSI circuits 24000 are served by a single converter 32000. Therefore, four converters 32000 are required for a 1920-port system containing eight TSI circuits 240000 Converter 32000 receives a serial binary data signals constituting TDM sense data channels SF0~, SFl' and SS0'-SS7' from TSI circuits 24000. It reformats the data bits, and places them in parallel on the tri-state buses for transfer to combin-: ,atorial logic organization 34000 and port data store 33000.
Conversely~ the converter 32000 receives parallel control ¦ binary data from the tri~state buses from port data store 33300, "CL organization 34Q00 and CCP interfaces con~roller 54000, and ¦sends these in serial form to the TSI circuits 24000. mese j serial-to-parallel and parallel-to-se.rial conversions are accom-plished by random-access memories and shift registers contained in converter 32000.
0.~
Port data storage device 33000 consists of a sequentially-accessed RAM ~ontaining a 256-bit port data memory field 33500 to be described in the following section, Fig. 29 for each o~
the 1912 ports served by a TSI matrix network 403. Storage 1~450~g 1~.
l, device 33000 also contains parity check circuitry9 and tri-state buffers for bi-directional input/output data buses. Because 64 bits of each memory field are used for digit storage, ea-^h port leffectively has its own digit storage register.
Timing and addressing for interfacing with combinatorial ¦¦logic (CL) organization 34000, parallel-serial binary signal l'converter 32000, and call control processor (CCP) interfaces ¦Icontroller 54000 is obtained from the timing and control circuit l'28000.
' P ~
1. General Descri~ion.
Combinatorial logic (CL) organization 34000 and call control processor (CCP) subsystem 408 co~municate with the port data , fields 33500. ~ach individual field 33500 provides storage and I 'control information for a port equipment position. Stated another ; way, each port is assigned a dedicated memory field 33500. The data associated with a call state is maintained in the memory ields 33500 of the ports involved in the call.
Referring now to Fig. 2, port related memory field 33500 ' contains the following information subfields: Port Communication ¦¦Subfield 33501; Port Command Subfield 33502; Call State and State Timing Subfield 33503; Response Subfield 33506; Supervision Control Subfield 33510; Through Signalling Subfield 33512; Freeze Control Subfield 33514; Digit Storage Subfield 33S16; P~P Working Storage Subfield 33518; and CCP Working Storage Subfield 33520.
In general, CL organization 34000 performs the real-time functions of system 400. It does this by operating sequentially on a timeslot basis in conjunction with the data in each port data field 33500. CL organization 34000 reads port command subfield 33502 and an appropriate one of its functional logic units executes the command~ CL organization 34000 and its component 1~019 ~,fl~ctional logic units are responsive to the bits in the command llsubfields 33502 of the ports on a time shared basis with all the I ports. Outputs from the ~unctional units which are components !~of CL organization 34000 are either communicated to the port via ¦¦the control channels of TDM sense/control network 403, or commun-icated to the appropriate subfield of memory field 33500.
CL organization 34000 invokes the operation of call control i! processor CCP subsystem 408 by setting a processor request flag (PRF) bit and the event code (EVC) bit area of response subfield 33506. The PRF bit is set when the EN~ o~ the port has been entered into an appropriate queue, which is scanned by the ~executive routine of call control processor stored program 56002.
, . ~ i ~ 2. Port Communication Subfield 33501 - ~ , .
There are 20 bit areas/bit locations which are available for port communication via TDM sense/control network 407. 10 of these I
are bits for communicating from memory field 33500 to the port, via control channels of network 407. These bi-t areas/bit locations are designated with a prefixed "C". Another 10 of these are bits from communicating from the port to memory field 335Q0, via sense channels of TDM network 407, these bit areas/bit locations are liprefixed with an "S"~ Two bit areas of each set of 10 bit areas/
bit locations are termini of fast sense/control data TDM channels (F0 & Fl), and these are updated every 1 millisecond. The remain-ing 8 bits of each set are termini of slow sense/control TDM
channels (S0 through S7), and these are updated every 4 milli seconds. I
Figure 16 shows the assignment of the various bit areas/bit locations in subfield 33501 for different port types.
CL organization 34000 operates on a given memory field 33500 once every 4 milliseconds. Hence, it operates upon 4 samples of 1145~L9 ¦the fast control and fast sense bits at the same time. me 4 isamples of each fast sense bit and each fast control bit are ¦suffixed "A'7; "B"; "C"; "D" in chronological order in real time, ! with "A" being the oldest and "D" being the most recent.
I ~ . Four bit ¦lareas of four bit locations each are used to record real-time fast ¦~sense and control data which are transmitted to and from the port ¦ivia sense/control TDM network 407. These consist of 2 fast ¦Icontrol bit areas (CF0, CFl) and 2 fast sense bit areas SF0, SFl.
The fast control bit areas may be set or reset by either of call ~control stored program 56002 in CCP subsystem 408 or CL organi-~zation 34000 to provide control data to the port. TDM network 407 ; operates without any need for intervention by CL organization 34000 or CCP subsystem 408 to provide 2-way transmission of one imillisecond update of sense and control data.
, ~ ~ Sixteen (16) bit locations of port communication subfield 33501 record the slow channel data. The utilization made of the slow data channel ¦lincludes operation of 2/6 MF coding, operation of ring relays.
ight bit locations (SC0-SC7) are for storing control data to be jltransmitted to the associated port; and eight bit locations (SS0-ISS7) are for storing sense data transmitted from the associated port. The 8 slow sense bit locations are read only memories.
me 8 slow control bit locations may set and reset by either the call control processor (CCP) subsystem 408 or CL organization 34000, to provide control data to the port. me binary data in ¦bit locations CS0-CS7 and SS0-SS7 are transmitted and received, ¦respectively, by TDM network 407 every four mill.iseconds. ~very ¦two milliseconds the binary data from two of the eight bit locations of the control set or sense set are transmitted or received, ~Lg45~

I Fast control bi-t locations CF0A-CF~D and CFlA-CFlD may be lladapted as slow bits by appropriate connections at the port. That is to say they may be used as bits which are updated every 4 milli-,seconds.
To simplify the circuitry of line circuits 2000, the circuit ~updates 4 functions every 1 millisecond. This means that the ISS0, SS2, SS4 and SS6 leads are "ganged" together, as well as SSl, , SS3, SS5, and SS7 leads. In the case of slow sense bit connected I to line circuits, these ganged functions are designated SA and SB.

3. Port Command Subfield 35002 i In general port command subfield 35002 provides an instru- ;
mentality by which call control processor (CCP) subsystem 408 communicates to the port events processor (PEP) 406.
New Command Code (NWC) Bit, One of the bit locations of port command subfield 33502 indicates that the command code in the command ~CMD) bit area is new. This is called the new command (NWC) bit. All command sequencers, timers, etc., involved in the execution of a command are initialized by NWC. mis bit is reset by a combinatorial logic CL organization 34000 after such initial-, ization. It is the function of call control stored program 56002 llin call control processor CCP subsystem 408 to set this bit when ja new command is introduced.
Halt (HLT) Bit. Another bit location of port command subfielJ
33502 is called the Halt (HLT) bit. In order to enable an under-standing of the function of this bit, it will be appreciated that means are required to provide for -the orderly shutdown of port commands in execution in order to avoid illegal and/or undefined port behavior. The setting of the Halt (HLT) bit by call control stores program 56002 causes the port command to halt (or finish) in the shortest possible time. ( in contrast, when a "halt" is ~531~

initiated by CL organization 34000, the universal event code ''halt'' is generated by CL organization 34000.) To avoid reporting ,other event codes after the halt bit is set, the event code (~VC) ¦Ibit area of subfield 33506 is checked for empty and the halt bit is l¦set under protection of the freeze option~
! Command Code (CMD ~Bit Area. Four (4) bits of port command l subfield 33502 which comprises the command code (CMD) are ,~contained in a predetermined area. The call control stored program ~56002 in call control processor (CCP) subsystem 408 requests telephone port related functions (i.e., send digits, ring line, etc.) by setting this field with the desired binary code. The port events processor (P~P) logic 34000 reads this field and enters the functional logic unit or units which process the command. me format of the command field is:

Code Command Descri~tion 0000 No-op 00~1 Receive Digits (RD) 0010 Send Digits (SD) 0011 Sense Supervisory ~vent (SSE) 0100 Transmit Supervisory ~vent (TS~) 0110 Ring Line (RGL) 1111 Spare ~ Twelve (12) bits of information constitute the so-called Arguments 1-6 bit areas/bit locations. These argument bit areas/bit locations provide independent variables which are employed in performing the commanded function.

4. Call State Information Subfield 33503 Call Stat_ (CS~ Bit Area. The CST bit area comprises eight 1145~

~¦bits of information, which represent the call stats (CST) of call - llcontrol stored program 56002. A binary code is assigned to each call state. For example, O = Idle, 2 = Dial Tone-Dial Pulse, etc.
i ~ . In general, call ;control processor ~CCP) subsystem 408 is given access to this bit ¦larea when an event code is generated by combina-torial logic organi-¦lzation 34000. CL organization 34000 detects occurrence of the port Ij conditions which require generation of an even-t code (including timeout" and error conditions). Using access to this bit area, call control stored program 56002 determines which of its component call state transition routines to employ as a result of the detec-tion of the occurrence of the condition. This bit area is updated by CCP subsystem 408 upon completion of the change of Call State by the call state transition routine. Only CCP subsystem 408 may i have access to this bit area.
i Port T~pe ~PT~ Bit Area. The PTY bit area comprises five (5) bits of information, which identify the generic port type (PTY);
~of the port associated with a particular port related memory field 33500. This bit area is used by the CL organization 34000 to deter-mine the generic characteristics of the port. It determines the meaning and uses of the control and sense bits of the port.
The 5-bit, binary code format for this information is shown on llthe following table:
~ ~;
Code Port ~pe 00000 Not Lquipped 00001 Standard Line (1) 00010 S-Lead Line 00011 Unused 00100 TMF sender 00101 TDMF sender 00110 TMF receiver 00111 TDMF receiver iL1450~9 ~

Code Port TyPe 01000 Trunk Loop 1001 Trur~, :E & M
~1010 Trunk, S X S
01011 Unused , 01100 Port Group Control - 01101 Universal Adapter Interface Port Ordinal Call Position Identity Number (PID~ ~ ea.
Four (4) bits o~ information, which represent the so called 'tport ordinal call position identity number1l (PID#) are contained in another area of subfield 33503. This bit area identifies the ordinal position of the port relative to a call state. For example ~in a line to-line call talking state, the calling line is refer-;enced as PID ~1 and the called :Line is referenced as PID ~2. This bit area is accessed only by CC]? subsystem 4080 i ~ . Six (6) bits of information, called a "State Timer" (STO), are contained in another area of subfield 33503. The STO bits specify the duration o~ time after llwhich a timeout type event code is to be generated if conditions ; causing the generation of another event code have not been :
generated. The format of the State Timer field is shown in Fig. 2 where bits 5-4 represent the following scale value:

Bit 5-4 Scale 00 256 msec.
01 2.048 sec.
16.38 sec.
11 131.075 sec.
Bits 3-0 represent the step value, i.e. values = 0 - 15.
The value of the state timer is determined by the product of the scale and step fields. Actual duration is from nominal setting to one step less due to digital graininess.

~L~4~i019 When the whole timer ~ield is filled with binary l's no timing will be performed. Elements of call control stored program 1l56002 in call control processor subsystem 408 initialize the timer Ito the desired value. Combinatorial logic (CL) organization 34000 ~will decrement the "step" field at the "scale" rate.
If port condition which causes generation of an event code is ~¦detected before the timer expires, decrementing of the state timer jis discontinued except during presence of the receive digits (RD) command code in the CMD bit area of port command subfield 33502.
If the state timer decrements to zero before such a port condition .
occurs, the event code for "state timeout" is requested. In this latter case~ the value of the timer is set to "all ones" to prevent , ;~ ~a repeat detection by the expired timer.

~; ; Out-Of-Service ~S2 Bit_Area Three (3) bits of information ~which represent the Out-Of-Service (OSS) condition of the port are ,contained in another area of subfield 33503. The binary code format for this information is shown in the ~ollowing table:

Code Out-Of-Service Condition 000 Spare 001 Normal (in service) 010 Manual O/S Request 011 Manu~l O/S Active 100 Automatic O/S Request 101 Automatic O/S Active 110 Spare 111 Spare This bit area is controlled by the call control stored program 56002 in call control processor (CCP) subsystem 408. Combinatorial logic ~CL) organization 34000 reads the OSS states and inhibits re-porting of event codes during the "OSS Active" states (011 and 101) i~45~

unless the test call bit, to be described next, is set. CL organ~
¦¦ization 34000 performs normally in all other OSS states.
~ The OSS request states (010 and 100) are provided to store a ¦Idecision by an automatic fault detection means (which is beyond the scope of the disclosure of this specification) to take the port out of service because of either manual or automatic action, when - jthe call state precludes immediate action on the port. When the ~¦port goes to the idle call state, the processor will change the "request" OSS state to the "active" state.
, 1 I Test Call (TCL~B t. One (1) bit of information is a so-called Test Call (TCL) bit. This bit is controlled by CCP
llsubsystem 408 and is used to indicate that a test call i3 in progress on this port. CL organization 34000 will operate regard-less os the OSS status, but will not create alarms. Hence, test , calls can progress over out-of-service ports.

Identity of Party (PTI) of a Mu_tiparty Line Bit Area. Four ~l(4) bits of information which depict the identity of the party j'using a multiparty line are also contained in subfield 33503. This bit area can be set by call control stored program 56002 which is ai ' part of call control processor CCP subsystem 408 after receiving a j ., i ,circle digit, i~ applicable. The four (4) bit binary code format '!for this information is shown in the following table:
i Code ~

0000 Party Not Identified 0001 Party 1 0010 Party 2 0011 Party 3 0100 Party 4 0101 Party 5 0110 Party 6 0111 Party 7 ~LI4sals Code ~ y ' 1000 Party 8 1001 Unused 1111 Unused . This one (1) bit of information indicates whether the port is in the operator busy verification ; loop. It is contained in subfield ~350~. When set, the BVB, bit indicates the port is in the busy verification loop. It is con-; trolled solely by call control processor CCP subsystem 408 and itis set when an operator busy verification call originates, and is reset when the operator releases. The module of stored program 56002 which provides the busy verification feature is beyond the scope of the disclosure of this specification.

5. ~
In general, response subfield 33506 provides a means for communication from CL organization 34000 of port eve~t processor (PEP) 406 to call control processor (CCP) subsystem 408.
. One (1) bit of response Isubfield 33506 is the so-called processor request flag (PRF)~
¦¦This bit is set after a new event code is placed in the hNC bit larea and the equipment number ~N# of the related port has been ¦placed in one of the queue registers (physically in timing and ¦control 24000, but conceptually a part of CCP interfaces controlle~
¦54000) which are scanned by the executive routine of call control stored program 56002. This bit is reset by action of stored program 56002 of C~P subsystem 408. When the PRF bit is set, a PRF watchdog timer is initialized and started. It will be stopped by the PRF bit being reset. Should it expire, a signal to an ~4~)19 ¦automatic fault detection means (not disclosed in the present specification) will be generated. The watchdog timeout period is 6 sec. 1 3 sec.
. Another two (2) ¦bits of Response Subfield 33506 specifies the queue to be used for ¦the EN# when new event code is to be entered in the ~VC bit area.
¦Its values are:
, 00 Priority 0 01 Priority 1 Priority 2 11 Spare I This bit area is controlled by call control stored pro~ram 56002 of call control processor (CCP) subsystem 408.
Event Code (E~VC) Bit Area. me so-called "event code" com-'prises four (4) bits contained in a predetermined area of subfield ;33500. The event code is generated by CL organization 34000 in response to conditions at the associated port as communicated via sense channels of sense/control TDM network 407. The event is generated to invoke action by call control processor (CCP) sub-system 408. Call control stored program 56002 utilizes this field , to determine which of its transition routines is to be called to perform a transition to a new call state.
, The event code is cleared by call con-trol stored program 56002 when the call control processor (CCP) subsystem 408 is ready to receive a new event.
The four (4) bit binary code format for the event code is shown in the following table:
Code Event ~ Comment , _ _ 0000 No event code Universal event 0001 Error Universal event 0010 Halt Universal event I

Code ~vent Description Comment 0011 Alarm Universal event 0100 Release Universal event 0101 S-tate timer timeout Universal event 0110 External service request Universal event 0111 Reserve for software generation Universal event of event codes ; 1000- Unique to specific functional 1101 units Cl organization 34000, and described in connection therewith 1110 Spare 1111 Spare ' The "no event code" is simply the absence of any event code.
The "error" event code is written by CL organization 340007 -when the latter detects illegal conditions. The amount of error checking is a function of the design of the individual functional unit of CL organization 34000 in which detection takes place.
The 'Ihalt" event code is w~itten by CL organization 34000~
when a com~anded halt has been accomplished by either an orderly exit of the logie or the command being allowed to proceed to ` completion.
The "alarm" event code is written by CL organization 34000 jwhen an alarm condition is detected while a port is in service (i.e., the OSS bit area of call state information subfield ~3503 is "normal~'.) The "release event" code is written after the supervisory-in bit is on-hook for the specified time, provided the seizure-in bit is set. It is requested by one of two sources. In the presence of a port command "SS~, ONH, TMIN, TMAX", it is requested by a sense supervisory event/transmit supervisory event (SS~/TSE) functional logic unit 38000 of port event processor (PEP) logic ~4~
1, ' li ¦ 34000. Release timing ~hich is performed concurrent with other commands is requested by a logical sequence within a common logic functional unit 36000 of CL organization 34000~
The "state timer timeout" event indicates that the state ¦jtimer has dacremented to zero before an even-t occurs.
¦ The "external service request" event relates to the operation iof an interface port circuit for providing functions normally provided by call control processor (CCP) subsystem 408 fr~om an external means.
The individual events represented by binary codes "1000"
through "1101" are described in the following subdivisions T
thgough W of this Division II, describing functional logic units 38000,40000, 42000/45000 and 44000f45000 in ~hich they are generated.
When more than one euent is detected simultaneously, the ;following rules for priority are used to determine tha code to ,~ 1.
be reported:

"Error over halt, over alarm7 over release, over .~: i. i tlmeout, over port co~mand dependent events".
The generation of a new event code will actuate call control ~processor ~CCP) subsystem 408 to provide a transition in call ~,state~ and in turn a new command to CL organization 34000 In response to any given command, CL organization 34000 controls its ¦condition detecting independent of past history. I'herefore, no further events will be generated, until CCP subsystem 408 makes a transition to a new call state.
An excep-tion to the rule of the last paragraph exists in the ¦case of operation of CL organization 34000 in the presence of a ¦receive digits (RD) command in the CMD bit area of port command subfield 33502. In this situation, the event code for digit count 1~L45~319 is greater than or equal to digit expected (DCT ~ D~X) does not ilcause a call state transition. Stated another way the event does jlnot cause an "exit from" the port command that produced it.
Instead of the DCT '- DEX event code being entered in the EVC bit area, it is stored to be entered into the ~VC bit area when call ¦!control stored program 56002 clears this bit area. However, any I~
¦¦action of stored program 56002 to otherwise cause a state trans-¦!ition while the DCT - DE~ event code awaits clearing of the EVC
bit area prevents the DCT ~- DEX code from being subsequently written. In the latter case, the NWC bit will be "set" to indicate to CL organization 34000 to ignore any such pending event code.
Lo~c OPeration Associated With The Event Code Bit Area. Some l~of the intricacies of the setting o~ the EVC bit area will be better understood with reference to the logic flow chart of Fig. 17.
An event code request, which consists of an internal signal within CL organization 34000 from one of its functional logic units, represented by a block 33506a, initiates the ~ollowing ;~ ,genaralized logical sequence.
The main loop o~ the flow is through steps 33506a through i 33506f. Under normal conditions, step 33506f will write the ~requested event code if an event code is requested (decision step 33506d) and no event code is present in the event code area ¦(decision step 33506c). Should no event code be requested, decision step 47006d provides for an immediate return to the beginning of the loop. Should a new command bit (NWC) be present, a new command is initialized and decision step 33506b prevents ¦any action. Should the halt bit be set (decision step 33506e) ¦process setp 33506g will cause the '1halt" event code to be written, rather than the requested event codea Should an event code be present in the EVC bit area, decision step 33506 causes ~he logical sequence to branch to another loop Icomprising steps 33506h, 3~506j, 33506k and 33506m, which handlés jlsetting up the queue ~hich is scanned by the executive routine of ¦Istored program 56002. Process step 33506k cVmm~nicates the equip-I ment number (~N#) of the port associated with the memory field 33500 to the call processor via the queue if the queue is not full, as determined in the preceding decision step 33506j. A full queue ¦¦causes the logic sequence to return to the begi~ning and a new attempt at inserting the equipment number into the queue will be made during the next time slot in which PEP logic 34000 operates ~upon the memory ~ield 33500. When the equipment number is .. ;
i inserted in the queue by step 33506k, the consecuti~a step 33506m sets the PRF bit (also in subfield 33506) which is used to alter the logic look. In subsequent iterations through the loop the answer to decision step 33506j will be "yes", which in turn will ¦Icause a sequence to branch around steps 33506k and 33506m, Finally, decision steps 33506m and 33506n are designed to ! remember event codes which may be requested during the time an ¦'event code is present in the event code area. This is necessary ,Ifor those event codes which do not cause a eall state transition.
,, , 6. Supervision Control Subfield 33510 Supervision control subfield 3~510 senses and controls super-~vision incoming and outgoing at the port and the recognizition of its states. me supervisory-in, (SPI), release timing enable (RL~) and seizure-in (SZI) bits relate to sensing of incoming supervision~
~ 8n~ q3~=~lL ~ . This bit indicates the current in-coming supervisory state. This bit is controlled by CL organiza-¦tion 34000 and it is set and reset following the incoming super-vision at the port. mis information is provided by the fast sense bit area (SF0) in port communication subfield ~3501 coming .5'~

iin from the port. Within CL organization 34000 there is digital ,filtering applied to this data stream, with a time constant of about 16 milliseconds. During execution of a receive digits (RD) command, -this filtering is reduced to a time constant of about 8 ¦milliseconds~ It will be appreciated that in the perfo~mance of !' this ~iltering, bits with historical data are required. They are ji ;contained in the LLl and LL2 bits of port event processor (P~P) working storage subfield 47018 to be later described.
, ~ . mis bit indicates whether the port is in a seized or non-seized state, mis bit is set by CL organi-zation34000 when the port command requires the recognition of ; seizure. It is reset when either the operation of the release detecting logic of CL organization 34000 pursuant to a port command or the operation of an automatic release timing function also in CL organization 34000 detects a release. (me automatic `timing function operates without need of a command.) It will be apprecia~ed that the term "Seizure" as used in describing this bit location refers to continuous incoming off-hook supervision.
It includes seizures, answer supervisions~ CAMA reversals, etc.
Release Timin~ ~nable (RL~) Bit~and Release Timin~ Speed . These two bits which are compositely known as the "release timing bits", provide ~or release timing ~,specification~ I
Release timing can be specified either by a port command lnstruction, or cocurrently ~with other port commands. When Release, Timing is speci~ied by the port command ~SSL, ONH9 TMIN, TMAX", by means of CL organization 34000, the detection of a release event is performed by sense supervisory event/transmit supervisory event (SSE/TS~) functional unit 3BOOO. CL organization 34000 will ignore the release timing bits in this case.

i~4S~19 .
When release timing is concurrent with other commands, release timing is performsd as specified in the release timing bit when the llrelease enable (RLE) bit is set. Release timing will only monitor I the state of the supervision-in (SPI) bit when the seizure-in (SZI) ¦¦bit is set. Otherwise no timing of the SPI bit is performed. When a release is detected under these conditions, the universal event code ~release~ (0100) is requested In either case, the seizure-in (SZI) bit is reset when a release is detected.
Release timing will start at -the time the state of the super-vision in (SPI) bit changes to on-hook, or should the SPI bit be on-hook at that time immediately after the change in command.
When the release timing speed selector (RSP) bit is set, this specified that 20 millisecond release timing is used. If not set, the standard 180 millisecond re:Lease timing is used.
The formats of the release timing enable (RLE) bit, and of the release timing speed selector (RSP) bits are as follows:
RL~: Release Timing Enable 1 = Enable ; O = Disable 1~ RSP: Release Timing Speed Selector O = 180 milliseconds with tolerances of ~20 milliseconds O milliseconds 1 = 20+ 4 milliseconds

7. T~ h Si~nalling Subfield 3~512 ¦ The items of information stored in through signalling subfield 33512 is part of a through signalling system which provides a cap-i ; ability for real time, port-to-port communication7 This communi-cation takes place over four through signalling highways and time-slot interchange RAMs at a 4 millisecond rate under control of subfield 33512.

i The main application of this system is to provide end to end I signalling and supervision during the conversation phase of calls through the office. It is also used when several ports must operate in real time correlation for the proper execution of ¦commands (i.e., party test interacting with the ring-line port type ¦of operation.
. This bit area contains the equipment ~umber of the port from which through signalling is to be received.
Throu~h Signallin~ Send Data (THSD) Bit. This bit contains the data -to be sent through the -through signalling system at the ; ~next synchronous access.
Through Signallin~ Send ~nable (THSE) Bit. This bit, if set, causes updating of THSD bit from supervisory-in (SPI) bit of sub-field 33510 every 4 microseconds.
Throu~h Si~nallin~ Receive Data ~THRD) Bit~ This bit contains the last data recei~ed from the through signalling system.
Throu~h Si~lallin~ Receive Enable (THRE~_Bit. This bit, if .
set) causes the THRD bit to control the outgoing supervision of the port.
When there is a conflict for the control of outgoing super-vision between a port command and "through signalling", the port ¦¦command has priority, and through signalling is ineffective.
On certain ports there may be other bits which must be controlled for proper action. ~or instance, the shut SH relay in the loop T~K is required for proper pulsing. The through signall- ' ing system will not operate the SH relay function.

8. Freeze Control _ubfield 47014 The two (2) bits within subfield 47014 are part of a freeze control system which i~hibits changes to the port data field 33500, ~ i l ~
! with the exception of changes which are -the result of any one of:
, (i) random access from call control processor (CCP) subsystem ¦ 408; (ii) operation of the freeze control system itself; and (iii) updating of sense bits. The function of the freeze control system ¦¦is to provide non-ambiguous modification of data field 33500 by ~guaranteeing no changes in field 33500 during a situation in which the CL organization may respond to illegal and/or ~ndesired trans ¦~itional states in port data field 33500 during modification cycles~
caused by call control processor (CCP) subsystem 408.
CL organization 34000 is stopped during the time the freeze is in effect. Hence, the operation of the freeze control system tends to cause a real time error to be made in the operation of CL organ-ization 34000. For this reason, the freeze operation cannot be used without discrimination. Hence, a timeout on the freeze is necessary.
. This bit is controlled by call control pro-cessor (CCP) subs~stem 408. Whi:Le it is set all write actions into port data field 33500 are inhibi-ted with the exception of data '!written therein by CCP subsys-tem 408.
. This bit is set by the call control processor (CCP) subsystem 408 when a freeze is commanded. The first timeslot in which CL organization 34000 operates upon port ¦data field 33500 after the freeze is in effect will reset it. The timeslot in which CL organization 34000 operates in conjunction with data in port data field 33500 after the freeze is in effect will cause timeout. The FRZ bit will be reset and the n~ mal operation of P~P logic 34000 is resumed.

9. Di~it Stor~, Sub ~
The digit storage subfield 47016 provides storage for up to 16 4-bit digits and related pulse counts and information for index-,ing. Combinatorial (CL) organization 34000 re-trieves digits from this area when sending digits and stores digits here when receiv-ing digits~ This area may be used as a working storage area CL
llorganization 34000 is not receiving or sending digits.
~ G mis four (4) bit area contains the index for fetching or storing the next digit. When receiving digits, this bit area is updated by CL organization 34000 when a , digit is stored. When sending digits, this field is used to ~etch ,the digit and is updated to the next digit after the digit has been outpulsed. It is the function of call control stored program , 56002 of call control processor (CCP) subsystem 408 to initialize this field. A ring line (RGL) functional logic unit 40000, which is one of the component functional logic units of P~P logic 34000, uses this bit area as a working storage area.
. This four (4) bit area contains the current number of on-hook pulse intervals or digits in binary code format. Combinatorial logic (CL) organization 34000 utilizes !
;this ~ield for immediate storage when sending and receiving digits.
When receiving dial pulse (DP) digits, this field contains the ,current number of on-hook pulses detected. CL organization 34000 ~i ,clears this field when the digit is stored, When receiving MF
digits, the PCT area is used as intermediate storage from beginning to the end o~ the tones. When sending, the digit to be sent is temporarily stored in PCT During DP sending, the PCT area is ~, decremented after each pulse sent. Ring line (RG~) functional logic unit 400Couses this field as a working storage. I
Di~it 0 - Di~it 15 ~64 Bits~. This area provides storage for 16 4-bit digits in binary coded format.
I 1.

10. P~P Workin~ Stora~e Subfield 33518 Timer 1 Bit area and Timer 2 Bit Area. ~ach of the two timer ¦¦bit areas in word 6 consist of 8 bits. They step from 0-63, with the time periods specified by their respective 6th and 7th bits.
e code format for the bit time period specified by the 6th and 1,7th bits is as follows:
i CODE FORMAT TIME PERIOD
¦ 00 5 Milliseconds ~ ! ol 16 Milliseconds 500 Milliseconds If bit 6 and 7 are both ls, the scale is disabled and a new scale is defined by the Argument 3 and Argument 4 bit areas of subfield 33502.
; ~ . me port event processor state (PEPS) bit area indicates the current port event processor ~state in conjunction with the operation of combinatorial logic ~ 1 (CL~ organization 34000.
Ii RLSC Bit Area. The RLSC bit area indicates the current state ,f the release timing function in con~unction with the operation of ~CL organization 34000.
' ~ . Bits LLl and LL2 are the so-called , ''last look bits". m ey provide the historical data required in connection with the digital filtering of incoming supervision in 1Ideriving the supervisory-in (SPI) bit status.
;' ~ . The CTRL A and CTRI B bits indicate which ringing control (A) or (B) is on-line in conJunction with the operation of ring line (RGL) functional logic unit 400~ m ey ¦are also used for other working storage purposes in conJunction with the operation of the other functional logic units in combinatorial logic (CL) organization 34000.
Release Timer (RLST) Bit~Area. The release timer bit area is set to a timeout period of either 20 milliseconds or 208 milli-seconds by the RSP bit in supervision control subfield 33510 when ;3~9 Il ~an on-hook is detected. When the timer is the decremented to zero, ¦'a universal "release" e~ent code is generated by combinatorial ! logic (CL) organization 34000.
i

11. Main Processor Sçratch Pad Subfield 47020 ¦ Words 14 and 15 contain scratch pad areas SCRl and SCR2 for luse by call control processor (CCP) subsystem 408.
. ~ ~

QO COM3INATORIAL LOGIC ORGANIZATION ~4000 Referring now to Fig. 18~ what is shown is a diagrammatic and not a conventional block diagram. This diagrammatic has as its purpose the illustration of the control of enablement of the functional logic units. In order to accomplish this purpose, the snapshot registers and decoders which are in~olved in the logical control of enabling the individual functional logic units are shown as though they were apart from the functional logic units which they control. In fact these snapshot registers and decoders are parts of the circuit assemblies which comprise the functional logic units. The actual location of the snapshot registers and decoders (as opposed to their representation as separate elements in the diagrammatic of Fig. 18) may be identified through their reference character. The reference characters a~e of the numerical series of the functional logic unit which actually contains the snapshot registers or decoders. For example, command register ~6001 and command decoder 36005 are in actuality contained within ¦
common logic unit 36000 as may be discerned from the fact that their reference characters are in the 36XXX series.
Reference is now made to Fig. 18 which is a diagramatic (i.e.,l not strictly a block diagram) of combinatorial logic (CL) organi- ¦
zation 34000. For purposes of emphasi7ing the logical circuits for enabling the individual functional logic units, the logic ~L145~

elements involved in enabling these units are shown as though llthey were apart from the functional units which they enable. In liactuality logic elements controlling enablement of individual functional logic units are contained within such logic units In the diagrammatic of Fig. 18, the circuit assembly of which an jelement outside of the dashed-line block 34000 is part, may be identified by their reference characters series. For example, command register 36000 is identified as a part of common functional logic unit 36000 because it is designated by a 36XXX reference character.
A series of snapshot registers 36001, 36002, 38001, 40001, 42001, 44001 and 45001 serve as buffers between the port data field 33500 and the units of CL organization 34000 which perform the processing.
; Command code snapshot register 36001 holds the coding of port command subfield 33502, Fig. 2. It is operatively connected to a command decoder 36003. A series of combinatorial logic (CL) state registers ~6002, 38001, 40001, 42001, and 44001 hold the I combinatorial logic state (CLS) bits read from P~P working storage subfield 335180 Their output is connected to a series of CL state decoders 36004, 38002, 3800~ 40002, 42002, and 44002.
¦ Combinatorial logic (CL) organization 34000 is comprised of the ~ollowing set of functional logic units, each of which is formed as a discrete printed wiring board circuit assembly.
Common functional logic unit 36000 provides logical progres- ¦
sions which are shared in the operation o~ the other functional logic units, as well as a few miscellaneous logical progressions which do not relate to any other unit.
l Sense supervisory event/transmit supervisory event/supplement ¦to common unit 38000 provides three functions. First is a sense supervisory event (SSE) function which is comprised of logical progressions which sense incoming supervision along line or trunk j!
, I'circuits. Second is a transmit supervisory event (TS~) function l~which is comprised of logical progressions for generating the following port supervisory signals: (i) wink, (ii) hookflash, I,(iii) wink off, and (iv) delay dial. The third function consists llof logic which supplements the logical functions o~ common logic ¦lunit 36000. The arrow extending from unit 38000 to unit 36000 ¦!depicts this role of unit 38000 in supplementing the functions of i lunit 36000.
Ring line (RGL) functional logic unit 40000 causes ringing to be applied to line circuits, until a ring trip or special termin~
ation for special ringing occurs.
Send digits (SD) functional logic unit 42000 operates in conjunction with receive digits (RD)/send digits (SD) functional logic unit 45000 to store digits in digit storage subfield 33516, to be sent to the port circuit for outpulsing. Unit 42000 also ',~updates the digit count bit area o~ subfield 33516.
Recei~e digits (RD) functional logic unit 44000 operates in conjunction with RD/SD unit 45000 to provide logical progressions which collect and rack the digits received at the port circuit.
;These digits are sent to digit storage subfield 3~516. The digit count (DCT) bit area of subfield 33516 is utilized as a pointer by ,logic unit 44000 for the placement of the next digit to be stored.
The functions of RD/SD unit 45000 in operational association ~ with SD unit 42000 and RD unit 42000 was mentioned. In addition : ~ RD/SD unit 45000 contains the snapshot register for holding the status of the CTRL A and CTRL B bit locations of P~P working storage 35518. Tha outputs of -this register are communicated (not shown in Fig. 18) t,o SSE/TS~/supplement to common unit 38000, RGL unit 40000, and SD unit 42000.
As previou51y discussed CL logic organization 34000 strobes each port data field 33500 ~or a 1.95 microsecond scan period.
This scan period is the time during which the particular port data ~bP~

field is addressed by the address counters within timing and control circuit 28000. (This address counter is later herein identified as counter 28022, Fig. 19).
The functional logic units provide up to two parallel logical operations which are performed during a 1.953 microsecond scan period. One of these is the logical operation of common logic unit 36000, which occurs during every scan period. Unit 36000 performs such functions as state timing, release timing, port decoding, and generation of event codes (~VC's) which must go on I ! regardless of what other operation is being performed. The other logical operation is an operation provided by a selected one of unit 38000, unit 40000, unit 42000 in combination with unit 45000, and unit 44000 in combination with unit 45000.
In general, the command code present in snapshot register 1 36001 which, if any, of units 38000, 40000, 42000 and 45000 in I l combination, or 44000 and 45000 in combination are enabled tooperate in parallel with unit 36000. In addition, the setting of ,, the CTRL A and CTRL B bits in shapshot register 45001 sometimes plays a role in determining which unit is enabled.
The opera-tion of the logical progressions during a given 1.953 microsecond scan interval may include changing the combin- ¦
atorial logic state (CLS) and transmitting the new CLS back to ¦snapshot registers 38001, 40001, 42001 and 44001 (as well as the CLS bit area of subfield 33518) via tri-state bus BCLS ~-4. The combinatorial logic states (CLS) are instrumentalities which provide "~umps" between different logical progressions within a functional logic unit, or between different ~unctional logic ; units~
Stated another way, one of the series of state decoders 36004,~
38002, 38003, 40002, 42002 and 44002 reads an existing CL state, and thereby enables the appropriate ~unctional logic unit to ~i operate upon it, including the capability to make a logical deter-mination to jump to a new CL state. The new state is entered in operation subfield 33518 and in the various snapshot registers.
At such next scan of the port, one of the state decoders responds ¦¦to the new state causing the appropriate logic unit to operateO
, Each of the ~unctional logic units other than common unit ¦ 36000 provide the portions of a sequence which make a determination ithat an e~ent code (~VC) is to be entered into subfield 35006.
~However, the actual changing of the ~VC is performed by a jump to common functional logic unit 36000, which contains a logical pro-gression 3600~ for changing subfield 33506. The changed event code is sent to subfield 33506 via bus B~VC 0-3.
There are two logical sequences of common functional logic unit 36000 which are activated concurrently with the operation of .
iall the functional logic units. One of these is a "state time-out" logical progression 36008. me other is a "rslease timing"
logiaal progres~ion 36009.
The other major path between CL organization 34000 and port ;
data field 3~500 (there are other minor paths) are the buses for write/read access to and from the binary control bit areas and bit location and the binary sense bit areas and bit locations of port communication subfield 33501. That is the buses for writing isubfield 33501 bit areas/locations CF0, CFl, CS0-CS7 and ~or ireading bit areas/locations SF~, SFl, SS0-SS7, as depicted in ~the drawing.
. I
R. ~
' Common functional logic unit 36000 card operates primarily ¦in conjunction with the other functional logic unit of Telephone ¦Preprocessor 34000 as they perform their functions. Logic Unit 36000 receives Combinatorial Logic State (CLS) codes and command l, :
l.
¦ (CMD) codes from port data fields 33500 and uses these to generate ¦ event codes for "Jumps'l to other functional logic units. In ¦Iaddition, the card performs state timing, release timing9 and ¦Iport type decoding.

, S S~NS~ SUPERVISORY EVENT SS~ TRANSMIT SUP~RVISORY ~VENT

¦l 1. Basic DescriPtion The sense supervisory 0vent (SSE)/transmit supervisory event j ';(TS~ supplement to common functional logio unit 38000 senses and transmits supervisory signals ~rom and to the ports. It does thisl via the instrumentality o~ the binary sense and control bit areas , and bit locations of subfield 33508~ It also includes a Timer No.
1 and a Timer No. 2. Unit 38000 is a printed wiring board unit l containing mainly integrated circuit components.
; ,i Unit 38000 provides the SS~ functions of detection of one ,of the following types of eventsV according to the SS~ command it I i ireceives: (1) seizure/release; (2) wink/hookflash; (3) stop Idial; and (4~ delay dial. Arguments 1 and 2, which are bits within subfield 33503, speci~y the type of event to watch for.
i'Arguments 3 through 6, which are bits or bit areas within subfield -~ I 33502, give timing information. Upon command, SSE monitors the ~; Iport and times the conditions, reporting the particular event if detected.
Unit 38000 provides the TSE function of sending signals to the port to generate one of the following ~unctions: (1) wink;
(2) hookflash; (3) wink off; and (4) delay dial. The 6 Arguments serve functions similar to those for SSE. Upon command, TS~
uses the timers to generate the specified event.
In addition, logic unit 38000 supplements common logic 36000 by providing timer operations (Timers 1 and 2). It also i includes incoming supervision filtering and detection operations to the other functional logic units.

,, ! 2. Functional DescriPtion of the on of l Logic Unit 3~000 with CP Subsystem 408 I' ja. General i The presence of a binary code 0011 in the Command (CMD) bit ~area of port command subfield 33502 enables functional logic unit 38000 to operate to sense supervisory events. Logic unit 38000 responds to the setting of the Arguments 1-6 bit areas of subfield ~1 33502 to selectively sense one of the ~ollowing supervisory events:
Seizure Release Wink Signalling Hook Flash Signalling End of Stop Dial Signalling (sometimes referred to as "Stop-Go" Signalling) End of Delay Signalling (sometimes referred to as "Delay Pulse Signalling", "Delay Dialing A", or "Delay Dialing B") Further, certain timing factors associated with sensing ,~these functions are adjustable.
The tables of Figs 20A through 20D describe the formats of the Argument bit areas in relation to the selection of supèrvisory events to be sensed; and in relation to the selective adjustment of a minimum time period threshold (TMIN) and of a maximum time period threshold (TMAX) associated with the supervisory event.
When unit 38000 completes its function, it selectively causes the entry of one of two codes into the ~VC bit area o~ subfield 33506.
The format of these codes is described in Fig. 20I.

1~L450~L9 li I, !I b. Ground Rules Which Underlie The Formats The settings o~ Arguments 1-6 define the selection of the ¦~supervisory event to be sensed and define the adjustment of any l,associated minimum and maximum time period thresholds in accord-¦jance with the following basic ground rules:
1. Any supervisory event lasting less than the specified minimum time period threshold (TMIN) is totally ignored.
2. Any supervisory event exceeding the specified maximum time period threshold (TMAX) is reported as an ~xcess Event.
3. Specifying a minimum time period threshold (TMIN) of zero and a maximum time period threshold (TMAX) of infinity, will cause an arbitrarily long event to be detected.
~` ` ;
4. Specifying a maximum time period threshold (TMAX) o~
, zero with a finite maximum time period threshold ~TMIN) will cause an event code (~VC) to be generated when the event is present for the specified TMIN. This form of specification can be used for both seizure and release detections.
5. Interruptions (of on-hook or off-hook supervision) which are less than 18 milliseconds in duration are ignored.
A change from on-hook to off-hook, or vice versa9 is only recognized after a minimum of 18 milliseconds (MSEC) ¦
o~ continuous opposite supervision. I
6. When logic unit 38000 per~orms a release sensing function, any release sensing function which happens to be specified by presence of a ~ bit in the RLL bit area of subfield 33510 is inhibited. Stated another way, the SS~ command code plus the setting of Arguments 1-6 to cause logic i.
~i unit 38000 to sense a release, takes precedence over the operation ! of common logic functional unit 36000 to sense a rele~se when the i1iRL~ bit is set.
i~ c. ~
i Referring again to Figs. 20A through 20I~ Arguments 1 and 2 ¦of subfield 33502, Fig. 2, together specify the basic type of event to be sensed or detected. The four basic events to be ~sensed are: (1) on-hook transitions5 (ii) off-hook transitions, (iii) stop dial, and (iv) delay dial. Arguments 3 and 4 specify the value of time scale to be employed in specifying TMIN and TMAX. Argument 5 specifies a TMIN multiplier, which when ,~multiplied with the time scale provides TMIN. The resultant ~value of TMIN, i.e., the minimum time period threshold, represents the minimum duration of time which must be detected in order to confirm that an event is sensed. Argument 6 specifies a TMAX
multiplier, which when multiplied with the time scale provides TMAX. The resultant value of TMhX, i.e., the maximum time period ~threshold, represents the maximum duration of time which may be detected in order to confirm that an event is valid.
Arguments ~ and 4 specify time scales of 16, 64 or 256 milli-seconds~ as depic-ted in Fig. 20B. Argument 5 may specify the ~"base 10 integers1' 0 through 15 as depicted in Fig. 20C. Argument ¦6 may specify the "base 10 integers" 0 through 14, and also a setting of infinity ~00), as depicted in Fig. 20D.
d. Format For Sensin~ "Seizure" or "Release" Supervisor~ ~vents In order to sense the "seizure" supervisory event the following settings of Arguments 1-6 will be provided: (i) Argumen-ts 1 and 2 ~re to specify "off-hook"; (ii) Arguments 3, 4, and 5 are -to speci.fy the required minimum seizure recognition time; and (iii) Argument 6 is to be set to zero.

Reference is now made to the timing charts of Fig. 21. mey ¦Idepict various cases of timing of the transition from on-hook to , off-hook occur relative after the SS~ command is recei~ed.
If the incoming supervision is not off-hook when the command is received (case A),logic unit 38000 starts timing an incoming ¦ioff-hook supervisory signal when the transition to off-hook status itoccurs. If the incoming supervision is off-hook when the command is received (cases B, C, and D), the timing is started immediately.
If the off-hook signal is sustained for the minimum time ~period threshold as specified by ~rguments 3, 4~ and 5, a seizure is detected (cases A~ B, and C). Thereupon, logic unit 38000 J
causes a jump in Combinatorial Logic State (CLS). This in turn causes common functional logic unit 36000 to generate the ~nd of Task code (1000) to be entered into the ~VC bit area of subfield 33506. After this logic unit 38000 ceases to perform a seizure sensing.
If an on-hook signal occurs before the seizure is detec-ted, the off-hook timing is ignored and the unit 38000 continues to look for a seizure event (case D).
The sensing of a Release is the complement of sensing for seizure. The only difference in format is that Arguments 1 and 2 l¦must specify on-hook as opposed to off-hook.
~e.
In order to sense a wink supervisory signal, the following settings of Arguments 1-6 will be present. (i) Arguments l and 2 are to specify "off-hook"; (ii) Arguments 3 and 4 are to specify the Time Scale, and Arguments 5 and 6 are to specify the TMIN
Multiplier and the TMAX Multiplier, respec-tively.
Reference is now made to the timing charts of Fig. 22 for a description of what happens with various cases of timing of the transition from off-hook to on-hook relative to when the command is received.
1 In the event that incoming supervision is not off-hook when ¦¦the SS~ command is received, logic unit 38000 does not start a ¦¦timing action until the incoming supervision changes to off-hook ¦~(cases A, C, and D).
If the incoming supervision i3 off-hook when the command is received, the timing is started immediately (case B). Should supervision return to on-hook before TMIN (case C), the timing ; .
~operation is stopped and logic unit 38000 continues to sense incoming supervision for winks. Should the supervision return to on-hook after TMIN but before TMAX (cases A and B~, logic unit 38000 actuates common functional logic unit to enter the ~nd of Task code (1000) in the ~VC bit area of subfield 33506, and ceases to perform monitoring for a Wink. Should the off-hook s-tatus continue beyond TMAX (case D), logic unit 38000 activates logic unit 36000 to enter the Excess ~vent code (1001) in the ~VC
bit area of subfield 33506. mereupon, logic unit 38000 cPases to per~orm monitoring for a wink. The fact that the ~xcess ~vent code is entered into the ~VC bit area represents what is sometimes referred to as the "Excess Wink" conditionc The sensing of a hook flash supervisory event is the comple~ , ¦ment of sensing a wink event. The only difference in format is that Arguments 1 and 2 specify on-hook as opposed to off-hook.

In order to sense the end of a stop dial supervisory signal the following settings of Arguments 1-6 will be present: (i) Arguments 1 and 2 are to specify Stop Dial; (ii~ Arguments 3, 4, and 5 are to specify the required delay time before monitoring for end of stop dial; and (iii) Argumen-t 6 is to be set to zero.

~Ll4sals Reference is now made to Figa 23 for description of what happens with various cases of timing of the translation from o~f-hook to on-hook status relative to when the command is received.
me timing for the specified minimum time threshold (TMIN) ;~ commences simultaneously with the enablement of logic unit 38000 in response to receipt of the sense supervisory event command code (1000) in the ~VC bit area of subfield 33506. After TMIN
j¦is timed out, and ~nd of Stop Dial is recognized as soon as the ¦on-hook incoming supervision signal is detected. Thereupon, logic unit 38000 actuates common functional logic unit 36000 to cause ~the End o~ Task Code (1000) to be written into the EVC bit area of subfield 33506. Once this is done logic unit 38000 ceases to ~,perform monitoring for End of Stop Dial.
g. Format :Eor Sensin~ E~d of a Dela~ Dial Signal In order to sense the end of a Delay Dial supervisory signal, !
¦the following settings of Arguments 1~6 will be present: (i) ¦
¦¦Arguments 1 and 2 are to specify delay dial; (ii) Arguments 3, 4, ¦iand 5 are to specify the Minimum Time Period Threshold (TMIN) ¦over which a delay dial signal should be present; and (iii) ¦iArgument 6 is to be set to zero.
Reference is now made to the timing charts of Fig. 24 for a j¦description of ~hat happens with various cases of timing of the jtransition from off-hook to on-hook status relative to when the command is received. Logic unit ~8000 starts monitoring the in-coming supervision signal for an off-hook condition at the time when logic unit 38000 is enabled in response to receipt o~ the SSE command code (1000) in the EVC bit area of subfield 33506.
If an off-hook status signal is not received before expiration of TMIN, logic unit 38000 activates common logic unit 36000 to cause the excess event code (1001) to be written in the EVC bit area of subfield 33506(case B~. mereupon logic unit ,l38000 ceases to perform sensing of the End of Delay Dial.
If the transition from on-hook to off-hook occurs before iTMIN (case C), logic unit 38000 ignores the transition and waits ~ until a subsequent transition from off-hook to on-hook before ¦¦recognizing an end of Delay Dial. The recognition of end of a IDelay Dial signal for other cases are depicted in cases A and D of Fig. 24.
ilh.
.
There is logic circuiting for the orderly shutdown (called a ~'halt" sequence) of the relays equipment in the port positions, in order to prevent their unauthorized operation. (Unauthorized oper-ation of -this equipment can cause annoying momentary ringing of the subscriber's telephone set or damage to relay contacts) This . .~
circuitry (not shown in the drawings for Divisions I, II~ or III3 is partially within the functional logic unit which is executing the command instruction to be halted, and partially within common ;logic unit 36000. The circuitry for implementing a halt operation !
Ls initiated by the presence of a HLT bit in port command subfield ;33502. That bit location is set by call control stored program 56002. When a halt seauence is finished, CL organization sends a "halt" event code to the ~VC bit area of response subfield 1i33506.
However, the operationof the sense supervisory event (SSE) function does not change the status of th~ telephone network external to switching system 400. Therefore~ this function can be interrupted or halted at any time without adv~rse effects.
Accordingly, when the SS~ command code ("0011") is present in the CMD bit area of subfield 33502 it may be changed to a different command code without need ~or recourse to a special halt sequence.

!
i j 3. Functional DescriPtion of the Interaction ,I CCP Subs~stem 408 a. General The presence of a binary code 0100 in the command (CMD) bit ¦larea of port command subfield 33502 enables functional unit 38000 ¦¦to operate to transmit supervisory events. Logic unit 38000 res-ponds to the setting of the Arguments 1-6 bit areas of subfield l33502 to selecti~ely transmit one of the following supervisory '`events:
1. Wink-Off 2. Wink (sometimes referred to as a "temporary off-hook"3 3. Hookflash (sometimes referred to as a "temporary on-hook") 4. Delay Dial Further, certain timing factors associated with the transmis-,sion of these events are adjustable.
The tables of Figs. 25A through 25~ describe the formats of ~the Argument 1-6 bit areas o~ subfield 33502, Fig~ 2 in relation to the selection of supervisory events to be transmitted, and in relation to the selective adjustment of: (i) the duration of event, and (ii~ the seizure recog~ition time which is to expire before transmission of a delay dial signal. Upon completion of its function, unit 38000 actuates unit 36000 to write an "end of 'task" code into the EVC bit area of subfield ~3506. The format of this code is described in Fig. 25 b~ ~
Referring now to Figs. 25A through 25D~ Arguments 1 and 2 to-gether specify the type of supervisory event which is to be trans- !
mitted. The four types are: (i) wink-off; (ii) wink; (iii) hook-flash; and (iv) delay dial. Arguments 3 and 4 specify the value I

of time scale to be employed in specifying duration o~ event and ¦ISeizure Recognition Time Period. Argument 5 specifies the "dura-tion of event multiplier", which when multiplied by the time scale provides the duration of event. Argument 6 specifies the "seizure recognition time period multiplier'?, which when multiplied b~J the ,time scale provide the '1seizure recognition time period". This ¦¦period is the period of time over which seizure must be recognized ¦before a Delay Dial signal is transmitted.
Arguments 3 and 4 may specify time scales of 16, 649 or 256 milliseconds, as depicted in Fig. 25B. Argument 5 and 6 each specify any one of the "base 10 integers" 0 through 15 as depicted in Figs~ 25C and 25D, respectively.
c. Format for Transmittin~ a "Wink-Off" Event In order to transmit the "wink-of~" supervisory event the following settings of Arguments 1-6 will be provided: (i) Argu-ments 1 and 2 are to specify "wink-off"; (ii) Arguments 3, 4 and 5 are to specify the duration of the wink-off event; and Argument 6 is not used.
This command is only valid on sleeve control trunks. The ground on the sleeve is interrupted for at least the time specified ! in Arguments 3, 4 and 5 and until the SZI bit location of subfield, ~ l ;~1 l33510 recognizes the release (the RSP bit location is set in con-¦ijunction with this command). The sleeve is reenergi~ed, and logic unit 38000 actuates common functional logic unit 36000 to enter the End of Task Code ("1000") in the ~VC bit area o~ subfield 33506.
Reference is now made to the timing diagram of Fig. 26 for a description of what happens pursuant to alternate situations of timing of the telephone network response relative to when the command is received. (These alternate situations are represented by the solid line timing chart and by the phantom line timing s~ ~

chart, respectively.) When the command is issued, logic unit 38000 immediately causes the sleeve ground to be interrupted, and to remain open for the duration of event specified by Arguments 3, 4, and 5. As a response to the sleeve interruption, Ithe originating end of the trunk will go on-hook. mis on-hook !i condition is first recognized by the supervisory-in (SPI) bit in ¦Isubfield 33510 going to its on-hook state, then after release ,timing, the SZI bit goes to its on-hook state. If SZI is already on-hook unit 38000 will restore the ground on the sleeve at the ~end of the specified duration of events (as depicted by the solid line timing chart). I
The case in which SPI is off-hook at the end of the duration 1, of event is depicted by phantom lines. Unit 38000 will wait until SZI goes on-hook and only then restore the ground on the sleeve.
Upon restoring the ground on the sleeve, logic unit 38000 actuates common functional logic unit 36000 to cause the end of ~ i task code (1000) to be entered into the ~VC bit area of subfield 33506, and logic unit 38000 ends its operation.
d. Format for Transmittin~ "Wink~' Su~ervisorv Si~nal In order to transmit the "Wink" supervisory event, Arguments 6 are used in the same manner as for selecting the transmission ¦¦of a Wink-Off except that Ar,guments l and 2 are to specify "Wink".
Referring now to Fig. 27, the outgoing supervision of the port will go off-hook for the time specified in Arg~ment 3, 4, and 5. At the end of this time the outgoing supervision will return to on-hook and the "end of task" event code will be entered in subfield 33506.
e. Format for Transmittin~ "Hookflash" Supervisor~ ~vent The transmission of the "Hookflash" is performed in exac-tly the same manner as the "Wink" except that the Arguments l and 2 I~ .
lare to specify 'Ihookflashl'. The operation is -the complement o~
the operation shown in Fig. 27 for the Wink.
,;
In order to transmit the "delay dial" supervisory event the ~ollowing settings o~ Arguments 1-6 will be provided: (i) ¦¦Arguments 1 and 2 are to specify "delay dial"; (ii) Arguments 3 and 4 are to specify the time scale; and Arguments 5 and 6 are to specify the "duration of the delay dial signal multiplier" and "the seizure recognition time period multiplier", respectively.
Referring now to Fig. 28, the incoming supervision is moni-tored to determine a valid seizure. A valid seizure is defined as one which ~asted for the seizure recognition time specified by Argument ~, 4, and 6. After recognition o~ seizure, outgoing supervision will go off-hook to initiate the delay dial action.
The outgoing supervision will remain of~-hook 7m til changed by call control processor (CCP) subsystem action when all equipment necessary to receive digits is available. After initiating the delay dial action, logic unit 38000 times out the Duration of Event specified by Arguments 3, 4, and 5 and thereupon activates common logic unit 36000 -to enter the end of task event code (1~00), into the EVC bit area of subfield 33506~ , g It will be appreciated that the transmit supervisory event function does produce signals which go out into the external telephone network. An arbitrary interruption of their execution could cause unauthorized signals to be sent over the network and/ ¦-ior an unauthorized sequence of relay contact operation and there- !
¦¦fore is not allowable. The halt sequence ~esigned to avoid this was previously herein referred to in subsection 2(h) of this sub-~division II(S).

_99_ ll T. RING LINE FUNCTIONAL LOGIC UNIT 40000 I 1. Basic Description ¦ Ring line functional logic unit 40000 applies ringing to a jline ~hen required. Ringing is provided for normal, emergency rering~ and revertive calls as follows:
(i) Single frequency~ 20 Hz bridged ringing for single-party lines.
- (ii) Single frequency, 20 Hz ringing for two-party lines.
Four-frequency bridged ringing for four-party lines.
(iv) Four-frequency divided ringing for eight-party lines.
Two types of ring buses are used in ringing system, a multiple frequency type of ring bus (MFRB) and single frequency type of ring bus (SFRB). Each bus has a ringing cycle of six Iseconds divided into four phases. During each phase, a de~ined iIringing frequency is present on the MFRB to allow relay action ~iin a port to select a ringing frequency by making the port selec-'tively response to a control signal timed to coincide with the ¦,phase on the bus. The frequencies are designated FRl through II~FR4 and the phases are designated PH0 through PH~. The MFRB
; ¦~type bus is used for four- and eight-party lines. The SFRB
type bus is used for single- and two-party lines and has alter nating phases of 20 Hz ringing and silence. To distribute the load evenly, system 400 has ~our MFRBs and two SFRBs.
2. Functional D scription Of The Interac~ion of L~E~lE~ OO

a. ~
Each port group unit 402 is provided with two types of ring buses:
a. Single Frequency Bus (SFRB). Used for single and two party ringing.
b. Multiple Frequency Bus (MFRB). Used for 4 and 8 party ringing !' ' The ~ollowing table depicts the frequency assignment on all MFRB and SFRB phases:

Multiple Frequency Buses FH0 PHl PH2 PH3 MFRB0 FRl FR2 FR~ FR4 MFRBl FR2 FR3 FR4 FRl MFRB3 FR4 FRl FR2 FR3 SFRBl FR FR

Where: (1) FRl-FR4 Denote ringing frequencies 1-4 (2) FR Represents 20 Hz (3) PH0-PH3 Represents Ring Bus Phase ~ach port group utilizes three buses as ~ollows:
(1) SFRB. This is one of the SFRB's and is used for 1 and 2 party ringing in the group.
(2) MMFRB (Main MFRB). This is one of -the MFRB's and is used for all 4-party ringing and all 8-party ringing.
(3) AMFRB (Alternate MFRB). This is another of the MFRB's and is used for 8-party revertive calls when both parties have identical ring frequencies, but opposite sides of the line (Note: With a line circuit the tip and ring cannot be rung simultaneously~ Also, each port in this group accesses either the SFRB (1 or 2-party~ or both the MMFRB and AMFRB (4 or 8-party) by strapping option provided in the line inter~ace circuit 2000.) The allocation of ring buses to port groups is staggered to distribute the load over all phases. me single frequency ring bus allocation corresponds to even and odd numbering of the port group number, i.e., odd port groups receive SFRBl. The assignment Il' jlo~ main multiple frequency ring buses is made by the last two ¦!binary bits of the port group number, i.e.1 port groups 0 and !;4 receive multiple ~requency ring bus 0. The alternate multiple ¦~frequency ring bus is two designations removed from the main ¦¦multiple frequency ring bus (i.e., port groups which receive ¦¦multiple frequency ring bus 1 have alternate multiple frequency ¦ring bus 3, etc ).
' b~ Ground Rules For Rin~ing !
! ab~ L~b~ `uL_~LL~b~a~ To ri~g a given frequency on a line, the ring relay of that line must be operated during the phase at which the desired frequency is on the allocated ring bus. The R relay will connect the line to the corresponding SFRB or MMFRB. The G relay (on multiple-party lines) causes the MMFRB to be replaced with the AMFRB. The RV relay applies ringing to the tip side of the line. Concurrent operation of 1, 2, or 3 o~ these relays is required to produce the necessary ringing on the line. Proper sequencing of these relays is irequired to a~oid undesired ringing of other parties on the line.
Emer~ency rering. It is a requirement o~ this operation ,that all parties which may have placed the call be rerung. Hence, ,lall parties on the line must be rung for one ring cycle, without !I ring trip. At the end of the cycle ~6 seconds) the ringing ceases- (A new command of the emergency dispatcher can be used to repeat the ringing cycle.) In emergency rering, all parties are rung for 4-party ONI
and 8-party lines. In the latter case each party is rung only for .75 seconds to limit the overall cycle to the 6 seconds. For i 2 and 1 party lines, only the identified party is rung, if available, and both otherwise. In each of the latter situations call control processor (CCP) subsystem 408 must specify the side and phase for each party to be rung.

- ~ ^ ~

Control Philosop~hy. 'rhe operation o:? i'unctional logic unit ¦ 40000 is synthesized from the ringing bus structure and the re-! lated allocation of frequencies by phases. The translation from ¦,the desired ringing frequency to the required bus and phase is ¦¦performed in the call control processing or subsystem 408.
Functional logic unit 40000 allows selqctive ringing of ¦¦either 1 or 2 par-ties simultaneously on the same line. For each ¦party the following must be specified: (i) the side of the line, ~(ii) the phase, and (iii) the bus. W~len both parties to be rung ~,have the same frequency, one of the subscribers must be rung from the alternative multiple frequency ring bus. To minimize cont-ention, the calling subscriber is specified in this manner.
Single frequency ring buses have two acti~e phases. It is possible for CCP subsystem 408 t;o provide control action which causes logic unit 40000 to utilîze the next available phase in order to minimize ringing delay for the subscriber.
:~ !
The command waits until the end of the current phase to start ringing. This prevents operating relay RV during the active portion of the ring cycle.
Specifying ringing with a silent phase of the single frequency . ~ .
I ~ ~ring bus results in open tip and ring toward the subscriber during l1.5 seconds~ This is used for applications such as "lift-off" of lkey system lines.
c. ~ .
Before describing the formats of Arguments 1-6, the parties to a plural party line revertive call (which is the most complex call handled by the format) will be defined. me called sub-scriber is designated party A~ while the call~ party is desig-nated party B. ~eferring now to Figs. 29A and 29B Arguments 3 and 5 are used to specify the ringing for party At Argument 3 specifies the side to be rung whether ring or tip. Ari~ument 5 i:l4SQil~9 ¦specifies the phase to be rung. Argument 5 bit settings 0000 through 0011 specify phases PH0 through PH~, respectively~
Settings 1000 and 1001 specify the next available even or odd phase for single frequency operation, and settings 1101 and 1110 specify 4 or 8-party emergency ringing. Bit value llil is used to specify that party A is not to be rung.
Similarly, Arguments 4 ~ig. 29A)and 6 (Fig. 29C) specify '! I
¦!ringing for party B. Argument 4 specifies the side and Argument 6j !the phase. The Argument 6 bit settings "0000'l through "0011"
specify phases PH0 through PH3 on the main multi-frequency ring bus (MMFRB). Settings ~0100ll through "0111~' specifies phases PH0 through PH3 on the alternate bus. Setting "1111" is used to specify that party B is not to be rung.
, , , Finally, Ar,gument 1 is used to specify emergency ringing.
!d. Event Code Descr~ption !
Referring now to Fig. 29D, RGL logic unit 4OOOO can result !
in the following event codes being written into the ~VC bit area j, of subfield 33506.
CODE COMMENTS
10~0 Ring Trip. This means that the line being rung has been answered.
1001 Emergency ring complete. This means that all parties on the line have been rung once.
e. Description of O~ration of Unit 40000 and Associated Relays.
Stàrt of Operation of the relays is delayed until the end of I
the phase existent at the time the command is received. This is i `
done in both emergency and normal rings. The purpose of doing this is to avoid switching unnecessary current with the relays.
In the case of an Emergency Reri~g, the R and RV relays are assigned to the specified phases by the Arguments. Four full ringing phases elapse 9 and then a sequenced shutdown precedes the 13L~

¦Irequesting o~ the event code "Emergency raring complete".
¦l In all cases, except revertive ringing the logic reiterat-ively tests for the detection of ring-trip, and rings the line ¦with the specified parameters.
a"~ i~ D---ct---. This is accomplished with the line . .
¦circuit working with an analyzer in functional logic unit 40000.
Briefly, the analyzer operates on the principle that the line interface circuit (e.g., circuit 2000) will not respond to the ; l'positive half oP the ringing waveform. Hence, "On-Hook" will be liseen during ringing as a maximum of 50/0 contact closure from relay CB as transmitted by fast sense data channel bus SBFO.
When a subscriber answers, a direct current (D.C.) component is added which guarantees more -than 50% make contact closure from relay CB; which is interpreted by the analyzer as the o~f-hook ¦Icondition.
¦l When ring trip is detected, all relays except CB are dis-abled. R is sequenced first to prevent undesired ringing of uninterested subscribers during relay transien-ts. The RV and G
relays ~ollowg and the writing of the event code 'IRing Trip" in the EVC bit area of subfield 33506 ends the sequence of unit ~40000 ,f. Halt Considerations.
¦ mis Command is not interruptable. The halt sequence, previously referred to in subsection (S) (2) (h) of this section II, must always be used because proper down sequencing of relays is essential to avoid temporary connection o~ ringing voltages to uninvolved subscribers.

, ~ -105-i~

U. SEND DIGITS (SD) FUNCTIONAL LO&IC UNIT 42000 , AND REC~IVE DIGITS/SEND DIGITS (RD/SD) FUNC-TIONAL LOGIC UNIT 45000 (THE LATTER BEING
~MPLOYED ON A SHARED BASIS WITH RD_UNIT 44000) 1. Functional Description Send Digits (SD) functional logic unit 42000 and Receive Digits (RD/SD) functional logic unit 45000 perform the digit outpulsing function of the digits contained in the digit storage areas of subfield 3~516 of a given port data memory field 33500.
(Unit 45000 operates on a shared basis with both unit 42000 and ; ¦44000. Digit sending may be either Dial Pulsing (DP) or Toll I Multi~requency (TMF) tones. Units 42000 and 45000 are each a ¦Iprinted wiring board unit chiefly composed of integrated circuit components.
The sending mode is determined by the port type. If the port type is a trunk, DP sending is performed by loading each ~four bit binary number in turn f:rom the digit storage area into a counter which is decremented by one count for each pulse sent.
¦Interdigital time is inserted between the digits as they are out-pulsed. When the port type is TMF Sender, the ~our bit binary ~¦code representing each digit is converted to a two of six code llwhich controls the TMF sender tone selection logic via the slow binary control channels of other-than-voice data TDM network 407.
The value in the digit count (DCT) bit area of subfield 33516 is -~ used as a pointer to fetch the next digit from the digit storage areas. Call control processor (CCP) subsystem 408 initializes this value before the command is received, to thereby point to the next digit loca-tion to be outpulsed. After the digit is out-pulsed, the digit count value is updated to the next digit location by operation o~ logic units 42000 and 45000. Sending stops when tha ~irst empty digit location is detected or when the digit count ~ield count exceeds 15.

~L14SIl~

~ 2. Interaction Of Units 42000 And _3~
¦a. General . ..
I A presence of a binary code 0~10 in the command (CMD) bit iarea o~ subfield 33502 enables logic units 42000 and 45000 to ¦operate tc send dîgits. Logic units 42000 and ~5000 respond to ¦the settings of Arguments 1-6 bit areas of subfield ~3502 to ¦selectively perform the following types of digit sending:
Outgoing Trunk DP Sending TMF Sending jFurther, certain timing factors and other parameters associated j'with the digits which are to be sent are adjustable~ in response to settings of the Arguments. For dial pulse sending both the on-hook and off-hook periods can be specified. The supervisory signals associated with sending digits (sometimes called "sending ~control signals") can be sensed 'both before and after a string of dial pulse digits are sent. In multifrequency digit sending, an option is available to either include or omit the KP character.
1 Units 42000 and 45000 send the 4-bit binary code digits 'stored in the digit storage area of sub~ield 33516 to the port circuit for outpulsing in either the DP or MF mode.
, me digit count ~DCT) bit area of subfield 33516 is utilized as an index to fetch the next digit value from the digit storage area, and point to the next digit location. The value in the digit count bit area at the beginning of the se~uence is controlled by call control (CCP) processor subsystem 408. After a digit has been outpulsed, the digit count (~CT) ~ield is incremented.
Sending will terminate when the ~irst empty digit location is detected (i~e., digit value is equal to 0000), or when the end of the digit storage area is reached.
The sending mode is a function of the Port Type (10 PPS DP for trunks, and 2/6 MF code for MF senders).

I ~

I The Argument bit areas and bit locations for the Send Digits `
!`Command are defined for two port types; namely, trunk and multi-; , frequency sender.
i., .
For multifrequency sending the only Argument which is used isArgument 1 It specifies whether or not the KP character is to be~
sent ahead of the digits, as shown in Fig. 30~.
In the case of trunk type ports, the sending is done in the dial pulsing mode. Arguments 1-4 are used to specify the speed and duty cycle of dial pulses as shown in Figs. 30A and 30B.
Arguments 1 and 2 are jointly used to specify the on-hook timing of the pulses. Arguments 3 and 4 are jointly used to specify the off-hook timing of the pulses.
Argument 5 is used to specify the presending supervision (also called before sending control), i.e., the supervisory signal, to be received before sending is to commence. Argument 6 is used to specify the post sending supervision (also called "after sending control"), i.e., the supervisory signal to be sensed at the end of the digit sent~ As shown in Figs. 30C and 30D a variety of supervisory condltions may be specified by the different binary settings for Arguments 5 and 6.
It will be appreciated that two timings are available ~or most supervisory eventsO One of them corresponds to standard Bell ¦System interoffice signalling specifications. For instance, bit settings of "0011" of Argument 5 specify a standard ~merican Telephone & Telegraph Corporation ("Bell'1) System wink o~ lOO to 352 milliseconds. Bit setting of "0010" specifies 24-352 milli-Iseconds which is broader than Bell standard specification. The ¦latter enables system 400 to be adapted to situations where the foreign office does not meet Bell standards.

Ic. Other Memory Field Formats Which Are Involved In The 'Interactive Role Of Units 42000 and 45000; A Description Of Their Utilization i,~--~
. In li I'the Digit Storage Bit Area, the digits to be sent are stored in ¦la continuous string followed by at least one empty (0000) digit Illocation~ For MF Sending, the KP character is not part of the ;Idigit string. However, the ST character is inserted as the last ! digit to be sent if required (which is normally the case)O
Sending will stop at the first empty location.
~ Pulse Count (PCT~ Bit Area Of Subfield 33516. This bit area t - does not require initialization. Functional logic units 42000 and 45000 con-trol it during the send digits command. When sending MF I
with the KP option9 the desired KP character must be stored in the !
PCT bit area by CCP subsystem 400 before the beginning of the ~ ~ sending function.
I Slow Control ~ata Bit Location CS2. mis bit location controls the Outgoing Relay (OG) via the corresponding CS2' channel of ~;other-than-voice data TDM network 407. CCP subsystem 408 prior to the time that subsystem 408 invokes a send digits command for a !
loop trunk type port.
~d ~vent Codes Described O ~
The event codes which may be entered into the ~VC bit area ' of sub~ield 33506 as the result of operation of Xunctional logic units 42000 and 45000 are as followsr ¦ ~vent Code Descri~tion 0101 nd of Task. This is detected when the specified "after sending" event is received.
0110 Excess ~vent. This is detected when an illegal event is received either before or after sending, ~vent Code Descr~tion 0111 Pc l~ritv rl:~ cK F~il 1110 Error.

e.
!, i Multiple SuPervisory Si~nals Received on the Same Gall.
. . .
¦l, There are calls which require one or more points in the digit i train at which supervisory signals are to be received. A separàte, insertion of the SD command code in subfield 33504 is required for each section of the train.
SH Relay Control ~sed in Loop Trunk~. The SH Relay operated , ~
by slow control data bit location of CSl of subfield 33501. It is energized,during ou-tpulsing and de-energized during reception o~
supervisory signals from the far end. That is to say, the SH
Relay is operated after the pre-sending supervision, and is released before the post sending supervision.
f. Description of Operation of Units 42000 and 45000 Dial Pulsing (DP). For Dial Pulse (DP) signalling functional~
logic units 42000 and 45000 provide the numerical value of each digit by the number of or.-hook intervals in a train of pulses to the trunk at ten pulses per second (10 PPS) with "make" and ,~"break" times as specified in Arguments 1-4. me next digit (4-bit binary code) is fetched from the digit storage area and stored in the pulse count (PCT) bit area for outpulsing. m e Digit Count (DCT) Bit Area is used as an index to fetch the next digit, and must be set by CCP subsystem 408 to point to the next digit location before the command is received. DCT is incremented after the fetch, and the fact of whether DCT overflowed is stored.
Reference is now made to the timing diagram of Fig. 31. If the next fetched digit location is not empty (~ 0000), a 200 MS~C delay is introduced before the first on-hook break interval.
At the end of the on-hook break interval (specified by Arguments - - -¦11 and 2) the of~ hook make interval (specified by Arguments 3 and 114) is generated. At the end o~ the make period, one pulse has been sent. The pulse count (PCT) value is decremented by one.
1'l The proceduxe is reiterated until the pulse count (PCT) value ¦lequals 0~00, indicating that the end o~ the digit has been reached The digit count (DCT) overflow is tes~ed to determine if Digit 15 has just been sent (which is the last possible Digit Bit location). If the 15th digit has just been sent, the sequence of operation of logic units 42000 and 45000 advances to event recog=
nition after sending. If the last digit sent is not Digit 15, the digit location specified by DCT is read and its contents trans-ferred to PCT. DCT is again incremented after the fetch.
If PCT (next digit to be sent) is empty, the sequence of ~operation of logic units 42000 and 45000 advances to event recog- j nition after sending. If PCT contain3 a digit, a wait of 660 ,IM~C is introduced (interdigital pause) and the sending of this digit begins. At the end of sencling) the port remains seized.
"
. Reference is now made to the timing diagram of ,IFig. 32, for a description of the operation of functional logic ~units 42000 and 45000 in the case of Multifrequency (MF) Pulsing.
Units 42000 and 45000 provide MF 2/6 codes to the MF sender port 'I
,with digit and interdigital periods of 70 milliseconds each to ¦perform MF outpulsing. Fig. 21M illustrates the variation in I operation depending upon whether the option of KP Sending is exercised or not, as specified in Argument 1. The digit specified ¦
by the DCT value is loaded into the PCT area, and sending begins with a silence section of the TMF outpulsing cycle. After a digit has been sent, the DCT value is incremented and the next digit transferred to the PCT bit area for sending. This process repeats itself until either an emply digit location is found or the DCT
bit area overflows.

1145!)19 j ~ For the case of a port type ¦¦which is a trunk (and therefore Dial Pulse sending is involved)) ¦¦the pre-sending supervision and the post-sending supervision are ¦¦selected by Arguments 5 and 6y respectively as previously ¦¦described.
e function of sensing the specified controls is performed ¦¦by sense supervisory events/transmit supervisory events (SS~/TSE) jfunctional logic unit 38000 At the appropriate point in the ¦sequence of operation of sending digits, units 42000 and 45000 in~oke operation of unit 38000. When unit 38000 has per~ormed its function, the operation of units 42000 and 45000 in perfor- !
mance of sending digits is resumed, if required.
g. Halt Considerations l The ha't sequence previously described in subsection (S) (2) ¦I(h) o~ this Division II, is used in interrupting a send digit ~¦operation when MF outpulsing is performed. me co~mand in inter-ruptable in the DP mode, with the following constraints:
a) Outgoing supervision will be undefined at interrupt and ust immediately be redefined by C~P subsystem 408.
! b) The next call state must be of the ~uardl~ or ~1No-Op~ !
~type (in which no command is executed) and hence no down sequencing of relays is required.

V. R~CEIVE DIGITS (RD) FUNCTIONAL LOGIC UNIT 44000 AND
RECEIVE DIGITS/SEND DIGITS (RD/SD) FUNCTIONAL LOGIC
UNIT 45000 (THE LATTER BRING EMPLOYED ON A SHARED
BASIS WlTH RD UNIT 420003 _ _ 1. ~t~Z~
A receive digits (RD) command causes port event processor (PEP) 406 to collect and store the digits which are received at a port position interface circuit, placing them in the digit storage areas of subfield 33516 of port data memory field 33500. The Port Type (PTY) bits o~ call state and state timing subfield ~3503 ¦ispecify the operating mode (lO pulses per second dial pulsing for lines and trunks, or tones ~or DTMF and toll MF receivers). me ldigit count (DCT) bits of subfield 33512 is used as a pointer to ¦store the receive digits. It is updated by units 44000 and 45000 l~after each digit is stored, These bits always indicate the current ¦¦digit count (DCT) stored. They are initiali~ed by call control ¦Iprocessor (CCP) subsystem 408 to point to the location where the next digit is to be stored.
e impulse analysis parameters (make/break ratio, inter-~digital pause, etc.) may be adjusted by the setting o~ the argument bits of subfield 33504.

2. Interaction of Units 44000 and 45000 ; I ~r -- CCP Sub~ m 408 __ ,a. General The presence of a receive digits binary code 0001 in the command (CMD) bit area of port command subfield 33504 enables ~functional logic unit 44000 and receive digits/send digits function logic unit 45000 to jointly operate to receive and rack rotary dial pulse digits, DTMF digits, or ~MF digits, as appropriate. (unit .45000 operates on a shared basis with both units 42000 and 44000.) Further, certain timing factors and other parameters associated ¦with the receive digits are adjustable, in response to settin~s of the Arguments. Which of these three is received is specified by the port type (PTY) bit area of subfield 33503. The capacity of digit storage subfield 33516 is 16 digits. This count includes the ST digit at the end of MF inpulsing. That is to say, the ST
digit is racked into the digit storage area. Units 44000 and 45000 are each a printed wiring board units which are chiefly composed of integrated circuit components.

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; Functional logic units 44000 and 45000 Jointly operate to jcollect and rack received digits into the 16 digit storage bit ¦¦areas of digit storage subfield 33516. The digit count (DCT) bit larea of subfield 3~516 is u-tilized as a pointer to store the digits received, and is updated by operation of units 44000 and 1¦45000 after a digit is stored. The DCT bit area is initialized ¦Iby CCP subsystem 408. Subsystem 408 initializes it to the next ¦Idigit location to be used. Call control stored program 56002 can interrogate the DCT bit area to determine the number of digits received.
If another digit is received after DCT = 15, the next digit count will be zero, this zero meaning 16. Thereupon logic units 'i 44000 and 45000 will actuate common functional logic unit 36000 ~to write the event code "Register Full" (1101) or "ST Received"
(1011), as the case may be. That is to say, DCT = 0 means 16 in these cases.
~ b. ArFumt~nts 1-6, Broken Down By Function -~ , Referring to Figs. ~3A through 33C, it will be seen that there . . .
~are ~our port types represented in the definition of the Arguments.
~These are: Line, Trunk (any type), DTMF Receiver (which is for a subscriber loop employing a DTMF pad), and TMF (Toll Multiple ¦Frequency) receiver which is for interoffice signalling. As can be seen on Fig. 33A, the meaning of the various Arguments varies from port type to port type.
Argument 1 is used to define the start function. When Argument 1 = 0, the logical sequence implemented by units 44000 and 45000 remains in an iterative loop until an incoming seizure is present. When Argument 1 = 1 the sequence does not require this, ¦iterative loop. When Argument 1 is 1 and the port type is a line, units 44000 and 45000 perform impulse analysis to detect a digit which is started without delay. When Argument 1 is l and the port type is a trunk such analysis is started after transmitting a wink 5~L9 I .
, supervisory signal. Units 44000 and 45000 include the logic to ltransmit the wink signal. ~That is to say, under these circum-¦ stances the transmission of the wink signal is not performed by SS~/TSE functional logic unit 38000.) Argument 2 in conjunction with Arguments 4 and 5 define critical timing. When Argument 2 is set, the critical timing function is enabledO Argument 4 will specify the critical timing speed. If Argument 4 is not set, this specifies the use of ,normal critical timing speed (i.e., 3.5 seconds). I~ Argument 4 is set, this specifies the use o~ slow critical timing speed (5.5 seconds). Argument 5 specifies the digit count (DCT) after which critical timing is to be performed. Any DCT ~rom ~ to 14 can be specified. me "llll" code in Argument 5 is used to speci~y critical timing after each and every digit.
Argument 3 is used to specify the interdigit timing speed.
If Argument 3 is not set, this specifies normal interdigit timing , of 27 seconds. If Argument 3 is set, this specifies an arrangement of accelerated interdigit timing consisting of 13 seconds before the first digit, 7 seconds between any other digits.
Argument 6 specifies the digits expected. me primary use of this parameter is to specify the DCT after which call control l;processor subsystem 408 will translate the racked digits. Argument ¦16 values from l through 15 are used to specify values DCT = l through 15. An Argument 6 value of 0 is used to indicate processo~
access at the next pulse or tone.
c . 3, el~ t Co~e~ D~c~ibed Referring now to Fig. 30D, the event codes which may be ~written into the EVC bit area of subfield 33506 as the result of ¦operation of functional logic units 44000 and 45000 are as ~ollows: -115-s~
I

¦ EVENT CODl~: DESCRIPTION
1000 DCT 2 DEX or "Di~its Rec~eived". The current digit ~1 ' count (DCT) is equal to or greater than the digit expected count (DEX ~ 0), or next digit started, i, if DEX = 0. This event code does not stop the ¦ execution of the command.
lool c lcrl r.m.... ut The next dial pulse or digit was not received within the specified critical time.

1010 In.erdi :t T~ne-~'. The off~hook interval ~rom the end of the last on-hook pulse exceeded the specification of Argument 3. This function is inhibited i~ the TCL bit of subfield 33503 is ! set. (the latter avoids I/D timeouts during testing.) ~:; " 1011 ST Received. Any standard ST MF character as defined by Bell Telephone Systems (ST, STP, ST2P, li ST3P) was received. The ST character will be ', racked as a digit.

1100 Overdial. More than 15 on-hook pulse intervals were detected after the last interdigital period.¦
~, I
¦1101 Register Fullo A non-ST digit was stored into DCT 15. Hence9 no more digits can be racked.

d. TMF Digits Code Assi~nment The format of sso-~37 slow sense data bit locations as representations of received DTMF impulses are as follows:

~s~ ~

SLOW S~NS~ DATA
; i BIT LOCATIONS
~SUBFI~LD 33501) : ,'DIGIT BINARY_CODE S7S6S5$4S3S2Sl FREQUENCIES _~H~
; ll 1 000~ 0 0 1 0 0 0 1 697 + 1209 2 0010 0 1 0 0 0 0 1 697 ~ 1336 , 3 0011 1 0 0 0 0 0 1 697 + 1477 4 0100 0 0 1 0 0 1 0 770 + 1209 l 5 0101 0 1 0 0 0 1 0 770 + 1336 6 0110 1 0 0 0 0 1 0 770 ~ 1477 ' 7 0111 0 0 1 0 1 0 0 852 ~ 1209 8 1000 0 1 0 0 1 0 0 852 + 1336 9 1001 1 0 0 0 1 0 0 852 + 1477 O 1010 0 1 0 1 0 0 0 941 + 1336 . * 1101 0 0 1 1 0 0 0 941 + 1209 # 1111 1 0 0 1 0 0 0 941 ~ 1477 Ii, I,e. Toll Multifre~uency Digits Code , i .
'. The format o~ sso-~37 slow sense data bit locations as representations o~ received TMF impulses are as follows~
. i SLOW SENSE DATA
I BIT LOCATIONS
j, (SUBFIELD 33501) : TMF DIGIT BINARY COD~ ~ ~ j .. ~
1 0001 0 0 0 0 1 1700 + 900 2 0010 0 0 0 1 0 1700 ~ 1100 3 ooll o o o l l ogoo i lloo 4 0100 0 0 1 0 0 1700 + 1300 0101 0 0 1 0 1 0900 ~ 1300 6 0110 0 0 1 1 0 01100 + 1300 7 0111 0 1 0 0 0 1700 + 1500 8 1000 0 1 0 0 1 0900 ~ 1500 9 1001 0 1 0 1 0 01100 ~ 1500 O 1010 0 1 1 0 0 01300 + 1500 2/6 COD~
¦TMF DIGIT BINARY COD~ ~ FREQUENCIES ~Z~
:-- ~
ST3P 1011 1 0 0 0 0 1 700 ~ 1700 I STP 1101 1 0 0 0 1 0 900 + 1700 ¦I KP 1111 1 0 0 1 0 0 1100 + 1700 ST2P 1110 1 0 1 0 0 0 1300 + 1700 ST 1100 1 1 0 0 0 0 1500 + 1700 If. Other Bit Areas Which Are Used In Conjunction With The Receipt of Digits See the descriptions of the DCT and PCT bit areas, section P (9) of this division II.
g~ ~E~l~e Anal~is Desi~n Consideration Dial Pulse Reco~nition. The SPI bit area of subfield 33510 is monitored by functional logic units 44000 and 45000 to detect ,Idial pulses, consisting of make and break periods. A break period ilis recognized when on-hook is present for a minimum interval of 24 ¦¦milliseconds to a maximum of 180 milliseconds (after seizure has i~been detected for a minimum interval o~ 65 milliseconds for immed-iate dial trunks). A make period is recognized when off-hook is ¦Ipresent for a minimum interval of 12 milliseconds to a maximum of 180 milliseconds after the made period has been detected.
11 Interdig~tal Period Reco~nition (End of Di~it)o An inter-' i jdigital period is recognized when the interval from the end of the I
last on-hook pulse of one digit train of dial pulses to the begin- i ning of the first on-hook pulses of the next digit train is a minimum of 180 milliseconds.
Tone Detection. The applicable tone (PTMF or TMF~ Receiver will present two signals slow sense data channels of other-than-voice data TDM network 407 when a valid digit is detected. The two signals will disappear when the tones have ended.
Interd~it Timeout. This timeout is between the last pulse of one digit and the first of the next for DP, and from the end of I

one tone digit to the beginning of the next for tone digits. Pro-tection against infinitely long tones (stuck tone pads or senders) I! is provided via the state timeout (STO) function of common funct-I ional logic unit 36000. This state timeout (STO~ function is ¦¦described in subdivision O of division III, following.
If port type = loop trunk, the SH (Shunt) relay will be operated by the functional Illogic units 44000 and 45000 when the receiving of digits actually begins I~ Arguments 1 = 1, it happens immediately. If Argument l = O, it happens after seizure recognition. Release of the SH
; relay is performed by call control processor (CCP) subsystem 408.
h. Generalized Description of Operation of Units 44000 and 45000 In the Receiving and Racking of Address Signals (Dial_Pulse or Multifrequency Pulses). _ Reference is now made to Fi~. 34, which is a diagrammatic representing the functional process steps which are performed by functional logic units 44000 and 45000 in the receipt and racking of dial pulse or MF pulse signals. The diagrammatic is of a non-~conYentional type which depicts logic flow paths by block having ',imultiple logic exists rather than the strict single exit decisionblock of a conventional logic flow chartO
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Start Fu ction For Trunks & Lines (Step 44002). When Argument jill specifies the logical sequence of unit 4~000 and 45000 must rec-ognize a seizure before proceeding, the SPI bit area of subfield 3~510 is monitored and timed. After a 65 millisecond off-hook period, the command proceeds to the initialization process step 44004. If the Port Type specifies a Loop Trunk, the SH relay is operated at this time.
When Argument 1 specifies immediate start, the seizure det-ection is omitted. When Argument l specifies a wink start, a '~
wink of 160 ~ 10 milliseconds is sent out from the port, via the appropriate control data bit area or bit location and the corres-s~

!I ponding binary control data channel of other-than-voice data net-i work 407. m e bit areas or bit location and channel which are i appropriate are a function of port type.
' Initialization (Step 44004). Ini-tialization is performed ¦Iwhen functional unit 44000 is enabled, and each time a digit is !1` detected. The pulse count (PCT) and the timer for Interdigital iTiming are initialized.
Di~it Expected Check & Port Tvpe Check (Step 44006). A check is performed between digits to determine if the DCT 2 DEX condition ; is met. Should the condition be met than common function logic unit 36000 is actuated to enter the digits received event code , ("lO00") into the EVC bit area of subfield 33506. In either case, the next step is selected on the basis of port type.
Tone Digit Detection (Step 44008~. m e full process of tone digit detection requires a recognition of the beginning and the end of each tone digito Recognition of the beginning is needed to initiate detection ~,and re~ognition of the end is needed to act upon it. m e criteria , ;
for recognition of the beginning of a digit from the tone receiver port is the simultaneous detection of two frequencies. The value of the digit is decoded and the corresponding binary code is stored in PCT. If Argument 6 = 0 (i.e., specifying the very next set of tones as the digits expected), units 44000 and 45000 actuate common functional logic unit 36000 to enter the event code "Digits !
Received" (10~) in the ~VC bit area o~ subfield 35206.
When the end of the digit tones is recognized, the digit is tested to determine if it is a KP or ST digit. I~ it is a KP
¦digit, DCT is reset to zero to cause overwriting of the existing digit and the sequence of steps reverts to step 44004. If it is an ST digit, the unit 36000 is actuated to generate the event code (EVC) "ST Received". me ST character itself is racked in the 11~5Q~L9 digit storage area (perfsrmed as internal 50mponent of step 44008), jand the sequence of operation of functional units 44000 and 45000 is terminated. If it is not a KP or ST digit ti . e., it is a valid , digit) the sequence operation of units 44000 and 45000 will proceed l¦to step 44012.
If end of digit is detected, the sequence of opera-tion pro-j,ceeds to step 44014.
Dial Pulse Digit Detection (Step 44010). Units 44000 and ~45000 monitor and analyze the SPI bit area of subfield 33510 to detect the appearance of valid pulses. PCT is incremented at the ` end of each valid pulse. A continuous off-hook condition having a duration in excess of 180 milliseconds indicates the end of a ;-;digit. When this is detected, the sequence of operation proceeds to step 44012.
If DEX = 10~ the event code "DCT ~ DEX", or otherwise called "Digits Received" (10003 is entered at the end of the next pulse received.
Unit 38000 is actuated to generate "Overdial" event code (110~) if more than 15 dial pulses appear in a digit and the sequence of operation is terminated. This action avoids the , .
ambiguity which would result from exceeding the capacity of the 'IlPCT bi-t area of subfield 47016.
IIf no end of digit is detected, the sequence of operation proceeds to step 44014.
~ . The Pulse Count (PCT) field which contains the value of the digit to be stored is transferred ¦
to the particular digit storage area which is indexed by the ~digit count (DCT) valueO The DCT value is then incremented so ¦that it points to the next available digit area. If the digit ¦storage areas in subfield 33516 are all full, this incrementing causes ~CT to become "0". Thereupon, units 44000 and 45000 ~L45Ql9 . .

I¦actuate common logic unit 36000 to write the event code "Register ! Full~' (1101) in the ~VC bit area of subfield 33506 and the sequerlce lof operation is terminated. If the digit storage areas in subfield ; l 33516 are not full, the next step to be performed is a repeat of ¦the initialization step; namely, step 44004.
, Critical & Interdi~ital Timeout Checks (Step 44014~. From the time the sequence starts its process of digit detection (which is step 44004 at the end of the last digit or after the start functionj and until a new digit is detected, the sequence of steps proceeds through step 44008 or 44010 to step 44014, and then back to 44006~ The operation of step 44014 will first determine whether a critical timeout is exceeded, if specified by the Arguments 2 and 4. In the event that "critical timeout" is exceeded, the event code "critical timeout" (10~1) is written into the EVC bit area of subfield 33506 and the sequence of operation is terminated.
If critical timeout has not timed out9 a second chec~ is per-~formed to determine whether interdigital timeout has been exceeded.
In the event the interdigital timeout period is exceeded the event ~I code "Interdigital Timeout" (101~) is written into the ~VC bit area of subfield 33506 and the sequence of operation is terminated.
~If the interdigital period is not exceeded, the operation returns ~to step 44006.
i ~ i . u- I = r ~ id- r3 t~
i mis com~land is interruptable except when wink start has been specified. In the latter case, it is necessary to use the halt sequence previously referred to in subsection S ~2) (h), of this Section II.

W. PROC~.SSOR UNIT 50000 Processor Unit 50000 is a digital equipment corporation (D3C) KDll-F, LSl-ll, microcomputer processor module (i.e., a unit made llup as a printed wiring board circuit from integrated circuit components). The relevant jumper options are as factory installed (as specified in table 5-2 of the Deck Microcomputer Handbook, I¦Copyrighted 1976) except that jumper W10 is inserted rather than ¦¦removed (enabling rather than disabling reply from resident memory during refresh); and jumper Wll is removed rather than inserted l(disa~ling rather than enabling on board memory), 1 ', X. CCP INTERFACES CONTROLLER ~ OOQ) The call control processor (CCP) interfaces controller 54000 provides the required interfaces to enable the call processor (CP) subsystem 408 to communicate with port data store 33000, TSI
matrix network 403, and timing and control circuit 28000.
Controller 54000, driven by processor unit 50000, provides Icall processor address decoding for TSI matrix network identifi-cation and individual TSI circuit selection. (The feature if TSI
,.matrix network identification accommodates systems having a plur-,ality of TSI matrix networksO System 400 is provided with only a "single TSI matrix network.) Monitor logic provides two status bits to processor unit 50000 when certain TSI matrix network/
controller communication conditions occur. Controller 54000 also lldoes transport-delay compensation to relieve processor unit ¦50000 of this task.

i Y. MhMORY 56000 Memory 56000 comprises two circuit assemblies of conventional MOS-type memory, each containing 16,384 (16K) 16 bit words. (How-ever7 only 28K words of the 32K are used) ~hey are conventional commercially available circuit assemblies which are manufactured by.
Digital Equipment Corporation (DEC) as units which are compa-tible with the input/output bus of the KDll-F processor unit 50000.

11459~
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I The memory circuit assemblies have no parity feature and no ¦¦memory refresh. Refresh is accomplished by external conventional circuitry using the DMA access of the KDll-F processor unit 50000.

i~

-12 Z. CALL CONTROL STORED PROGRAM 56002 ¦l 1. Overview of Pro~ram ! The basic mode of operation of call progression stored program 56002 is to respond to the recording of a new event code in response subfield 33506 o~ a port data field 33500. (In ~¦general an event code represents a change of conditions in the line, trunk or other equipment in the port circuit. The concept i~f a change o~ conditions includes timeouts and invalid conditions.3 il me changes in port conditions are detected by port event processor i (PEP) 406. Within timing and control circuit 28000, are provided a set of three EN queue registers (introduced later herein as regis-ters 28094, 28096 and 28098, Fig. 35 ) whîch function as queues of port position equipment numbers (EN's) for each of the three pro-cessor request priority (PRP) levels. me PRP for a given new ,,even-t code condition is determined by the value recorded in the ~IPRP bit area of subfield 33506. The priorities are designated 00, , 01 and 10 with priority 00 the h:ighest. me value of PRP for a given port is written into subfield 33506 by call control processor ,(CCP) subsystem 408, and it represents the desired priority with ,which call progression stored program is -to respond to a certain ¦,detected event. Call progression processor subsystem 408, and in ~turn CCP stored program 56002, has access to the EN queue registers ¦through CCP interface controller 57000.
Several program modules in executive tier 56004, constitute the executive routine of program 56002. m ese modules operate an interrogation loop which constantly polls the ~N queue registersp in order of the processor request priorities which they represent, to detect an event. The EN queue registers contain the equipment ~, numbers (EN's) of those port positions for which event codes (EVC's), have been generhted. me EN's are recorded in the queue registers j ,in approximate chronological order of the generation of the event `,code. When the program module finds a queue entry, it interrogates ithe port related memory field ~3500 ~or the port represented by l~the ~N for status information which may be pertinent to call pro-i¦gression. This may include: call state (CST); event code (EVC);
¦Iport ordinal call position identity number (ID#), digits received;
,lcontrol and sense data bit areas and bit locations CF0, CFl, CS~-7, SF0, SFl, SS0-7, etc. The module of tier 56004 which constitutes ~the executive routine handles each event which it detects as a 'separate task. It passes processor control to an appropriate task handler formed by the linkage of a number of subroutines. This task handler is re~erred to a "state transition routine" reflecting the fact that it effects a transition from a given call state to a succeeding call s-tate. Such a task handler is herein usually ,called a "state transition routine". Each state transition routine is processed to completion before returning to the executive.
On completion of each task, the memory field 33500 of each jlport associated with the call which has been handled is updated to ~reflect the new state of the call. Control then returns to the ;executive routine which resumes polling the EN queue registers for the next task.
, Transitory call data associated with calls in progress is maintained in the data fields 33500 of the associated ports.
Calls in stable states present no load to CCP subsystem 408.
The operation of subsystem 408 is invoked on a "request basis"
Iby PEP 406 when the latter detects a change of port conditions Irequiring the generation and recording of a new event code (EVC) ¦in response subfield 33506.

2. ~

Call progression stored program 56002 is resident in the 16K

~9L4~
1 .
I .

¦Iword memory 56000. Referring now to Fig. 36, it is organized in I a modular fashion as a hierarchy of tiers of program clusters.
~ach cluster contains one or more modules. Modules are the basic ! units of coding which are used to implement the program. The llcontrol of CCP subsystem 408 is generally transferred between ¦,hierarchical tiers by a higher tier calling a lower level tier ; I~followed by return to the higher level tier. mis confers an inverted tree structure on the program, with vertical interfaces between modules.
3. Description of Program 56002 at the Level of Tiers of Module_Clusters _ a. Executive Tier 56004 Again referring to Fig. 36, tier 56004 contains an execùtive cluster 56040.
Executive cluster 56040 contains the modules which comprise I the executive routine for call processing. These modules provide i the scanning of the EN queue registers for new event codes (~VCs) which have been generated by port event processor (PEP) 406.
When a newly generated ~VC is detected, the executi~e routine transfers control of CCP subsystem 408 to the state transition routine comprised of modules from the various lower tiers, When the task of the state transition routine is completed, control of ~subsystem 408 is returned to the executive routine.
! In order to perform its function, the executive routine ¦fetches data from the memory field associated with the port for ¦which the new event code (EVC) was generated. Based upon this ¦data, a specific state transition routine is formed through linkag~
lof subroutines comprised of modules in the lower tiers. There is !
ia distinct state transition routine for each different situation ~of a new event code, although many of the subroutines are common to a number of state transition routines I b. State Transition Tier 56006 ; ~ The clusters in state transition tier 56006 contain the mod-ules which are executed in direct response to calls from modules in executive cluster 56040. The modules in tier 56006 provide the function of advancing calls from one state to the next. They do this by a series of calls to modules in the lower tiers. me jicombination of a module in tier 56006 and the modules from the lower tiers which are called by it provides the state transition routine which causes system 400 to progress from its existing j call state to a new call state with respect to the port which is involved.
i The modules in tier 56006 are grouped into state transition clusters. In general, there is a one-for-one relationship between each of these clusters and certain functions provided in call pro-gression. A cluster 56100 includes the modules provide linking up `
of themselves with lower tier modules which constitute state trans-ition routines for originations and dial tone functions. A cluster ~; 56140 provides the receiving digits function for a line-to-line and ~,trunk-line call~. A cluster 56180 provides the line-to-line con-~nection/disconnection functions for a line-to-line and trunk-line calls. Cluster 56220 includes modules which provide linking up of ,themselves with lower level tier modules, which constitute state ¦lltransition routines for line-trunk connections and disconnections involved in incoming trunk calls.
c. ~La~U~
me modules within the clusters in shared subroutine tier 56008 are gensrally executed in response to calls from modules in tier 56006. The modules of tier 56008 in turn call upon the ¦utility modules in the tier there below. The modules of tier ¦56008 perform functions which are common to a number of transition ¦routines .

1~450~9 Examples of the type performed by modules in tier 56008 are:
invoke sender, release trunk, etc. However, they must call upon the still lower shared input/output utilities for the actual ¦performance o~ the function. The modules are grouped into clusters according to type of task. A cluster 56400 encompasses the modules which provide equipment connections. A cluster 56440 performs tasks relating to equipment release, and a cluster 56480 encom-passes modules which perform translation types of tasks.
dd Shared In~ut/Output Utilities Tier 56010 Tier 56010 is the lowest level of the hierarchy. It contains modules which serve as input/output utility subroutines to send , and receive coded signals to and from components of system 400 outside of CCP subsystem 408. These modules also give a trans- !
ition routine access to the system data bases in stored program !56002. ("System data bases" are those data bases which are estab- I
¦,lished for use by more than one module) in contrast to data bases i which are parts of a specific moclule.) The modules of tier 56010 are grouped into clusters according to types of tasks which they perform. A port utilities cluster 56800 encompasses modules for performing read and write access to ~the port data fields 33500 of data store 33000. A network utili-! ties cluster 56840 encompas-ses modules which control matrix switch network 24000 and perform busy/idle mapping in conjunction with th~
matrix switch network. A data base utilities cluster 56880 encom-passes the modules which provide access with the program data base.
e. Transfer of Control Amon Modules The dominant form of transfer of control processor 50000 among the different modules is through subroutine linkages, using the '~JSR" (jump to subroutine) instruction of the KDll~F processor.
Thus, an executive module calls a module in tier 56006 which init--12g-iates a specific state transition routine, In turn, the module in tier 56006 transfers control -to modules in lower level tiers.
Another mode of transfer control which is used to a minor degree is by means of the trap instruction capability of the KDll-F processor. Pursuant to this mode there is a fixed location in memory which identifies the address of a module which is to begin execution whenever the trap instruction is executed by the ¦processor. When such a trap instruction is invoked, the processor !begins execution of the module whose address is speci~ied in the - ~location regardless of the previous location in memory at which ,instructions were executed.
e arrows shown in the cluster diagram o~ Fig. 36 indicate the types of subroutine linkage and trap linkage transfers of ,control which occur from tier 56004 containing executive cluster 56040 down to tier 56010 containing input/output utilities.
¦f. Organization of Data Bases , The data bases for stored program 56002 are generally either I !at the level of the individual modules, or at the system level at ~¦which modules of data base utilities cluster 56880 must be emp-¦lloyed for input and output access. In general, there are no data Ibases at the cluster or tier levels of the hierarchical design of I program 56002.
4.
a. ~
me modules of executive cluster 56040 perform the ~unction of de-termining the next event to be processed, setting up certain conditions for the transition to be used, and giving control to a transition routine. The executive cluster is capable o~ calling all the transition routines, but is not called by any other routine of any call processing cluster. The only data base used in the executive cluster is a Transition Routine Vector Table~

b~ ~
In general~ the function of the originations and dial tone cluster 56100 is to initiate a state transition routine for handl-ing new originations on lines and trunks. More specifically) the functions of these modules are to react to seizure events, find and connect the required tone ports and receiving devices, and to establish the call state necessary for digit collection. The ~modules in this cluster also imitate miscellaneous state transit-ions routines associated with call progress tones. The modules of executive cluster 56040 schedule the modules within this cluster by decoding the call state and event code reported by telephone event processor 35000 in connection with the port associated with the call The modules of cluster 56100 in turn interface with several lower tier clusters.
c. Receiving Di~its Cluster 56140 ! -In general, modules oY rece:iving digits cluster 56140handle the progress of a call from dialing (or receiving, if a trunk) to the ringing state. More specifically these modules are responsible for handling the digit collection portion of calls from local subscribers and interoffice trunks. At the completion of dialing, and depending upon the specific digits received, the call is advanced to its next state. Modules of cluster 56140 are entered from modules in executive cluster 56040 together with the equipment ~umber of the port associated with the request for action. Control returns to executive cluster 56040 upon completion of execution. Modules of cluster 56140 form subroutine links with code point and number translators modules in tier 56008 and with buffer storage device utility and data base utility modules in tiers 56010, d Line-To-Line Cluster 56180 . ~...................................................... I
The modules of line-to-line cluster 56180 handle the progress . of a call from its transition starting in the ringing state to release. A Separate ~unctional subroutine iS provided for each possible event code generated by port event processor (PEP) 406 ,!during the performance o~ origination and dial tone ~unctions ~or ja line or a trunk. Modules of this cluster are called only by ~modules of executive cluster 56040 which also gives them the ~eqUipment number (EN) of the port which received the event that induced program action.
e~ Incomin~ Trunk Transitions Cluster 56220 In general, the modules of incoming trunk transitions cluster 56220 handle the completion of an inComing trunk call to a local termination. That iS to say9 they handle the processing of in-coming trunk eVents SUCh as release, timeout~ etc. Each module ~within the cluster represents an event code condition while in the various incoming trunk states; namely9 ringing trunk-line, ~,verifying, etc. When an event code is genera-ted~ a module in ex~
ecutive cluster 56040 will call or ~vector to~ the appropriate module within thiS cluster a~ter decoding the call state, port ordlnal call position identity number (PID#), and event codes stored in the port related memory field 33500 me executive cluster gives the EN of the port to the called module.

il Equipment Connect cluster 56400 encompasses those modules required to Connect one terminal to another. ThiS function in-cludes all path h~nting and path marking. Each module repreSents a unique connection to be made. Given the appropriate inpUtS, each module Will attempt to establish the connection ~or whiCh it is designated. An indication as to whether or not the task was accomplished iS returned to the calling module.
g. Equipment Release Cl~uster 56440 Equipment release cluster 56440 ContainS those modules required 1~L4S~ `

Ito release one terminal from another. They handle matrix path ¦lunmarking and the updating of the port related memory field ~3500 for the terminals involved. ~ach module represents a unique ¦Irelease to be made (i.e., release tone, release receiver). A
¦¦module of tier 56006 calls for execution of these modules and passes the required parameters. The module of tier 56006 also interfaces with tier 56010 clusters for input/output operations.
I¦The tier 56010 clusters handle all the needs for access to the idata base and for transmitting and receiving signals to and from circuit components~
h~ Translations Cluster_ 56480 In general, the modules of translations cluster 56480 perform the functions of digit analysis and directory number conversions.
~More specifically, they provide a buffer between the call process-; ;ing functions a~d installation dependent parameters to enable call progression stored program 56002 to operate in widely varying enviro~ments~ Code point and numbertranslators are provided to ~ ~interpret incoming digits in order to determine proper disposition `; of service requests. The cluster includes a code point translator -module and a directory number translator. From an input-output point of view, the code point translator is gi~en a string of ~,digits and produces a route treatment index. me directory number translator (used on local calls only) is presented with a directory Inumber and outputs a corresponding equipment number and ring code.
¦The modules in this cluster are called by modules in tier 56006, ¦and in turn, they make extensive use of modules of port da*a store lutilities cluster 56800 and modules of data base utilities cluster l!56880.
i Port Data Store Util ti_s_Cluster ~
Cluster 55800 of input/output utility subroutines provides program accesses and updates of data in the port related memory

13~-I
1~ .
field 33500 o~ the port requiring action. All modules which change lldata in memory field 33500 operate through these utilities. Only modules of cluster 56800 directly process input and output signals to and from memory field 33500. Cluster 56800 includes functional imodules which perform retrievals or updates to and from respective ¦~sets of coherent bit areas of memory field 33500. mese coherent ¦sets are based upon expected functions required by subroutines of higher tiers calling this utility cluster. A port store utilities IlMAcRos (PSUM) module (introduced later herein as 56802, Fig. 154) is assembled as MACRO coding for greater efficiency in execution time. The resulting code is in the form of trap instructions which are handled by a port store utilities trap handler (PSUTLS) module (later 56804, Fig.155). In this way, retrievals or updates ;of data in a port data memory field are more expeditiously executed ` fast to better enable the processing of a task to occur within real-time restraints. The modules of cluster 56880 may be called `!by any other cluster.
jO Network Utilities Cluster 56840 .
In general, network utilities cluster 56840 has the function ;of sending and receiving output and input signals to and from !CCP interf2ce controller 57000 in connection with the operation ~lof TSI matrix network 24000. The modules in this cluster are ¦!responsible for finding, marking, tracing, changing and erasing network paths through network 24000. Each module of the cluster performs a specific operation in connection with the network.
~'he basic operations in setting up a conversational path are~
finding a path timeslot, and (ii) marking the path. The basic operations in releasing a conversational path are: (i) unmarking the path, and (ii) idling the path timeslot. Modules within this cluster may interface with any higher level cluster modules.

l l ~, k. ~
i, The modules in da-ta base u-tilities cluster 56880 provide llprogram access for the other clusters to the system data base of ! program 56002. me provision of these utilities subroutines ¦¦provide a high degree of independence between the program instruc-¦¦tion content of program 56002 and data base storage techniques.
¦¦Most modules in this cluster are called by higher level clusters, ¦Iwhile a few are called internally. This cluster interfaces with I any module which must retrieve or update data in the system data base.

i" _ '. i .~ ; ~ '.

-~¦ A. LINE INTERFACE CIRCUIT (~000l OR 2000' WHEN_MUETIPARTY) ~¦ 1. Overview of Functions j~ Referring now to Fig. 37, line interface circuit 2000 is ¦ the point of interface between the analog signal on the telephone I line to a subscriber (or subscribers in the case of an interface,circuit 2000' for a multiple party line) and the analog side of the PCM CODEC/Filter circuit 3500. Circuit 2000 includes a CB
, relay 2002, a ringing relay 2004, and a test access (TA) relay 2006. Test access relay 2006 allows testing of the tip and ring leads into the switching system or out toward the subscriber.
¦I The ringing (R) relay 2004 is used to apply a ringing signal to ; the line and to perform party tests. After being switched through contacts of relays 2006 and 2004 the tip and ring leads ¦' are connected to a line inductor 2008, and via capacitor 2012 to a hybrid transformer 2010. The line inductor serves to provide a direct current path -to the transmitter of the subscriber's telephone.
The hybrid transformer is used to convert from the two wire ~ubscriber line to four wire path going to the CODEC. The connection to CODEC/filter 3500 includes a balance network 2014 i consisting of a register and capacitor.
Conversely, the stream of digital voice data bits from ~SI
matrix network 403 are demultiplexed and demodulated by the PFM
CODEC/filter 3500. The analog signal that results is applied to hybrid transformer 2010 for transfer to the tip and ring leads of !
the line. The analog signal is carried through the relay contacts described previously and thereby transferred to the subscriber.
Referring now to Fig. 37 the test access relay 2006, and ringing relay 2004 are activated by signals of the binary control channels of other-than-voice data TDM network 407 strobed into a control bit register 2016 by the port strobe (PS~ signal on lead 2018. The CB relay 2002 is activated by the detection of an off-hook condition at the subscriber's telephone. The functions of these relays are described in detail in the following paragraphs.

! 1 2. Operation of Test Access Relay 2006 The test access relay 2006 is activated by binary control ; channel bit CSA' (SA = CS0', CS2', CS4' & CS6'), of network 407 which is applied to the control bit register 2016 as the CSA bus (CBSA) signal 2020. When the relay is activated, the contacts 2006a and 2006b transfer the T and R leads from tip and ring, respectively, to "test tip out" (TT0) and "test ring out" (TR0) leads 2024 and 2026, respectively. The contacts 2006c and 2006d connect the port-side tip and ring leads to the "test tip in"
,, ¦! (TTI) and ~'test ring in~ (TRI) leads 2032 and 2034, respectively.
With relay 2006 activated, TT0 and TR0 cab be used to test separately the condition of the tip and ring sides of the line - to the subscriber. TTI and TRI can be used to test the path from the relay into the system 400 via the line interface circui-t When the test access relay is not activated, the normally closed contacts including contacts 2006a and 2006b connect the tip and ¦I ring leads to the line inductor 2008.

3. OPeration of Rin~in~ Relay (Single PartY Line?
Ringing relay 2004 is activated by fas-t binary control channel CFl' of TDM network 407, the CF1' channel is applied to the control bit register 2016 as the CFl bus (C~Fl) signal on ; lead 2036. When the relay is activated and contact 2004a ac-tivated, the following functions are produced:
1. A single frequency ring bus (SFRB) lead 2038 is connected l, ~

! to the ring lead via: one winding of CB relay 2002, one coil o~

~l line inductor 2008, and through the ring side of the subscriber's ' line.

, .
~` ! 2. SFRB is used to apply the ringing signal to the ring lead.
Ii When -the ringing relay 2004 is not activated, talking ! battery is applied to the ring lead, and ground is applied to ; the tip lead of the line via the CB relay 2002 and line inductor 2008.

4. 0 eration o~ Ringing Relay Four Party Line) In the case of an interface circuit for a four party line, the ring signal applied to the make contact 2004a comes in via ` mu]tiple frequency ringing bus (MFRB) lead 2038 (shown in , phantom). The operation is the same as the case of a circuit 2000 for a single party line, However the signal from fast control data channel bus CBFl is selectively controlled to operate the ring (R) relay 2004 during the phase of the MFRB
signal which corresponds to party's ringing frequency.

, 5. Operation of CB Relay for Supervision Sensin~
, The CB relay is activated by an off-hook condition on the line. When activated, the rela~ contacts 2002a apply ground to ¦ one input of a sense bit driver 2040, generating the corresponding level output over fast sense channel SF~' of TDM network 407.
This occurs upon receipt of the,next port strobe signal 2018 from PGH MUX/DEMUX circuit #2 (18000) on lead SBFO of sense ¦1 and control buses 402', Fig. 37.
.
I

6. Operation of CB Relay for RinF Trin Function 1 The CB relay 2002 is used in conjunction with an up/down '1 counter, 40024 and 40026, in Ring Line Logic Unit 40000, Fig. 93 i to determine the point when the subscriber being run has answered. If the subscriber answers during the silent interval ¦'l between ringing bursts CB relay 2002 operates and remains operated on the ac current flow occurring when the subscriber's phone is taken off-hook. The contact of CB closes 7 setting the SBFO bus '110w", which in turn is communicated to the ~ bit ~; location of subfield 33501 by the SFO' channel of other-than-voice data network 407. The stream of SBFO bits will be all ,. i "low" causing counter 40024 and 40026 to count "up" to the count of 32 indicating the "ring trip" condition has been reached, causing the unit 40000 to remove ringing current from the line.
During the ringing burst CB relay 2002 operates on the negative-going half cycles and releases during the positive-going half cycles of ringing voltage due to the diodes 2018a and 2018b in shunt with its windings. This results in the bit stream SBFO
being only 50% or less low bits; equivalen-t to 50% make or less at the CB relay contact. The up/down counter of Ring Line Logic Unit 40000 is arranged~to count UP one step on each "low" SBFO
bit and to count DOWN one step for each "hi-gh SBFO bit; therefore, with 50% make or less from the CB relay contact, it carnot count up to a count of 32, which is the count chosen to represent the ring trip condition.
If the subscriber answers during the ringing burst, CB
relay 2002 wil~ have a direct current (due to the 48 volts dc superimposed on the ringing supply) component in addition to the alternating ringing current. This causes CB relay 2002 to have an increased per cent of "make" at its contact. The up/
down counter of Ring Line Logic Unit 40000 therefore receives 11~5~19 i more "low" than "high" bits in the SBFO bit stream causing it to count up to 32 and indicate the ring trip condition. This in turn results in ringing current being cut off from the line by release of R relay 2004 under control of Ring Line Logic Unit 40000.

, 7. Control Table ; The utilization of the various relays of circuit 2000 during the progress of a call are depicted in the control table of Fig. 38. The control table is generalized to include a number of other versions of the circuit.

.
I B. E & M TRUNK INTERFACE CIRCUIT (3000) The E&M trunk interface circuit 3000 interfaces voice and supervision signals transferred between another local or distant office and swi-tching system 400.
Referring to Fig. 39, relays in each trunk circuit are operated by the signals from binary control channels CF~', CFl', .
CSA' and CSB' of internal supervisory data network 407. These signals in turn have been generated by port event processor (PEP) 406, The PL (pulsing) relay 3002 is used to connect negative 48 volts via a resistance lamp to the M lead 3006. The TA (test access) 3008 relay provides test access to the tip and ring leads 3010 and 3012. Similarly, the TB (test access B) relay 3014 provides test access to the signalling leads consisting of M lead ¦
3006 and E lead 3016.
Analog voice signals received from a local or distant office on the tip and ring leads of the E&M trunk circuit are connected to a hybrid transformer 3018. The hybrid transformer serves to convert the two-wire subscriber's line to a four-wire path going to and from PCM CODEC filter 3500. Associated with the hybird transformer is a balance network 3020.

¦ Signalling from the trunk circuit to the distant office is accomplished using PL relay 30020 This relay is operated by il fast binary control channel CF0' of TDM network 407 which is ¦¦ received on lead CBF0 of sense and control buses 402', Fig. 39 ¦ When relay 3002 is operated its contacts 3002a switch M lead ¦ 3006 from ground -to minus 48V.
Return supervisory signalling may be present on the E lead ¦¦ 3016. Presence of return signalling causes the binary sense channel SF0 to be set high. The output of the driver is sent to PGH MUX/DMUX circuit #II (18000) when a port strobe is addressed to the trunk circuit. The binary sense channel SSA' -transmitted t Il along bus lead SBSA serves as an indication that the trunk i~i circuit is installed in the system.
The TA and TB relays 3008 and 3004, respectively, provide test access to the voice path and to the signalling path. TA
~I relay contacts 3022 and 3024 break the tip and ring leads just i outside the hybrid transformer 3018. When operated contacts j, the line side of tip and ring to the TTO and TRO test leads 3026 and 3028, respectively. TA relay 3008 connects the switçhing ~ system side of tip and ring to TTI lead 3030 and TRI lead 3032, !
'' respectively. These connections allow the line side and the ¦I switching system side o~ the subscriber loop to be tested independently. Operation of relay TA 3008 also completes the path to ground for the -48V battery across the coil of the TB
relay 3014, which operates the relay.
The TB relay 3014 breaks the E lead 3016, just outside an optional coupler 3034 and switches the line side to the TEO
test lead 3036 and the equipment side -to the TEI test lead 3038.
At the same time, relay 3014 breaks the M lead 3006 just outside the contacts 3040 of PL relay 3002 and switches the line side to the TMO test lead 3042 and the signalling system side to a TMI test lead 3044. Thus, the line side and the equipment side t of each signalling lead can be tested independently.
¦ The utilization of the various relays of circuit 3000 ¦I during progress of a call are depicted in the control table ¦¦ of Fig. 40.
' I
CO PCM CODEG CIRCUIT ~3500) LL-2~c~ L
Referring to Fig. 41, a pulse code modulation coder-decoder (CODEC) and filter circuit assembly 3500 has six (6) separate codecs along with associated circuitry common to all six (6) codecs-filters including a timing generator and associated gates 3502, and a reference voltage source 2503. Each codec-filter consists of a transmit filter 3504, a receive filter 3505, referring to Fig. 42, a sample and hold circuit 3512, and a hybird circuit 3514 containing the coding and decoding circuits. Referring to Fig. 41 in conjunction with Fig. 447 a timing generator 3502 takes an incoming 128 KH~ clock signal (CLK), Fig. 44, and a 8 KHz synchronization signal (SYNC) and d~rives therefrom even and odd encode/decode pulse signals "E
(E)" and "E (O)", even and odd start pulses, "S (E)" and "S (O)", I
and even and odd sample and hold pulse signals "S/H (E)" and "S/H (O)".
A set of three multiplexers 3515a, 3515b, and 3515c) each multiplex the outputs of two (2) codec~filters in response to steering of the E (O) pulse odd and the E (E) pulse even. The demultiplexing takes place internally with the hybrid circuit 3514 for coding and decoding (within each codec-filter 3501).
As a result of this scheme, there are three (3~ DO (transmit) outputs and three (3) RCV (receive) inputs from and to each circuit assembly 3500.
Minus reference voltage circuit source 3503 provides a -10 volts to each hybird circuit.

~142-2. Descrl~tion of Codec-Filter Circuit Reference is now made to Fig. 42 which is a block diagram of an individual codec-filter 3501 in circuit assembly 3500.
A transmit filter 3504 consists of four (4) filtering stages.
The first stage 3516a is a high-pass section providing rejection to 60Hz. The second stage 3516b provides a real pole for in-band response and out-of-band rejecticn. The third stage 3516c produces a pole pair (resonance) in-band and a null at about 4600 Hz. The fourth stage 3615d produces an additional resonance in-band and a null at about 6600 Hz.
Sample and hold amplifier 3512 takes the signals from the transmit filter, samples the voltage levels and holds each of the sampled levels. It samples the voltage levels for 54.7 usec and holds 7Q.3 usec. The sampled voltage is stored in a .
capacitor 3517.
Hybird circuit 3514 provides the coding and decoding action. It is physically constructed of five (5) integrated circuit units or ''chips''c The five (5) integrated circuit units consist of a standard commercially available type 311 comparator unit 3518, a standard commercially available type 25L02 successive approximation register 3519, a standard commercially available type DAC 86 companding digital to analog converter 3520 (produced by Precision Monolythic Incorporated, Santa Clara, California), and a standard commercially available type 741 operational amplifier 3522. The fifth integrated circuit unit 3524 is a special purpose interface circuit which steers the incoming and outgoing pulses during coding and decoding times.
The analog to digital conversion uses the successive approximation technique.
The digital to analog conversion is accomplished using the ~AC circuit 3520. Because the DAC circuit is used for ..
both A/D and DtA conversions, it is time shared. The proper ; steering for this time conversion is provided by interface i circuit 3524.
; The signal out of DAC circuit 3520 is fed into the OA
(operational amplifier) 3522. The signal out of amplifier 3522 is a 50% duty cycle pulse amplitude modulated (PAM) signal, i which is the input signal to receive filter 3505.
; Receive filter 3505 contains three (3) filtering stages.
The first stage 3527 forms a null at 8 KHz.
The second stage 3528 produces a pole pair for in-band frequency shaping and a null at about 4600 Hz for out-of-band rejection.
The third stage 3530 produces a higher Q pole pair (resonance) for in-band frequency shaping.
Referring again to Fig. 41, the six (6) codecs-filters 3501 in each circuit assembly 3500 are designated as three even codecs and three odd codecs. The common circuitry includes a set of multiplexers 3515 which provide three (3) transmit outputs. This multiplexes pairs consisting of odd and even codecs. Each multiplex circuit of the set is conventional and ~ constructed of a 74L$51 type integrated circuit multiplexer.
; The demultiplexing of the two received channels takes place ; l in the codec-filters 3501.
1I The portion of the common circuitry and associated ¦I gates 3502 which derives the timing signals of Fig. 44 is ¦l constructed of conventional divider and logical gating circuitry.
The signals ~g and ~YR~ come from mux/dmux circuit 16000, i and are given the signal designations C CLK and C SYNC therein.
Reference is now made to Figures 45 in conjunction with Fig. 43 for a description of the operation of interface circuit 3524. As stated earlier, interface circuit 3524 provides the proper steering and interfacing mechanisms for comparator 3518, ~1 .

,1 successive approximation register (SAR) 3519, and digital to ' analog converter ¦DAC) 35200 The encoding process will be described for an even sequence. The same process applies for an odd sequence.
Encoding starts when the S (E) pulse, Fig. 44 goes high.
At this time DAC 3520 is still in the decode position. It is during this time that the sign of the input signal from sample I and hold amplifier 3512 is determined because there is no '~
comparison voltage or feedback from DAC 3520. This,establishes the value of the first bit in SAR 3519. Once the first bit is ~¦ in SAR 3519, logic network 3521 identifies the sign of the analog signal and controls SM 3519 in a way in which successive ~ bits represent magnitudes. At the next clock pulse DAC 3520 - ` is switched to encode, and the value of the second bit in SAR
3519 is established by comparing the signal fed back from DAC
I ' 3520 with the input signal. DAC 3520 is kept in the encode i state for 62.5 microseconds and the values of the remaining bits are successively established in a similar way. The encoded word bi-ts sequentially appear at the XMT output at a 128 KHz rate with a 1 bit delay.
While the encoding process is taking place, the receive ', digital signal (RCV(E)) is being steered into the shift register ¦~ 3532 by the receive clock (RCV CLK(E)) pulses generated within interface circuit 3524. As soon as the encoding interval is complete, the contents of shift register 3532 are steered in parallel into the DAC 3520 where they are held for the duration of microseconds (which is the complement of the appropriate j encode timet i.e. E (O) or E (E), Fig~ 44. The output from DAC 3520 then goes into operational amplifier (OA) 3522 and out into receive filter 3505. The circuiting for performing this operation is diagrammatically depicted in Fig. 43.

1~

Reference is now made to the electrical schematic of Fig. 45 which is partially a block diagram and partially an electrical schematic. The electrical schematic is a detailed representation of interface circuit 3524. A logical network 3534 derives the signal for clocking the digital input, RCV
into shift register 3532. The output of network 3534, designated the RCV CLK signal, is derived from both the CLK signal and the appropriate encode E signal Fig. 44. After the digital input signal is clocked into shift register 3532 a logic network 3536 s-teers each bit position of the shift register into the corresponding input of DAC 3520, and maintains the signal levels at these inputs for 62.5 microseconds. This is sufficient to permit DAC 3520 to present the analog output ~or the 50% duty cycle.

D. VOICE DATA MULTIPLE:~ER/DEMULTIPLEXER (16000) 1. Basic Structur e~a.i^r Refe~ring now to Fig. 46, voice data multiplexer/
demultiplexer circuit 16000, converts parallel data received from the thirty (30) CODEC channels (five PCM CODEC/filter circuit assemblies 35000, each providing six channels) to serial data for transfer sense/control data multiplexer/demultiplexer 18000, and converts serial data received from the multiplexer/
demultiplexer 18000 to parallel data to be sent to the CODECs.
In addition to these parallel-to-serial and serial-to-parallel conversions, circuit 16000 reformats the data transferred in each direction to match the requirements of the CODECs to those of the port group highways (PGHs) 402' and 402 " connected to TSI matrix switch network 403.
Data ~rom the 30 CODECs are received on 15 parallel inputs~
each bearing multiplexed data from one odd-numbered CODEC and ~` one even-numbered CODEC. A multiplexer 16002 multiplexes II these parallel data streams received at 128 KHz to a single serial bit stream of 2.048 MHz. A transmit RAM 16004 transforms I the format of data to that required by PGH frame 402'. The ij serial output of transmit RAM 16004 then is sent to sense/control ¦¦ data mul-tiplexer/demultiplexer circuit 1~000, from which it is ¦ -transmitted to the TSI network 403 via PGH 402.
' Data received from TSI network 403 via port group common utility circuit 20000 and multiplexer/demultiplexer 18000 is ' reformated by a pair of receive RAMs 16006a and 16006b to conform to the requirements o~ the CODECs. The outputs of these receive RAMs 16006a and 16006b are demultiplexed by a pair of 16-bit sh ft registers 16008a and 16008b. The parallel data from each of these registers are applied alternately by tri-i state drivers 16010a, 16010b to the 15 outputs to the CODECs.
''' 2. Transmit Data Multiplexin~
a. Data Format Conversion and Multi~lexing Referring now to Fig. 47 the input data from the 30 CODEC
channels enter multiplexer/demultiplexer 16000 on 15 parallel ,j inputs labeled XMT 0-1 through XMT 28-29. A sixteenth input, XMT 30-31 contains diagnostic data. Each of the input leads i 0-1...28-29 carries, alternately, an 8-bit serial word from an even-numbered port and an 8-bit serial word from an odd- ¦
numbered port. These 8-bit words are presented, most significant bit (MSB) first, to 16-to-1 multiplexer 16002.
Operating at 16 times the CODEC data rate, 16-to-1 multiplexer 16002 selects one of the 16 XMT leads at a time and transfers the bit from that lead to the data input lead of a transmit RAM 16004. In this way, all 16 parallel bits from the CODECs are ~itten serially into the RAM before the next set oi L45~

¦ parallel CODEC data appears.
¦I Transmit RAM 16004 stores 256 bits, constituting a frame of ¦l eight bits from each of 30 ports, and the bits of diagnostic data~ Data is both written into and read from the RAM at 2.04~
MHz. For each 488 nanosecond period corresponding to this rate, one bit of data is written into the RAM during the first 244 nanoseconds (half-period), and one bit of data is read out of the RAM during the last 244 nanoseconds. The addresses for the write and read cycles are applied through a 2-to-1 selector 16012, which receives the addresses from binary common counter 16014a and XMT RAM address counter 16014b. The addresses are selected in such a manner as to change the format of the data received from the CODECs into a format compatible with the frame of transmit PGH 402'. In turn, the format of PGH 402' is compatible with the circuitry o:E TSI network 40~.
1 The change of format is accomplished by writing the data ¦~ into one sequence of locations of transmit RAM 16004 and then f li rsading the data from these locations in a different sequence.
¦¦ ThusJ bit 7 from all the even-numbered CODECs, or channels, is written into -the first 16 locations of transmit RAM 16004. Then bit 6 from all the even-numbered channels is written into the ', next 16 locations. This pattern continues until all eight l ! bits from all 16 even-numbered channels have been written into I the first 128 sequential locations of transmit RAM 16004. Then the entire process is repeated for all eight bits from all 16 odd-numbered channels placing them into -the second 128 sequential locations of transmit RAM 16004. Each bit is written into i-ts location approximately 200 nanoseconds after the leading edge of the C2MHz clock occurs. Approximately 44 nanoseconds later the 2-to 1 address selector 16002 switchss -to present the read address to ths transmit RAM 16004. The bit read from the addressed location is clocked into the transmit flip flop 16016 by the trailing edge of the next ~ pulse.
; The format conversion upon readout from RAM takes place I l~ in the following manner. Bit 7 for channel O is read from the field of even-channel location in tramsit RAM 16004 RAM.
Then bit 7 for channel 1 is read from the field of odd-channel I locations in the RAM of the RAM. This alternating between even-iI channel and odd-channel fields of the RAM occurs each cycle of ; - the C2MHz clock until all eight bits for all 32 channels have been read from the RAM. Then the reading of a new frame of 32 8-bit words begins, providing a continuous stream of transmit voice data to sense/control data multiplexer/demultiplexer 18000.
b. Transmit RAM Address Counter (16014) Write and read addresses for the 256 bit locations in Transmit RAM 16004 are provided by 4-bit Common Counter 16014a and 4-bit Transmit RAM address counter 16014b. These counters ~ operate from the C2~z clock signal and are synchronized by the ; , SYNC pulse, which occurs every four milliseconds to synchronize the system. A count of 133 is loaded into this combination of counters when SYNC occurs to offset the CODEC from its associated TSI circuit 24000 by half a frame plus a few bits to compensate ¦ for latch delays and skew. The square waves output by these counters range binarily from 1024 KHz out of the least significant output to 8 KHz out of the most significant output.
c.
The eight binary address leads of transmit RAM 16004 are switched by 2-to-1 Address Selector 16012 to the appropriate output leads from counter 16014a and 16014b for the write operation, and then to a different 8et of output leads from the counters for the read operation. This takes place every ,~ 1145~9 ii~
¦1 488 nanosecond period of the 2.048 MHz clock signal. In order ! to split this period into first a write portion and then a read portion, a delay line 16018 is used, giving approximately 250 nanoseconds total delay. A flip-flop contained in transmit ¦! address selector con-trol 16020, is controlled by both direct ¦¦ and delayed 20048 MHz clock pulses. This flip~flop is used to switch the address selector from the write mode to the read mode and vice versa.
d. Readin~ of Data From Transmit RAM
Data is read from the transmit RAM 16004 and applied to transmit flip-flop 16016 when 2-to-1 Address Selector 16012 switches the binary address leads of RAM 16004 from performance of a write operation to performance of a read operation. This I applies the read address to the RAM. At the end of the 488 nanosecond period of the clock, the data is latched into transmit flip-flop 16016 by the positive-going edge of the C2MHz signal.
The output of flip flop 16016 is then transferred to sense/
control data multiplexer/demultiplexer 18000.
, 3. ~
The CODECs require a clock pulse at 128 KHz and a synchronizing pulse to align the CODEC frame with the frame in the associate TSI circuit 24000. The CODEC clock (~ ) is ¦j derived by combinational gating 16022 from the outputs of the ¦¦ common counter 16014a. The signal produced by the clock ¦I generation gating 16022 is latched by CODEC sync pulse (~
¦~ is derived similarly by combinational gating 16022 from the outputs of transmit RAM address counter 16014b and 128KHz output of the common counter 16014a. The signal produced by the sync generator gating 16022 occurs at 8 KHz. After being latched by a CODEC Sync flip-flop 16026, this signal is driven -to the CODECs.

-~ l ~

¦ 4. Receive Data_Demultiplexin~
a. ~
j~ The conversion of the format of the receive voice data I from sense/control data multiplexer/demultiplexer 18000, is I performed in a manner similar to that for the transmit voice I data from the CODECs. However, to convert the receive data, two receive RAMs 16006a and 16006b are used for alternating, in a ping-pong fashion, for the conversion of 256-bi-t frames of data. While data bits from the multiplexer/demultiplexer 18000 ~- are being written into one of the RAMs, data bits to be sent to the CODECs are read from the other RAM.
Data bits are written into the Receive RAMs in the format in which they come, the receive port group highway (PGH) 402".
Therefore, bit 7 for channels O through 31 is written into the :., i thirty two bit-7 locations according to the pattern described ; 1i in connection with reading transmit RAM 16004. Then "bit-6s"
for channels O through 31 are written into the thirty two bit-6 locations. The writing of data continues according to this pattern until the entire 256-bit frame has been written. Then the next frame begins to be written into the other of RAMs ~~ 16006a and 16006b, and the frame ~ust writ-ten begins to be read i~' from the first RAM.
Data bits are read from the Receive RAMs 16006a and 16006b in a serial pattern, which when converted to parallel form, becomes the format in which they are sent to the CODECs. First, bit 7 for all seven channels is read from the RAM and strobed into serial in, parallel out shift Register 16008a. Next, bit-6 for all even channels is read from the RAM and strobed into serial in, parallel out shift register 16008b. The tri-state drivers 16010a and 16010b are enable alternately to apply the parallel outputs of each shift register to the 16 CODEC RCV

¦l leads. The reading of bits continues in this fashion until all ¦l eight bits for all 16 even channels have been read, shifted, j and transferred. Then the process is repeated for all eight !' bits for all 16 odd channels~ With the reading of one 256-bit il RAM of RAMs 16006a and 16006b thus completed, the reading of ¦¦ the other RAM begins.
~! A 42-bit delay shift register 16028 delays the serial ¦l data stream received from sense/control data multiplexerj demultiplexer 18000. This delay, when added to that of TSI
circuit 24000, the 16-bit serial in, parallel out shift ; register 16008a/16008b, and other circuits, aligns the reformated data with the CODEC frame.
b. Receive RAM Addres~_~g~
A 4-bit Receive Ram Address Counter 16014c is used along with common counter 16014a to generate the address inputs for receive RAMs 16006a and 16006b. The combined receive/common counter is preset (not shown in Fig. 4) to 16 by the carry output of the transmit RAM Address Counter 16014b upon the next clock pulse after the combined transmit/common counter reaches 255. This offsets the data frame being read from receive RAMs i 16006a, 16006b to compensate for the delay incurred in loading !i the bits into the 16~bit serial in, parallel out shift registers ¦ 16008a, 16008b-¦ c. Receive RAM Address Selectors_(16030a,_16030b~
The eight binary address leads of receive RAMs 16006a, 16006b are switched by 2-to-1 selectors 16030a, 16030b to the appropriate output leads of counters 16014a and 16014c for the write and read functions to accomplish the format change. This is done in reverse order to that described for transmit voice data. The address selectors are controlled by a RAM alternating flip-flop Contained in receive RA~I write/read control 16032, which changes state at the end of each receive voice data frame.

,~ This flip flop also gates -the Write Enable (WE) pulse to the receive RAM 16006a or 16006b that is in the write mode and gates the data output from the RAM which is in the read mode.
d. ~
¦¦ Data bits from 42-bit delay shift register 16028 are applied ¦, to both receive RAMs 16006a and 16006b, but are written into 1~ only the RAM that receives the write enable (WE)pulse. A receive ¦I voice data bit is written into one of the two RAMs during the ~ ! second half of each 488 nanosecond period of the C2MHz clock ; I signal.
e. ~
, When the R~ pulse is not being applied to one of the receive j !
RAMs 16006a or 16006b, that RAM is in the read mode and a bit o~
data from the location specified by the currently selected address is present on the output lead. As each bit of data is read from the RAM, it is put into one of 16-bit serial in parallel out shift registers 16008a, 16008b, and shifted one stage upon each C2MHz CLK pulse. When 16 bits have been loaded, the register is allowed to stand with these bits feeding out in parallel, via enabled drivers 16010a or 16010b, to the CODECs.
Meanwhile, the next 16 bits of data are shifted into the other 16~bit shift register 16008. This is the method used for demultiplexing the serial data onto 16 parallel leads to the CODECs. These shift registers alternate in a ping-pong fashion every 16 bits. Tri-state drivers 16010a, 16010b that send the 16 parallel data bits to the CODECs are enabled alternately by the straight and inverted 64R output of receive RAM address counter 15014c. Thus, each of these signals enables the drivers with which it is associated for 7.8125 microseconds. With this arrangement, one even bit and one odd bit is sent to all even CODECs every 15.625 microseconds until all 16 even CODECs iQ~9 have received the entire 8-bit data word. Then one even bit ¦ and one odd bit are sent to each odd CODEC until all 16 odd ¦¦ CODECs have received the entire 8-bit word. This completes the trans~er o~ one 125-microsecond, 256-bit data frame.

E. SENSE/CONTROL DATA
MULTIPLEXER/DEMULTIPLEXER ~18000) I 1. Overview Description ¦ Sense/control data multiplexer/demultiplexer circuit 18000 multiplexes the transmit voice data from voice data multiplexer/
, demultiplexer 16000 and a data stream of sense information of ! sense/control TDM network 407 ("sense bits") and sends the combined signal to a TSI circuit 24000.
Conversely~ circuit 18000 receives from the TSI circuit 24000 (via port group common utility circuit 20000) a combined signal representing receive voice data and supervisory control li information ("control bits") in the format of the TDM frames of jl receive port group highway (PGH) 402 " , Fig, lB. Circuit 18000 ¦~ partially demultiplexes this signal, sending the receive voice !i data to multiplexer/demultiplexer 16000 and the control data to the port circuits the control buses of sense and control buses ¦ 401 "', Fig. lB.
The supervisory sense and control data contained in timeslots`
~30 and #31 of the TDM frame formats of transmit and receive PGHs 402' and 402 " are clocked from or to the appropriate port equipment positions by port strobes, which are generated within circuit 180000 The PGC #I 18000 also contains circuitry that allows the sense/control data paths to be tested. This circuit,ry loops the fast control data signal on bus CBFl back on fast sense bus SBFl when port strobe 31 occurs.
Clock and synchronizing signals are received by the circuit -15~-11~5~
i l ¦ 18000 from the connected TSI circuit 24000~
:~ l ' 2.
¦llReferring now to Fig.48, a port group highway binary counter and decoder 18006 is driven by the C2MHz clock signal. Counter ~ and decoder 18006 provides timing signals for internal use by I sense/control data multiplexer/demultiplexer 18000 in order to I' handle sense or control data, control port strobe generator ¦, 18003, and generate the Select 1 millisecond (SEL IMS) signal on line 18018 and the Select 2 millisecond (SEL 2MS) signal on line j 18020 that can selectively gate the data of the various slow TDM channels to time share the sense and control data bus wires between circuit 18000 and the port equipment circuits.
, .
~l3. Receive Data Demultiplexin~
; 1lThe serial bit stream from TSI circuit 24000, received via port group common utility circuit 20000 contains both voice data and sense/control data. These are separated by circuit 18000. This is accomplished by applying the data stream both to 2-to-1 data selector 18014a and in turn to control data .i :
i formating logic 18014b. Control data ~ormating logic 18014b is timed to store data from the bit stream when the control data portion of the stream is present. 2-to-1 selector 18014a is timed to pass the data stream on to multiplexer/demultiplexer 16000 when voice data bits are present. It will be appreciated ; that part of the demultiplexing of the data stream involves stripping off and reformating the control data bits.
During each l-millisecond period, port group timeslots 30 and ~1 occur twice for each port. During each of these timeslots, a control bit is stripped from receive port group highway 402 "
by 2-to-1 data selector 18014a. The four control bits received serially during each port group frame couplet by each port in -`` !l !

, . , this manner during a l-millisecond period are demultiplexed by control data formating logic 18014b, and applied as four parallel bits to be sent to the por-t circui-t via control bits the control bus wires of sense and control data bus 402". Two of these I wires (CBF~ and CBFl) transmit the fast control channels; and i! the other two (CBSA and CBSB) transmit the slow control channels.
Bus wires CBSA transmits one of the even slow control channels CS0', CS2', CS4', or CS6'. Bus wires CBSB transmits one of the odd slow control channels CSl', CS3', CS5', or CS7'. Bus wires CBF0, CBFl, CBSA, and CBSB are connected to all the ports equipment positions in the port group unit, and also to PG
common utility circuit 20000, but are latched and used only by the port to which -the port strobe is sent, or by circuit 20000 when port strobe 31 is generated.
Port strobe generator 18003 cycles through 32 port strobes is one millisecond. During the first of these cycles, the data bits of fast control channels CF~' and CFl' and slow control channels CS0' and CSl' are strobed into each of the 30 ports and into PG common utility circuit 20000. A different port is strobed last in the cycle. During the next cycle, updated ; from fast control channels CF~' and CFl' are strobed into all the port circuits and circuit 20000 along with data from slow ; ~ channels CS2' and CS3'. During the third l-millisecond cycle, updated data from fast control channels CF~' and CFl' are again i strobed into the port and circuit 20000 along with data from slow control channels CS4' and CS5'. During the fourth 1-millisecond cycle, updated data from fast control channels CF0' and CFl' are strobed into the ports and circuit 20000 along with data from slow ccntrol channels CS6' and CS7'. Thus, during the four milliseconds required to transfer to all the ports and circuit 20000, the entire set of data from eight slow channels and four sets of data from fast control channels are 1145~19 transferred. This sequence is repeated every four milliseconds.
Formating logic 18014b consists of three pairs of flip-flops clocked by signals derived from outputs of port group control counter and decoder 18006. As the control bits occur on receive por-t group highway 402 ", during port group timeslots 30 and ~1, they are clocked into the first pair of flip-flops.
One of these flip-flops stores the bit from timeslot 30, which is assigned to the fast control bits. The other flip-flop stores the bit from timeslot 31, which i5 assigned to the slow control bits.
The outputs o~ the firs-t pair of flip-flops are applied to the other two pairs in an alternating fashion such that each pair stores one fast bit and one slow bit. These flip flops are clocked in pairs by an output from port group counter and decoder 18006. Sixteen microseconds after all four control bits are available on the CBFO, C3Fl, CBSA, and CBSB lines to the port circuits, the next por-t strobe is genera-ted to store the four control bits in the port equipment interface circuit or in the PGC common utility circuit 20000, as addressed by the port strobe. This sequence is repeated for each port strobe until all 32 port strobes have been generated.

4. Transmit Voice Data and Le~e D~t~ Vu~ l~x~l~
Referring again to Fig. 48, sense/control data multiplexer/
demultiplexer 18000 receives serial voice data from the multiplexer/demultiplexer 16000 along a transmit voice data bus 16000' and sense data along the sense wires 18002 of sense and control data bus 402 " ', Fig. lB. In circuit 18000, the transmit voice data is multiplexed with the sense data to produce a serial TDM data stream which is applied to TSI circuit 24000 via PGH highway 402'.

Four parallel sense bus wires (SBF0, SBF1, SBSA, and SBSB) are received by circuit 18000 from a port in response to the corresponding port s-trobe (also generated by circuit 18000) along sense wires 18002 of bus 402 "', Fig. lBo Transmit voice data and sense data selector 18012 multiplexes these four bits with the transmit voice data received from multiplexer/
demultiplexer 16000. The output of transmit ~oice data and sense data selector 18012 is then communicated to TSI circuit 24000. The arrangement for sense data is similar to that previously described for con-trol data in that bus wire SBF0 and SBFi transmit fast sense channel data every millisecond;
and bus wires SBSA and SBSB transmit, respectively, data fro~
even slow sense channels (SS0', SS2', SS4', or SS6') and data from odd slow sense channels (SSl', SS3', SS5', or SS7') every four milliseconds.
Data on bus wire SBF0 and SBSA, are strobed into the sense bit latches 18004 every 16 microseconds by a timing signal ~rom port group control counter and decoder 18006. The outputs 'i o~ the sense bit latches then are applied to four inputs of 8-bit transmit voice data and sense data selector 18012. Sixteen microse-conds later, the data transmitted SBFl and SBSB are inserted into the next port group timeslots 30 and 31. In this manner, two fast and two slow sense channels from all 30 ports are multiplexed by circuit 18000 during a l-millisecond period.
Every four milliseconds, four sets of data from two fast channels and one set of data from eight slow channels are multiplexed.
!

Il il ll, 1 5 Port Strobe Generation Port strobe generator 18007 generates thirty-two 7.8125 microsecond port strobes over a period of 1 millisecond.
l, Strobes 0 through 29 are used at the thirty port equipment ¦I positions both for receiving control data and for sending sense ¦I data. Strobe 31 is used in circuit 18000 to complete the port test supervisory bit loop and in PG common utility circuit 20000 for sending and receiving data bits used by the circuit 18000 and also data bits used by circuit 20000 itself.
The por-t strobes are generated by two 4-to-16 bit decoders included in generator 18003, but now shown) with common strobe and data inputs.

6. Port_Test Loo~
Circuit 18000 contains logic that stores a bit of control data, and then returns it to port data store 33000 as a sense data bit. This arrangemen-t allows maintenance logic (not showr.) to check the sense and control data path in both directions ; between port data store 33000 and circuit 18000.
~ A data bit from bus wire CBFl, after being demultiplexed i from the receive voice data and control data input is stored i, in a latch (not shown) by the trailing edge of the port strobe ~or timeslot 31 (PS(31-~). The leading edge of the next applies the stored control bit to the supervisory input latch (included in latches 18004) via bus wire SBFl.
This is an example of the use of a fast channel data path as a diagnostic tool looping around by way of the port group control circuit 20000 from the port data store ~0000, and back ¦ again.
Referring to Fig. 4, the last two couplets of each fast 114S~
i!
, bit frame; namely, 30 and 31 are not used for line or trunk ports but are available for, for instance, couplet 30 being used for maintenance purposes and couplet 31 being assigned ~ for con-trol functions of the por-t group control circuit 20000 9 ¦l itself. The port test loop is an example of the use of one of - ¦I these bits.
Il, ¦I Fo PORT GROUP COMMON UTILITY CIRCUIT (20000) 1 1.
The functions of port group common utili-ty circuit are ,! a5 follows. It provides a trans~er path for data and supervisory bits from TSJ circuit 24000 to sense/control data multiplexer/
demultiplexer circuit 18000. Circuit 20000 also contains relay circuits for establishing test access paths to the port circuits.
; The data path relationships between circuit 20000 and the rest of the port group circuitry is illustrated in Fig. 49. It further provides the transfer paths for the ringing signals , for interrupter-serializer 21100 to the ring buses, and in turn line circuit 2000 or 2000'24000.
' Referring now to Fig. 49. Five relays 20002, 20004...
20010 allow test access to the port circuits from the test ' interface circuits for test purposes. Relays 20002, 20006, i, 20008, 20010 form a network for switching among sets of signal ¦~ sources from test interface circuits. These four relays allow testing of the tip and ring leads both inside the port and on to the subscriber. Relay 20004 establishes a test path for the E and M leads both inside and out of an E and M trunk circuit.
Serial voice data and control data in the PGH format from TSI circuit 24000 are received on a balanced line 20012, and applied to a balanced line receiver driver 20014, which provides the data as an output signal sense/control data mux/demux 18000.

9L~45~

Relays 20006, 20008, 20010, and 20002 are used to connect the test access tip and ring leads of a port circuit to either Il the receiver off-hook tROH) generator 21200 or one of test ¦¦ access buses 20016, 20018, or 20020. When an ROH tone or a test access is required, slow control data channel CS5' operates I relay 20002 which connects the test access leads of the port ¦¦ under test to the selected test access bus. For test access, ¦¦ slow control data channel CSO' operates relays 20010 and 20008.
Il Operation of relay 20010 connects the port test access leads to I test access bus 20016. Operation of relay 20008 has no effect I unless slow control bit CSl operates relay 20006. When relay Il 20006 operates, the port test access leads are switched fro~
I test access bus 20016 to either test access bus 20018 or test , access bus 20020, depending on -the state of relay 20008.
When ROH tone is to be app:lied to a line, relay 20002 operates and the tone is applied through the normally closed ¦l contacts of relay 20010. Because the subscriber loop is closed by the ROH condition of the line, relay ROH 20022 operates.
Contacts of ROH relay 20022 close to pu-t 1500 ohms across the tip and ring leads to the port. When the subscriber goes on-hook, the loop is opened and ROH relay 20022 releases.
I The table of Fig. 50 lists the supervisory control bits and the relays these bits operate to select each of the -test access bus sources.
I Test sources for the E&M leads in an E&M trunk circuit are selected by operating relay 20004. As shown in Fig. 50, I relay 20004 is operated by slow control bit CS4- When relay 20004 operates, the normal signaling loops are broken and test sources on the TEO, TEI~ TMO, TMI, TM30, and TMBI leads are connected to the selected E&M trunk 3000.

11450~9 ¦ G. INTERRUPTER-SERIALIZER &

,1 The interrupter-serializer and ringing monitor circuit 21100 provides both cadence for single-frequency ringing and phasing for four-frequency ringing. Referring to Fig. 51, the ringing monitor and serializer includes a ringing interrupter circuit 21102 and a ringing monitor 21103. The input to ringing interrupter 21102 comes from ringing generator 21000 which applies continuous ringing voltage superimposed on -48V (office battery) to ringing interrupter 21102.
The single-frequency interrupter section produces output cadences consisting of two 1.28-second period of ringing alternating with two 1.79-second period of silence in a 6.144-second cycle.
The four-frequency interrupter produces four outputs with the same cadence, but shifted in phase with respect to each other, Each of these four-frequency outputs comprises four 1.28-second periods of ringing alternating with four .25-second periods of silence in a 6.1~4-second cycle. Each of the periods of ringing during a cycle of a particular output is at a different frequenc~. !

2. Single Frequency Interrupter Section A timing diagram of the operation of the Interrupter circuit 21102 is shown in Fig. 53A. Both the single~frequency interrupter section and the four-frequency interrupter section operate from a set of four pulse leads generated in the ring line (RGL) functional logic unit 40000 of comblnatorial logic organization 34000.

l~g 5~19 The.se are fed to the interrupters via balanced lines terminating in optical couplers 21106a, 21106b, 21106c and 21106d~ Fig. 52. These leads are shown as containing signals PH0, PHl, PH2, and PH~, representing four phases of the basic ringing pulse of 1.28 seconds within the 6.144-second cycle.
The output transistor of each of the optical couplers are Darlington-connected to relay driver transistor 21108a9 21108b, 21108c and 21108d. Relay 21110 is driven from phases PH0 and PH2. ~en operated~ its make contact 21100a applies ringing voltage to the single-frequency ringing bus 0 (SFRB0) lead.
A relay 21112 operates make contacts 21112a during phases PHl and PH~ and applies ringing voltage to the SFRBl lead.

~. Multifrequen~y Interrupter Section Referring now to Fig. 53, the multi-frequency ringing interrupter section contains relays 21114, 21116, 21118, and 21120, which select the ringing frequencies to be sequenced onto the four ringing buses multi-frequency ringing bus (MFRB 0-3).
The circuit also contains relays 21122 and 21124 which do the making and breaking of the ringing path to the office. Relay 21126 is arranged for slower release than 21122 or 21124 due to capacitator 21128 and resistor 21130 across its coil. This allows a make contact of relay 21126 to prevent any of relays 21114, 21116, 21118, or 21120 from releasing until relays 21122 and 21124 have released, thus ensuring that relay 21122 and 21124 break the ringing current path, instead of relays 21114, 21116, 21118, or 21120 breaking the ringing current path. At the start of a ringing phase, make contacts of relay 21126 in the path to relays 21112 and 21114 also ensure that relays 21122 and 21124 operate after any of the relays 21114, 21116, 21118, and 21126 so that contacts of relay~ 21122 and 21124 make the ringing path 131 gSQ~9 1 1 '' closure and relays 21114, 21116, 21118, or 2112G do not make the ringing path closure.

;!
4. Rin~in~ Monitor Section ll Reference is now made to Fig. 54 which is an electrical l! schematic of ringing moni-tor 21103. A relay 21128 and a relay ¦¦ 211~0 monitor ringing buses SFRB0 and SFRBl, respectively.
i~ Relays 21132, 21134, 21136 and 21138 monitor buses MFRB07 MFRBl, MFRB2 and MFRB3, respectively. The basic circuit for each relay is the same and therefore, only the details of relay 21128 will be described.
Circuit 21128 includes a coupling capacitator 21144, a series resistor 21146, and a full wave bridge rectifier 21148 ~ feeding rectified AC to a mercury-wetted-contact relay 21128.
;~ , Capactitator 21150 prevents chatter. Contacts of these six relays are connected to perate relay 21142 during each of the four ringing phases. This tests to determine that all of relays 21132, 21134, 21136, and 21138 operate during each phase and that either 21128 or 21130 operates during each phase. Relay 21142 has an R-C network connected to its coil via contacts of , relay 21140. Relay 21140 is arranged to operate during the time between ringing phases, when none of the monitor relays are operated. Thus, relay 21142 is arranged to remain operated i¦ continuously unless a failure of either ringing voltage or the ¦ interrupter relays occurs.
l When a failure occurs, relay 21142 releases (possibly ¦ intermittently), opening a monitoring path via GEN FAIL leads ,i to the service group diagnostic circuitry.
!I Each time that relay 21140 operates~ it closes a path ¦ between the EOPH and EOPHG leads. This indicates the end of each phase to ring line (RGL) functional logic unit 40000 of combinatorial logic (CL) organization 34000.

.
! H. ~
¦¦ Referring now to Fig. 55, a single TSI circuit 24000 Ii provides switching of binary voice data path, by means of a time ¦I division multiplexing technique. Up to eight TSI circuits are operatively connected with each other in a TSI matrix switch 1, circuit 403. Each TSI circuit 24000 receives voice and other-¦, than voice binary data signals from up -to eight transmit port I ¦ group highway 18001-0... 18001-7. Each port group highway 18001 Il carries voice and other-than-voice data from up to 30 port i equipment positions. Voice data signals received by TSI circuit ; 24000 from any port group unit 402 can be switched to any port ! i group unit served by that TSI circuit or to a port group unit ¦ served by one of the other TSI circuits in the TSI network 403.
Thus, any port equipment position can communicate with any of 1919 other port equipment positions operatively connected to TSI matrix network 403.
Referring again to Fig. 55, TSI circuit 24000 comprises two i sections of circuitry that operate independently of each other.
I A send sec-tion 24013 receives input signals from up to eight ,transmit port group highways 402-0' and 402-7'. Each transmi-t port group highway (PGH) carries serially multiplexed voice and sense/control data from up to thirty (~0) port equipment positions.
Send section 24013 generates serially multiplexed data on a single line, called a cross-office highway XOH-O. Cross-office highway XOH-l goes to a receive section 24014 and to the receive sections of the other TSI circuits~ Receive section 24013 also ¦has inputs fro~ cross office highways XOH l...XOH-7 from the other ¦seven TSI circuits 24000 in TSI network 403. It selects data from these cross-o*fice highways under control o~ software stored program 56002 of CCP subsystem 408 and switches the data to the assigned port gro~p highways 24001-0...24001-7 going out of receive section 24010 to the port groups.
¦Referring now to Fig. 56, the serial TDM data stream format on cross-office highway XOH out of send section 24013 consists of recurring 15~62 microsecond time frames 24015, ~ each frame being divided into 128 bit positions called timeslots.
¦~ Each of the 128 timeslots contains a data bit from a different port; every 128th timeslot contains a data bit from the same port. Thus 9 the cross-office highway can accommodate, at any time, only 128 of the possible 240 ports served by the send section 24013.
;~ For communication paths to be established, the send section 24013 must multiplex and store the bits from the eight por-t units 402-0~..402-7 (240 ports) which the TSI circuit serves. Then, in the sequence specified by a signal from call controll processor tCCP) subsystem 408 via CCP interfaces controller 54000, the send section 24013 assigns the bits from each port to one of the 128 recurring timeslots on the cross-' office highway XOH-O until all 128 timeslots are filled. During j each timeslot, CCP subsystem 405, via CCP interfaces controller I 54000, controls the receive section 24014 of each TSI circuit 24000 to select a specific cross-office highway of the cross--office highways XOH-O...XOH-7 and store the data bit present on that cross-office highway during that timeslot. The receive section 24014 then assigns the stored bits to a selected receive port group highway of eight output port group highways 402-0'~..402-7' (and, ultimately, the port) that is specified by subsystem 408 via controller 54000. The data bits to be outputed by receive section 24014 are demultiplexed onto the 1145~19 !l .
il :
j, eight port group highways. Each of -these port group highways then are demultiplexed to up to 30 ports by voice data Ii multiplexer/demultiplexer 16000 and by sense/control data ! I multiplexer/demultiplexer 20000. Therefore 9 a one-way i communication path for a call is established by assi~ning the same cross office highway timeslots to the transmitting port in a send section 24013 and to the receiving port in the selected receive section 24014.
, Relerring now to Fig. 57, the circuitry in send section 24013 -that assigns timeslots to transmitting ports consists o~
! three elements: random access memory (RAM) send buffer unit 2400~ composed of an EVEN buffer section 24016a which contains a pair of-128 x 1 RAMs and o~ an ODD buffer section 24016b which also contains a pair of 128 x 1 RAMs: a 128 x 8 RAM address buffer also called send store 24017; and a recycling counter called the send timeslot generator 24018.
Each of buffer sections 24016a and 24016b is composed of , a "128 by 1" bit RAM memory organization for the first 128 port , equlpment positions (including virtual ports) and another "128 ; by 1" RAM memory configuration for the second 128 ports (including virtual ports) in a port group unit. The addresses of the total ~, series of 256 RAM bit locations are assigned to the corresponding series of the 256 port equipment positions. Since the addresses of -the bit locations in buffer sections 24016a and 24016b of send buffer unit 24003 have the same binary form as the equipment ' num~ers o~ the ports, each port has a dedicated location in each bu~fer section into which its bits are written~ During this write operation, these locations are addressed in sequence by the outputs of timeslot generator 24018. During each 15.62 microsecond time ~rame 24015, Fig. 56, port data bits are written into the 128 x 1 RAM memory organization assigned for ports 0-127 in one of EVEN and ODD buffer sections 24016a and 24016b and in the 128 x 1 RAM memory organization assigned for ports 128-255 in the other of EVEN and ODD buffer sections 24016a and 24016b. During the same time frame the contents of the 128 x 1 RAM memory organization assigned for ports 0-127 of the other of EVEN and ODD buffer sections 24016a and 24016b and the contents of the 128 x 1 RAM memory organization assigned for ports 128-255 of -the one of EVEN and ODD buffer sections 24016a and 24016b are read and placed on the cross-office highway (XOH) 24008a. The bits which are read and placed on XOH were stored in their RAM locations during the preceding time frame.
During each successive time frame the roles of EVEN and ODD
buffer sections 24016a and 24016b alternate between: (i) storing data bits from ports 0-127 and reading out data bits from ports 128-255, and (ii) storing data bits from ports 128-255 and reading out data bits from ports 0-127. This is a so-called ping-pong" mode of operation.
Timeslot generator 24018 cycles through 128 counts every 15.62 microseconds. These outputs simultaneously address the 128 x 1 RAM memory organization, assigned for ports 0-127 in one of EVEN and ODD buffer sections 24016a and 24016b and the 128 x 1 RAM memory organization assigned for ports 128-255 of the other of EVEN and ODD buffer sections 24016a and 24016b.
Timeslot generator 24018 provides two things: (i) the write address which corresponds to the port equipment number (EN ~) for send bu~fer unit 24003; and (ii) the read and the write addresses which correspond to cross-office highway timeslots for send store 24017.
Send store 24017 contains equipment numbers (EN ~ that are used to address the port data bits in one of the EVEN
buffer section 24016a and/or ODD buffer section 24016b during the 1 45~9 read operation. The CCP interfaces controller 54000 loads the ~! equipment ~umbers (EN #s) into send store 24017 in the ssquence !

j, required to address each data bit during the appropriate timeslot.
~" As timeslot generator 24018 cycles, these equipment numbers i are applied as address inputs to the appropriate 128 x 1 RAM
` ¦¦ memory organization of the appropriate one of E~EN and ODD bu~fer¦I section 2LL016a and 24016b during a given read cycle of the ping-1l pong write-read cycles of send buffer section 24003. The data bit at the location within EVEN buffer section 24016a or ODD
buffer sections 24016b that is selected on the basis of port EN # is read out and placed on the cross-office highway (XOH) where it is transmitted to the receive sections 24014 of all the TSI circuits in TSI network 403. At the end of each XOH
time frame, the writing and reading operations are reversed as between EVEN and ODD buf~er section 24016a and 24016b so that stored data can be outputed from the send buffer unit 24003 while new data is input to it, providing the "ping-pong" mode ; of operation.
Note that bits from all 240 ports connect with a TSI circuit , 24000 are written into the send buffer unit 24003 during a 15.62 microsecond time frame. However, bits from no more than 128 ports are read out of the buffer and placed on cross-office highway (XOH) during the time frame. Once 128 EN #s have been specified, any other subscriber who goes off-hook will have his call blocked until one of the 128 parties already assigned a timeslot goes on-hook. It will be appreciated that it is the limitation of send store 2Li017 to a physical size of "123 x 8"
bits which is the direct cause of this possible blockage. A
major reason that blockage is accepted is that the 15.62 microseconds available period is too short to permit reading of more than 128 bits with the state of technology o~ Schottky TTL

1145~
1 !

logic circuitry, In each receive section 24014, the circuitry that assigns timeslots to the data receiving ports conslsts of five elements:
RAM receive buffer unit 24005 composed of an EVEN buffer section 24022a which contains a pair of 128 x 1 RAMs and an ODD buffer section 24022b which also contains a pair of 128 x 1 RAMs; a RAM address buffer 24024 (also referred to as the receive store);
cross-office highway selector 24004; a RAM address buffer 24028 (also referred to as the cross-office store); and a receive timeslot generator 24029.
Receive timeslot counter 24029 generates sequential write and read addresses for receive store 24024 and the cross-office store 24028. These addresses correspond ~inarily to cross-office highway (XOH) timeslots. During initialization, and, subsequently, at the beginningof each call, the CCP interfaces controller 54000 uses these addresses to load equipment numbers (EN ~s) into the receive store 24024 and cross-office high~ay codes into the cross-office store 24028. The function of receive store 24024 is to address receive buffer unit 24005 during the write operation. The ~unc-tion of XOH store 24028 is to address XOH selector 24026 during the write operation.
The function of timeslot generator 24029 is: (i) to generate the addresses for the receive store and XOH store respectively;
and (ii) to generate the address to read receive buffer unit 24005.
The bit present on the selected cross-office highway during the timeslot that corresponds to the output of timeslot generator 24029 is gated through XOH selector 24026 to the input sides of EVEN buffer section 24022a or ODD buffer section 24022b. During each timeslot, the output of the timeslot counter 24029 addresses a location in the receive store 24024. The equipment number (EN#) read from that location is used to address the location in the receive buffer unit 24005 in-to which the cross-office i highway (XOH) data bit is to be written. In the same manner as with ~VEN and ODD buffer sections 24016a and 24016b of send i¦ buffer unit 24003, EVEN and ODD buffer sections 24022a and ¦i 24022b each have a "128 x 1" bit RAM memory organization for ! the first 128 ports and a second "128 x 1" bit RAM memo~y ~; , organization for the second 128 ports. During each 15.62 microsecond time frame, data bits on XOH are ~ritten into the 128 x 1 RAM memory organization assigned for ports 0-127 in one of EVEN and ODD buffer sections 24022a and 24022b, and in the 128 x 1 RAM memory organization assigned for ports 128-255 in the other of EVEN and ODD buffer sections 24022a and 24022b.
During the same time frame the contents of the 128 x 1 RAM
memory organization assigned for ports 0-127 of the EVEN and ODD buffer sections 24022a and 24022b the contents of the 128 !
x 1 RAM memory organization assigned for ports 124-255 of the one of EVEN and ODD buffer sections 24022a and 24022b are read and applied to demultiplexer and control data injection buffer i 24006. The bits which are read and applied to buffer 24006 were stored in their RAM location during the preceding time frame. At the end of each time frame these read and write operations are reversed as applied to the 128 x 1 RAM for ports 0-127 and to the 128 x 1 RAM for ports 128-255 of each buffer section providing a ~ping-pong~ mode of operation. The term "ping-pong mode of operation", means that in order to get continuous bit stream of data, writing and reading is ultimately performed by two separate receive buffer RAMs.
During the read operation in receive section 24014, the outputs of receive timeslot generator 24029 are interrupted by receive buffer unit 24005 as equipment numbers These equipment ~l ~

¦ !
¦ numbers, which are generated in sequential order are simultaneously applied to the 128 x 1 RAM assigned for ports 0-127 in one of EVEN and ODD buffer sections 24022a and 24022b Il and the 128 x 1 RAM assigned for ports 128-255 of the other of ¦¦ EVEN and ODD buffer sections 24022a and 24022b, reading one bit from each. These data bits then are stored in suitable ¦l flip-flops (now shown) while logical "O's" are written into the ¦¦ locations from which the data bits were just read~
To summarize the operation of TSI circuit 24000, cross-j, :
li office high~ay selector 24004 works in conjunction with receive unit 24014 to complete the call paths initiated through a send section 24013. Selector 24026 and receive buffer unit 24005 do this by assigning specific timeslots on specific cross-office highways to the correct receiving port. During every 15.62 microsecond time frame 24015 Fig. 56, the same timeslot l carrying a data bit from the same sending port is directed to the same receiving port. Of course, each path is uni-directional.
¦l Thus, in the case of two ports involved in the call which are ii served by the same TSI circuit 24000, two timeslots on the same cross-office highway (XOH) must be assigned.
Just as the XOHs that interconnect TSI circuits 24000 are divided into timeslots, the port group highways (PGHs) that interconnect a TSI circuit 24000 port group units 402 are divided into timeslots. However, instead of being divided into 128 timeslots of 122 nanoseconds each) the port group highway is divided into 32 timeslots of 488 nanoseconds each.
Referring now to Fig, 57A during the first 30 PGH timeslots, 16 precise tone data bits from tone buffer circuit 25100 are shifted into a pair of 8-bit tone data bits serial shift registers 24031a, 24031b. During the same period of 30 PGH
timeslotæ, 240 voice data bits (one from each port) are brought ~1 ! ' in on the PGHs 402'o During the last two PGH *imeslots (30 and 31), a total of 16 sense data bits are brought in from the eight PGHs and shifted into a pair of 8-bi-t TDM sense bits Il serial shift registers 24009a and 24009b. Registers 24031a, ¦¦ 24031b, 24032a and 24032b are a part of multiplexer and sense ¦¦ data/tone data exchange buffer 24002 of TSI circuit 24000. At 1I the same time that sense data bits are shifted into registers ; l` 24009a and 24009b, the tone bits are shifted out of registers 1 24031a and 24031b and b]ended into the two streams of data bits I l emerging from buffer 24002 before the two streams are written into the ODD and EVEN buffer sections 24016a and 24016b of send , buffer unit 24003. Because PGH timeslots 30 and 31, during which the tone data bits are written into send buffer unit 24003, correspond -to XOH timeslots 120 through 127, those bits are written into the eight highest-order location in each half of each buffer section. Thus, the 16 tones are assigned equipment n~mbers which correspond binarily to numbers 120 through 127, and 248 through 255. Each of these tones then can be transmitted to any I/O port by assigning the equipment number of the tone to the XOH timeslot assigned to the equipment number of the port During the next 30 PGH timeslots, the 16 sense data bits !
are shifted out of registers 24009a, 24009b in buffer 24002 to the parallel-serial binary signal converter 32000.
During this same time, control data bits from the parallel-serial converter 32000 are shifted into a pair of 8-bit TDM
control bits serial shift registers 24010a and 24010b, Fig. 58 in demultiplexer and control data injection buffer 24006. These control data bits are shifted out of buffers 24010a and 24010b during PGH timeslots 30 and 31 and applied to the two two-to-one multiplexers 24030a and 24030b and thence to PGH highway demultiplexer 24012 for transfer to the port group wnits 402 on the receive PGHs 402'.

TSI circuit 2400¢ responds to thirteen commands from the ¦ CCP interfaces controller 54000. Six are write commands, six I are read commands, and one is a search command. The bit codes ¦ for these commands are defined in the TSI Circuit Command Code Table Fig. 60. With these commands the following operations can be performed.

1. Preload equipment numbers into send and receive stores ¦ 24017 and 24024 to pre-assign timeslots to the prescribed ports , during initialization.

; 2. Reassign equipment numbers in the send and receive stores , 24017 and 24024 to establish new data paths.

! 3. Search for a specified equipment number in the receive store 24024 and read the timeslot assigned to that equipment i number j;
4. Assign an XOH to complete a data path through the TSI
¦I matrix switch network 403.
,l 5. Clear equipment number and XOH assignments to cancel ¦l data paths~
¦¦ Referring now to Fig. 59, in conjunction with the Table of Fig. 60 commands are received on the IOWD 3 bus from the CCP
, interfaces controller 54000 by the TSI circuit command decode logic 24036. Bits 4 to 7 from the IOWD 3 bus are decoded by the logic 24036 to produce write enable signal WEN SE~D STORE, WEN
7 and WEN g~ signals which are communicated to the appropria-te one of store RAMs 24017; 24024 and 24028 during write commands. These enable the appropriate inputs to the I/O word selector 240~8 during read commands, and gate the outputs of the receive store latch 24040 to the compare logic 24042 during search commands. Of the six write commands executable by the matrix switch, three enable the writing of data to the real halves (location 128 through 255) of the store RAMs, and three ~L4~

¦, enable writing to the reserved halves (locations O through 127) of these RAMs. Similarly, three of the read commands involve the real halves of the store RAMs, and three involve the reserved ¦, halves. The search command affects only the real half of only ¦I the receive storeO
11 A command code with bit 6 HIGH specifies a write command.
!¦ Bit 6 HIGH inhibits generation of the read or search strobe in , decode logic 24036, preventing any output of the I/O word selector 24038 from being placed on the IOWDl bus from driver receiver (DRVR RGVR) 24044 to controller 54000 Bits 4, 5, and 6, as shown in the table of Fig. 60, determine which write enable signal (~EN SEND STORE, WEN REC STORE, or .
WEN XOFF STORE) is generated by command control logic 24036 and applied to the WE input of the appropriate store RAMs. A LOW
level on the WE input of each RAM of the store allows the bit present at the data input to be written at the location specified by the send timeslot counter outputs (STSQ 1-64) present at -the address input.
Bit 7 of the command code determines whether a bit is to be written into the real or the reserved half of each store RAM.
When bit 7 is LOW, bits 4 and 5 are interpreted by command decode logic 24036 to produce one of ~3-~E-3~ or RES RECEIVE STORE
or R~S XOH STO~ Each of these signals, when generated, is applied to the address input of the store RAMs with which the signal is associated, addressing the lower numbered 128 locations (O through 127) in each RAM. These lower numbered 128 locations are designated the reserve port on of the RAM and are used to reserve communication paths in advance of the actual connection.
When bit 7 is HIGH, R~ E-ND STO~, TDI~r~rrr-7rSPL, and ~
XO~-STORE are inhibited, and the write operation is addressed to the real portion (locations 128 through 24255) of the selected Q~ ~

store RAMs of RAMs 24017, 24024, and 24028.
Bit 6 is LOW in a read command. A LOW bit 6 inhibits generation of write enable by command decode logic 24036 enables generation of the read or search strobe signal at the output of AN~ gate 24046, and enable the drivers 24044 that send the bits read from the store RAMs to controller 54000. The read or search strobe clocks the output of the I/O word selector 24038 into the I/O word buffer 24048 for transfer over the IOWD 1 bus to the common control sector controller. The strobe is generated by the next C8MHZ pulse after the comparator has found the timeslot specified by controller 54000 on the IOWD 2 bus.
Bits 4 and 5 of the read command code specify whether the I/O
word selector 24038 is to gate the current outputs of the send store latch 24050, the receive store latch 24040, or the cross-office store latch 24052 to the I/O word buffer 24048. In addition, these bits cause the compare multiplexer 24054 to gate the send timeslot bits (STS~ 1-64)produced by counter 24016 to comparator 24042 to be checked against those supplied by , controller 54000 on the IOWD 2 bus. When the specified timeslot occurs the COMPARE signal from the comparator 24042 allows generation of the read or search strobe from AND gate 24046, which clocks the data gated by the I/O word selector 24038 into the I/O word buffer 24048.
As in a write command code, bit 7 in a read command code specifies whether data bits are to be read from the real or the reserved halves of the specified store RAMs. A LOW "bit 7"
specifies that bits be read from the reserved store area. A HIGH
"bit 7" specified that bits be read from the real store area.
A command code with a LOW "bit 4" specifies a search of the receive store 24024 for the equipment number that corresponds to that supplied by the controller 54000 on the IOWD 2 bus. "Bit 7"

1~1L45Q~L9 ;

,, Il of the search command code always is set to limit the search to the real half (locations lZ8 to 255) of receive store 24024. The HIGH and LOW levels of "bits 5 and 4", respectively, produce the SEARCH signal, which causes compare multiplexer 24054 to gate the output of receive store latch 24040 to the comparator 24042.
When the equipment number currently being read ~rom receive store 24024 equals that provided by controller 54000 on the IOWD 2 bus, the comparator 24042 generates the COMPARE signal along output lead 24056.
The trailing edge of -the next C8MHz pulse clocks the COMPARE
signal into the compare flip-flop 24058. "Bits 4 and 5" of the command code, which is applied to the I/O word selector 24038, gate the outputs of the send time slot counter 24016 through the I/O word selector 24038 to the I/O word buffer 24048. The leading edge of the next C8MHz pulse generates the READ OR SEARCH STROBE
at the output of gate 24046, which clocks the current output of timeslot counter 24016 into I/O word buffer 24048 for trans~er to controller 54000. Because receive store latch 24040 and the compare flip-flop 24058 must be clocked in succession, the time-slot that is placed on the IOWD 1 bus to controller 54000 is two timeslots greater than that actually associated with the equipment number found by the search. This delay is compensated by con-troller 54000 and more particularly by an arithmetic and logic unit (later introduced as ALU 54064, Fig. 99) thereof.
Reference is now made to Fig. 61 which is a more detailed block diagram of send 24013. This section handles the stream of voice da-ta undergoing switching, sense data, and broadcast -tone data. The stream of data undergoing switching from the eight port group highways 402' are multiplexed and written into the send buffer unit 24003. Then, according to the order in which they are read out of send buffer unit 24003, the voice data bits ~.456~

¦l are assigned to timeslots on the cross-office highway XOH and are sent to the receive section 24014 of either the same or ; another TSI circuit 24000. Sense data bits received on the port li group highways 402-0'...402-7' PGH timeslots 30 and 31 are ¦ extracted (by strobing same into network 407 sense bit shift ¦ registers 24009), from the stream of data undergoing switching, I stored in register 24009 and then transferred to parallel-serial j~ binary signal converter 32000. Broadcast tone data bits received from tone buffer 25100 are stored and then inserted into the , stream of data undergoing switching in place of the extracted sense data bits. These tone data bits then are assigned timeslots on cross-office highway XOH in the same manner as the voice data ; bits from the portsO
Timing for the send operation is illustrated in Fig. 9.
I~ Reference is now made to Fig. 62 for a more detailed ; ll description of receive section 24014 of the TSI circuit 24000, i which completes the communication path ini-tiated through send ,, ~
il section 24013 and provides the means for injecting control data ' ¦l into the data streams sent to the ports. During each cross-office highway (XOH) timeslot, the receive section 24014 selects one stream of data undergoing switching from one cross-office i highway and stores it. The stored stream of data undergoing ¦switching are then demultiplexed by demultiplexer and control data injection buffer 24006 to the eight port group highway 402-0' ...402-7' to the respective port group unitsO Control data bits received from the parallel serial binary da-ta converter-32000 are stored temporarily in receive section 24014. Then they are injected into the stream of data undergoing switching and de-multiplexed onto the eight port group highways 402' to the port groups during port group highway timeslots 30 and 31. Timing for the receive sec-tion 24014 is illustrated in Fig. 13.

Io PRECISE TONE GENERATOR 25000 ~ ! Precise tone generator 25000 provides the ~ollowing 1 1 functions:

; ~ a. Generation of mixes of four fundamental frequencies (350, 440, 480, and 620 Hz) to produce the six basic tones required ¦¦ as the broadcast tones.

b. Generation of a 1004 Hz test tone (IMW tes-t tone).

Referring now to Fig. 6~ all frequencies are digitally derived from the 2.048 MXz system clock (C2MHz). The two megahertz (2.048) megahertz clock drives a four bit driver 25010 the output I
, i of which is formed into a two phase clock by the decoding network ;
25012, each clock phase is divided and mixed with a derivative of the other phase~ This mixture of the derivatives of the two phases is ~urther divided and mixed by a dividing and mixing network of the pulse deletion type to produce pulse rates which are sixteen times the desired output frequency (16 fo).
Each of the outputs of network 25014 are applied to a pulse rate modulation generator 25016. Re~erring now to Fig. 64, each generator 25016 has at its front end a 25018 which is a sixteen-step up/down counter, which counts up from 0 through 8 and then counts back down to 0, continually repeating this up/down cycle.

The binary outputs o~ these program-cycle generators 25018 are translated by encloding logic 25020 into approximately sine-value BCD program inputs to the pulse-rate modulators. Referring now to Fig. 65, the approximate sine value which is set forth in ordinal column 25022 reflected by solid curve 25022a. The true sine va.lue set ~or-th in ordinal column 25024 is reflected in the dotted curve 25024a. Referring again to Fig. 64, a pulse-rate modulator 25026 produces an output which comprises programmed percentages of the 1.024 MHz input. An AND gate 25028 is functionally apart from the coding logic 25020. It gates through the full clock count this is shown in Fig. 65 at count 8 (abscissal value).
Stated another way network 25014 comprises a frequency synthesizer, and the pulse rate modulation generators 25016 comprise sine converters. Their output is fed through suitable low pass filters to a network of mixers 25030. The outputs of the filters are fed into the mixers 25030 to produce the broadcast tones as indicated on the drawing.
The operation of circuit 25000 will now be described in greater detail. In order to synthesize the frequencies required for the precise tone plan (350 Hz, 440 Hz, 480 Hz, and 620 ~z, plus 1004 Hz test tone~, the 2~048 MHz system clock is first divided down and appropriately gated by divider 25010 and decoding network 25012 to produce a 256 ~z two-phase clock. As shown in Fig. 63, each 256 KHz clock phase (wave forms 25032 and 25034, !
Fig. 66) is further divided by decade-rate-multipliers (which act as pulse-deleting circuits). The resulting output of each clock phase divider, (wave forms 25036 and 25038) is ORed with an appropriate divider output (or clock) of the opposite phase to produce rates which are sixteen times the fundamental frequency desired. The resulting mixes, wave form 25040, of the two phases is further divided wave forms 25042, 25044, 25046~ and 25048 by appropriate number of binary dividers required to produce a frequency of sixteen times -the desired output frequency (16 fo) waveform 25050.
Each frequency thus generates is applied as a clock input to a program-cycle generator 25018 in its respective sine converter 25020 (including 25028). The program-cycle generator 25018 consists of an up/down counter and a direction control latch 25052. Each clock pulse increments the program-cycle ~145~9 generator 25018 until a count of eight is reached. For each step (0 through 7) a corresponding binary value is produced at the program-cycle generator outputs (A through D). At the count of seven, the direction control latch 25052 is reset, thereby causing the program-cycle generator to decrement back down to zero on the succeeding clock pulses. At the count of zero, the carry signal (from output TC) from program-cycle generator 25018 sets the direction control latch 25052 back to its original state, causing the sequence to be repeated.
The way the binary outputs of the cycle generator 25018 are used is better understood after considering the operation and input requirements of the pulse-rate modulator 25026. This circuit is a decade rate multiplier, which receives a 1.024 MHz input signal from the precise tone generator. During the interval that a binary code is present on programming inputs A through D
the code defines the number of pulses out of every ten from the input signal that are to be output by the modulator. As the code varies, so the percentage of pulses from the base signal varies.
Thus, regularly recurring variations in the code produce an output signal with a regularly varying (modulated) pulse rate.
Considering again the outputs of the cycle generator, it is apparent that one complete cycle of the program-cycle generator produces 16 binary counts. These counts are translated, by gate combinatio~s in the sine function encoding logic 250Z0, into sine ¦
cyclic, BCD codes for the pulse-rate modulator programming inputs.
The first eight codes of the program cycle generator define increasing percentages of pulses to be output from the 1.024 MHæ
input signal. During count eight of the program-cycle generator 4018, the 1.024 MHz signal is gated by gate 4028 directly through the modulator to the output, unmodified. Therefore, 100 percent of the input pulses are output during this peak period of the cycle. The final seven input codes of program-cycle generator !
"

25018 define decreasing percentages of pulses from the input signal to be output. Since one cycle of modulator 25026 corre-sponds to 4016 counts by the program-cycle generator 25018, this produces a modulation rate of 1/16 the program-cycle generator Il clock frequency~ The following table lists the selected modulator ¦¦ code inputs and resul-ting pulse rate factor that correspond to each count of the cycle generator. Fig. 65 illustrates how closely these codes approximate those that would be necessary to produce an ideal sine wave. I
CYCLE GENERATOR/MODULAR RELATIONSHIPS
CYCLE GENERATORMODULATOR CODE RESULTING PULSE- !
BINARy COUNT _INPUTS SELECTED RATE FACTOR
O (NONE) O
1 A .1 2 B .2 3 A & B .3 4 A & C .5 A,B,D .7 , 6 D .8 7 A & D .9 8 UNITY CASCADE 1.0 7 A & D .9 1, 6 D .8 ¦; 5 A,B,C .7 j 4 A ~ C .5 3 A & B .3 ', 2 B .2 ¦~ 1 A .1 Referring again to Fig. 63, the outputs of the pulse rate modulators are filtered by low pass filters 25054 to remove the 1.024 MHz component and to provide some attenuation of harmonics.

~l s~

Adjustable gain states included in mixer network 25030 for each , frequency provide isolation from the digital circuitry and a low impedance source for mixing and signal distribution. Mixing is ! accomplished using resistor networks with unity gain followers to provide an impedance transformation from the high mixer input I impedance to a low source impedance for signal distribution.

J. TONE BUFFER 25100 1. Functional Overview of Structure and Operation Referring now to Fig. 67, tone buffer circuit 25100 is the formatting and distributing circuit for precise and toll multifrequency (MF) tones. It receives digital pulse-rate-modulated (PRM) tones from a toll MF tone generator circui-t 25070 (if any), buffers these, and sends them to the tone plant inter-face circuit 3270 (if any). Circuit 25100 also receives analog precise tones from precise tone generator 25000. All the analog precise tones are applied to six CODEC circuits 25102 and converted to pulse-code-modulated (PCM) digital signals.
Multiplexing logic 25104 multiplexes the outputs of the six CODECs to produce a stream of serial bits that are written ihto j~ a pair of "ping-pong" RAMs 25106a and 25106b. A 2-to-1 selector ' 25108 and a demultiplexer 25110 read the bits out of RAMs 25106a and 25106b in an alternating or "ping-pong" fashion and demulti- ¦
plex them in a format that harmonizes with the requirements o~ i the TSI circuits 24000 that receive the tones.
I The PCM tone bits at the output of demultiplexer 25110 are ¦ applied to the interrupt gating logic 25112 along with ringing cadence signals from the ring line functional logic unit 40000 of combinational logic organization 34000 and the outputs of an interrupt counter 25113. The interrupted tone signals output from gating logic 25112 include the four phases of audible ringing ~ Q~
~ .

used for (ring-back), the idle channel (silence), and the broad-jl cast tones. A tone multiplexer 25114 multiplexes these into a serial stream that is transmitted by a tone out flip-flop 25116 and driver circuits 25118 to the TSI circuits 24000 of TSI matrix ¦~ network 403.
i.
2. Operat-on of CODECs ~ !i Referring now to Fig. 67 and Fig. 68, six analog signals I ' corresponding to the six basic tones, or combination o~ tones, from precise tone generator 25000 are received by tone buffer ~;~ circuit 25100. The CODECs 25102 comprise CODECs 3500a',~
3500f', each of which is the same as the previously described PCM CODEC/filter circuit 3500 except tha-t no transmit ~ilter 3502 is furnished. CODECs 3500a'...3500f' respectively convert the six analog signal tones. The six CODECs are paired (CODECs 3500a and 3500b; CODECs 3500c and 3500d; and CODECs 3500e and 3500f). The outputs o~ the CODEC are time multiplexed alternately`
introducing into the bit stream one CODEC and then the other of :i the pair. This multiplexing is performed by a 6-to-3 multiplex gating network 25120, Fig. 67, which is a part of multiplexing logic 25104. The three output channels from multiplexing network 25120 are designa-ted XMT NRZ 0-1, XMT NRZ 2-~, and XMT NRZ 4-50 Each channel provides multiplexed digital information from two CODECs. A 3-to-1 multiplexer 25022 further multiplexes these channels into a single signal. Multiplexer 25022 is also a part of multiplexing logic 25104. This signal, representing the six char,nels of 8-bit words from the CODECs, is applied to "ping-pong"
RAMs 25106a and 25106b, as will be subsequently described.
A CODEC timing generator 25024 generates a 128K clock signal which is applied to each of CODECs 3500a'~..3500f'. The 128K
clock signal is derived from a RAM address counter 25026, the _1~4-114S~19 C2MHz clock being the timing input for address counter 25026.
` The data from one of the two CODECs on a channel i5 stable for a duration of 7 8125 microseconds after each rising edge of the ¦ 128K clock. This data from the three channels of digital CODEC
¦ information is written into ~ping pong~ RAMs 25106a and 25106b ¦ at a 2MHz rate as will be presently described.
~ .
3. Ap~lication of Tone Data to RAMs The 3-to-1 multiplexer 25122 selects bits from the three channels of CODEC data in sequence at a 2MHz rate. Thus, at address O from the address counter, channel XMT NRZ 0-1 is , selected, with data from CODEC O (Bit 7) being present at that time~ On the falling edge of the 2MHz clock, that data bit is , written into one of the ping-pong RAMs 25106a and 25106b. At the j next rising edge of the 2MHz clock, channel XMT NRZ 2-3 is select-1l ed; at the falling edge, CODEC 2, bit 7, is written into the RAM
! at address 1. Similarly at the next falling edge, channel XMT
j , NRZ 4-5 is selected, and bit 7 oi` CODEC 4 is written in address 2.
, At the next falling 2MHz clock, a zero is written into address 3.
This pattern is redundantly repeated through address 15 of the 256 bit RAM. Thus the same information is entered in addresses 0, 1, 2~ After 16 counts of the address counter from address 0, I the ~ clock goes high and data bit 6 of CODECs 0,2, and 4 are j present on the three channels~ These bits are written into the RAMs at addresses 16 through 31 in the same manner as described for addresses O through 15 Similarly, data bits 5~413,2,1 and O are written into the RAM up through address 127. Then the three channels provide the data from the odd CODECs tl,3,5) starting at bit 7 and extending through 255. The first rising 2MHz clock after address 255 switches the write and read modes between the two RAMs. The one into which data was just written ii45Q~L9 ¦I now is placed in the read mode for the next 256 2MHz clocks I (125 microseconds).

! 4. Synchronization Wi-th Timeslots of TSI Circuit 24000 CODECs 3500a = chronization ¦ signal as a reference for the digital data they generate. CODEC
timing generator 25124 generates CODEC SYNC, which signal is derived from outputs of address counter 25026. The CODEC SYNC
goes low for 3.9 microseconds every 125 microseconds (8KHz).
The rising edge of the 128K clock, occurring 1.95 microseconds after the start of CODEC SYNC, is applied to 6-3 multiplex gating 25120 to synchronize the outputs of the CODECs 3500 with the time-i slots of -the operation of TSI circuit 24000.
Reference is now made to Fig. 69 depicting CODEC timing relationships. The most significant bit (MSB) (bit 7) of the ¦, even numbered CODECs are generated on the XMT NRZ lines and ~`~ i remain there for 7.8125 microseconds. For each succeeding 128K
rising clock edge, bits 69 5, 4, 3, 2, 1 and 0, respectively are generated for 7.8125 microseconds each. At the next rising ; l, clock edge, bit 7 of odd-numbered CODECs are generated for 7.8125 - i' microseconds, and, similarly, the bits 6 through O are generated ¦, for 7.8125 microseconds each. Thus, it takes a total of 16 I~
clock periods to generate the eight bits of data for the e~en CODECs and eight bits of data for the odd CODECs for a total time of 125 microseconds.

5, Reformatting Data from RAMs 25106al 25106b During the read mode a RAM of ping-pong RAMs 25106a, 25106b, the output data from CODECs 3500a'...3500f' that has been stored in the RAMs are applied to 2-to-1 data selector 25108. The data bits from the selec-ted RAM are then strobed into six latches that Il constitute the channel demultiplexer 25110. The same bit position ¦ from each CODEC is loaded into the six latches when the data is ¦ read ~rom the RAMso To accomplish this, address selector 25128a and 25128b route the least significant bit of the address counter Il to the most significant bit of the RAM being read. Thus the first six addresses read are 1, 128, 1, 129, 2, and 130~ which represent I . , Bit 7 of the six CODECs. No more data is latched until the address counter reaches 16. Then the six addresses read are 16, 144, 17, 145, 18, and 146. These represent bit 6 of the six CODECs. Thus the same bit from all CODECs is read every 32 MHz clocks, or every 15.625 microseconds. To read all eight bits (7 through 0) takes 125 microseconds. The data in the RAMs other than each group of six addresses is not latched.

6. Ou~puts The six channels of digital data from demultiplexer 25110 are applied to the appropriate gates in interrupter gating logic 25112~ Ringing interrupt gating 25130 causes the 440/480 Hz tone to be interrupted by ringing cadence phases 0, 1~ 2, and 3 to form the four phases o~ ring back cadencing. These four digital data streams become the first four inputs to 16-channel tone multi-plexer 25114. The ~ifth input to multiplexer 25114 is a continu-ous logical high signal representing an idle portO The 350/440 Hz (dial tone) channel is fed directly to the multiplexer as the sixth input (i e , it is uninterrupted). A 256-step interruption counter 25136 provides 60 IPM or 120 IPM interruption enable signals to broadcast tone interrupt gating 25134. Gating 25134 lnterrupts the 440 Hz and the 480 Hz channels by 60 IPM or 120 IPM and applies them to multiplexer 25114 as the seventh and eighth inputs respectively. The interruption rate is selected I

~145~ L9 i from among the choices of 170 IPM, 6G IPM, or non-interruption by a strapping option in conjunction with interrupt gating 25134.
The 480/620 Hz channel, interrupted at 120 IPM by interrupt gating 25134, is the ninth input. The 480/620 Hz channel, interrupted ¦1 at 60 IPM by interrupt gating 25134 is the tenth input9 and the ¦ 480/620 Hz with customer options of 60 IPM or 120 IPM or un-interrupted is the eleventh input~ The 1004 Hz test tone is fed as the twelfth inpu-t to multiplexer 25114. Interrupt gating 25134 generates a tick tone by interrupting the 480 Hz channel with a tick tone enable signal. This is the thir-teenth input to the multiplexer The 440/480 Hz channel signal is inverted and applied directly as the fourteenth input to the multiplexer. The other two inputs to the multiplexer (15 and 16) are spares.
Tone multiplexer 25114 converts the 16 channels of tone data into serial form. This serial bit stream then is transferred to the matrix switches at 2.048 MHz by the tone out flip-flop 25116 and four line drivers 25118. The bit stream must be in synchro-~; nism with the S STROBE signal with which each TSI circuit 24000shi~ts the tone bits into a register. To ensure that the correct tone bit arrives at the TSI circuits at the correct time, the address counter 25126 ~or ping-pong RAMs 25106a and 25106b must jl be preset to a count of 254 and a timeslot counter 25136 for I the tone multiplexer 25114 must be preset to a count of 13 at the arrival of Z~E-~Y~
Tone multiplexer 25114 places -the tone bits in the serial stream in a predetermined order so that TSI network 403 may assign a given tone channel to a desired port and port group timeslot.
The timing diagram of Fig. 70 illustrates the order in which the broadcast tones are generated with regard to timeslot counter outputs and with regard to timeslot identities of timeslots 30 and 31 of the PGH highway format entering TSI circuit 24000.

~\ ~

" K. TIMING AND CONTROL CIRCUIT (2 i '.
lo General Description :: .
Referring to Fig~ 71, timing and control circuit 28000, operates on a basic 1.953 microsecond cycle to generate the ~ ¦ control signals required to make data transfers to and from l; ¦ port data stOre 33000 and to a memory section (not shown) in converter control cir-cuit 30000. The circuit also contains three priority queues (not shown in Fig. 71) for storing j : .
I ~ equipment ~umbers (ENs) which represent port position equipment that require processing by call control processor subsystem 408.
Specifically the ENs are those which have generated new event codes. Six clock phases are also supplied to combinatorial ~ logic (CL) organization 34000 for timing its operation.
;~ Referring now to Fig. 19, timing and control circuit 28000 ! can be divided into four functional areas: counters (including count-decode, error-detection, and resynchronization circuits) 28002, address selector network 28004, ~ueues (including control logic) 28006, and enable generation logic 28008.

. ~ .
2. ~
"
The operation of timing and control circuit 28000 is based ¦l on a 1.95~ microsecond cycle. These memory cycles operate the RAMs in port data store 33000 and allow data to be transferred from one location to another in a specified sequence. A total of ¦
2048 memory cycles are required to process data for 64 port groupsj 1920 ports, and other memory areas reserved for maintenance circuits. This means that each memory location is accessed every 4 milliseconds.
Referring to Fig. 72, each memory cycle 28010 is divided into five functional sub-periods 28012, 28014, 28016, 28018 and l~
l l 28020.
These sub-periods are used to do the read and write operations for port data store 33000 between data store 33000 and the combinatorial logic (CL) organization 34000, or between data store 33000 and call control processor (CCP) interfaces controller 54000 at specified times during each cycle.
Each memory access between port data store 33000 and CL
organization 34000 is done in a 128 bit byte. Since each port data field 33500 contains 256 bits, a second CL access is some-times required during the same memory cycle. This second access is done at memory location N+2.048K (first access at location N).
It will be appreciated that N is always the contents of the address counter 28022, in counter organization 28002. This counter is the source of the sequential timing of access to the port positions for system 400.
Because of the 16 bit structure of the CPU bus, CCP interface controller 54000 can only access port data store 33000 in 16 bit bytes.
Accesses to the port data store 33000 are allocated as , follows. During the first 448 nanosecond period (28012)~ the memory is read at location N (determined by address counter 28022 which counts from 0 through 2047), and the data is trans-ferred to the CL organization 34000. During the final 245 nanoseconds period 28020, data from CL organization 34000 is written back into data store ~3000 at location N. These two accesses are for the benefit of CL organization 34000 ? and have no relation to the operation of CPU interfaces controller 54000.
The remaining 1464 nanoseconds of the cycle are either: (i) used for access to CL organization 34000 for purposes of a read-modify-write function when CL organization 34000 dictates that s second access is required, or (ii) used for a 16-bit controller l~ 54000 read-modify-write access when the following conditions are met:
a. CL organization 34000 does no-t need a second access~
' b. The con-troller 54000 requests access.
c. The address requested by the controller 54000 is different from the current first read address by CL
organization 34000.
` I There are three types of memory cycles, differing only in which of the following three uses are made of -the middle 1464 nanoseconcls.
1. CL organization 34000 accesses the second 128 bits of data for a port at address N+2.048.
2. Controller 54000 accesses a 16 bit word at any address N.
3. The memory remains idle (neither CL organization 34000 I nor controller 54000 request access).
Although second accesses by CL organization 34000 normally ', , have priority over requests for access by controller 54000, the final 64 cycles in each 4 millisecond period (not used for processing data3 are devoted to CCP subsystem 408 so that it is guaranteed a minimum amount of access time.
.

3. Memo~ C~cle for Converter Control Circuit 3000_ ¦
Convert control circuit 30000 also operates on a 1. 953 microsecond memory cycle which is synchronous with that of port data store 33000. However, the buffer control memory cycle consists of a write-read operation at addresses provided by con~ert control circuit 30000 and is independent from memory control for data store 33000. All the memory control signals for buffer control circuit 30000 occur unconditionally each cycle and no enable signals are provided for data transfer.

1145Q~L9 4. Co~nters Timing and control circuit 28000 has two binary counters consisting of address counter 28022 and a state counter 28024, Fig~ 19. The address counter 28022 is an 11 bit counter which increments every 1.953 microseconds while counting from 0 to 2047. State coun-ter 28024 is a 4 bit counter which increments every 122 nanoseconds in counting from 0 to 150 State counter 28024 is used to define subperiods 28012, 28014, 28016, 28018 and 28020 (Fig~ 57) and to enable generation of control signals at specified times during each cycle. All state counter counts are decoded providing 16 discrete 122 nanosecond state count signals during each memory cycle which are indicated in the second row of the timing chart of Fig. 73. Every ~our milli-seconds, both counters are checked for count errors and resynch-ronized (reset to zero) by synchronization and error detecting circuit 28026, Fig. 19.
State counter 28024 consists of a single 4 bit synchronous binary counter which counts up on the rising edge of the ~
clock. A parallel load command is given every four milliseconds by the 4 millisecond sync signal. This signal loads all zeros synchronously on the rising edge of the 8 MHz clock and causes all four output bits to reset. If any were set at the time of the load command, the state counter would be in error and an error flip-flop will be set in an error logic circuit 28026. The counter cycles through states 0-15 in 122 nanosecond increments once each memory cycle. Two 3-to-8 decoders included in a state decoder 28028 are used to generate the 16 discrete state signals.
These signals are used to enable logic 28008 to generate timing signals for internal use and for output to other circuits.
Address counter 28022 is a 12 bit synchronous binary counter which counts up from 0 to 2047 and is then reset by the 4 milli-second sync signal. The coun-ter consists of three cascaded 4 bit synchronous binary counters. (The MSB of the most significant counter is not used). The address used in access with combinatorial logic (CL) organization 34000 is provided by address counter 28022 plus the output of a J-K flip flop (not shown) in enable logic 28008 which sets in each cycle during the second access period. This bit is used as the address MSB and provides the address jump from N to N~2.048K. The address counter 28022 (address bits 0-10) is incremented at the end of state 15 on the rising edge of 8 MHz. The MSB (bit 11) sets at the end of state 3 and resets at the end of state 11. Count 2047 of address counter 28022 is fully decoded and applied to the error-check and resynchronization logic 28026. Counts 1984 through 2047 of the address counter 28022 are decoded to inhibit the CL organization 34000 from requesting a second access to provide CCP subsystem 408 a guaranteed access period.
Every four milliseconds bo-th address counter 28022 and state counter 28024 are checked for correct counts and an error signal is generated if either count is incorrect. This is done by enabling the J input of the sync error flip-flop in synchronizing !
an error detection logic 28026 with the condition that address . ; .
counter is e~ual to 2047 (the terminal count3 or the count condition of state counter ~8024 being equal to 14 or 15. The LSB of state counter 28024 is not used because o~ the set-up time requirement of the flip~flop. If the flip-flop is enabled by an incorrect count, it will set on the rising edge of 8 MHz when the 4 millisecond sync pulse is present. The resulting error signal is sent to the port control diagnostics. This flip-flop is reset by a CLR ERR signal from a diagnostics circuit. The same signal which is used to clock the synch error flip-flop (4 ms sync C8i~Hz) is also used to clear both counters to all zeros .

Since they should bo*h already be in the zero s-tate, the clear pulse normally has nc effect.
Three quad 2-to-1 data selectors 28030 in POM address , selector network 28004 are used to provide the 12 bit POM address ¦I bus with the required address~ The select control originates at Il a SEL CCP flip-flop (now shown) in enable logic 28008. When this I flip-flop is reset, it causes the 11 address counter bits and the output of the MSB flip-flop (previously discussed as the flip-flop which advances the address from N to N+2.048K which is located in enable logic 28008) to be applied to an addréss bus ;28031. When the SEL CCP flip-flop is set, the CCP requesting II address, contained in a CCP address latch 28032 is applied to , .
bus 28031. A REG SEL BIT 3 signal from the controller becomes the CCP address MSB. The SEL CCP flip-flop is set during s-tates through 11 when the three conditions for a 16 bit read-modify-write access (previously discussed in Section 2) are met.

5. Enable Logic Enable logic 28008 generates as outputs all the actual timing and control enable signals for supporting functions internal -to timing and control circuit 28000 as well as for operation of l combinatorial logic (CL) organization 34000, port data store ¦l 33000, CCP interfaces controller 54000 and converter control 30000.
The enable logic 28008 arbitrates and grants second CL
organization or CCP subsystem access request. All output signals are synchronous with the 8 MHz clock, some with the rising edge and some with the falling edge. With the exception of timing ¦pulses CPl~CP6 (28032, 28036, 28038, 28040, 28042 and 28044, Fig. 73), all signals are generated by gated J-X flip-flops clocked by 8 MHz. CPl-CP6 are generated by a hex D flip-flop 1145~19 (not shown) with state decodes as inputs and clocked by 8 MHz.
The enable logic outputs will be discussed at a later point herein.
The CL REQ signal is the logical OR of five bits read from the port data store 33000 during the first read of each memory cycle. These bits are RD2SD, RD2RD, RD2RGL, RD2SRS and RD2COM2.
The ORed function of these bits is ANDed with decoded counts 1984 through 2047 of address counter 28032 which, in effect, denies a second POM access request during these address counts.
When the CL REQ signal is in its ASSERTED state, the enable logic receives indication that the CL organization 34000 requires a second access to data store 33000 to obtain bits 128-255 of the port data ~ield for the current memory cycle.
This request will always be granted since CL organization 34000 has priority over CCP subsystem 408.
The CCP REQ signal is synchronously generated as follows:
The previously discussed CCP REQ flip-flop in enable logic 28008 is set at state 2 if CCP subsystem 408 is requesting access (ENABLE S-R =1). This is shown as curve 28046 of the timing diagrams of Fig 73. If the address of the CCP request is not equal to the current count of address counter 28022 (determined by the A=B output of a comparator 28048~ Fig. 19, which compares the address provided by CCP address latch 28032 with the address from address counter 28022) and if CL organization 34000 is not reque~ting a second access (except during address counts 1984- ¦
2047) then the previously discussed SEL CCP flip-flop will be set at state count 4. This is shown as curve 28050, Fig. 73. The SEL CCP signal causes the address ~lector 28030 to switch to the CCP address and allows the CCP data transfer signals to be generated by enable logic 28008. These transfer signals consist of CPUB-CPU (curve 2805Z), CPU-CPUB (curve 28054~ and RAM CPUB

(curve 28056). The CCP REQ flip-flop in enable logic 28008 is reset at the end of state count 11 if the SEL CCP flip-flop was set during that memory cycle. It will be appreciated that enable circuit 28008 is using the fact that SEL flip-flop was set as an inf~ication that CCP subsystem 408 has gained access during this memory cycle. A PS DONE signal (not shown), which is the com-plement of CCP REQ, goes HIGH to inform the CCP interface controller 54000 that the CCP access is completed. If the CL
organization 34000 had requested a second access, or if the CCP
address had been the same as the current address count, the CCP REQ flip-flop would have remained set until a subsequent f cycle when conditions were right for a CCP access. The SEL CCP
flip-flop resets unconditionally at the end of state count 11.
Functional characteristics of the various enable signals from enable logic 28008 will not be described with referenca to the timing diagram of Fig. 73.
The RAS 0-7 signal, (one example of which is shown as curve 28058), generated as an active HIGH, is used to latch the six row address bits into the RAM chips. RAS normally becomes active three times during a memory cycle as follows: (1) to latch the address for 34000 first read (interval 28012, Fig. 72); (2) to latch the address for CL 34009 second read or for a CPU access (interval 28014, Fig. 72); and (3) again for the CL 34000 first write (interval 28020, Figo 720) A RAS transition is not required ¦
for either a CL second write or a CCP write (cumulatively shown as in-terval 28018, Fig. 72). The reason is that the second write always occurs at the same address as -the second read, and there-fore the RAM already contains the proper address. In a cycle where no CL second access or CCP access is required, RAS remains inactive during the center part of the cycle as shown by dashed line portion of the curve 28060, Fig. 73. Eight indivldual RAS

t signals are provided to port data store 33000. During a normal CL access, all eight RAS signals are active simultaneously to access 128 bits as required by the telephony preprocessor 34000.
, During a CCP access, only one of the RAS signals is active -to provide access to only one 16 bit word as required by controller ¦ 54000~ Controller signals REG SEL BIT 0-2 along multiple leads 28062, Fig. 19 are decoded within enable logic 28008 to provide i an enable for the proper RAS line. In addition, if the FRZ bit read from port data store 46000 during the first CL read has been set, all RAS lines except RAS 3 will remain inactive for the rest of the cycle. RAS 3 allows the CL org~nization 34000 to modify only that word con-taining the FRZ bit.
The CAS signal, curve 28064, which is also generated as an active HIGH is used to latch the six column address bits into the RAM chips~ CAS is generated from the RAS signal and becomes active 122 nanoseconds after RAS. Unlike RAS, CAS is inhibited only when no CCP or CL second access is required in the center portion of the cycle. 3nly one CAS signal is provided to port ; ' data store ~3000.
The R/~ signal, curve 28066, Fig. 73, 66, is used by port ;~ ~data s-tore 3~000 to control multiplexing of the 12 memory address ~ lines onto the six address lines required by the 4096 RAM chip.
-~ ¦When R/C is high, row address bits ADR0-ADR5 are applied to the RAM. When R/C is low, column address bits ADR6-ADRll are applied to the RAM. R ~ is always high when RAS becomes active and goes low 82 nanoseconds after the RAS transition to select the column - address before CAS becomes active.
The write enable (W~) signal, curve 28068, Fig. 73, which t ¦is generated as an active HIGH is active unconditionally between state counts 10 and 15 of each cycle. This signal is used in conjunction with CAS to enable write operations to be performed.
During a CCP or CL second write, the tr~nsition of ~ while CAS

I
I

is active initiates the write operation. During the CL first write, the transition of CAS while WE is active initiates the write operation. When no write operation is to be performed (no CCP or CL second access), the inactivity of CAS inhibits the ~rite operation. It will be appreciated that no second access is required at the time write enable becomes active. The inactivity of CAS will prohibit the memory from writing at that time.
The signals DB-CLA thru DB-CLD curves 28070, Fig. 73, are four parallel identical outputs which are used as first read data strobes. They originate from the same flip-flop in enable logic 28008. These signals are 122 nanoseconds active low pulses occurring unconditionally between state count 2 and state count 3~ Data output from the RAM is latched into CL organization 34000 at trailing edges of these signals~
The DB-CLE through DB-CLJ signals, curves 28070 and 28072, Fig, 73, which function as the second read data strobes are equivalent to DB-C~A - DB-CLD and function to latch second read data into CL organization 34000. There is single source of these signals (designated DB-CL2) within the circuit 28000. DB-CL2 is generated only if the CL REQ signal is true and address count=
1984-2047.
The ~ b~ thru CLJ-1bB signals (curve 28074, Fig. 73) which function as the CL second write data enables are parallel outputs originating from a single source designed ~E~E~ within circuit 28000. This signal occurs for 366 nanoseconds between state counts 9-12 if CL organization 34000 has requested a second read.
The signal is used to allow data to be transferred from the CL
organization 34000 to the port data store 33000 for the second write operation (modified second read data).
The CLA-DB thru CLD-DB signal (curve 28076) function as the ``` I!

I .
.
CL first write data enables. The source of these parallel out-i puts is designated CLl-DB within circuit 28000. The signals are equivalent to CLE-DB - CLJ-DB but occur between state count 13 and state count 0 to enable communication of first write data ¦ frOmr CL organization 34000 to port da-ta store 33000.
The RAM CL Signals, curve 28078 ~ functions as the RAM to I telephony CL organization 34000 output control. Its generated ; I unconditionally each cycle as an active high during state counts 1-8. During a CCP subsystem access, the signal is inhibited during state counts 4-8. It is used to enable tri-state drivers ~ in port data store 33000 to pass read data to CL organization `~ ~ 34000.
The RAM CCP signal, curve 28056, functions as the RAM to CPU output control. This signal is active high during state ; counts 7 and 8 during a CCP access and allows read data to pass ~rom port data store 33000 to controller 54000.
The CCBB-CCP signal, curve 28052, functions as the CCP
Read Data Strobe. It occurs between state counts 7 and 8 during a CCP access. The trailing edge of this pulse latches CCP read . ~ .
data into the controller 54000.
- The CCP-CCPB signal, curve 28054, functions as the CCP
write data enable. It occurs between state counts 9 and 12 during a CPU access. This signal allows modified data to pass from controller 54000 to the port data store 33000 during a CCP write operation.
The CLKPRT si,=,nal, curve 28080, is a 122 nanosecond pulse occurring unconditionally between state counts 3 and 4. It again occurs conditionall~ at state count 8 if either the CCP or CL organization 34000 is making a second access. It is used to provide control to the port data store parity circuit.
The M~TTCP/PL signal, curve 28082, which is normally HIGH, I' will go LOW during state counts 9-12 only during a CPU access.
This signal is used by port data store 33000 to control CCP write opera~ions.
The GP1-CP6 signals, curves 28034, 280363 280389 28040, 2804-2 and 28044 are a series of discrete 122 nanosecond pulses which occur unconditionally each cycle and are used to control operations o~ CL organization 34000.
The TS RAS signal, curve 28084, functions as a row address strobe for memory units o~ buffer control circui-t 30000. TS RAS
occurs unconditionally during state counts 3-6 and 10-13 of each 1.95~ microsecond memory cycle.
The T~r~ signal, curve 86, functions as a column address strobe for the memory units in buffer control 30000. TS CAS is a 244 nanosecond pulse occurring when TS RAS is ASSERTED.
The ~ signal, curve 28088, is a multiplex control signal used by converter control 30000 to select either a row or a column (6 bit) address for the buffer control memory.
The RS R/W signal, curve 28090, is a read-write control signal for the memory units in converter control 30000. The FEN AD signal, Cur~e 28092, is used by converter control circuit 30000 to select an appropriate 12 bit memory address.
1, i j 6.
,;
¦¦ Referring now to Fig. 19, three identical EN register queues l! register 28094J 28096, and 28098 store equipment numbers (ENs) ¦l for which there is a new eve~t code (other than zero) in the I, event code bit of response subfield 33506, Fig~ 2 of the !~ individual port data field. EN's are stored into a specified queue during a given port memory cycle according to priority determined by the PRP0 and PRPl bits. The queues permit the controller 54000 to determine which EN's (port equipment 1145~19 positions) require CCP accessing and subsequent processingO
Three status signals Ql EMPTY, Q2 EMPTY, and Q3 EMPTY eminating from the respective queues indicate to controller 54000 if a queue should be read. Each queue consists of three 4 bit x 64 ~rd FIFO memories (one bit is not used in storin~ the 11 bit EN). The chip con-trol signals are logically combined to operate three memory chips as a single 11 X 64 FIFO memory. Address counter 28022 applies its output to each of -the queues so that when an EN number is to be stored in a particular priority determined by the PRP0 and PRPl bits this address will be inserted into the applicable queue. Queue outputs are 11 bits of EN data for each queue. A feature o~ the FIFO chips used in the queues is that chip loading and reading may be done asynchronously.
This allows controller 54000 to read any selected queue independ-ent of loading operations.
Each FIFO queue memory has three functional signals associated with write operations. These are: (i) data input (i.e., the EN) (ii) shift input for the purpose of loading the data into memory, and (îii) input ready for the purpose of sensing that the queue is ready to accept a new data word (i.e., previous shift input completed). Referring now to Fig. 35, the input ready signal is used by queue load logic 28100 along with timing signals from the enable logic 28008 priority bits PRP0 & PRPl, FREEZE bit, PRIORITY REQUEST FLAG bit, and the event code bit to generate a selected queue load (shift input) at state count 7 during a memory cycle. - -Queue loading is accomplished as follows. When the CL firstread is performed, DB-CL is used to clock the PRP0 & PRPl bits, the PRF, and the FREEZE bits into priority bit register 28102.
PRP0 & PRPl are applied as inputs to a 2-to-4 decoder in shift clock select logic 28102. Three separate decode outputs are ,' provided and are gated with the corresponding queue input ready ,j signals from each queue. These three signals are then ORed ~! together in logic 28103 to generate a signal indicating that I ' the selected queue is ready to be loaded. If the PRF is reset, I a qu~ue load flip-flop in load logic and timing circuit 28100 I' is set at s-tate count 6. This enables the shift clock select logic 28103 which also contains another 2-to-4 decoder to decode the priority bits. The decode outputs are gated with CP2 to produce the actual shift input clock.
When the CL first write is performed, the PRF bit is set and written back into port data store 33000 if a queue has been loaded. This is done by using CLl-DB to enable a fixed bit to the PRF input of priority bit register 28102. This is made possible by using tri-state buffers to send three of the register bits from t~e output back to the input and, thus, to the port data store 33000 during first~write. The PRP0 & PRPl bits are also recirculated. However, they are independent of queue loading and are always written back into data store 33000 un-changed. The PP~F bit is only written back unchanged when a queue was not loaded. The FREEZE bit is used to inhibit queue loading and is under control of CL organization 34000 only. This is why the FREEZE bit is not recirculated as are the other status bits.
The 11 QUtpUtS from each queue are connected to tri-state drivers which are wired together at their outputs to form an 11 bit queue data bus (which carries CCPB O~lO)a The 11 queue data bus lines also connect to the input terminals of the CCP address latch 28104. The queue data bus is, therefore, a bi-directional bus. An address for a port da-ta store access by controller 54000 is latched into the timing and control when LOAD CPU EN is asserted by controller 54000. Controller 54000 controls queue data and address transfers on this bus. Because queue reading ll, is accomplished asynchronously with queue loading, controller 54000 may select a queue and read its contents in a straight-i forward manner. To read a queue, controller 54000 sets one of I the queue read bits (CCPPR0-2) along lead 28106. This causes i! the Gorresponding queue to shift out one ll bit data word and ,1 enables the corresponding tri state buffer. Only one queue can ¦I be selected at one time and a CCP address cannot be transferred during -this time. The Ql-3 EMPTY lines provide an indication ' to the controller that a queue contains data to be read.

7. Miscellaneous Si,~nals Timing and control circuit 28000 also generates a PSD SENSE
signal which switches to a low level during states 2, 3 and 4 of ~ each timing and control circuit cycle in which the incoming SB
; SENSE line is at a high level. The signal is used to control whether the CF0, CFl and CS0-7 bit areasllocations of port data field 33500, or the corresponding sense channels in other than voice bit buffer 32000 shall be the source of the sense bits received by CL organization logic. These bits may originate I from either the buffer 32000 or port data store 33000.

I L. ~
,I The converter control circuit 30,000 generates and supplies ¦~ the clock and control signals needed by parallel-serial binary ¦ signal converter 32,000 to route data between TSI matrix switch network 403 and port communications sub~ield 33501. Referring to Fig. 74, circuit 30000 includes a bank of four counters 30002 to generate the signals needed -to direct the other-than-voice data bit switching and storage operations. The counters are synch-ronized to different phases and decoded by decoders 30003 (same as 30030, 30044, 30046, Fig. 76 (introduced later) to obtain the required signals. Address signal~s from the buffer control are il45~

', used to program converter 32000 to communicate alternately with TSI matrix network 403 and subfield 33501.
Referring to Fig. 75~ the C2MHz clock signal and SYNCH
jl signals on leads 30004 and 30006 are used to clock and synch-¦¦ roni~e the four buffer control counters, 30008, 30010, 30012 ! ¦ and 30014.
, Sense write counter 30010 outputs control the writing of sense bits into converter 32000 from TSI matrix network 403.
Referring to Fig. 77 and Fig. 78, the WS4 signal from counter 30010, -the WS16, and SW 32 signals from coun-ter 30012 are write sense signals which are decoded by a decoder 30016, Fig. 78 to generate the ~ZrZ~, SA CLK, Fl CLK, and SB CLK signals, which clocks the binary data of slow sense charnels SF~, SFl' and SS0/'-SS7l into the four input shift registers 32016 in parallel-serial binary data converter 32000, Fig. 10.
; ' Write sense signals WS 1 from counter 30010, WS16, and WS 32 ~rom counter 30012, (Fig. 77) are decoded by a decoder 30018, , Fig. 76, to generate the ~g~ and CCK0 pulse -trains, ~2 1~ clocks the sense bits from the input shift registers to RAM
32002a and 32002b, Fig. 10. CCK0 is used during the control read operàtion to clock control bits via the data selectors 32028 and :, .
32028b to the output shift registers 32006 of converter buffer 32000.
The WSl, WS16, and WS32 signals are also decoded by a decoder ¦ 30020, Fig. 78, to generate SlRW and S2RW signals which alternate-¦ ly enable the write inputs of RAMs 320029 and 320026, Fig. 10.
l Write sense signals WS2, WS4, WS8, MS3, MS4, MS5, MS6 and ¦ MS7 from counter 30010, Figs. 77, pass through 2-to-1 data selectors 30021 and are used to address RAMs 32002a and 32002b of converter circuit 32000, Fig, 10 to allow sense data to be written into the RAMs.

ll ~
1~5 !
,, Write sense signals MS8 and MS9 from coun-ter 30010, Fig. 77, generate the SlMS signal on lead 30022, Fig.76 and an S2MS signal on lead 30024, Fig. 77, respectively~ which control sense binary data write-in to the RAMs. The SlMS and S2MS signals are empl~yed in converter 32000 to permit write-in o~ sense data bits during each millisecond o~ the 4-millisecond write-in cycles.
The SRPPC output of the sense write counter 30010, Fig. 77, is used to generate the SlEN and S2EN ~ignals on leads 30026 and 30028~ These signals enable readout of the sense bit RAMs during the sense bit readout operation.
The cutput sense bit read counter 30008, Fig. 81, controls the readout of sense bits from RAMs 32002a and 32002b, Fig. 10 ii in converter 32000.
Read sense signals RS4 and RS8 produced by counter 30008 are decoded by decoder 30030, Fig. 76, into SENA and SENB, SENC, and SEND signals at output leads 30032, 30034, 30036, and 30038 'i which enable one of the four associated converter 32000.
The RS16 read sense signal produced by counter 30008, Fig. 81 becomes S SEL0 at the output of buffer 30040, Fig. 77, and is used to select the output of either RAM 32002a (S SEL0 low) or RAM 32002b (S SEL0 high).
Read sense signals PS0 through PS7 produced by counter 30008, Fig. 81, pass through data selectors 30021a and are used to address RAM5 32002a and 32002b to allow sense data to be read out to combinatorial logic organization 34000.
The outputs of control bit write counter 30014 control the writing of control bits into converter 32000 from combinatorial logic organization 34000.
Write control signals WC1 and WC2 produced by counter 30014 are decoded by decoder 30042, Fig. 76, to generate a CCK strobe pulse every two microseconds. Each CCK pulse strobes the 16 p~ ~

I binary control data bits for one port from combinatorial logic organization 34000 into 16 latches 32026, Fig9 10, in converter 32000.
Write control signals WCl, WC2, WC4, WC8 and WC16 produced ! by c~unter 30014, Fig. 81 are decoded by decoders 3004 and ¦¦ 30046, Fig. 76 to generate the ClRW0 through ClRW7 and C2RW0 i through C2RW7 signals~ These signals sequentially enable write-in to RAMs 32004a and 32004b, Fig. 10 during alternate 4-milli-i second cycles. While control`bits are being written into oneRAM, they are being read out of the other ~AM as will be described later.
Write control signals PC0 through PC7 produced by counter 30014, Fig. 81, pass through data selectors 30021b and are used to address RAMs 32004a and 32004b to allow control data to be written into the RAMs.
Write control signals WC4 and PC0 produced by counter 30014, Fig. 81, generate C SELA and C SELB signals9 respectively, on leads 30048 and 30050 7 Fig. 77. These are used to clock control bits from converter 32000 to TSI matrix network 403 during the control bit read operation.
The output control bit read counter 30012, Fig. 77, controls the readout of control bits ~rom the RAMs 32004a and 3Z004b, Fig. 75, in the converter 32000.
The CRPPC output of the control bit read counter 30012, Fig. 77, enables readout of either RAM 32004a or RAM 32004b, Fig. 10. Read control signals ClMS and C2MS produced by counter 30012, Fig. 77, generate ClMSCE and C2MSCE signals at output ! leads 30052 and 30054, respectively, which control readout of ¦' the control bits from the RAMs 32004a and 32004b, Fig. 10, via the 4-to-1 line data selectors 32032 connected to shift registers 32006, Fig. 10. The ClMSCE and C2MSCE signals are employed in converter 32000 to permit readout of certain control bits during I

I
each millisecond of the 4-millisecond readout cycle.
The control bits for a one millisecond period are clocked from -the RAMs 32004a and 32004b via data selectors 32028 to all four output shift registers 32006 by eight pulses ~ on lead ¦l 3005~, Fig~ 78.
¦' The CGK0 pulse train uses of half of a 15.625 microsecond ' frame. During the other half of the frame, the F0 CLK, ~ E~, , and ~ E~ signals, Fig. 82, clock the data out of shift registers 32030 to 4-to-1 line data selector 32032 which selects the bits to be fed serially to the matrix switch.
; Read bit control signals MC3 through MC7 produced by counter 30012, Fig. 77 are used in conjunction with write bit ~ sense signals WS2, WS4 and WS8 produced by counter 30010, Fig. 77, - to address RAMs 32004a and 32004b, Fig. 10, to allow control , data to be read out to TSI matrix network 403.
'; '~ , i, _ .i _ ', l I
__ I
ll M~ PARALLEL-SERIAL BINARY SIGNAL CONVERTER (32000) 1. ~3e~ga~
In the operation of other-than-voice data TDM network 407, TDM binary sense data channels SF0', SFl', and SS0'-SS7' are ¦separated from the voice data going through TSI matrix network ¦403 by stripping the 30th and 31st timeslots from the PGH frame data streams entering TSI circuit 24000. These stripped off , binary signals are sent to parallel serial binary signal converter 32000 in the form of a binary serial data stream. In the case of ' fast sense channels SF0' and SFl the binary data is updated every ' millisecond. In the case of slow sense channels SS0'-SS7' the binary i5 updated every 4 milliseconds. Converter 32000 converts these signals into parallel form and sends them to port communica-tion subfield locations SF0 A-D, SFl A-D, and SS0-SS7 via combina-torial logic (CL) organization 34000. This communication is via a single tri-state bus extending through CL organization 34000.
Arbitration circuitry within CL organization 34000 controls which source will set the memory field in the event of contention between the sense char~els and the logical condition of CL organization 34000. It will be appreciated that the port communication sub-field locations are effectively the output termini of the sense ; data channels of other-than-voice TDM network 407.
Conversely, 16 port data memory field bit locations (CF0 A-D,~
¦ICF1 A-D, CS0-CS7) effectively constitute the input terminus of the !
~control data channels of TDM network 407. These bit locations are set by either CL organization 34000 or call control processor (CCP) ¦interfaces controller 54000~ Again, the tri-state bus passes ¦through CL organization 34000, and arbitration logic therein icontrols whether the control data channel will transmit the output jof CL organization 34000 or it will transmit the instant setting ¦of the port communication subfield bits in the event of conten-tion.

Parallel-serial binary signal converter ~2000 converts the ¦I parallel output form of these memory field bit locations into a binary serial signal and sends it to the associated TSI circuit 24000, where the serial binary data is injected into timeslots i 30 and ~1 of out-going port group highway frame.
Il This exchange of data between the TSI circuit 24000 and sub-I field 33501 permits the system 400 to respond, on a delayed basis, to status changes on any of the 1920 ports. The serial-to-parallel and parallel-to-serial conversions are done in converter , 32000 using random-access memories (RAMs) and shift registers.
Four parallel-serial binary signal converters 32000 are used ; together to serve 2048 ports and other control channels. The present description will describe a single converter for 512 ports, it being understood that four such identical units are used, one for every two matrix switches ~` , Referring now to Fig.'s 10 and 11 , separate converter chan-nels 32001a and 32001b are provided in parallel-serial binary ;~ signal converter 32000 for handling sense and control data, I ~ respectively.
Con~erter 32000 includes buffer memories consisting of ran-dom access memories (RAMs) 32002a and 32004b in channel 32001b.
, Each RAM is composed of sixteen 256 x 4 static RAM chips which store the binary sense data or binary control data. Each chip ~ has four data input lines for writing data into the memory, four ; data output lines for reading data from the memory, and a chip select lead, which must be low to enable writing or reading of the chip. The chip contains an R/W lead which enables the read (high) or write (low) function. Eight binary address leads are used to select one of 256 locations for reading or writing of four bits in parallel. The memory is organized with the data of specific TDM binary data channels appearing on certain data lines of each RAM as shown in the following table:

i ~l II RAM LINE TDM BINAR~ DATA CHANNE ~ M NETWORK 407,1 1 F0' Z SA' (S0', S2', S4', and S6') ; 3 Fl' ! 4 SB' (Sl', S3', S5', and S7') 2. TDM Sense Channels The binary data of each sense channel is received from a pair;
of individual TSI circuit 24000 (illustrated as 24000-0 and 24000-1~ on sense data leads 32015a and 32015b and are clocked into 8-bit shift registers 32016a...32016d after passing through the input buffers 32018a and 32018b. The input to the respecti~e buffers 32018a and 32018b are ~rom each of two different matrix switches. The order in which the bits appear on the sense data lead from each matrix switch is shown in Table 32000-A, following.
. .
The Timing of the TDM channel bits and their relationships to the input and output clock pulses are for the 8-bit shift registers shown as wave forms Fl/F0 CLK and SB/SA CLK on the timing diagram of Fig.'s 14A, 14B a~d 14C.
Fig.'s 14A, 14B, 14C, 8A, 8B, and 8C constitute an overall timing diagram of the paths of the TDM sense and control channels of TDM network 407.
'~ The 16 data bits (one for fast channel and one for slow ¦ channel for each of eight port groups) in an even frame are received on a sense data lead 32015 as four data bits of fast ¦ channel F0', four data bits of slow channel SA' bits, four data ¦ bits of fast channel F0'~ and four data bits of slow channel SA'.

For an odd frame, the order is four data bits of fast channel Fl', four data bits of slow channel SB', four data bits of fast channel Fl', and four data bits of slow channel SB', as shown in Table 32000--A. These are clocked into two of the four 8-bit !
.
ll ~I shift registers 32016 during each 15.625 microsecond frame.
iI During odd frames, data bits of TDM channels FO/SA are clocked into registers 32016a and 32016b and during even frames, those of I TDM channels FO'/FA' are clocked into registers 32016b and 32016a.
The clocking is done by clock pulses shown as wave form F1/FO CLK
wave 32000" on the timing diagram of Fig.'s 8A, 8B, and 8C
' from the converter control 30000. Converter control 30000 ; i performs a similar function when data bits of the TDM control channels are clocked out of the shift regis-tersO

Bit Sequence in terms Bit Sequence in terms - of Data Channel under- of Data Channel under-Port Port ~oi~g Communication going Communication Time Group ~During an Even Port ~During an Odd Port Slot Unit No Group TDM Frame) _ roup TDM rame) _ _ 0 FO' F1~
1 FO' F1' 2 FO' F1' 3 FO~ F1' , 31 0 SA' SB' 31 1 SA' SB' 31 2 SA' SB' 31 3 SA' SB' j 30 4 FO' Fl' 3 FO' Fl' 6 FO' Fll j ¦ 30 7 FO' Fl' ! 31 4 SA' SB' I
1 31 5 SA' SB' 31 6 SA' SB' 31 7 9A' SB' ~L145C~19 The data bits of the TDM sense channels in the input shift registers 32016 are al-ternately written into one and the other of sense data RAM buffer 32002a cr sense data RAM buffer 32002b during successive 4-millisecond cycles. While sense data is ¦, bein~ written into RAM 32002a, the contents of RAM 32002b are ¦¦ being read out to port data subfield 33508 9 and vice versa. The 1' output clock for the shift registers is SCKO, which provides seven pulses during the second half of each 15.625-microsecond frame. Data clocked out of the,shift registers is applied to the data input terminals of the RAMs during the time that a write pulse (S IRW or S2-RW) is applied to the proper RAMs.
Referring now to Fig. 83 , the RAM output disable (OD) is controlled during data write-in as by so-called "Chip Enables."
The so-called`"Chip Enables" for the RAM are shown as wave forms lCSO and 2SSO, lCS1 and 2SS1, lCS2 and 2SS2, lCS3 and 2SS3, 2CSO
and lSSO, 2CSl and lSSl, 2CS2 and lSS2, 2CS3 and lSS3. lSSO/2SSO
is low during the first millisecond of the 4-millisecond cycle, lSS1/2SSl is low during the second9 lSS2/2SS2 is low during the third, and lSS3/2SS3 is low during the fourth. The leads carry-...
I ing these wave forms steer the data to the proper RAM during sense bit write-in.
After four milliseconds of write-in to RAM 32002a or RAM
32002b, during which one complete set of data bits of the sense TDM channels for up to 2048 ports can be stored, the RAM is read out to subfield 33501 via 2-to-1 data selectors 32020~ The readou-t occurs at a rate of 16 parallel data bits every 2 micro-seconds on leads SFOA through SS7. Data is read out from RAM
32002a or RAM 32002b when ~ or ~ , respectively, goes low ¦ under control of the converter control circuit 30000. This puts a low on the output disable OD of each of RAMs 32002a or 32002b, l`l The parallel data output on leads 32002a and 32002b from RAM
32002a and 32002b, respectively7 are applied to 2-to-1 data selectors 32020 which select either RAM 32002a or RAM 32002b and I also provide a tri-state output to a 16-wire tri-state bus inter-: ¦! con~ecting parallel serial converter 32000 combinatorial logic ¦l (CL) organization 34000 and port data store 34000.

3. TDM Control Channels ! Control data for a given port is received from one of sub-field 33501 combinatorial logic (CL) organization 34000, or CCP
interfaces controller 54000 on a 16-wire tri-state bus under control of a strobe pulse from converter control 30000. The strobe is repeated every 2-microseconds, in port number sequence, !
until the data for every port has been received over a 4-milli-second scan cycle. Each set of data bits of the control channel of TDM network 407 is clocked into sixteen control bit latches 32026 and is available at the latch outputs until the next 16 data bits are clocked in.
The control data bits from latches 32026 are alternately ~- written into one and the other of control data RAM buffer 32004aor control data RAM buffer 32004b during successive h-millisecond cycles. While control data is being written into RAM 32004a, the I li contents of RAM 32004b is being read out, and vice-versa. The - data output from the latches is applied to the data input termina~
of the RAM during the time that a write pulse is applied to the proper RAM. The "Chip Enable" inputs are controlled during data write-in as shown by wave ~orms lCS0 and 2SS0 thru wave form 2CS3 j and lSS3 of the timing diagram of Fig. 8~. lCS0/2CS0 is low during ¦ the first millisecond of the 4-millisecond cycle, lCSl/2CSl is low during the second, lCS2/2CS2 is low during the third, and lCS3/2CS3 is low during the fourth. The leads carrying these I! .
) ~
~i waveforms steer the data to the proper RAM during control data write-in.
After the 4-millisecond period of write-in to RAM 32004a or RAM 32004b (during which one complete set of control bits for up to 2048 ports can be stored), the buffer is read out to 4-line to l-line data selectors 32028a and 32028b. Data is read out from RAM 32004a or 32004b when lead ClEN or C2EN, respectively, goes low under control of converter control circuit 300000 This puts a low on the output disable (OD) of each RAM, RAM 32004a or RAM 32004b. Also it passes through 2-input OR gates (not shown) and puts a low on -the "Chip Enable" input of each RAM by way of leads lCSO, lCSl, lCS2, and lCS3 or 2CSO, 2CSl, 2CS2 and 2CS3.
The 4-line to l-line data selectors 32028a and 32028b select the data bits corresponding to one of the four l-millisecond periods of the 4-millisecond cycle to be sent to the output shift registers 32030a, 32030b, 32030c, 32030d.
The con-trol data bits from the data selector for one l-millisecond period are clocked into all four output shift registers 32030a, and 32030b, simultaneously by eight pulses on the co~on clock lead CCKO from the converter control 30000.
These eight pulses occur during the second half of each 15.625 microsecond frame. In the other half of the frame, data is clocked out of the shift registers in serial form by signals shown as wave ~orms Fl/FO CLK and SB/SA CLK, Fig.'s 14A, 14B~ and 14C, The control data bits clocked out of shift registers 32030a are applied to another 4-line to l~line data selector 32032 which selects the bits to be fed serially to the TSl circuit 24000.
The order in which the bits are sent to TSC circuit 24000 on the control data bit leads 32034a and 32034b is shown in Table 32000-~Buffer Amplifiers 32036a and 32036b, which are connected to the output of data selector 32032, drive the control data bits to the matrix switch cards.

lll N. PORT DATA STORAGE D~VICE 33000 i (Level II Description) i i I lo OGn =~=~
,l, Referring now to Fig. 84, port data storage d0vice 33000 ¦¦ is composed of ~our identical RAM data storage circuits 33001a...
!1 33001d. Each circuit 33001 contains four 17-bit words for each !~ data memory field 33500~ The individual circuits 33001 are i, ~ormed of RAMs and conventional integrated circuits mounted on a ¦I single printed wiring board.
; Each of the 2048 ports served by a common control sector is allotted 256 bits of storage, 64 of which are used for dialing digits. Thus, each port effectively has its own digit storage register. Each storage device 33000 also contains parity check circuitry and tri-state bus drivers for use with the call control processor-port data store (CCP-PDS) bus 54010 and the combinatori-~i al logic organization port data store (CLB) bus 34002, CCP-PDS
bus is connected to CCP interfaces controller 54000. CLB bus 34002 comes from functional logic unit 38000, 40000, 42000, 44000, I and 450000 Operation of stora~e device 33000 is based on 1.953-i microsecond memory cycles. These memory cycles operate the RAMs ~; in device 33000 and allow data to ~e transferred from one location ¦-to another in a specified sequence. A total of 2048 memory cycles are required to process data for 1920 port, 64 port groups, ard 64 maintenance circuits. This means that each memory location is accessed once every four milliseconds. Each memory cycle is divided into subperiods which are used in the performance of read and write operations between combinatorial logic (CL) organization ¦ 34000 and device 33000~ and between controller 54000 and device j 2. ~
Referring now ~o Fig. 85. A memory access cycle begins when ¦ the 12-bit address (ADRO-ADRll) is received from timing and con~
trol 2800G. The address is applied to 2:1 data selectors 33031aO.
il 330~}d under control of the R~ signal. When R/~ is high, row address bits ADRO-ADR5 are selected and when R ~ is low, column ¦I address bits ~ ARDll are selected. All da-ta selector outputs address both the lower word ~DROL-ADR5L) RAMs 33031c and 33031d ~ and upper word (ADROU-ADR5U) RAMs 33031a and 33031b in all of the I buffer storage device sections 33022a.. 33022d. After R/C goes high and sends the row address to the RAMs, RAS0 and RASl (row address select lower and upper) go high and are inverted and then applied to the RAMs and RAS0 and RASl. These low RAS-signals strobe the row address bits into the RAMs. Eighty-two nano-seconds after the RAS-transition, R/C goes low and sends the column address to the RAMs. Th~ column address select (CAS) ~, i signal goes high 122 nanoseconds after RAS and is inverted and :: i `~ ~ applied to the RA~Is as CAS, The low CAS strobes the column address into the RAMs. The 1,953-nanosecond memory cycle has now advanced to the 244-nanosecond point (T1 of Fig. 72) and is ready to read 128 bits of data from device 33000 at the selected address, i, This address i5 designed as N, which is any given address between O and 2048.

3 First Read ~
As soon as the column address is latched into each of RQ~Is 33031a .033031d, the data (bits 0-127) stored at address N are read out from the DO pins and applied to bus drivers 33032a and 33032b. The outputs of drivers 33032a and 33032b go to combina-torial logic (CL) organization 34000 as signal PLB 0-31 and to the parity checkers 33034a and 33034b as signals RPRT 0-31.

j; A pari-ty bit was set in the associated parity RAMs when the data was initially stored to provide even parity if there are no errors. The parity check output is applied to the alarm latches which are part of parity controls and alarm latches 33036a and j¦ 3303Çb. The alarm latch is clocked at the 448-nanosecond point 1~ of the cycle, Fig. 72. If parity is correct (even), the parity ¦~ checker output is low and the alarm latch remains in the reset state. If, however, a parity error is detected, the parity checker output goes high. At the 448-nanosecond point the alarm latch is clocked which sends a low PARITY ERROR signal to timing and con-trol circuit 28000.
. , 4. Second Read Decision_~Whether to Read Second Hàlf of Referring again to Fig. 72. After combinatorial logic (CL) organization 34000 receives the 128 bits of data stored at address N, logic circuiting within CL organization 34000 makes a deci-sion on whether a second memory access is required by CL
organization 34000 during the current memory cycle. If it is required, CL organization 34000 addressing begins at the 610-nanosecond point (T3 of Fig. 72) of the cycle. If a second read by CL organization 34000 is not required and the call control processor (CCP) subsystem 408 has requested access at an address other than N, addressing by subsystem 408 begins at the 610-nanosecond point, T3, of the cycle. If neither CL organization 34000 nor CCP subsystem 408 request access at this time, the memory remains idle for 854-nanoseconds.

5.

Second read addressing by CL organization 34000 is similar to the first read addressing described hereinbefore in Subsection 2, except that the address is N+2K.

¦¦ 6. e ~
A second read by CL organization 34000 starts at the 854-nanosecond point (T4 of Fig. 72) of the cycle and is similar to - the first read and parity check hereinbefore described in Section 3, except that bits 128-255 are read. CL organization 34000 can now modify the data during the next 244-nanoseconds in prepara-tion for writing at the same memory location of port data store ~` 33000.
~ '~
7~ ~
_oin~ the Writin~ ;
~The second write operation occurs at the same address (N~2K) Ias second read. After the data has been modified by CL organiza-tion 34000, it is returned on leads CLB 0-~1 and applied to 2:1 data selectors 33038a, 33038b. Data selectors 33038a and 33038b connect the DI (Data Input) pins of R~Ms 33031a and 33031c with ' the CCP-PDS bus 54010 (consisting of leads CCP-PDS 0-31) at the ¦I period of time between T6 and T7 , Fig~ 72. This lS in response to the MWTCP/CL signal produced by timing and control circuit 28000 shown in Fig. 73, and more specifically in the period shown by dashed line 28083 thereon. Each output of data selectors 33038a and 33038b is applied to a RAM DI pin and to parity genera-tors 33040a and 33040b respectively.
Referring now to Fig. 73. For the second read, ~E, RASU, and CAS go low and remain low for the second write operation.
When WRT goes low, the data on the RAM DI pins is written into ¦I memory at location N+2K. At the end of write-in, RASL7 RASU~ and 3 again go high in preparation for the first write operation at j location N.
The write parity generators 3~040a and 33040b provide parity bits~for -the upper and lower 16 bits of memory of RAMs 33031a and 33Q31c. The parity bits (PRTDIU and PRTDIL) are stored in the i two parity RAMs 33031b and 33031d during write-in for use in ¦l parity checking during readout as hereinbefore described in Section 3.
. .
; 8 First Write Addressin~ ~By C~ zation 34000) The first write addressing by CL Organization 34000, Times T7~T89 Fig. 72, is similar to first read addressing as herein-before described in Section 2. At the end of addressing, the cycle is at the 1708-nanosecond point (T8, Fig. 72).
.
.
li 9- Eir~ W~ite (By CL Or~anization 34000) ,~After data bits 0-127 have been modified by CL organization :
34000, they are returned to port data store 33000 and applied to the RAMs as hereinbefore described in Section 6. As soon as the , column address is latched into the RAMs by ~S, the data on the DI pins is written in (also by CAS). After write-in, all control ¦ signals return to normal in preparation for the next memory cycle of data store 33000.

10. ~
If a second read by CL organization 34000 is not required and call control processor (CCP) subsystem 408 has requested access at an address other than N, addressing by subsystem 408 begins at the 610-nanosecond point (T3, Fig. 72) of the cycle.
The 12-bit address ~ -ADRll) received from timing and control l ~ .
circuit 28000, Fig. 71, is applied to data selectors 33030 which select RAM row and column address bits under control of the R/C
signal.
Because call control processor-port data store (CCP-PDS) ¦I bus ~4010 (consisting of leads CCP-PDS 0-15) has a 16-bit capacity, each access which subsystem 408 makes to device 33000 involves only 16 bits. Therefore, 16 RAMs on each one of the four RAM
,j , ~j data storage circuits 33001a...33001d, Fig. 84, are accessed at !;
one time by subsystem 408. Address selectors 33030 address the lower (ADROL-ADR5L) and upper (ADROU-ADR5U) 16 RAMs on each circuit. However, only the lower or upper row address selector signal (for example, RASO or RASl) is active on only one of RAM
data storage circuits 33001a...33001d during access by subsystem 408.
After R/C goes high and sends the row address to the RAMs, either RAS0 or RAS1 may go high, and is in~erted and then sent to the selected RAMs as RAS0 or RASl. The low RAS signal strobes the ;- row address bits into the RAMs. Eighty-two nanoseconds after the RAS transition, R/C goes low and sends the column address to the RAMs. The CAS signal goes high 122-nanoseconds after RAS and is in~erted and applied to the RAMs as CAS. The low CAS latches the ! column address into the RAMs. The memory cycle has now advanced to the 854-nanosecond point (T49 Fig. 72) and is ready to read ~! 16 bits of data from the RAMs at the selected address.

As soon as the column address is latched into the RAMs, 16 ~¦ data bits are read out from the DO pins on the 16 enabled RAMs ¦and applied to bus drivers 33032a, 33032b. The bus driver outputs go to 2:1 data selectors 33042 and to parity checkers 33034a, 33034b which operate as hereinbefore described in Subsection 3.

1145~

Output data selectors 33042 are enabled only during a sub-~ I system 408 read access by a low RAMCPUB signal. The MRDCCPBU/L
¦;~ I signal causes the selection of either the 16 upper bits or the 16 lower bits, depending on the state of RASl. The selected bits are communicated to processor unit 50000 via common control sector controller 54000, as call control processor bus signals CCP-PDS 0-15. 2:1 data selectors 33038a and 33038b are inhibited ¦~ during read operations so that this data is not reintroduced by them.
Call control processor subsystem 408 can now modify the data during the next 244-nanoseconds in preparation for writing at the same port data memory field 33500.

;~ 12. Write ~peration By CCP Subsystem 408A write operation performecL by subsystem 408 occurs at the I same address as the read operation performed by subsystem 408.
After the data has been modifiecl by the call processor subsystem , .
!i 408, it is returned on leads CCP-PDS 0-15 and applied to 2:1 i, data selectors 33042. The MWT CP/PL signal went high while the data was being modified by the subsystem 408 and now selects the inputs from subsystem 408. The 16 outputs of selectors 33038a and 33038b are applied to the DI pins on the 16 upper or lower RAMs and to parity generators 33040a and 33040b as WPRT 0-15 or WPRT 16-31.
For the read performed by subsystem 408, CAS and either RASL
~ or RASU goes low and remains low for the duration of the write I I operation. When WRT goes low, the data on the DI pins of the ¦ addressed RAMs is written into memory. At the end of write-in, _ ~
RAS and CAS again go high in preparation for the CL organization 34000 first write operation at location N.

iL~45Ql9 j .
, .
, o. ~

Common functional logic unit 36000 uses the binary code appearing in the combinatorial logic state (CLS) bit area of subfield 33518 and the coded in~ormation in the command (CMD) bit àrea of subfield 33503 to generate event codes. These event codes then are stored in the particular port related memory field 33500 associated with the port circuits requiring attention by call control processor CCP subsystem 408. From these event codes, the subsystem 408 determines the type of action needed.
Logic unit 36000 also times the period during which an event should occur and decodes the por-t type field in the Port Type (PTY) bit area of subfield 33502 to identify the kind of port to which the action applies. If the event requires it, the logic unit 36000 also provides release timing.
Referring now to Fig. 86, common functional logic unit 36000 communicates almost exclusively with the port data store 33000.
The two exceptions are the timing signals received from the timing and control circuit 28000 and the port type decoder out-puts which are transferred to the other functional logic units (38000 - 44000).
Data from port data field 33500 is strobed into the temporary storage registers 36002, 36001, 36010, 36011, 36012, 36013, 36014,`
and 36016. In response to signals DB-PL (A-D) from timing and control circuit 28000 (not ~hown), register 36002 stores the encoded data in the CLS bit area; Register 36001 stores the data in the CMD bit area; Register 36010 stores the data in the Out of Service Condition (OSS) bit area of sub~ield 33503; Register 36011 stores the data in the PTY bit area of subfield 33503;
Registers 36012 and 36013 store the data in the State Timer (ST0) bit area of subfield 33503; Register 36014 stores the data in ~ 5¢;3 I i :
Release Timer (RLST) bit area of subfield 33518; and Register ¦l 36016 stores the data in the release timing speed selector (RSP) bit area, the release timing (RLE) bit area, the seizure-in (SZI) ¦ bit-area in the supervisory-in (SPI) bit area of subfield 33510.
ll ~The data stored in the combinatorial logic state (CLS) ¦I register 36002 and in the Command (CMD) register 36001 are decoded ¦I by decoders 36018 and 36003, respectively, if the Freeze (FRZ) bit location of subfield 33514 is not set.
The outputs of these decoders along with the NORMAL output of an Out of Service Status (OSS) decoder 36022 are used by an Event Code (EVC) generator 36024 to produce event recognition ~ signals. These are applied to an encoder 36025 which generates I the actual 4-bit event code.
The CLS and CMD register outputs also are used to generate ~; ~ the next CL state via the write CLS control logic 36026.
The possible combinations of CLS and EVC generated functional unit 36000 for each of the possible events detected by PEP 406 u~der various port command codes are shown in the Table of , Fig. 87. The CLS and EVC bit areas are written by common functional logic unit 36000 by event code generator 36024 and ,~ , write CLS state control logic 36026 in response to CLS codes (0-15 only) generated by the other functional logic tmits (38000 - 4~000).
The state timeout (ST0) function is provided in logic unit 36000 logic by state timeout registers 36012 and 36013 that store a 6-bit field received from subfield 33503. The two most significant bits of the state timer bit area (ST0) determine the scale or period at which the timer will be decremented (256MS, 2.048S~ 16.3S, or 131S). The four least significant bits of the state timer bit area represent the number o~ times to decrement.
When the four least significant bits have been decremented to ~223-zero, an event code is generated (ST0 EVC). Between times to decrement, the value held by the ST0 register/counter is written back into the ST0 bit area.
Release timing may be considered as a "port event processor func~ion within a por-t event processor functionO~ It contains a release state control register 36028 which acts as an independent register for this ~unction, so that the function may be, and is, performed concurrently with any other PEP function which may be in progress. The release timing control logic 36030 monitors the RSP, RLE, SZI, and SPI bits of subfield 33510. The release timing logic loops in Release State Control (RLSC) state 0 until SZI, RLE, and RSE off-hook are received. When this occurs, the RLSC register 36028 is set to state 1. The release timing loops in state 1 as long as the SPI shows an off-hook condition. When an SPI on-hook condition is detected, the release timer field is set according to the state of the RSP bit in subfield 33510, that is, to either a release speed of 20MS (RSP=l) or of 208MS (RSP=0).
With the initial timer value set, the RLSC is advanced to state 20 In state 2 the timer field is decremented at the rate designated by the RSP bit every 4MS (RSP=l) or every 8MS (RSP_0) until the -timer has been decremented to zero with the SZI bit present.
When this occurs, a release event code (RLS E~C) is generated by event code generator 36024, Fig. 86. Simultaneously, the common logic writes the CLS state to CLS0, clears the SZI bit, and sets the RLSC state to 0. I~ the SZI bit is negated before the timer decrements to zero, the release timing logic sets the RLSC state to 0 to reini ate the sequence.

5~
Il, i P. SENSE SUFERVISORY EVENT (SSE)lTRANSMIT SUPERVISORY EVENT (TSE) ¦I E
'' 1. Overview of Functions Logic unit 38000 serves three functions: (i) sense super-I~ visory events (SSE); (ii) transmit supervisory events (TSE); and (iii) certain functions which supplement the operation of common ¦, logic unit 36000.
In its SSE function, unit 38000 provides the timing and ; control necessary to sort out incoming supervisory signals and classify them as:
1. Seizure/Release : 2. Stop Dial 3. Delay Dial Unit 38000 also provides timing and control to generate the following TSE outgoing supervisory functions:
: ' 1. Wink 2. Hookflash , 1 Yi. Wink-Off ; 4. Delay Dial ~, In its function of supplementing the operation of common logic unit 36000, unit 38000 provides the function of Timer No. 1, Timer No. 2, and incoming supervisory signal filtering and detec-tion which i~ one of the functions which operates in conjunction with unit 38000 itself as well as with other functional logic units.

2. Structure and Operation iof Unit 38000 With Re~ard to SSE
Function _ Referring to Fig. 88, a sense bit majority logic 38004 moni-tors the four bit location SF0A - SF0D, subfield 33501, Fig. 2, I !
I ~ , 11 :
which represent the preceding four outputs of the corresponding fast sense data channel of TDM network 407. Whenever any three of the four F0 sense bits are asserted, the Last Look 1 (LL-l) bit is written back as asserted in an LL-l and LL-2 snapshot register 38005. The LL-l bit will be rewritten as asserted only if any two of the SF0 bits are asserted when the LL-l bit is read out of register 38005 as having been asserted on the previous 4-millisecond port addressing signal for the given port (which is provided by address counter 28022, Fig. 19). If the LL-l bit is read ou-t~asserted, the LL-2 bit will be rewritten asserted in the next 4-millisecond port addressing signal period.
A supervisory input (SUPY IN) signal is used by RD functional logic unit 44000 in seizure detection~ It is generated by digital logic array 38008 upon the simultaneous assertion of all of the above signals in combination with the supervisory input bit (SPI) from subfield 33510 and/or the receive digits (RD) command in port command subfield 33502. The generation of the SUPY IN
signal is per~ormed by a first SUPY IN filter logic unit 38010 and li a second SUPY IN filter logic unit 38012. The purpose of digital logic array 38008 is to cause unit 38000 to ignore momentary interruptions (on-hook or off-hook) which are less than 16 milli-seconds in duration.
, , .
`; , The type of SSE detection to be psrformed by unit 38000 is specified by the Argument 1 and Argument 2 bits of por-t command subfield 33502. The Timer 1 and Timer 2 bits of working storage subfield 33518 are preset to the val~es specified in the I¦ Argument 5 and Argumen-t 6 bit areas of subfield 33502, respec-¦¦ tively. Then these values are decremented by Timers 1 and 2 i (38014 and 38016 of Fig. 91). For all commands other than the ¦ send digits (SD) command, the rate at which the Timers are decremented is specified by Argument 3 and Argument 4 of port 5C~

command subfield 33504. For the SD command, the rate of decre-menting the Timers is specified by the two most significant bits of the respective timer bit areas in working storage subfield 33518. When the timer(s) have beer. decremented to the appropriate value(s), the timer state decode logic units 38017 and 38019 send the appropriate signal to SSE CL progression logic 38021, which in turn controls SSE CL state encoder logic 38022, Fig. 89, where the proper TEL state is generated to control the SSE sequence.
JCLS 0-15 signals are sent to common logic unit 36000 to generate the appropriate event code. The formats of SSE arguments are shown in Fig.'s 20A, 20B, 20C, 20D, 20I. I
` i !
1 3. Structure and O~ration of Unit 38000 With Re~ard to TS
Function The performance o~ the TSE ~unctions by unit 38000 employ j, the same Argument bits and bit areas of command subfield 33502 as were employed in performing the SSE functions, except that i !
the speciflc values and functions are as shown in Fig.'s 25A, 25B, 25C, 25D, and 25E. The Argument 1 and Argument 2 bits define which type of send supervision function is to be performed. The ! timing for generating these functions is established by decre-menting the Timer 1 and/or Timer 2 bit areas o~ working storage subfield 33518 while in the appropriate combinatorial logic state ¦
, CLS. The duration of the event and the seizure recognition time ¦ are specified by Argument 5 and Argument 6, respectively. The ¦ Timer 1 and Timer 2 bit areas of subfield 33518 are set to these values and decremented at the rate specified by Arguments 3 and 4.
When the timer(s) has been decremented to the appropriate value, the timer state decode logic 38017 and 38019, Fig. 91, sends the appropriate signal to TSL CL progression logic 28023, which in turn controls TSE CL state encoder 38024, Fig. 89.

1,1 The CLS information and the timer decode logic signals are , used by transmit supervision control logic 38026, Fig. 90, to I selectively set bit areas CF0 (A-D) or CFl (A-D) (which con-trol i~ the corresponding fast control channels of TDM network 407), port I comm~hications subfield 33501. A LINE OR TRUNK (except SXS TRK) ¦ signal will enable writing the CF~ (A-D) bit area. If the port 1, type is SXS TRK, the CFl (A-D) bit area will be selectively set.
i, A THRD signal may also set the CF~ or CFl bit areas of sub-1l~ field 33501 (which control the corresponding channels of TDM
network 407) whenever the THRE signal is asserted. The choice of I writing the CF0 or the CFl bit areas is again contrclled by the port type as previously stated.
, 4. Structure and Operation _f Unit 38000 With Reg~rd to S~

Uni-t 38000, in its ~unction of supplementing logic unit ' 1 36000 provides unit 36000 with a set of timing signals which mark ; periods o~ 256 milliseconds, 2.048 seconds, 16.38 seconds and ' 131.07 seconds duration. Unit 36000 in turn relays these signals to other functional logic uni,ts. The Timer 1 and Timer 2 cir cuits (38014 and 38016, Fig. 91) and their associated preset `, control, decrement controls and output coding provide the "trip 1, points" used in various other functional logic units in order to 1, ,~ advance the combinatorial logic state (CLS). The output decoding o~ these timers also sets the snapshot registers associated with various bit areas in a port data memory field 33500.

-22~-:1~45~11~

~` RING LINE (RGL FUNCTIONAL) LOGIC UNIT 40000 1. Overview of Functions - Ring line functional logic unit 40000 provides the timing and eontrol necessary to generate the proper ringing cycle to be ¦l applied to the line interface circuits. In response to the bit ;~ ', settings in port command subfield 33502 which have been made by call control program 56002, logic unit 40000 also controls the application of ringing voltage from the appropriate ringing bus to the proper port circuit. Logic unit 40000 also performs ring trip timing and filtering.

Structure and O~eration of Unit 40000 With Re~ard to Ringin~
Cycle Generation Referring now to Fig. 92, a 256 millisecond clock signal (RT256) which is provided by functional logic unit 38000 is , divided down by a counter 40003 and decoded by a 4-to-16 decoder :
40904 -to produce half-second (.512 second) phases at the outpu-t of decoder 40004. These half-second pulses are ORed by ring phase forming logic 40006 in groups of three to generate four phases of ringing. Each phase consists of approximately 1.5 seconds of ringing followed by approximately 4.5 seconds of silence during a cycle. The ring phases thus generated are transmitted via di~-l ferential drivers 40008 -to interrupter-serializer circuit 21100, Fig. 51. The ring phases are also used within logic unit 40000 by ring phase selection logic 40010 and 40012.
Selection logic 40010 is designated to be for party A; i.e., the called party. It employs the Argument 5 bit area of port ¦ command subfield 33502 to define the phase on which single party ringing will take place. The Argument 3 field specifies whether ringing is applied on the tip side or the ring side of party A.
ArO~ument 6 controls selection logic 40012 which is designated for par-ty B. Argument 4 specifies whether ringing is applied on the up side or the ring side of party ~.

3. 0 eration of Unit 40000 With Re~ard to the jl StrUltcaltieo~alndof Rin~in~-Volta~e to the Proper Port Circuit Ringing control logic 40014 uses the outputs of ring phase j, selectors 40010 and 40012 along with the combinational logic ! state (CLS) decoder 40001 to set the appropriate bit areas and , bit locations of communication subfield 33508 which control the control channels of network 407 to actuate the designated ring bus and path. The combinational logic state (CLS) is updated by means of an up/down counter 40018. Timer setting logic 40020 sets -the Timer 1 bit area of working storage subfield 33518 as a means for generating delays of 8 milliseconds or 32 milliseconds duration to allow for operating delays of the ring relay (R) and the RV relay. The assertion of Argument 1 enables emergency re-ring, sometimes called "operator ringback." The other arguments assign the R and the RV relays to the specified phases.
Event codes are enabled by a combination of operation of enable event code logic 40022 and "jumps" to common logic unit 36000 for the enabling of the various event codes (EVC's) associ-ated with specific combinational logic states (CLS).
i~ The conditions initiating the enabling,either the "ring trip"
or emergency re-ring complete event code, are: combinational logic state (CLS) = 21; timer 1 = 0; HALT bit of port command ~; subfield 33504 is not asserted; and CTRL B = 1. If the preceding !
conditions are true and Argument 1 is asserted9 a jump to CLC6 is enabled, and common functional logic unit 36000 generates the event code ~or an "emergency re-ring complete1' action. If the conditions are -true and Argument 1 is not asserted, a jump to CLS 5 is enabled, and the common functional logic unit 36000 generates the event code for reporting that a "ring trip" has 1.
I
Il occurred. If CTRL B is not asserted, a jump to CLS 2 is made and ¦I the event code representing an error condition is generated. If the H.T. bit is set, the event code representing a halt condition is generated by a jump to CLS lo 4.
~ l` Timin~
;~ Referring now to Fig. 93, ring trip timing is accomplished by updating the pulse count (PCT) and digit count (DCT) bit areas of digit storage subfield 33516 according to the contents of up/down counters 40024 and 40026. These counters are incremented by one count for each of bit locations SF~A - SF0D (of subfield 33501) that is asserted and decremented by one count for each of bit locations SF~A - SF0D that is not asserted during the presence of a given port(s) address in address counter register 28022, ~` Fig. 19, which occurs at a cyclic repetition rate of one appear- ¦
; ance every 4 milliseconds. The cyclic recurrence of the address which gives port event processor 406 access to the port data field ; 33500; i.e., that in address counter register 28022, Fig. 19, is i produced as a part of the operation of timing and control circuit 28000.
, In addition to providing the update of port data memory field, 33500 for those bits directly related to the ring line (RGLN) function, functional unit 40000 also provides the "write back"
registers (if a "second read" and subsequent write back is neces-sary) for the call state (CST) and port ordinal call position number PID#) bit areas of call state information subfield 33503.
These bi^t areas are in word 8 of memory field 33500 and therefore a part of 'che second read cycle in connection with the operation of port data store device 33000.

ll i.
~L45~19 QO
' I~
` 1. Overview of Functions Send digits (SD) functional logic unit 42000 provides timing I and ~ontrol for the outpulsing of both dial pulse (DP) signals i and toll multi-frequency (TMF) tone signals~ The make/break ~; ~ periods for DP sending are selectively responsive to settings of , the Argumen-t bit areas/bit locations of port command subfield 33502, which in turn are set by call control stored program 56002.
The TMF tone on/off periods are fixed at approximately 70 milliseconds for the digit signals, and a 100-millisecond ON
time for the KP signal.
Presending and/or post sending supervision is provided by logic unit 42000 in response to the setting of Arguments 5 and 6 of port command subfield 33502, Fig. 2, which in turn are set by I program logic 56002. In pro~iding presending and/or post sending supervision, logic unit 42000 operates in conjunction with SSE/TSE/supplement to common functional logic unit 38000. The presending supervision includes a polarity check option.
,' ~ ' - I
2. Structure and Operation of Unit 42000 1 Referring now to Fig. 94, the combinatorial logic state (CLS) is latched by register 42001 and decoded by decoder 42000 if the 1I CMD bit area of port command subfield 33510, Fig. 2, contains the ¦
¦¦ send digits (SD) command, as is indicated by assertion of the ENSD
I! signal from command decoder 36003 (Fig.'s 18 and 86) in common 1, functional logic unit 36000. When the port type is a trunk (and ¦ therefore DP sending will be performed), presending supervision I logic 42004 examines the Argument 5 bit area of port command sub- I
field 33502 during the presence of CLS 16. Logic 42004 examines Argument 5 to determine if outpulsing is to proceed immediately af~er receipt ~ ~ome ~upervi~ion si~nalling, ~r after a polarity ¦, check which is performed by polarity check logic 42006. The ¦ format of Argument 5 for the various presending supervision ¦ signals which may be specified are shown in the table of Fig. 30C.
.A similar provision is made for post-sending supervision, which employs the Argument 6 bit area in combinatorial logic state (CLS) 21. This is done by the operation of post-send supervision logic 42008 to examine Argument 6 during CLS 21.
The post sending supervisions along with the respective formats . ~ , of Argument 5 are shown in the table of Fig. 30D.
The detection of the supervisory event is performed as a SSE
' function o~ SSE/TSE/supplement to common functional logic unit ;' 1,! 38000. The update CLS state logic 42010 and the control A and B
register initiate transfer of control to logic unit 38000 while a send command is present in the CMD bit area of port command sub-field 33504. This is effected through the mechanism of controll- ¦
'I ing the CTRL A and CTRL B bits of working storage subfield 33518, , in accordance with the following control table:
~i CTRLA = 1 Disable SD CLS decoder and enable SSE CLS decoder CTRAL = O Enable SD CLS decoder (NORMAL) , CTRLB = 1 Return to SD upon detection of specified supervisory event.
¦, SSE logic resets CTRLA.
Il CTRLB = 0 Exit SSE command when specified supervisory event has been detected without returning to SD command. SSE logic clears CTRL A&B.
When the port type is a trunk (and therefore DP signals are invol~ed), the break/make periods are defined by Argument 1 and Argument 2 and by Argument 3 and Argument 4~ respectively. The formats of these Arguments for specifying various times are shown in the table of Fig.'s 30A and 30B, respectively. T~ese Argument bits are decoded by DP make/break period decode logic 42014 as ~LgtS~
l ~
¦I two bit fields which set the Timer No. 1 value. Upon logic unit 42000 entering a DP sending mode, send ~P con-trol logic 42018 i sets the CF0 ~A-D) bit area of port communication subfield 33508, ¦! Fig. 2, to zero in order to set the pulsing (PL) relay. If the i Argu~ent 5 setting requests a polari-ty check, send TMF control ~ logic 42020 sets the CFl (A-D) bit area to "ones" to clear the I ~ reverse battery (RV) relay. Also, the supervision-in (SUPY-IN) signal from unit 38000 (or in the alternative, the SPI bit of supervision control subfiel~ 33510) is examined by polarity check logic 42006 for an "OFF-HOOK" condition. Send DP control logic 42018 operates to initiate outpulsing of the first digit.
When the port type is a TMF sender, the sending of a KP tone pulse may be selectively omitted by Argument. 1 being set to 1 and ~;Argument 2 belng set to 0. Send TMF control logic 42020 controls the on/off time via the mechanism of setting the CFl (A-D) bit area of subfield 33501. The on--time and off-time for digits is 68 milliseconds "on" and 68 mil:Liseconds "off". The KP tone is held on for lOQ milliseconds. The two of six tones for each digit or code of the TMF signalling system are enabled by RD/SD
functional logic unit 45000 as will be described in subdivisions , of this division III. Briefly, logic unit 45000 contains the "second read7' access registers and the encoding logic required to implement this operation using the CS0-CS7 bits of port communica-l tion subfield 33501. (A "second read" of port data storage device¦
33000 is requested in order to get the next digit to be sent from digit storage subfield 33516. This is the case with regards to both DP and TMF sending.) As will be described in detail in connection with RDjSD logic unit 45000, as each digit is sent, the digit counter (DCT) bit ¦ area of subfield 33516 is incremented and the value in the DCT
bit area at the time of the "second read" acts as a "pointer" to - ~ \

l) specify which digit in subfield 33516 is to be transferred to the pulse count (PCT) bit area of subfield 33516. Thus the digit contained in the PCT bit area is either decremented once for each i pulse when sending DP, or con~erted to one of the TMF two-of-six : ¦I code~ by a BCD-to-two-of-six encoder for TMF sending in RD/SD

'I! logic u~lit 45000.

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I .

R, ~ L r~A~
Receive digits ~RD) functional logic unit 44000 converts j race~ved dial pulse (DP) signals, dual--tone multifrequency (DTMF) I¦ signals, and toll multifrequency (TMF) supervision signals to a I 4-bit binary code format representing the digit received. The l digits are stored in the order in which they are received in digit storage subfield 33516 of the port data storage field 33500, Fig. 2, assigned for -the port at which the signals are received.
Event codes are generated requesting processor action if logic unit 44000 detects any of: (i) a dig~t count greater than or equal to the digit count expected, (ii) critical timeout, (iii) interdigital timeoutS (iv) ST received, or (v) overdial.
~' .

: , I
` ~ 2. Structure and Operation of Unit 44000 Referring now to Fig. 95, port type steering logic 44022 monitors the port type signals received from common functional logic unit 36000 and the combinatorial logic state (CLS). The CLS is held in a register 44001 and decoded by decoder 44002 Logic 44022 monitors these signals to enable either line or trunk ¦, functions or to enable tone receiver functions.

! ~D start function logic 44025 is controlled by the Argument 1 bit area of subfield 33502. When Argument 1 = 0 the supervisory input(SUPY IN) signal from SSE/TSE/supplement to common logic unit 38000 is monitored. After a 64-millisecond off-hook period is timed by Timer ~2 (38016 of Fig. 91) of SSE/TSE/supplement to common logic unit 38000, the pulse count (PCT) bit area of digit storage subfield 33516 is cleared b~ lo~ic 44025. Timer ~1 up-dates logic 44026, initializes the interdigital timing function to the value specified by Argument 3, and the contents of the digit ~l ;

¦! count (DCT) bit area of subfield 33512.
When Argument 1 = 1 and the por-t type is a line, RD start , ~unction logic 44025 omits the seizure detection (i.e., detection of an off-hook condition for a 64-millisecond period).
i¦ ~If -the port type is a trunk and Argument 1 = 1, a wir~ of : ¦! 160 milliseconds is sent out by logic 44025 by means of buses ¦! WCF0 and WCFl.
~ When a KP character (indicating the start of digits) is ; 1, detected on a TMF receiver port, the digit count (DCT) bit area of digit storage subfield 33516 is set to 0 by an OR gate 44027 ,~ in preparation for the rac~ing of incoming digits, When Argument 2 = 1 the critical timeout (CTO) function is ;~ enabled by Timer ~2 update logic 44028. If Argument 4 = 0, the : critical timing is 3.5 seconds~ If Argument 4 = 1 the timeout ' period is set for 5.5 seconds. Comparator 44030 performs the jl detection of the critical timeout, starting at the digit defined i I
by the Argument 5 bit area of subfield 33502~ when that digit has ' been racked in subfield 33516 and Argument 2 = 1. When Argument 5 = 15, critical timing is performed on all digits. If the next ; dial pulse or digit is not received within the time specified by Argument 5~ the critical timeout event code is initiated by Timer #2 (380169 Fig. 91) in SSE/TSE/supplement to common logic !. unit 38000. . I
As previously mentioned, Timer #1 update logic 44026 presets !
the interdigi-tal timing period to the value specified by Argument ¦
3 and the contents of the digit count (DCT) bit area of subfield 33516 logic 44026 sets Timer #1 for 27 seconds if Argument 3 - 0. j If Argument 3 = 1 and DCT = 0, the Timer is set for 13 seconds.
I~ Argument 3 = 1 and DCT = ~, the Timer is set for 7 seconds.
Interdigital timing begins when the digit is present in the PCT
bit area. If the next digit is not received within the inter-digital time specified, generation of the interdigital timeout Il :

I' event code is initiated by Timer #1 (38014, Fig. 91) of SSE/TSE/supplement to common logic unit 36000.
The Argument 6 bit area indicates the digits expected (DEX), which is the number of digits which logic unit 44000 will process bef~re comparator 44032 initiates the generation of the DCT _ DEX
event code to thereby evoke operation of call control program 56002. Each time a digit is racked, the DCT is incremented one count. When the DCT count is equal to or greater than the expected digit count (DF.X), the event code DCT ~ DEX is initiated ~ by comparator 44032 and generated by common functional logic - unit 36000~ If Argument 6 = 0, the DCT _ DEX event code is initiated and generated after the next DP or tone, by a jump to , the appropriate CLS.
,' When logic unit 44000 is operating in its dial pulse (DP) ., mode and more than 15 on-hook pulse intervals are detected after the last interdigital period, an overdial event code is generated by common logic unit 36000 by a jump to the appropriate CLS.
When the port type is a TMF receiver, the ST receive event code is generated when the ST code is detected. The ST code i5 racked as a digit in the digit storage bit area pointed to by the ' DCT.
The tables of Fig.'s 33A, 33B, and 33C show the formats of Arguments 1-6 for selecting the various functions provided by glC unit 44000.

~_ -2~a-1145~
l l, ! s. ~
, Z

`` ¦ Receive digits/send digits (RD/SD) functional logic unit ¦ 4500~ decodes DTMF and TMF codes into a 4-binary format. The unit also converts from 4 bit binary f`ormat to two-of-six code for TMF sending. Latches within unit 45000 temporarily store the contents of the digit storage bit areas of digit storage subfield ¦i 33516 of the port data memory field 33500, Fig. 2, assigned to the port at which the digits are being manipulated. The digit bit areas each comprise 4 bits which are accessible through an I addressing mechanism employing digit count (DCT) logic cont~ined 1 in unit 45000. Up to 16 4-bit digits are accommodated by the i di~it storage bit areas o~ subf`ield 33516.
, RD/SD logic unit 45000 is employed on a shared basis with either send digits (SD) functional logic unit 42000 or receive j!
digits (RD) functional logic unit 44000. During the operation o~ SD unit 42000 or RD unit 44000, as the case may be, the 64 bits constituting the digit storage bit areas of digit storage subfield 33516 are loaded into a 64-bit storage register 45002, Fig. 96. This occurs at the point in the RD or SD sequence at which a second read of port data storage device 33000 is requested~
1, I
2. Descri tion of the Structure_and c~erat~9sL5D~3~ }~ L-~2 When RD/SD logic unit 45000 is operating in conjunction with RD logic unit 44000, the settings of` slow sense bit locations SSl-SS6 are converted into 4-bit binary code by either a DTMF-to-4-bit decoder 45004 or a TMF-to-4 bit decoder 45006, depending upon the port type. The 4-bit code representing a digit is stored in the digit position of the digit storage area of digit storage subfield ~3516 which i9 indicated by the value of digit counter .~ i ~ 5i~
,, (the DCT bit area of subfield 45016). This value is held in a ' DCT register/counter 4500~.
The DCT is set to ~ at the beginning of a sequence of opera-tion of RD logic unit 44000 and is incremented once for each ~ ¦¦ digi~ received. If the port is receiving dial pulse (DP) rather - ¦~ than tone signals, the pulses are used to increment the pulse I!
count (PCT), which is then loaded into the digit storage area i, ~pecified (i.e., "pointed to") by the DCT value. The PCT is reset at the time the command code for a receive digits (RD) operation initiates the RD logic unit 44000, and then after each transfer ~ its contents into digit storage portion of storage subfield 33516.

3. S-rurt~_e ~ ~ O~eration of Unit 45000 in Coniurction With ; ~b~_5~ Y~ L_~a h~ y~it 42000 When send digits (SD) functional logic unit 42000 is operat-ing in response to presence of the send digits (SD) code in the CMD bit area of port command subfield 33502, the value in the DCT
bit area of digit storage subfield 33516 is used as a pointer which addresses a digit multiplexer 45010 at the output of digit storage register 45002. This allows the indicated four bits of the 64-bit digit storage area to be transferred into pulse count (PCT) register/counter 45012. If the port is a TMF sender, the PCT value is then encoded from 4-bit binary code, which represents a digit or control symbol, into a two-of-six code by encoder 45014. This code sets slow control bit location CSl through CS6 for TMF sending.
When the port is a trunk, dial pulse (DP) sending is per- ' formed using the contents of the PCT register/counter 45012, which represents the digit to be sent. When the PCT reaches zero, indicating the DP outpulsing for that digit is complete, the interdigital timing is started, The next digit is loaded into the ! `` ` `
I .
5~9 PCT bit area of subfield 33516, and the digit count (DCT) is incremented using the digit clock signal7 DCTCK, from SD function-i al logic unit 42000.
, The value in PCT is decremented once for each dial pulse (DP~
¦ cycl~ by the decrement PCT signal from SD unit 42000. When the ¦ PCT reaches zero, indicating the DP outpulsing for that digit is . ¦ complete, interdigital timing is started.
The next digit is loaded into PCT bit area, and DCT is incremented by the signal from SD unit 42000. _ _ _ DEIVIANDES OU BREVETS VOLUMIINEUX

LA PRÉSENTE PAP~TIE DE C:ETTE DEE~IANI:9E 013 C:E E~REVET
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SECI EST LE TOME / DE ~

NOTE: Pour les tomes adlditionels, veuillez con~acter le ~urGau canadien des breve~s . ` LL ~ ~ 6 --i-q ----~

- - ~UMIBO APPLllle~ A-~ENTS -` - _ .

TIIIS SECTIOIU OIF THE APPLICATION/PATEIUT C~ NTAII~IS l\llORE
THAN ONE VOLUME

THIS IS Vg:~LUME ~ OF Z~

NOTE: For additional volumes please contact ~he Canadian Patent Uffice

Claims (22)

The embodiments of the invention in which an exclu-sive property or privilege is claimed are defined as follows:

1. A telephone switching system for interconnect-ing plural telephone lines, said system comprising:
A. a plurality of port means each of which con-nects to a telephone line, each said port means transferring, to and from its corres-ponding telephone line, information in the form of supervisory signals representing te-lephone line conditions and other signals representing intelligence, B. port storage means for storing a plurality of port status information items represent-ing different conditions for each said port means and its corresponding telephone line, C. port event processing means connected to said port storage means for altering certain of said port status information items in said port storage means in response to oth-er port status information items, D. switching means connected to each said port means and to said port storage means for selectively establishing, i. signal paths that transfer the supervisory signals between said port storage means and each said port means thereby to control the operation of each said port means and, ii. signal paths that transfer the other signals representing intelligence between selected ones of said port means, and E. call processing means connected to i. said switching means to control the opera-tion of said switching means and, ii. said port storage means for altering port status information in said port storage means in response to other port status in-formation in accordance with a pre-deter-mined sequence of call progression steps thereby to control the operation of said port event processing means.

2. A telephone switching system as recited in claim 1 wherein the supervisory signals correspond to sense supervi-sory information and control supervisory information and said port storage means includes:
i. means for storing the sense supervisory in-formation, and ii. means for storing the control supervisory information, and each said port means includes:
i. monitoring means responsive to conditions on the telephone line for generating sense su-pervisory signals, and ii. control means for transferring signals onto the telephone line in response to control supervisory information signals, and said switching means includes:
i. sense data path means for transferring sense supervisory signals to said means for storing sense supervisory information for each said port means in response to conditions on the corresponding telephone line, and ii. control data path means for conveying, from said means for storing control supervisory information to each said port means, control supervisory signals that control the state of the said control means signals.

3. A telephone switching system as recited in claim 2 wherein said port event processing means includes:
i. timing means for generating a sequence of timing signals.
ii. control means connected to said timing means and to said port storage means for selectively transferring port status information to and from said port storage means, and iii. processing means connected to said timing means, said control means and said port stor-age means for processing port status infor-mation that includes the sense supervisory information and control supervisory informa-tion, said processing occurring for each said port means in a sequence established by the timing signals from said timing means.

4. A telephone switching system as recited in claim 3 wherein said system includes a plurality of port means organ-ized into at least one port group means, and wherein:
said port storage means includes:
i. storage means that store port status informa-tion for transfer as plural parallel signals, and ii. conversion means connected to said timing means, said storage means and said switching means for converting parallel signals received from said storage means into serial signals for transfer to said switching means, and said switching means includes i. means connected to said conversion means for combining the other signals representing in-telligence and the control supervisory signals in serial form from said conversion means for transfer to each said port means.

5. A telephone switching system as recited in claim 4 wherein said switching means also includes, for each said port group means:
i. receiver means connected to said combining means, and ii. routing means connected to said timing means, said receiving means and each said port means in said port group means for routing the con-trol supervisory signals to corresponding ones of the port means, and each said port means includes means for performing control func-tions in response to the control supervisory signals received from said routing means.

6. A telephone switching means as recited in claim 5 wherein said switching means further includes a plurality of switching circuit means each connected to a plurality of said port group means and each said switching circuit means includes means for combining the other signals representing intelligence and control supervisory signals for transfer to corresponding ones of said port group means connected thereto.

7. A telephone switching system as recited in claim 6 wherein said port storage means transfers signals in parallel form and wherein said port storage means includes:
i. means for generating at least one sense super-visory signal, and ii. means connected to said timing means and to said supervisory signal generating means for transferring these sense supervisory signals from each port means to said switching means in a time sequence, and said switching means includes, for each said port group means:
i. receiving means connected to each said port means in said port group means for transmit-ting binary signals in serial form represent-ing the sense supervisory signals from each said port and the other signals representing intelligence from each said port means in response to signals received from said port means, and ii. separation means connected to at least one of said receiving means for separating the sig-nals representing intelligence and the sense supervisory signals, and said port storage means includes conversion means connected to said separation means, said timing means and said port storage means for transferring sense supervisory signals in parallel to said sense supervisory signals storage means in said port storage means in response to the timing signals and the sense supervisory signals received serially from said separation means.

8. A telephone switching system as recited in claim 7 wherein said call processing means establishes parameters for controlling the operation of said port event processing means wherein:
said call processing means includes means for transferring the parameters to said port storage means, said port storage means includes a parameter storage for storing the parameters from said call processing means independently for each said port means, and said port event processing means further includes processor control means connected to said transfer control means and said processing means for receiving, independently for each said port means, the parameters thereby to control the operation of said processing means.

9. A telephone switching system as recited in claim 8 wherein the parameters transferred from said call processing means to said port storage means include commands to identify one of a plurality of processing functions and wherein said processing means in said port event processing means performs a first processing function, said port event processing means further including:
i. a second function processing means connected to said timing means and to said port storage means for performing a second processing function and, ii. selection means connected to said timing and control means and to said port storage means for selectively activating said first or se-cond function processing means in response to the commands retrieved from said port storage means.

10. A telephone switching system as recited in claim 9 wherein at least one said port means includes ringing means responsive to first control supervisory signals for transmitting a ringing signal onto the line, and said call processing means is adapted to transfer to said port storage means parameters including a ringing command and wherein one of said processing means in said port event processing means controls ringing func-tions, said ringing function processing means including:
a. ringing signal generating means for generating the first control supervisory signals for transfer to a said port means thereby to con-trol ringing, and b. ring trip means for transferring to said port storage means status information indicating that the line being rung has been answered in response to sense supervisory signals from the port means, said call processing means re-sponding to said ring trip means status information by progressing to another call progression state.

11. A telephone switching system as recited in claim 10 wherein a telephone line connected to a port means includes first and second conductors and said call processing means transfers to said port storage means parameters identifying which of the first and second telephone conductors is to receive the ringing signal and ring phasing information as other para-meters with the ringing command, said ringing signal generating means in said ringing function processing means including:
A. ringing control logic means for generating the first control supervisory signals, B. ring phase selection means responsive to the phasing information for phasing parameters for controlling the ringing signal timing, and C. control register means responsive to the con-ductor identification parameter for identifying to said ringing control logic means the con-ductor over which the ringing signal is to be transferred, said ringing control logic means generating second control supervisory signals for identifying the conductor in said port means including means responsive to the second control supervisory signals for selectively routing the ringing signal to the identified one of said first and second conductors of the telephone line.

12. A telephone switching system as recited in claim 9 wherein one of said port event processing means includes a supervisory signal processing means, and said parameters trans-mitted to said storage means include timing information, said supervisory signal processing means including:
A. sense supervisory signal means, B. control supervisory signal transmitting means, and C. timing means for generating timing signals in response to the timing parameters, said sense supervisory signal means and control supervisory signal transmitting means being responsive to said timing means.

13. A telephone switching system as recited in claim 12 wherein said sense supervisory signal means includes filter means for generating a supervisory input signal in response to processing of a succession of said sense supervisory signals.

14. A telephone switching system as recited in claim 13 wherein said port storage means includes means for recording successive input values of said filtered supervisory input sig-nals, and said filter means includes means for altering the contents of said storage areas, said filter means responding to the input values in said storage areas for generating the super visory input signal.

15. A telephone switching system as recited in claim 12 wherein said timing means includes first and second timers and means for controlling the operation of said first and se-cond timers in response to the timing parameters.

16. A telephone switching system as recited in claim 15 additionally comprising means for connecting said first and second timers to others of said function processing means in said port event processing means.

17. A telephone switching system as recited in claim 12 wherein said port storage means includes a seizure signal storage area and said sense supervisory signal means includes means for transferring to said port storage means a seizure sig-nal in response to the supervisory input signals.

18. A telephone switching system as recited in claim 17 wherein said port storage means includes a release control storage area that receives a release timing information from said call processing means and the supervisory input signal indicates whether the corresponding telephone line is charact-erized by an on-hook or an off-hook condition, said port event processing means further including release timing means connected to said sense supervisory signal means and release control stor-age means for generating a release signal when the supervisory signals indicate an on-hook condition for a predetermined time interval after the telephone line is seized.

19. A telephone switching system as recited in claim 9 wherein said call processing means can initiate as a call pro-gression step a send digits function wherein specified digits are transferred to a said port means, said port means including means for converting control supervisory signals from said port storage means into a sequence of signals that are transmitted onto the line and that correspond to the specified digits and said port storage means including digit storage means for stor-ing the digits from said call processing means and wherein one of said processing means in said port event processing means is a send digits processing means that generates control super-visory signals in response to the digits and that includes:
i. send digit transfer means connected to said timing means and said port storage means for retrieving from said digit storage means all the digits in the number in response certain of the timing signals, and ii. digit encoding means connected to said send digit transfer means and said timing means for generating the control supervisory signals in response to the digits in said port storage means and others of the timing signals.

20. A telephone switching system as recited in claim 19 wherein said port storage means includes a pulse count stor-age means for storing a dial pulse count for each digit in the telephone number in sequence and digit count storage means for storing a digit count that identifies the position of each digit in sequence and wherein said send digit transfer means includes:
a. digit register means connected to said digit storage means in said port storage means and said timing means for receiving information from said digit storage means in response to the certain timing signals, b. digit counting means connected to said port storage means, said digit encoding means and said timing means for altering a digit count from said digit count storage means each time a digit is transmitted, c. pulse counting means connected to said digit register means, said digit counting means and said digit encoding means for altering a digit value for a selected digit in said digit regi-ster means in response to the digit information signals, and d. means connected to said pulse counting means, said digit counting means and said timing means for transferring to said control supervisory signal storage means in said port storage means first control supervisory signals that corres-pond to the signals to be transferred onto the telephone line for each successive digit.

21. A telephone switching system as recited in claim 9 wherein said call processing means can initiate as a call pro-gression step a receive digits function wherein digits are trans-ferred from a said port means to said port storage means, said port means converts incoming signals representing digits in a telephone number into sense supervisory signals, and said port storage means includes digit storage means for storing the digits and wherein one of said processing means in said port event processing means includes a receive digits processing means that includes:
i. decoding means connected to said timing means and to said sense supervisory signal storage means in said port storage means for genera-ting digit information signals in response to the port status information and certain of the timing signals, and ii. digit transfer means connected to said timing means, said port storage means and said de-coding means for transferring to said digit storage means in said port storage means all the digits in the telephone number in re-ponse to the digit information signals and others of the timing signals.

22. A telephone switching system as recited in claim 21 wherein said port means converts signals representing an in-coming telephone number into first sense supervisory signals and wherein said port storage means includes pulse count storage means for storing a pulse count for each digit in the telephone number in sequence and digit count storage means for storing a digit count that identifies the position of each digit in se-quence and wherein said digit transfer means includes:
a. digit register means connected to said digit storage means in said port storage means and said timing means for receiving information from said digit storage means in response to the certain timing signals, b. digit counting means connected to said port storage means, said digit decoding means and said timing means for altering a digit count from said digit count storage means in re-sponse to the digit information signals, c. pulse counting means connected to said digit register means, said digit counting means and said digit decoding means for altering a digit value for a selected digit in said digit re-gister means in response to the digit infor-mation signals, and d. means connected to said pulse counting means, said digit counting means and said timing means for transferring to said digit storage means in said port storage means the number of dial pulses in each successive digit in response to the other timing signals.