CA1143470A - Digital control apparatus - Google Patents

Abstract

DIGITAL CONTROL APPARATUS

ABSTRACT OF THE DISCLOSURE

Disclosed is a decision making control circuit responsive to a digital data stream. A control output is provided in response to detection of a predetermined number of successive digital words in the data stream representing numbers having a magnitude greater than a threshold magnitude. Once the control output is provided, a predetermined number of successive words in the data stream must have a magnitude less than the threshold magnitude to terminate the control output.

Description

DIGITAL CONTROL APPARATUS
. . _ _ This application is a division of Canadian pa-tent application Serial No. 303,461 filed May 16, 1978.

BACKGROUND OE' THE INVENT~ON

This invention relates to recorcling systems and more particularly to a recording system for recording transduced electrical signals on a recording medium w.ith a recording apparatus having a mode of operation responsive to the transduced electrical signals. Even more specifically, this invention is directed to systems for recording dictation. With respect to such a recording system, it is known in the art to use a detection and control apparatus for initiating and terminating the recording mode of operation of a recording apparatus in response to the presence or absence of sound generated electrical signals so that the recording apparatus is in the recording mode of operation only when there is ~0 0 , , 1 -- ..

~ 7 dictation to ~e recorded.
The detection ancl control apparatus stacts the recording mode of operation of the recorclinc~ apparatus in response to sound generated electrical signals and terminates the recordin~ mode of operation of the recording a~paratus in response to the absenee of sound generated electrical signals for a predetermined length of time. A
detection and control apparatus is particularly useful in a recording system in whieh the source of the sound to be reeorded is an individual who wishes to reeord dictation and ~ho is remote from the recording apparatus with no means for eontrolling the recording mode of operation of the recording apparatus other than the sound of his voice and resulting sound generated electrical signals~
h diffieulty which has been encountered in the use of a deteetion and eontrol apparatus in a reeording systèm is that the recording apparatus is not instantaneously plaeed in a reeording mocle of opera~ion upon :the initial deteetion of sound generated electrical signals b~ the deteetion and control apparatus. Therefore, the recording apparatus is not operating in the recording mode OL operation when sound, such as the voiee of a dietator, initially reaches the recording apparatus to be recorded as sound generated electrieal signals. Thus, some of the soundr sueh as dietation, to be recorded is lost.
In order to solve this problem some prior art recorAing systems have use~ a sup~lementary reeording device as a stage in the transmission oE the sound gen~ratecl electrieal signals to the recording ap~aratus.

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¦¦ This supplementary cecording device records the initial ¦ so~lnd and all subsequent sound as sound generated electrical signals and plays the sound generated signals back after a time delay to the recordiny apparatus for recording by the recording apparatus. The length of this time delay is determined by the length of tlme needed for the re~ording apparatus to be placed in ~he recording mode of operation by the detection and control apparatus after detection of the initial sound generated electrical signals by the detection and control apparatus. Once placed in the recording mode of operation by the detection and control apparatus, the recording apparatus receives and records the delayed initial sound generated electrical signals and all subsequent si~nals from the supplementary recording device until sound generated electrical signals have ceased for a predetermined length of time to cause the detection and control ap~aratus to terminate the recording mode of operation of the recording apparatus.

A recording system having a continuous loo~
recording device as a supplementary recording device is an example of a prior art recording system which uses a supplem~ntary recording device. The continuous loop recording device has a recording head and a playback head positioned along a continuous loop of a recording medium, such as tape. The distance between the heads is such that the period oE time required for the transit of the tape from the recordin9 head to the playback head provides the time dela~ required for a detection and control apparatus to place the recording ap~aratus in the recording mode of Il - 3 -operation.
The c1isadvantages oF this and other prior art recording systerns using supplement~ry reco~ding devices are in the inherent risk of a mechanical failure or of tape brea'~age in the supplementary recording device. ~iloreo-~Jer, the duplication oE recording required the duplication of costly components in the supplementary recording device and in the recording apparatus and additional space to accor~r.odate both the supple~entary recording device and the recording apparatus. Furthermore, gradual degradation of the signal in the process of recording, playing back, and re-recor~ing sound generated electrical signals in~roduces a substantial amount of distortion into the final desired recording of sound by a recording apparatus and thereby dir~inishes the quality of the recording.
In an eEfort to solve some of the proble~s encountered with prior art recording systems using supplementary recording de~ices, the prior art has also used an analog shift register in a recording system for delaying sound generated electrical signals in their trans~ission to a recording apparatus. While this recording system avoids some of the problems of cost and size encountered with prior art recordlng systems using supplementary recording devices, as well a~ the problerns oE
tape breakage or rnechanical failure, this prior art recording system still causes a gradual degradation oE the sound generated electrical si~nals to be recorded by a recording apparatus and thereby diminishes the quality of the recording.

This diminution in the quality of the recording is unavoidable because the sound generated elec-trical signals are analog signals and because distortion of an analog signal usually occurs when an analog signal is amplified and processed through an analog shi~t register to provide a time delay.
Moreover, the infinite variety of distinct analog wave forms in an analog signal generated by sound such as human speech precludes any reconstruction of -the analog signal after it has been passed through the shift register.
Therefore, the quality of the recording is irretrievably lost after distortion in an analog shift register.
The invention disclosed herein solves this problem of distortion by gradual signal degradation and other problems encountered in prior art recording systems having a detection and control apparatus to control the recording mode of operation of a recording apparatus so that the recording apparatus is in the recording mode of operation when there is sound to be recorded.
SUMMARY OF THE INVENTION
The invention disclosed herein is a recording system which has a time delay device that delays the transmission of sound to be recorded by a recording apparatus until the recording apparatus has been placed in a recording mode of operation by a detection and control apparatus in response to the presence of sound to be recorded. However, it has neither the inherent disadvantages of recording systems which use supplemen-tary recording devices nor the distortion caused by gradual signal degradation as in prior art recording systems in which the sound generated signal is recorded, played back, and re-recorded or amplified and processed through an analog shift register to obtain a time delay.
This improvement in recording systems is provided by a

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recording system having a time delay device which converts sound generated electrical slgnals from analog signals into digital signals for processing through a d,igital signal delay device to a recording apparatus that has been placed in a recording mode of operation by a detection and control apparatus prior to the end of the time delay provided by the time delay device.
Depending upon the embodiment of the invention, the detection and control apparatus is responsive to the presence or absence of sound generated electrical signals as in prior art recording systems or is responsive to the presence or absence of digital signals generated in -the present system. The latter improvement provides a more reliable detector of human speech and control of the recording mode of operation of the recording apparatus than has been achieved in prior art recording devices~
Moreover, depending upon the embodiment of the invention, the invention provides for the recordiny by a recording apparatus of the transduced electrical signals on a recording medium either as analog signals which are substantially identical to the sound generated electrical signals or as digital signals that can be subsequently converted into analog signals which are substantially identical to the sound generated electrical slgnals. However, regardless of the embodiment o~ the invention, the invention provides a recording system in which there is substantially less dis-tortion of sound generated electrical signals to be recorded by a recording apparatus than in prior art recording systems. This :is because digital siynals are easily restored and reconstruc-ted since each bit of digital information possesses either one of two values.
Thus, circuit elements in, the time delay device are ahle to accurately amplify or reproduce the digital signals and to accurately reconvert them into -the analog siynals which the 3~
dlgital signals had accurately approximated for recording by the recording apparatus.
In this divisional application the invention comprehends a digital detection and control apparatus selectively responsive to digital input signals. I'he apparatus comprises a digital magnitude comparison means, a first counting means and a second counting means. The magnitude comparison means is responsive to the digital input signals, and detects digital input signals of a magnitude greater than a predetermined magnitude. The first counting means is responsive to the comparison means, and provides a control output in response to each occurrence of a first predetermined number of contiguous ones of the digital input signals greater than the predetermined ~agnitude. The second counting means is also responsive to the comparison means, and terminates the control output in response to each occurrence of a second predetermined number of contiguous ones of the digital input signals less than or equal -to the predetermined magnitude.
DESCRIPTION OF THE DRAWINGS
These and other features and advantages of the present invention will be more clearly understood upon consideration of the following specification and accompanying drawings in which:
Fig. 1 is a block diagram of an embodiment of the invention in which the recording apparatus records transduced analog electrical signals on a recording medium and in which the detection and control apparatus is responsive to the sound generated electrical signals prior to such signals entering the time delay device;
Fig. 2 is a block diagram of an embodiment of the invention in which the recording apparatus records transduced digital electrical signals on a recording medium and in which the detection and control apparatus is ~ 3~

¦I fesponsive to digital signals from the time delay device;
¦ Fig. 3 is a block diagram o~ an embodiment oE the ¦ invention in which the recordin~ apparatus records ¦ transduced analog electrical signals on a recording medi~lm ¦ and in which the detection and control apparatus is ¦ responsive to digital signals rom the time delay device;
¦ Fig. 4 is a schematic diagram of the analog to ¦ digital converter in those embodiments of the inventio~
¦ shown in Figs. 1, 2, and 3;
¦ Fi~. 5A is a graphic representation of the sound ¦ generated electrical signals as they enter the analog to l digital converter of Fig. ~;
¦ Fig. 5B is a graphic representation of the stepped analog signal provided within the analog to digital ¦ converter of Fig. g in response to the sound generated electrical signal of Fig. 5A;
Fig. 5C is a graphic representation of the operation o~ the successive approximation register in the I analog to di~ital converter of Fig. 4 and shows the 1 digital approximation of a voltage level corresponding to I ¦ the stepped analog signal that is shown between the points A and B on the time axis of Fig. 5B and that corresponds to ¦ the sound yenerated electrical signal shown bet~een points A and B on the time ~xis o~ Fig. 5A; and ¦ Fig. 6 is a block diagram oE the digital detection and control apparatus in that embodiment of the ~ inventiorl shown in Fig. 2 and 3.

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D~`T~,~IIED DESCP~IDTIo~l C~ THE EL130~ ,TS
, In the follo:~ing description of several ¦ em~odi~Qnts oE the invention, the invention is embodied in ¦ a recording system for recording souncl such as the I ~ictation of a dictator including a recordiny appara~us ll ¦ which is placed and maintained in a recording mode of ¦ operation by a detection and con~rol apparatus while there ¦ is sound to be recorded. However, it ~ill be understood that the invention may ~e embodied in other forms and in ' particular, it will be understood that the invention is not limited only to those recording syste~s described herein.
Rather~ the invention may be embodied in recording systems which record any form oE electrical signal whether initiaIly generated by a sound or not.
~loreover, it may be em~odied in a recording system ~7hich does no~ inclucle a detection and control apparatus and in which the time delay device disclosed herein serves only to improve the quality of the sound to be recorded by a recording apparatus ll.
This will be better understood ~rom a consi-deration of Fig. l which is a block diagram of a recordin~
system that embodies the invention disclosed herein. The recording system includes a recorc1ing apparatus ll which may be any conventional recording apparatus for recording ~sound as transduced sound generated analo~ or digital electrical signals on a recordin~ mediuM such as a ta~e or disc, an audio converter 2 ~hich may be any conventional transducer such as a microphone for converting the sound ~ into sound generated electrical s1gnals ~hich are analog ¦ signalsr a varia~le amplifier 3, a 1QW PaSS filter I
. l _ g _ ~3~ 1 1, f 4, an analog to digital convertec 6 for converting analog siqnals to di~ital sign31s, a digital signal ~elay device , ~, a digital to analog converter 8 for converting diqital signals to analoy signals, a low pass ~ilter 9, and a detection and control apparatus 10.
i As will be set forth more fully below, the ¦ purpo~e of the digital signal delay device 7 is to provide l a means for delaying or storing a digital signal for a .~ desired period of time after it has been generated by the 1 analog to digital converter 6 and before ~ransmitting it to ¦ the recording apparatus 11~ Thus, any digital hardt~are ¦ device or programmed digital device which will perform this :function by delaying or storing the digital signal for a desired period o:E time is a digital signal delay means . within the definition of the present invention. While the : I di~ital signal delay device 7 described in the present : ¦ embodirnent of the invention is a shiEt register~ it is : I further disclosed that an alternative embocliment of this ¦ invention may include a random access memory. In that I embodiment, the random access memory receives the ¦ successive digital slgnals from the analog to digital : ¦ converter 6 and stores the digital signals for a desired period o~ time after which the digital signals are I successively retrieved from the random access memory in the sequenc2 stored and transmitted to the recordincJ apparatus 11.
It will also b~ understood that the recording apparatus 11 may be any conventiorlal recording apparatus ~¦ for recording transd~lcecl ana].o~ or dig;tal electrical I' i~
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I signals or! a recording medillTn such as a tape or disc.
Inas~uch as the presellt invention pro~ides for convert;ng sound generated analog electrical signals into digital signal appro~imations ~f the sc)und generate(l analog electrical signals~ ~he signals are placed in conciition for I recording by a recorder adapted foc recording sound on a ¦ recording medium as transduced ~igital electeical signals.
The present invention also provides for reconverting the I digital signal approximations oE the sound generated analog l electrical signals into analoc3 electcical signals aEter ¦ said digital signals have been delayed by the digital signal delay device 7. The recon~erted analog electrical signals are then in condition for recording by a recorder adapted for recording sound o~ a recording m~dium as transduced analog electrical signals. The recording l apparatus adapted for recor~ing sound on a recording medium I ¦ as transduced digital electrical signals may be distinct rom a recording apparatus adapted Eor recording sound on a recording medium as transduced analog electrical signals;
however, the recording apparatus may also be ~adapted for recording sound on a recording medium both as transduced analog or electr;cal digital signals. Therefore, in the recording system of the present inve1ltiorl, the recorcling ¦ apparatus 11 is not limited only to recordincJ a2paratus ¦ adapted solely for recor~ing sound on a recording meclium as either transduced digital electrical signals or as transducecl analog electeical sic3nals, but is reEerred to as the recording apparatus 11 without furtner lim;tation.
11 In the embodime~t of the invention sho~n in ~ig.
30 ~1l ., I .
I, 1 1 '~ ' ' :' l, the sound to be eecorc1e(1 is the voice of a ~erson W~10 wishes to recorcl dictatior1 arld it will b~ u;1ders~ood that the sound generated electrical signals ~rom the audio converter 2 are in the auclio frequency range. In the embodi~ent of the invention shown in Fig. 1, as well as in the embodiments of the invention shown in Figs~ 2 an~ 3, the variable am~lifier 3, ~he low pass iltec 4, the analo~
to digital converter 6, ana the digital delay dewice 7 provide a time delay device D for causing the sound generated electrical signals from the audio converter 2 to reach the recording apparatus ll a predetermined length oE
time aEter the detection and control a~paratus lO or 30 has placed the recording apparatus ll in a recording mode of operation~ In the particular embodiment of the ~nvention sho~n in FigO l~ the detection and control apparatus lO is responsive to the so-1nd generated electrical signals fro~
audio converter 2r and as a result, the detection and control apparatus lO may be a conventional voice operated relay which operates the recording apparatus in conventional manner to cause the recordin~ apparatus ll to be placed in a recording mode of operation in response to the initial sound generat~d electrical signals from the audio converter 2 and to continue in a recording mode oE
operation until there have been no sound generated electrical signals from the audio converter 2 for a predetermined length of time.
However, it will be understood that in all of the embodiments of the invention shown in Fi-3s. l, 2 and 3, the sound generated electrical signals ar~ transmitted to the ~ 12 ~

~3~7~ i varia`~lle ai~"~ f-icr ~ OL- the tim~ flelay df.?Vi.Ce D which is selective]y varied in conventional manner to adjust tile amplitude oE the sound gellerated electric.ll signals ~rom the audio converter 2 to compensAte Eor any loss of a.mplitu~e because oE ~he length of the line l betweerl the audio converter 2 and the time delay device.
Those s!~illed in the art will understand that the time delay device D need not include the variable amplifier 3 if the line l is relatively short so that line loss is minimal or if the sound generated electrical signals would otherwise be of sufficient amplitude for process;ng through the time delay device D as describe~
herein when they reach the low pass filter 4.
~ hether t~e time delay device D includes a variable ampli~ier or not, ~he low pass filter ~ operates in conventional manner to pass only those frequencies of the sound g~neeated electrical signals which can be accommodated by the subsequent analog to digital converter 6 without distortion from undersampling. Moreover, in recording systems such as those in Figs. l, 2 and 3 in wh;ch the so~nd to be recorded is the voice of a dictator the low pass filter 4 can be selected not to pass fre-quencies over 3kh~ so as to eliminate back~round noise.
~ rom Fig. 4, it will be seen that the analoq to di~ital converter 6 includes a s~itching means 41, such as a complementary metal oxicle semiconductor analog switch, for selectively passing electrical currents, which when mor~entarily operated will caUae the capacitance 42 to charcJe to a voltage correspond7n~1 to the amplitude of the !

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sound generated electrical signals from the lo./ p35S filter

4 at the time that the switching means 4~. is momenta~
operated. During the periodic intervals oE time in ~thich the switching means 41 is not operating to int~o2uce the sound genecated electrical si~nals from ~he low pass filter 4, the charge oE the ca~acitance 42 is maintained at a constant level of voltage.
Thus, it will be ~nderstood the switching means 41 and the capacitance 42 serve as a sampling means for 10 : providing successive samples of the sound generated ¦ electrical signals such as the sample S-l represented between points A and B in Fig. SA, It will also be un~erstood that the operation of the switc~in~ means 41 is regulated in conventional manner by the successive ~ ¦ approximation register 46 which causes the switclling means 1~ 41 to charge the capacitallce 42 with a new sample of the : I sound generated electrical signals each time the successive ¦ approximation register 46 ends an approximation cycle as l described below.
¦ It will be ~nderstood that when the cap3citance ¦ 42 is successively charged to voltages corresponding to ~ ¦ successive amplitudes of the sound electrical signals, the I ¦ sound generated electrical signals a~e changed fro~
continuous ~ave analog signals as shown in Fi~. 5A to stepped analog signals as shown in Fiq. 5R. For exampl~, the continuous wave analog signal o~ the sample S-l between points A and B in Fig. 5~ becomes in the capaci.tance ~2 the stepp~d analog signal S-2 between points A and B in Fig.
! 5B.

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1 The ste~p~d ~naloq represent~tiol~ sho~ in Fic~.

Ii sr~ is then convelted iYltO a series o~ di~ital signal~i in ¦I which each di~ital signal represen~s a binary number approYimating the voltage of a corresponding step in the stepped analog re~resentation of the sound gerlerated electrical signal. A successive appro~ima~ion register 46 performs this function. The binary appro~imation is achieved by serially com2aring each of the stepped analog ~ I voltages, suc'n as the signal S-2 at the capacitance 42, with successive analog conversions o~ digital si~nals genezated by the successive approximation register 46 as ¦ s~ccessi~e hinary approximations of the analog volta~e~
¦ The conversion of each of these digital signals into analog ~ voltages is accomplished by using a digital to analog ¦ converter 47 to convert the digital signals~ each oE w'nich represents a binary approximation oE the stepped analog ¦ voltage, to their corres~onding analog voltages, such as ¦ the voltage S-3' in Fig. 5C. The analog conversion of a binary approximation is then introduced into the comparator 1 44 and co.~pared with the stepped analog signal to be ¦ ap~ro:~imated.
¦ It will be understood that, dependin~ upon the ¦ output Erom the co~parator 44 after the compacison of the stepped analog signal S-2 and the analog voltage S-3' corresponding to the first binary appro~imation of the analog voltaye 5-2, the successive appro~imation register 46 will ma~e another digital approximation which is convertecl to its corres~ondin~ analog voltage S~3'' by the ~; digital to ana1og converter 47 ancl then s;milarly compared I, - 15 -3~

~ittl the stepped analog signal S-2. This process is cont.inued for a predetermined number oE approximcltions N
until the step~ed analog signal S-2 at the capacitance 42 has been accurately approximated as by the analog voltage S-3~ in ~ig. 5C.
I Those skilled in the art will understand that ¦ upon completion of the successive approxirnations necessac~
¦ to accurately approximate the stepped analog voltage S-2, I the successive approximation register 46 will have generated a digital signal, consisting oE a sequence o~
electrical bits, electrically representing a ~inary nu~ber.
~oreover, they will also understand that the digital signal i corresponding to the analog voltage S-3N in Fig. 5C
represents a binary number which accurately corresponds to I the stepped analog voltage S 2 of Fig~ 5B which in turn I I corresponds to the sound generated electrical signal S-l of ~ Fig. 5A.
: ¦ It will also be understood that upon completion ¦ of the predetermined number oE approximations by the I successive approximation register 46, the successive approximation register 47 provides an end of cycle (EOC) output. The EOC output causes the sequence of electrical bits representing the binary number S-3W to be transerred from the successive appro~imation register 47 into the digital signal delay device 7. It also causes the switch 41 to close and charge the capacitor 42 to another stepped analog voltage such as that between points B and C in Fig.
5B.
ll Thus, the successive operat.ion of analog to 1, ~ - 15 -~3~
dic~ital convelter- 6 as clescribed a~o~ r~C;~Ilts in the sound gener~t~ lectrical sicJnals from the lo~"~ pasC.; filter ~
beirlg cha.,gecl from continuous ~a~e analog signals as sho~n in E~ig. 5.~ to a series of digital signals, e~ch consisting of of a sequence of electrical bi ts repLesentin~ a binary number. Those skilled in the art will understand that the accuracy with which these digital signals represent the sound generated electrical signals from the low pass filter 4 deDends upon the rate at which th~ sound generated electrical signals are sampled by the sampling means pro~ided by the switching ~eans 41 and the capacitance 42.
In the presently described embodiment, this sampling rate is in turn determined by the rate at wh;ch the successive appro~imation register 46 com~letes its predetermined num~er of approximations and provides an.EOC output to the s~itching means ~1. This rate of appcoximation completion is controllec3 by the frequency oE a cloc~ oscillator 45 and by the predetermined number of approximations N made by the successive approximation register 46.
Thus, in the analog to digital converter 6 as show~ in ~ig. 4, the clock oscillator 45 has a 100 khz frequency and the predetermined number oE approximations N
made by the successive approximation register 46 in response to the clock oscillator is nine followed by an EOC
o~tput to the switching means 41 and the simultaneous trans~er to the shift register 7 of the digital signal corresponding to the ninth approY~imation. As a result, the sampling rate at which the switchincJ means 41 is operated to sa~.ple the sound generated electrical signals from l, ~4~7 Il.
the low pass filter ~ is 10 khz. I~he s~mpling rate must he chosen to be at least twice as great as the highest ¦ frequency analog electrical signal to he approximated.
From this sampling rate, it will be readily understood by those skilled in the art ~hat Figs. 5A, 5B
¦ and 5C are merely illustrative since this rate causes the time be~ween the points A and B on the time lines in these figures to be only l/lOOOOth of a second and the ¦ fcequencies of sound generated electrical signals admitted ¦ through the low pass filter 4 is 3~hz or less. The period of the signals is therefore a'c least three times the period ¦ of each sample. Fig. 5A is merely illustrative of the ¦ technique and the sampling rate is exaggerated. Moreover, ¦ it will be readily understood that at this rate and at other rates which ~Yill be apparent to those skilled in the ¦ art, the digital signals from the successive approximation ¦ register 46 will accu~ately represent the sound generated electcical signals for the low pass filter 4.
¦ In those embodiments of the invention disclosed ¦ herein, the digital signals received from the analog to l digital converter 6 by the digital delay device 7 must be ¦ retained within the di~ital. delay device 7 for a suffic.ient period oE time to allow a detection and control apparatus 10 or 30 to cause the recording apparatus 11 to be placed in the recordin~ mode of operation. Accordingly, if the digital delay device 7 includes a plurality of digital shift registers, the nu~r of digital shift reg;sters must be suEficient to simultan~ously transmi.t the complete I sequence of electrical bits neecled to electriccllly .

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r~:~?:esei~t eclc~ hinary nu~ aer ~s e.lch ne~1 ~ligitat siyilal is ¦j r,?c~ived fco~n the analocJ to digital converter 6. ~k~reover, since the digital delcly cle~ice 7, in this case a ?lurality ' oF àicJital shiEt regist~rs, op~cat~s in respo~lse to the ~:OC
out~ut ~rom the analog con-~erter 6, each digital shift i register ~us- be of sufficien~ ca~acity so that, in spite ¦ of its successive operation in response to the EOC to keep up with the analoy to digital converter 6, the digital delay device 7 will retain the initial digital si~nal for a ~ ! sufficient ~eriod of time to allow a detection and control ¦ apparatus 10 or 30 to cause the signal recordinq apparatus ¦ 11 to be placed in a recordin~ ~ode of operation beore the initial digital signal passes rom the time delay device I D.
¦ For exam~le, with further reference to the ¦ alternative embodiment in lhich the di~ital delay device 7 :is a shift reyister and in which each d:igital signal Erom the analog to digital converter 6 at the end of each : I app~oximation cycle is a digital signal consist;ng of a 1 sequence of eight bits which represents a binary number, : ¦ the number of digital shift registers must be suffient to receive simultaneously all eight bits from the analog to di~ital converter 6. ~loreover, if each oE these eight bits is transmitted at the rate of 10 khz described above, through a shft register tlhich is sufficiently long to c~ntain 102~ distinct ~igital signalsr the pl~lrality of shit reyisters will serve as a digital signal delay device I and provide a time delay of 10~.4 milliseconds. Those ¦ skilled in the art will understand that this time delay and t ', - 19 -j, other time delays which can be read;ly obtainecl b~ va~yin~
the rate o- shift and the lenc3th oE the shift recJister ace adequate perio~s in which to place a recordin~ apparatus 11 in its recording mode of operation.
Similarly, in those alternative embocliments in which the digital signal delay device 7 includes a ¦ plurality of random access memories, the nu~er and capacity OL the random access mcmories must be sufficient to simultaneously store the desired number of digital signals, each consisting, for example, o~ eight bits, for I the desired period of time. Since the input and output of ¦ the random access memories are similarly controlled by the EOC O'ltpUt o the successive approximation r~gister 46, the l j collective storage capacity oE the ran~om access memories I t ~ust be large enough that a digital signal nsade u? oE eight¦ blts ~:hich l~as been stored in the random access memories ~ay con.inue to be stored within the random access memories for th~ de~ired period of time delay without havinc~ to be removed in the seq~ence in which it was stored in order to ~ake room for later arriving digital signals which are being introduced into the random access memory at the rate dictated by this frequency oE approxim~tic)n of the successive appro.ximation register 46. For example, if the successive approximation register 46 approximates the analo~ signals at a rate of 10 khz and each digital I approximat~on consi~ts of eight bits, the collective ¦ storage capacity of the random access memories needec~ in ~ order to provide a delay oE 102.4 milliseconds will be 8192 li bits. Tnis collective stor~ge capacity may, for ex~m~le, 11 ~
1,1 i'~

3~7~ l ~t' provi~ed hy eigllt ranclol!l access menlories each havincJ a stora~e ca~acity of 1024 t)its or by four randorn accesc;
memories each havinclZ a storage capacity oE 2048 bitso In t~e case where at least two bits oE the same digital signal are to be stored in the same ~ando~ acc~ss memory, the bits of input must be multiplexed for simul~aneous input and output.
In that embodiment of the invention shown in Fig.
1, digital signals from the time delay device D are transmitted into a digital to analog converter 8 for converting the digital signals from the time delay device D
into analog signals corresponding to the analog signals originally approximated by the analog to ~igital converter 6. The digital to analog converter 8 may be any one of a number o~ ~Jell known and commercially available cligital to analo~ converters. However, a digital to analog converter 8 which is well adapted to the embodiment o~ the invention shown in Fig. 1 is a digital to analog converter t~at generates a stepped signal based upon the successive binary numbers it receives as digital signals from the time delay device D.
These stepped electrical signals are transmitted through a low pass filter 9 which filters the higher harmonics in the stepped analog sic~nals for accurately approximating the sound ~enerated electrical signals, such as that of FicJ. 5A, that were initially introduced into the time delay device D. These analog sisnals may then be transmitted from the low pass filter 9 to the recording apparatus 11 and recorded.

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i' ~h~ embodiment oE the inventiorl s~lo~n in ~icJ~ 2 includ-s the audio converter 2, a recording apparatus 1l/
I and the time delay device D. However, it cli~fers frorn the ¦ embodiment of the invention s'nown in Fiq. 1 in that it does not include the digital to analog con~erter 8 and the lo~
pass filter 9. Thus, in the embodiment of the invention shown in ~ig. 2, the sound generated electrical signals from the audlo converter 2 are recorded by the record:ing , I apparatus 11 as digital signals.
¦ The embodiment of Fig. 2 also dif:E~rs from the embodiment of Fig. 1 in that the detection and control a~paratus 30 for cau.sing the recording apparatws 11 to be placed in a recording mode of operation is responsive to the digital signal from the analog to digital converter 6 ~ rather than to the sound yenerated signals ~com the aud~o I converter 2. In this r~spect the em~odiment oE the invention show~ in Fig. ~ is similar to the embodimen~
shown in Fig. 3 which is identical to the embodiment sho-ln in Fig. 1 and described above except that lt also includes a detection and contEol apparatus 3~ for placing the recording apparatus 11 in a recording mode o~ oper~tion in I response to the digital signal from the analog to digital I converter 7.
¦ Yro~ Fi~. 6, it will be seen that the digital ¦ detection and control a~p~ratus 30 inclucles at least two ¦ cligital magnitucle comparAtors 61 and 61 ' for detectin~ the ¦ ~resence of digital signals above ancl below a presel~cted di~ital value. The digital macJnitude comparators 61 and 6l' are connecte~l t~y an "or" gflte 62 whicll will p~ovi~1e an !
Ii .
., ,, - 22 -~43~7~ ~

1 up to an up-clown counter 63 outpUt si~nc~ response to ¦ a signal to a sigrlal ~rom either diqital magnitude comparator 61 or 61'. l'he arrangement of the com2arators 61 and 51' in the em~odiment illustrated in Fig. 6 makes the di~ital detection and control apparatus 30 responsive to digital signals which have values ~reater or less than a range of digital values between an upper limit V~ set into the digital magnitude comparator 61 and d lower limit VB' I set into the digital magnitude comparator 61'. This will be , i~ more clearly understood from a consideration of Fig. 5A in which the voltage Sl is the D.C. amplitude of the sound generated electrical signals shown in Fig. 5A and in which the voltages VB and VB' are voltages which have been arbitrarily selected as voltages which t`~ill generally be exceeded by the amplit~cle of sound generated electrical signals caused by human speech desired to be recordea~ but not by the amplitude of sound generated electrical signals caused by background nc>ise. It should be further understood at this point that the analog to digital ~ converter 6 w.ill provide digital signals corresponding to all analog signals converted by the audio converter 2 and passed through the low pass filter 4 regardless of amplitude, even if between B2 and B3t or greater than B~ or less than B3'.
It will be understood by those s.~illed in the art that digital magnitude comparators are digital logic devices ~lhich pcovide a particular output depending u~on the result of the comparison of a preselected digital value ~I selected for comparison with a separate di~ital input with 30 1I that sep2rate digital input. The digital input proviclec~
!
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for col~a-i~on Is the ~igital output Ero~ the analog to di~,ital converter 6 as set fo.th above. In the embodi:r~?nt o~ the analog to digital converter 6 which hcl-, bee~l described, the digital signal output from the analog to digital converter 6 consists of a sequence of ei~ht bits.
However, the comparison voltages VB and VB' may be determined by reEerence to the four most significant bits of the binary numbers representing VB and VB'. For example, the digital value of the threshold voltage of sound to be recorded might be determined to be 00l11011.
Any digital signal above 00110000 might be su~f.iciently near this threshold voltage that the detection and control apparatus could be responsive to all such signals without sacrificing any operational advantages. Therefor~, the diyital magnitude comparator 61 may be set to compare only the four ~ost significant bits of each digital signal from the analog to diyital converte[ 6 with the binary sequence OOllOOQ0. This preselected binary sequetlce is set into the digital magnitude comparator 61 in the convent;onal manner to function as the higher limit setting VB. Similarly, another binary sequence is set into the digital magnitude comparator 61' in the conventional manner to function as the lower limit settin~ VB'.
. Since, as indicated above, the digital magnitude comparator 61 provides a discrete "up" signal to the up-do~Jn counter ~3 through the "or" gate 62 inclicating when the digital signal from the analog to digital converter 6 is greater than the upper limit setting and the digital t~agnittde comæarator 61' pro~ides an "up" si~nal to the Il Il - 24 -.. . .

~3~7~

u~ wn c~ er 63 throu~h the "or" gate 62 inclicating ~ en the digital signal from the ~nalo~ to di~ital converter 6 is less than the lower limit settin~, it ~ill be understood that th~ digital magnitude comp~rators 61 and ~l' serve to provide "up" signals to the up-down counter 63 only when the digital signal output from the analog to di~ital converter 6 indicates the presence of sound generated electric21 signals rom the audio converter 2 as ~efined by amplitudes above VB and below VB' in Fig. 5A.
It is by only permitting "up" signals to be provided to the up-down counter 63 in response to electrical signals having a magnitude above VB or belo~7 VB' that the _omparators 61 and 61' detect the presence oE
¦ sound generated electrical signals provi~ed by human speech , or dictation desired to be recorded. Fur~her, it will be i understood that the comparators 61 and 61' will not provic3e "up`' signals to the up-~own counter. 63 in response to noise from the audio converter 2 and the low pass filter 4 as l deEined b~ signals having amplitudes bet~leen VB and VB' in 0 , ~ig. 5A. In addition, it will be understood that the sensitivity of the detection and control apparatus 30 in terms of its ability to respond to sound generated , electrical signals which are to be recor~ed, while not ¦ responding to noise, may be selectively adjusted by simply changing the higher limit setting, the lower limit setting, or both settinys.
As shown in Fig. 6, the up-down counter 63 which I receives up signals from the magnitude comparators 61 and I¦ 61' also has an input 65 from the EOC output of the 1.
, / .
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~3~
successive approximation register ~6 in the analog to di~ital converter 6. The ~oC output of the successive I approxima~ion re~ister ~6 provides a clock input 65 to th2 ¦ up-dol~n counter 63 and controls the up-down counter 63 to j cause it to operate only at the end of each approximation cycle of the analog to digital converter 6. Thus, the up-dor~n counter 63 only operates in res2onse to those "up"
signals from the comparators 61 and 61' which are caused by I the digital signals from the analog to digital converter 6 10~ which represen~ the final approximation of the sound ¦ generated electrical signals. It will be further ¦ understood that the up-down counter 63 will not be responsive to digital signals of large magnitude which may I be generated by the successive appro~imatio~l register 46 ¦ during the process of digitally approximating the sound ¦ generated electrical signals.
It will be un~erstood hy those s~;illed in the art ¦ that an u~/down counter may count in a binary system and ¦ that the binary number indicate~ by the up~down counter is 20I chanqed in response to the presence or absence of "up"
¦ signals at the input to the counter. It ~ill be further ¦ understood that the up/down counter ~ay have separate load I and reset inputs which cause the up/down counter to ¦ indicate a preselected number or zero, respectively, in j re.sponse to an input at load or reset. It will also be understood that an up/down counter ~hich counts in a b;nary system has separate outputs provided by the presence o~ a I "one" at particular places in the sequence of bits which.
¦ ~a~es up the ~inacy number. For example, an output ~ay be 30provided by the presence of a "one" at the seventh place in 1.

:I~L43~L~O

the binary number 01000000 which corresponc1s to the numl~er 64 in a decimal number system.
Referring now to the embodiment of the detection , and control apparatus 30 shown in ~ig. 6, the up/down ¦ counter 63 is a binary up/down counter which is responsive to the output of the "or" gate 62 each ~:ime the EOC input causes the up/down counter 63 to count. The pcesence of an "up" signal from the "or" gate 62 at the input of the up/down counter 63 causes the u,~/down counter 63 to count up thereby causing the number indicated to increase by one The absence of an "up" signal from the "or" gate 62 at the l input of the up/down counter 63 causes the up/down counter I ¦ 63 to count down thereby causing the number indicated to decrease by one.
The control output 73 is selected Çrom among the diffeeent outputs of the up/down counter 63 to cause output only aEter there have been continuous input signals for a desired p~riod of time to assure that the "up" is caused ¦ by continuous dictation. Thus, in the embodiment of the ! detection and contsol apparatus 30 shown in Fig. 6, the output is chosen to correspond to the eighth place in the binary counter so that a control output will be caused by the presence oE a "one" in the eiqhth place of the countec indicating that it has counted to binary 1000000~ (or 128 in the decimal system), the control output initiation number. As set forth above~ the frequency oE the clock oscillator 45 provides an EOC output from the successive apj?roxlmation register 46 at a frequency oE lOkhz.
l Therefore, continuous signals will be required for a ,li 1~
I i ~;3~
pQriod oE 12.8 milliseconds ln order for the up/down counter to cause a control output 73. r~oreover~ s~ch control output 73 will continue as long as a "one" remains at the eighth bi.nary position of the up/down counter 63.
The embodiment of the detection and contral a2paratus 30 shown in Fig. 6 also includes a feedbac~
circuit 64 from a preselected output of the up!down counter 63 to an "and" gate 70. For reasons that will become apparent, the output of the up/down counter 63 which will be chosen for the feedback circuit is the output that is provided by the presence of a "one" at the eighth binary position of the up/down counter 63. However, it will be understood that an output of the up~down counter 63 other than that caused ~y the presence of a "one" at the eighth binary position could have been chosen.
In addition to the input from -the feedback circuit 64, the "and" gate 70 also has inputs Erom the EOC
output o~ the successive approximation register 46 and from the "or" gate 62. Thus, the simultaneous presence of a "one" at the eighth binary position of the up/down counter 63 ~also causing a control output 73 ), an EOC signal ~ and an output Erom the "or" gate 62, inclicating the continuation o dictation~ callses an output to be provided from the "an~" gate 70 to th~ load input 74 of the up/dow~
counter 63~ Conversely, the absence of dictation re~lected by the absence of an output froln the "or" gat~ 62 precludes a load output from the "and" g~te 70. This permits the up/do~n counter 63 to count do~.~n b~ preventing the up/do~n counter 63 from lo~din~ the preselected nlembe..
30 :

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, , . - 28 -a3~
1.
As c1esceibed above, the effect of a load input 7 at the up/do~n counter 63 is to cause t~le up~down counter 63 to advance to a preselected number. The selection of this number can be made in suc~1 a manner as to cause the up/do~n counter 63 to be advanced a suEficient nu~ber of binary numbers so that, despite the continued absence of signals from the "or" ~ate 62 and the concurrent counting down o~ the up/down counter, a "one" wlll remain at the output of the up/down counter 63 chosen as the control output 73, in the case of the pcesent embodiment the eighth binary position, for a predetermined period of time. In the case of the present embodiment, the preselected binary nurnber chosen to be loaded is llllllll (the equivalent oE
decimal 255). Since a "one" is present in this preselected number at the binary position chosen as the corltrol out~ut 73, the control output 73 ~ill continue until there is no longer a "one" in the eighth binary position, even though the absence of dictation signals has caused the up/dowln counter 63 to count do~.~7n below llllllll.Thus, the person dictating may pause for a period of time, established by the number of cycles by ~hich the preselected number (255) exceeds the lowest nurnber at which a control output 73 is provided ~l2a) and the period of time between each EOC
signal ~0.1 milliseconds), without causing the recording apparatus ll to be taken out of the recording mode of operation. This period of time permi tted for a pause ~1ill be 12.8 milliseconds in the present embodiment.
It will be furthee understood by those skilled in the art that since the load in~ut 74 responsive to continued ~3~7~

dictation signals from the "or" gate 62 does not permit the up/down counter 63 to count above the preselected number, the period oE time permitted for a pause will be constant regardless oE the length of time for which the speaker has been dictatiny continuously prior to the pause.
As set forth above, the up/down counter 63 also has a reset input 75 which will cause the up/down counter 63 to indicate zero or 000000~0 in a binary number system whenever an input signal is received at the reset input. In the embodiment of the detection and control apparatus 30 shown in Fig. ~, the reset input 75 is electrically connected to an "and" gate 83~ Thus, the up/down counter 63 will be reset to zero whenever an output from the "and"
gate 83 is provided.
The inputs to the "and" gate 83 are provided by:
the EOC out~ut from the successive approxi~ation re~ister 46; the ~utput of a first inverte~ 84 responsive to the absence of dictation signals from the "or" gate 62; and the output of a second inverter 85 responsive to the absence of a signal from a preselected output of the up/down counter 63. In the presently disclosed embodiment, the output oE
the up/down counter 63 chosen to provide an input to the second inverter 85 is the output corresponding to the eighth binary position of the counter, the control output termination nu~ber. However, it will be understood that the preselected output may have been chosen from another output o~ the up/do~ln counter 63.
The "and" gate 83 will, therefore, only reset the up/do.~n counter 63 ~o zero at the end of an approximation ~,~' '' I

cvcle (EOC), ~1hen the absence of an output si~nal frol~ the "or" gate 62 indic~tes the absence of dictation and ~hen there is also no control output 73 from the up/do~n counter 63. Thus, in the present embodi~ent, the up/c1own counter 63 ~ill reset to zeco once the u~do~n CoLIntec 63 counts down from the second preselected load nurnber (255~ to belo~
the first preselected number ~128), which is therefore both the control output initiation and termination number, without a resu~ption of dictation~ It will be further understood that once the up/down counter 63 has counted below the preselected control output terminat;on number (128) and has been reset to zero, the zero will be maintained in the up/down counter 63 until the output from the "or" gate 62 indicates the resumption of dictation and the up/down counter 63 begins to count up. Thus, the continued absence of dictation will not cause the up/do~n counter to "count" down below zero and "roll-over" to produce a control output 73, but the up/down counter 63 will retain the zero until actual dictation 2S i~dicated by the output at the "or" gate 62 resumes.
It will now be understood by those skilled in the art that the digital detection and control apparatus 30 shown in Fig. 6 will provide a control output 73 to the r~cording apparatus ll to place the recording apparatus ll in the recording ~ode oE operation upon the detection of dictation. It will be~ further understood th~t the absence of a control output 73 cause~ by the absence of dictation Eor a Dredetermined period of time will cause the recorcliny anparcltus ll to be taken out of the recordin~ mode of operation. In addition, it ~ill be unc1e~stood that the digital aetection and control apparatus 30 is selectively adjusta~1e 50 as to provide a control ou~p~1t only upon the detection of desired sound signals of desired magnitud2 such as speech or dictation and not background noise. 1~he digital detection and control ap~aratus 30 is also I selectively adjustable so as to provide a control output ¦ only in the presence of continuous sound generated signals I of selected duration thereby eliminating a control output . I in respon~e to short loud noises which are not dictation.
¦ It will also be understood that the digital detection and control apparatus 3~ is selectively adjustable so that pauses or breaks in dictation of a selected short period l will not cause the recording apparatus ll to be ta~en out ¦ o~ the recording mode oE operation.
¦ The ~oregoinlg description sets forth illustrative ¦ embodiments of the invention ln a signal recording system comprising a signal recording apparatus and a si~nal time delay system. It is to be understood that the signal time delay syste~ may be used in any siynal recording sy~)tem, ~20 1 regardless of whether the signal is generated by an audio sisnal or not. It is further understood that the foregoing e~bodiments are rnerely illustrative e~bodiments oE the invention and that the scope of the invention i5 limited sol y by the appended c aim9.

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Claims (12)

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. A digital detection and control apparatus, selectively responsive to digital input signals, comprising:
a) a digital magnitude comparison means, responsive to said digital input signals, for detecting said digital input signals of a magnitude greater than a predetermined magnitude;
b) a first counting means, responsive to said comparison means, for providing a control output in response to each occurrence of a first predetermined number of contiguous ones of said digital input signals greater than said predetermined magnitude;
c) a second counting means, responsive to said comparison means, for terminating said control output in response to each occurrence of a second predetermined number of contiguous ones of said digital input signals less than or equal to said predetermined magnitude.

2. A digital detection and control apparatus as recited in Claim 1 wherein said digital magnitude comparison means includes at least one digital magnitude comparator.

3. A digital detection and control apparatus as recited in Claim 1 wherein said first counting means comprises an up/down counter.

4. A digital detection and control apparatus as recited in Claim 1 wherein said second counting means comprises an up/down counter.

5. A digital detection and control apparatus as recited in Claim 1 wherein said first predetermined number is selectively variable.

6. A digital detection and control apparatus as recited in Claim 1 wherein said second predetermined number is selectively variable.

7. A digital detection and control apparatus as recited in Claim 1 wherein said predetermined magnitude is selectively variable.

8. A digital detection and control apparatus, selectively responsive to the input of digital signals, comprising:
a) at least one digital magnitude comparator, responsive to said digital input signals, for detecting digital signals of a predetermined magnitude and for providing a first discrete output in response to each of said digital input signals of said predetermined magnitude and a second discrete output in response to each of said digital input signals not of said predetermined magnitude;
b) an up/down counter having a plurality of outputs selectively provided in correspondence to the number to which said up/down counter has counted, alternatively responsive to said first discrete output and said second discrete outputs to count in a first direction in response to each of said first discrete outputs and to count in a second direction in response to each of said second discrete outputs, for providing a control output after counting to a number in a first range between a first predetermined control output initiation number and a second predetermined load number in said first direction from said first predetermined

Claim 8 - cont'd ...
initiation number;
c) a load circuit means, responsive to the simultaneous presence of both said first discrete output and said control output, for loading said up/down counter to said second predetermined load number;
d) a reset circuit means, responsive to the simultaneous presence of said second discrete output and the absence of an up/down counter output in a range between said second predetermined load number and a third predetermined control output termination number in said second direction from said second predetermined load number, for resetting said up/down counter to a fourth predetermined reset number outside of said first range in said second direction from said first range thereby terminating said control output.

9. A digital detection and control apparatus as recited in Claim 8 wherein said third predetermined control output termination number is said first predetermined control output initiation number.

10. A digital detection and control apparatus as recited in Claim 8 wherein at least one of said pre-determined numbers is selectively variable.

11. A digital detection and control apparatus as recited in Claim 8 wherein said predetermined magnitude is selectively variable.

12. A digital detection and control apparatus responsive to an input carrying a digital number and a clock signal indicating the presence of a valid digital number on said input comprising:
a digital magnitude comparator for providing a direction output in response to said digital number being with-in a predetermined range of magnitudes;
a scale of N up/down counter, N being an integer, responsive to said direction signal and said clock signal to provide a counting function to increment upon each occurrence of said clock signal in the presence of said direction output and alternately decrement upon each occurrence of said clock signal in the absence of said direction output;
means for providing a control output when said scale of N counter contains a count greater than or equal to M, M
being an integer less than N; and presetting means for overriding said counting function and for presetting said counter to an integer K, K being less than M, upon each occurrence of said clock signal during the simultaneous absence of said direction output and said control output and for presetting said counter to an integer L, L being greater than M and less than or equal to N, upon each occurrence of said clock signal during the simultaneous presence of said control output and said direction output.