CA1138569A - On board integrated circuit chip signal source - Google Patents

Abstract

ON BOARD INTEGRATED CIRCUIT CHIP SIGNAL SOURCE
ABSTRACT OF THE DISCLOSURE

An on-board integrated circuit chip signal source which allows operation of the chip from previously incompatible and excessively high amplitude signal sources, and as well powers the chip from such sources as the input signal, a clock, etc. The invention utilizes a 3 plate capacitor, with the bottom plate formed of a heavily doped region of the silicon substrate. Signal is applied between the outside plates of the capacitor and a proportion of the signal is received between the centre plate and one of the outside plates. A diode clamp connected between the centre plate and a reference potential fixes the derived peak and average signal levels.

Description

~3~S~9 01 This application is a division of Canadian 02 application Serial No. 322,645 filed March 2, 1979.
03 This invention relates to a structure for 04 supplying signals to a semiconductor integrated circuit 05 from an external source previously considered incompatible 06 with the integrated circuit.

08 Integrated circuits require carefully controlled 09 input signal voltage amplitudes and power supply amplitudes for proper operation. For instance, if the input signal 11 amplitude to a linear MOS integrated circuit is excessive, 12 the circuit usually will saturate, or worse, forward 13 biasing parasitic diodes, causing destructive currents.
14 Power supply voltages must also be kept within given ranges, although they are usually less critical once the 16 operating parameters of the circuit have been established.
17 Where an excessively high input signal voltage is 18 present, it is necessary to reduce its amplitude by such 19 means as a voltage divider. The voltage divider is most economical if it is integrated with the circuit into the 21 semiconductor chip itself.
22 Integration of a voltage divider into a MOS chip, 23 with isolation of the source has previously been provided 24 using transistor voltage dividers, since transistors have

2~ traditionally been the easiest elements to fabricate.
2~ MO5FET transistors used in this manner typically have their 27 gates short circuited to their drains, to form diodes.
28 Since the diodes have predetermined threshold voltage 29 drops, series arrays of such diodes can provide voltage division.
31 ~owever, besides providing a voltage division, such 32 diodes automatically set up bias levels at the divider 1~38569 01 output relative to the chip substrate potential due to 02 their inherent threshold voltages. Consequently the amount 03 of voltage division available as well as the relative 04 positive and negative input signal amplitudes which can be 05 accommodated before saturation is limited by the self 06 biasing established as a result of the diode doping level, 07 the number of series connected diodes, etc.
08 In the present invention, there are no diode 09 threshold utilized to provide the voltage division, and consequently the self biasing offset is eliminated.
11 Consequently there is no saturation point w~ich is based on 12 the number of diodes in series, and the designer is given 13 substantially greater freedom in designing a given input 14 voltage drop. Further, the design freedom now allows the integration of an on-board chip power supply in the 16 semiconductor integrated circuit with which it is to 17 operate.
18 In the present invention, an integrated 19 capacitor voltage divider is utilized. While one would otherwise expect threshold potentials to be present due to 21 doping of the semiconductor substrate to form a capacitor 22 plate, and thus to exhibit undesirable effects due to the 23 presence of the diffused or implanted doped region within 24 the ~ubstrate, the present structure is fabricated so that the resulting semiconductor surface is already heavily 26 inverted even with no external bias potential applied.
27 Accordingly additional potential applied to the doped 28 region does not shift the operating point to a threshold 29 region where threshold potentials would affect the stability of the output signal with changes in input 31 ~2-1138S6g 01 signal.
02 The present invention provides for the on-board 03 derivation of signal voltages which are substantially 04 different in amplitude and with respect to external ground 05 than that of the input voltage. Means is also provided for 06 establishing an on-board power supply voltage of AC or DC
07 form.
08 Further, the present invention provides means for 09 deriving power supply voltages from hitherto unexpected or previously unsuitable sources, such as an external clock 11 source, which is particularly useful for use with CMOS
12 integrated circuitry. In this application other power 13 supply input leads may be dispensed with, assuming that the 14 clock source can supply all power supply requirements.
Accordingly the present structure provides a 16 substantially more flexible and improved means for 17 supplying power to the integrated circuit, for supplying 18 signals to the integrated circuit which are compatible 19 therewith from hitherto incompatible sources, using circuitry which is integrated in the chip itself, while at 21 the same time being of more economical form. Further, the 22 structure can be fabricated in MOS circuitry using either 23 metal gate, double polycrystalline layer technology or the 24 like.
SUMMAR~ OF THE INVE~TION
26 The invention in general is a semiconductor 27 structure including a three plate capacitor comprising a 28 lower relatively conductive region of heavily doped 29 silicon, having a first insulating layer covering the conductive region. A polycrystalline silicon relatively 113~56~

01 conductive layer is located over the first insulating layer 02 covering at least a substantial portion of the bottom 03 conductive region. A second insulating layer covers the 04 polycrystalline layer. An upper conductive layer is 05 disposed over the second insulating layer, and conductive 06 means contacts the polycrystalline layer for providing an 07 output signal when an input signal is applied between the 08 upper conductive layer and the lower conductive region.

A better understanding of the invention will be 11 obtained by reference to the detailed description of the 12 preferred and other embodiments below, in conjuction with 13 the following drawings, in which;
14 Figure 1 is a schematic diagram of the invention, including circuit means for use with the invention, 16 Figure 2 is a schematic diagram of an alternative 17 form of the circuit means, 18 Figure 3 is a schematic diagram of a further 19 embodiment of the circuit means, and Figure 4 is a cross-section of a physical 21 embodiment of the invention including a portion of the 22 circuit means.

24 Turning first to figure 1, a capacitor voltage divider comprising capacitors 1 and 2 is shown. While two 26 capacitors are shown, it is preferred that the structure be 27 fabricated as a single three plate capacitor. For example 28 the capacitor preferably is fabricated of a bottom 29 conductive plate 3, a single centre plate 4 which is

3~ insulated from bottom plate 3, and an upper conductive ~138569 01 plate 5 which is insulated from centre plate 4. Contact 02 may be made to the centre plate 4 at node A.
03 As is well known using capacitor voltage 04 dividers, an external AC voltage applied between capacitor 05 plates 5 and 3 is divided according to the inverse ratio of 06 the capacitance of capicitor 2 to the series capacitance of 07 capacitors 1 and 2. A reduced amplitude output signal may 08 thus be obtained between node A and capacitor plate 3, 09 contact to the latter which may be made at the chip substrate ground point 6.
11 While the concept of a capacitor voltage divider 12 is not being claimed as being new, such a structure within 13 an integrated circuit having a heavily inverted diffused 14 area forming the bottom capacitor plate (which provides particular advantages) is believed unique, particularly 16 when used in a structure described wherein.
17 Considering Figure 1 in conjuction with Figure 4, 18 the bottom or lower plate 3 is fabricated as a heavi~y 19 doped P+ or N+ region 7 within a P or N substrate 8. The P+ or N+ region may be diffused, or implanted by ionic 21 bombardment of boron or phosphorus, etc. according to the 22 particular process utilized. This region 7 forms the lower 23 relatively conductive plate 3 of the 3-plate capacitor, and 24 substrate 8 in figure 4 forms the ground point or plane 6 referred to in Figure 1.
26 The heavily doped region 7 exhibits a highly 27 inverted surface with no external bias required.
28 Accordingly the operating point of the structure is 29 substantially distant in voltage from the voltage threshold of the surface. As a result applied input voltages have ~138569 01 been found to not cause the inversion of the doped 02 substrate surface to become so biased that the threshold is 03 encountered.
04 The lower capacitor dielectric is provided by an 05 insulating layer 9, which preferably is silicon dioxide.
06 The centre conductive plate 4 is preferably fabricated of 07 polycystalline silicon, shown as layer 10 disposed over 08 insulating layer 9 in figure 4. It should of course be 09 located over the lower plate formed by conductive region 7.
The dielectric for the upper capacitor 1 is an 11 insulating layer 11 preferably formed of silicon dioxide.
12 The upper plate 5 is formed of a conductive layer 12. The 13 particular material used for this layer will depend on the 14 type of MOS process used. For instance where the silicon or metal gate fabrication process is used, conductive layer 16 12 would be made of aluminum. However where the double 17 polycrystalline silicon process is used, conductive layer 18 12 would be made of polycrystalline silicon. In the latter 19 case, there may be, if required, an additional metallized conductor making contact thereto, which conductor is shown 21 as reference 13 in figure 4.
22 ~ode A in Figure 1 is a location for connection 23 to the centre plate of the multiple capacitor. There is no 24 exact counterpart to node A shown in Figure 4, except that the centre plate polycrystalline layer 10 extends to the 26 right to make contact with other circuitry which will be 27 described further below.
28 A voltage reference establishing circuit is 29 connected to node A (Figure 1). In an MOS integrated circuit this preferably consists of a ~series of diodes 31 _~_ ~13Y569 01 fabricated of MOS transistors, such as four of such 02 transistors, 14, 15, 16, and 17. Each has its gate 03 connected to its drain electrode, and each successive one 04 has its source electrode connected to the drain of the 05 preceding one, except for transistor 17. The source of 06 transistor 17 is connected to a reference source of 07 potential. The reference source can be, if preferred, ~he 08 chip substrate ground point 6 as noted earlier. The 09 present embodiment will be described with the example of the reference source being at the ground point 6.
11 Operation of the circuit is as follows. A source 12 of AC signal 18 is connected to the upper plate 5 of the 3 13 plate capacitor, the other pole of the source of supply 18 14 being connected for AC to the chip substrate ground point 6. A capacitor 19 in dashed line is shown as a means 16 connected between external ground and the substrate point 17 16 for obtaining the AC coupling, but other means may be 18 used. The external ground potential thus can vary widely 19 from the ground potential of the chip substrate ground point 6.
21 While the 3 plate capacitor provides voltage 22 division, the actual potential of node A relative to the 23 ground point 6 is established by the total of the 24 thresholds of the series of diodes formed by MOS
transistors 14, 15, 16 and 17. These self-biased diodes 26 form a clamp for node A relative to the ground point 6 (or 27 other threshold potential, if capacitor plate 3 is 28 connected thereto.) With the thresholds of the MOS
29 transistors at, for example, 0.7 volts, the potential between node ~ and ground point 6 is thus heLd at 113~569 01 4 ~ 0.7 = 2.8 volts.
02 It has been found that relative to external 03 ground, the average AC potential as measured across 04 capacitors 1 and 2 shifts. Thus where a sine wave is the 05 form of the input voltage, a sine wave is produced as the 06 form of thç output voltage due to the shift in average 07 level, and distortion of the waveform is avoided, which 08 distortion would otherwise be expected using a series of 09 diodes as a clamp, with applied potential exceeding their threshold.
11 The output AC signal may then be applied to MOS
12 circuitry 20 as might be required.
13 It was noted above that the source electrode of 14 MOS transistor 17 can be connected to a DC reference potential point which is different from that at the chip 16 ~ubstate ground point 6. This further modifies the average 17 DC level of the AC signal applied to circuitry 20.
18 An alternative structure for MOS transistors 14, 19 15, 16, and 17 is shown in figure 2. In this case the reference is provided by a zener diode 21 in series with an 21 ordinary diode 22. The series of 2 diodes are connected 22 between node A and the chip substrate ground point 6 (or to 23 a reference potential if the design requires it).
24 As an example of the operation of this circuit, let us assume that the total series threshold voltage of 26 zener diode 21 and ordinary diode 22 are 21 volts, the 27 zener diode having a 20 volt threshold and the diode 22 28 having a 1 volt threshold. Accordingly the peak output 29 voltage will be 21 volts.
Assume also that the values of capacitors 1 and 2 113~569 01 are equal. Accordingly, an input voltage of, for instance, 02 20 volts peak to peak is divided such that the voltage 03 across each of the capacitors is 10 volts peak to peak.
04 This would be the case notwithstanding that the external 05 ground can be at a substantially different D.C. potential 06 than the substrate ground.
07 With the peak voltage at node A at 21 volts 08 relative to the ground point 6, and with one half the input 09 voltage (10 volts peak to peak) available, the output voltage thus is an AC signal having a minimum voltage of 11 11 volts and a maximum voltage of 21 volts above the chip 12 substrate ground point 6 potential.
13 It should thus be noted that the peak output 14 voltage, for diodes formed of MOS transistors, is n~d, where n is the number of diodes in series and Vd is the 16 threshold voltage of each of the diodes. The peak voltage 17 is referenced to and is above either the substrate ground 18 point or to a reference potential if desired.
19 Figure 3 shows the circuit of Figure 2, with further means for providing a power supply for the 21 integrated circuit. Diodes 21 and 22 are shown for example 22 as the clamp connected to node A. A rectifier diode 23 is 23 connected in series between node A and the utilization 24 circuitry. An additional on-board capacitor can be used for filtering, or other circuitry which is well known to 26 those skilled in the art.
27 It should be noted that the above described 28 on-board power supply can be used to supply power to the 29 chip either from an input signal or from a source such as a clock. If either of these inputs are used, one or both 31 _9~

01 power supply leads can be eliminated from the chip, 02 allowing the former power supply input terminal to be used 03 for other purposes. The present circuit therefore provides 04 an on-board power supply for an MOS integrated circuit 05 chip, and particularly for a CMOS circuit, which is derived 06 from an input signal or from a clock source.
07 Turning again to figure 4, an example of a single 08 MOS clamping diode is shown for example purposes connected 09 to the capacitor described above. The MOS diode is comprised of an MOS transistor having an N-doped source 24 11 and an N-doped drain 25 connected by an N-channel 26. Of 12 course P type doping could be used to form a PMOS
13 configuration.
14 A polysilicon gate 27 is located above the channel 26, insulated from the channel by silicon diode 16 layer 9, in well known form. The polysilicon gate is 17 connected directly to the drain 25, forming a short 18 circuit, similar to transistor 14 in figure 1. The 19 polysilicon gate is connected to the polycrystalline layer 10 which forms the centre plate of the 3-plate capacitor 21 which is formed of capacitors 1 and 2.
22 A contact 28 is connected to source 24 in a well 23 known manner. However rather than using contact 28, a 24 polysilicon layer can be used to connect the source to the gate and drain Gf a further series MOS diode, in a manner 26 similar to that first described between the centre plate of 27 the 3 plate capacitor and the MOS diode. Contact 28 is 28 thus shown for illustration purposes only.
2g Silicon dioxide layers 9 and 1l are shown insulating the just-described MOS structure in a well known ~9 01 manner. Field oxide 29 completes and protects the surface 02 of the integrated circuit.
03 The present invention thus provides on-chip power 04 supplies from external AC voltage sources without regard to 05 the particular DC ground potential of the external supply, 06 even in the presence of previously incompatible and 07 excessive external supply potentials.
08 Other uses, other embodiments, and variations may 09 now be conceived by persons skilled in the art understand-ing this invention. All are considered within this sphere 11 and scope of the invention as defined in the appended 12 claims.

~2~

Claims (6)

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:

1. A semiconductor integrated circuit structure comprising:
(a) a plurality of interconnected CMOS transistors, (b) a power input bus to said transistors, (c) an input terminal for clock signals connected to predetermined ones of said transistors, (d) a pair of series connected capacitor means, one capacitor means having a bottom conductive region of heavily doped silicon, a first silicon dioxide insulating layer covering the conductive region, and an upper conductive layer over the insulating layer covering at least a substantial portion of the bottom conductive region, (e) the junction between the pair of capacitor means being connected through circuit means to the power input bus, (f) the input terminal for clock signals being connected to the other terminal of the other of the pair of capacitor means, whereby the clock source provides both clock signals and operating power for said transistors.

2. A semiconductor integrated circuit structure as defined in claim 1, in which the circuit means is comprised of a plurality of series connected MOS transistors each having its gate short circuited to its drain, connected between the junction of said capacitor means and a source of reference potential.

3. A semiconductor integrated circuit structure as defined in claim 2, in which the source of reference potential is the integrated circuit substrate.

4. A semiconductor integrated circuit structure as defined in claim 1, 2 or 3, in which the circuit means is comprised of a rectifier connected between the junction of the pair of capacitor means and the power input bus.

5. A semiconductor integrated circuit as defined in claim 1, 2 or 3, in which said upper conductive layer and the pair of capacitor means is fabricated of polycrystalline silicon, and further comprising a second silicon dioxide insulating layer covering said upper conductive layer, and a top conductive layer disposed over the second insulating layer covering at least a substantial portion of the upper conductive layer.

6. A semiconductor integrated circuit as defined in claim 1, 2 or 3, in which said upper conductive layer of the pair of capacitor means is fabricated of polycrystalline silicon, and further comprising a second silicon dioxide insulating layer covering at least a substantial portion of the upper conductive layer, and a top conductive capacitor plate comprising at least a portion of a wire bonding pad disposed over the second insulating layer.