CA1138114A - Electronic control system - Google Patents

Abstract

ABSTRACT

An electronic control system particularly suited for use with an automatic fuel dispensing system uses a centrally located computer to supply serial polling signals to various sub-stations.
At the sub-stations, the polling signals are decoded into signals used to control the operation of specific system relays operated by the system. The status of the decoded polling signals as well as the operating status of the relays is supplied back to the computer for verification. A time-out control circuit continuously monitors the input polling signals applied to the relay terminal.
If activity does not appear on the input signal line at the terminal after a pre-established time interval, all of the system relays at the terminal are turned off or rendered inoperative, irrespective of the status of the relay control signal obtained from the output of the polling signal decoding circuit. As a consequence, if the remotely located computer should fail to properly operate for any reason, the system is placed in a "fail-safe" standby condition of operation.

Description

Case No. 4~ L . ~ ~

~138:1~4 I ELECTRONIC CONTROL SYSTEM

2 I ll The system disclosed herein is related to the type of 6 automatic fuel dispensing system disclosed in Patent No. 4,085,313 7 to Bradford VanNess and assigned to the same assignee as this 8 application.

'¦~ BACKGROUND OF THE INVENTION
11ji Automated fuel dispensing s,ystems and semi-automated fuel 12 ¦¦ dispensing systems have been devi3ed to permit unattended or 13 semi-unattended purchases of fuel by authorized customers of such systems. Customers using systems of this type typicallv include 15 1 municipalities, large trucking companies, and the like. When only ]6 ¦¦ a single customer uses a given facility, control of the fuel 171¦ dispensing facility is relative~y simple. When the system, 18~¦ however, is required to serve many different customers or a single g customer with a large number of driyers and vehicles, it generally lS necessary to have an attendant on duty at a central location in 21 the station for billing purposbs. ~ pically systems of this latter 22 type are the commonly known "self-~rvice" gasoline stations which 23 have a central location manned by a~ attendant who monitors volume 241 readers and the pump turn-on switch~controls for the fuel pumps located at the station. The custome~s pump their own fuel and then 261 go to the central location to pay for the fuel or othérwise take 2711 care of the billing.
28 1I Fully automatia self-servic~ fuel dispensing systems have 29 1 been developed in which a credit card or specially prepared document is inserted into a card reader to cause selected data 31 from the card to be transmitted td a remote central computer for 32 1 verification. If the document is verified as an authorized document, the system then permits the withdrawal of fuel under the 1 control of the credit card. The quantity of the fuel withdrawn is 2 monitored; and upon completion of the transaction, data

3~ representative of this quantity lS transmitted by the local

4 controller along with the credit card identification to the central computer for processing on the particular account number 6 indicated by the credit card being used. While such a system 7 permits the completely unattended operation of a fuel dispensing 8 service station for customers ha~ing credit cards usable in the 9 system, it re~uires committed transmission links between the 10 ~ location of the fuel pumps and the central computer location.
11 An improvement in fully automatic self-service fuel 2 dispensing systems which localizes;ithe credit card identification 13 and verification check of such credit cards is disclosed in the 14 above mentioned related patent. That system includes logic circuitry at a local control counsél associated with the card 16 reader for identifying and verifying the credit card as well as 17 controlling and recording the data Irelative to the transaction 18 itself. A store and forward memory then is utilized to temporarily store the information relative to `each transaction until that information is to be forwarded to~a central computer for further 21 processing.
22 In systems of the type di~closed in the above identified 23 related patent, variations include the use of a local computer or 24 microprocessor at a central loca~ion within the fuel dispensing station itself. For example, a number of card readers each càn be 26 located in a different fuel pump~j~island within the terminal for 27 I individually controlling a group of~fuel dispensing pumps or the 28 11 like. Typically a single card reader is used to control four or 29 ! more pumps at an individual island. A number of such islands, all linked with the central computer at the station, are used in a 31 large automatic bulk fueling station.
32 Operation of the system relays which actually control the 1¦ultimate dispensing of fuel from the various fuel pumps and the 2 Ilike is effected through decoding of the data at the card readers 3 1I by the central computer. The central~computer then supplies serial 4 1polling signals in some pre-established sequence over a polling

5 ¦signal line to the different control terminals at each of the G ¦islands. At the islands, the polling signals are decoded to uniquely operate the relays at the island in accordance with the 81 signals supplied to it. Generally such systems include an 9¦ automatic turn-off or shut down of the relays in the event of 101 power failure or the like. Situations exist, however, where a 11¦ failure of the computer may occur without a power failure at the 12 station. In such an event, it is desirable to render the system 13 relays at each of the islands inoperative to prevent spillage of fuel or unauthorized withdrawal of fuel whenever such a failure 15 loccurs. In addition it is desirable to continuously monitor the 16 1l status of operation of all of the relays at the various island 17 1¦ consoles or sub-terminals at the central computer to insure that 8 ¦i the operation as it actually exists is in accordance with the 9 Ipolling signals supplied from thç computer to the various 20 ¦terminals to initiate the operation.
21 I t , '~ .,i ~
23 Accordingly, it is an object of this invention to provide24 an improved electronic control syste~.
25 I It is another object of ~this invention to proviae an 2~ lelectronic control system for use in conjunction with a 27¦! utilization circuit rendered operative by decoded polling signals.
28 11 It is an additional object o~ this invention to provide an 29~ electronic control system for use with a utilization circuit controlled by polling signals received at a location associated 32 with the utilization circuit for monitoring activity on the ~ _3_ -~ ,.
!

11381~4 polling signal input line and rendering the utilization circuit inoperative whenever polling signal~ fail to appear on the polling signal input line for a pre-established time interval.
In accordance with a preferred embodiment of this inventiOn, there is provided:
An electronic control system having a central source of control and polling signals interconnected with a plurality of controlled terminal locations, the controlled terminal locations including in combination:
utilization circuit means at each controlled terminal location identified by a unique polling signal and having a control signal input terminal and responsive to signals applied thereon. to be selectively rendered operative or inoperative thereby;
polling signal decoder means at each controlled terminal location for said utilization circuit means and having an input and at least one output terminal, and responsive to the unique polling signal identifying the controlled terminal location in which said polling signal decoder means is located when such unique polling signal is applied to the input terminal of said polling signal decoder means to produce an out~ut signal on the output terminal thereof; .
driver circuit means at each controlled terminal location connected between the output terminal of said pollin~ si-3nal decoder means and the input termi.nal of said utilization circuit means for such terminal location to selectively render said utilization circuit means operative or inoperative in respol)se to the signals on the output terminal of said pollin.J signal decoder means for such terminal location;

polling signal supply means coupled to the input terminals of all of said polling signal decoder means for applying polling signals thereto from the central source, and separate control circuit means at each controlled terminal location coupled to receive signals from said polling signal 5 supply means and coupled to one of said driver circuit means and said utilization circuit means at such controlled terminal location for rendering said utilization circuit means at only such controlled terminal location inoperative in response to , the absence of the receipt of polling signals by such control 10 circuit means for a predetermined time interval from said ' polling signal supply means; each of said control circuit means at each of said controlled terminal locations operating independently of the control circuit means at other controlled terminal locations.
:;
,~ 15 BRIEF DESCRIPTION OF THE DRAWINGS
Figure l is a block diagram of a preferred embodiment of -' the invention; and -~ Figures 2, 3 and 4 are detailed circuit blGck diagrams 20 of the system shown in Figure 1.

DETAILED DESCRIPTION
Reference now should be made to the drawings where the same reference numbers are used throughout the several figures 25 to designate the same or similar components. Figure 1 is an overall block diagram of a preferred embodiment of the system ideally suitable for use with an automatic fuel dispensing system. Each station or terminal in the system is controlled by a computer 10 which may be individually and uniquely located 30 at a central operating point within the specific terminal, or the computer 10 -4a-.

1l3~ll4 1~ may be at some remote central locatlon and used to control a 2l number of widely separated bulk fueling terminals.
3 ll Specific operating information for operating particular 4~ relays at the fuel dispensing locations in a bulk terminal station 51 is supplied in the form of polling slgnals over a polling signal G¦ input lead 12 to the control consoles in each different fuel pump 71 island or dispensing location. This information may be originated I in the central computer lO itself, or it may oriqinate by the 9 operation of a card reader terminal of the type disclosed in the 0 1above mentioned Patent No. 4,085,313. If a card reader system of the type disclosed in the '313 patent is used, the information 12 1first is supplied to the computer 10 which then transforms the 13 ¦information into the desired serial polling signal supplied over 4 ! the input lead 12. This polling signal generally is in the form of 15` a continuous serial stream of binary signal information 5 ¦I specifically identifying particular bulk fueling terminals (if the computer controls more than one terminal) and the specific fueling 18 ¦1 islands or control centers within a terminal, down to the specific 19 jsystem relays at each of the islands for effecting the desired 20~ operation of the equipment and the delivery of the fuel located 21~ there. Under normal operation of the is~stem, the polling signals 221 continuously appear on the lead 12. ~
23 The polling signals at a local island or fueling station 241 at a bulk fueling terminal are applied to the input of a 25 Iserial-to~parallel converter 15 which transforms the sèrial 261 signals into a pair of parallel output signal groups identified as 27 a character scan group 18 and a bit gcan group l9 as illustrated 28 ¦l in Figure l. These two-parallel groUp~ of decoded signals then in 2gl¦turn are applied to corresponding inputs of a poll decoder circuit which responds to the groups~ to operate the utilization 31 Icircuitry at the terminal if the uni~ue address identifying the 32 Igroup of system relays controlled by the terminal is decoded by the poll decoder circuit 20. If thé specific poll decoder circuit 2l~ 20 for the particular portion of the system shown in Figure 1 is 3l, not uniquely addressed by the signals applied to it from the 4 converter 15, no operation of the remainder of the circuit shown in Figure 1 takes place for the particular station or terminal

6 shown.

7 For each group of system relays at a fuel pump island controlled by the computer 10, there is a separate poll decoder 9 circuit 20 coupled to the ~ output of an associated 10¦¦ serial-to-parallel converter circuit 15, as shown in Figure 1.
11 ~ Thus a single computer 10 simultaneously may be supplying polling 2 I input signals over a lead 12 to several different converters 15 13 I and their associated poll decoder`circuits 20. Each poll decoder 14 ¦ circuit 20 then operates to uniquely identify specific groups of l5 1l relays and then the particular ~relays within each group for IG¦ operation at the location controlled by that poll decoder circuit 17 1¦ 20. Typically, in a system whiCh has been operated, each poll ¦¦ decoder circuit 20 uniquely controls the operation of eight ~ different groups of eight relays each (for a total of 64 relays).
The output of the poll decoder circuit 20 is a parallel 21 encoded group of signals which uniquëly identifies for operation 22 the particular relay latch and driv~r circuits 21 for the selected 23 relay group, and within the group, the individual relay or relays 24 of the group which are to be opera~ed by the relay latch and 25 ¦ driver circuit 21. Thus under normal conditions of operation of 26 ~ the system, the system relays 22 are selectively turned on and 27~¦ off, or rendered operative and inopérative, in accordance with the 28¦~ changes in the signal applied to ~the system over the serial 291 polling signal input line 12 from the computer 10.
301 Typically, the computer :10 includes circuitry for 31 verifying the operation of the system in accordance with the data 32 sent out over the polling signal line 12. To accomplish this, the ,, , , , . . . , . .. . , . . .. . . " . , . .. . . ~ . ... . . . . . ..

1138~14 .
1¦~ output of the poll decoder 20 and the outputs of the relay latch t; :2 and driver circuit 21 are applied to a serializer circuit 25, i which in turn produces a serial verification output data signal ~-¦ stream on an output lead 27 connected back to the computer 10. The 5~ computer 10 includes comparison circuitry to compare the data received by it over the lead 27 with the source of data supplied by it over the polling signal lead 12. The manner in which this ;i8 I verification is made as well, as its utilization, may take on any ;9 1 of a number of conventional approaches. Typically, if there is a 10ll failure of verification, an alarm condition is established at the Il ¦ computer terminal 10. If such an alarm condition does exist, 12 I automatic termination of system operation or manual intervention, 13 ¦l as desired, may be effected. The particular utili7ation made of 4ll the verification signals on the lead 27 is not important to an 5l, understanding of the features of the invention disclosed in this IG I application~
Systems of the type described so far in conjunction with t~ ¦¦ Figure 1 generally include some type of "fail-safe" shut down in ¦ the event of a power failure or power interruption. This is 201 necessary to turn off various ones of the operated system relays 22 22 in the event such relays are controlling the delivery of fuel il or the like from the terminal. If a shut down system of this type !I were not provided, it is possible that fuel spillage or 24 ¦1 unauthorized withdrawal of fuel possibly could take place. If the 2S¦ Computer 10, however, should fail to properly operate to 2G ll continuously update and control the operation of the system relays 27 1~¦ 22, as described above, a similar problem exists. Therefore it is 28 1l important to create a fail-safe alarm condition or turn-off of 29l operated system relays 22 in the event the computer operation 3~ should fail for any reason, irrespective of whether or not there 31 is a power failure at the pump island or terminal shown in Figure ~
To accomplish a return of jthe system operation to a 2 1I standby "off" condition, a time-out circuit 29 in the form of a 3 Ibinary counter is used. The time-out circuit 29 has its reset 4 input connected to the serial polling signal line 12; and each S time a binary signal pulse transition appears in the signal applied from the computer 10 over the line 12, the time-out 7 circuit 29 is reset to an initial or zero count. Clock pulses for

8 advancing the counter of the time,out circuit 29 are applied to

9 1l the counter from a clock circuit 30.!The same clock circuit also lOIlis used to supply the operating clock pulses to the erial-to-parallel converter circuit 15 to synchronize operation 12 ¦of the signal decoding with the ciock rate of the serial signal 13 ¦1 applied to the converter 15 from the line 12. The clock 30 may be I4~synchronized in any suitable man~er with the operation of the 15 I computer 10; and in some installatio~s, the clock 30 is a common IG clock for all of the circuitry shown in Figure 1 including the 17 computer 10. ~, 18 The operation of the time~out circuit 29 is selected to 19 cause it to apply a relay reset signal over an output lead 32 in 20 response to the application of a pre-established number of clock 21 pulses from the clock circuit 30 fo~lowing a reset pulse. The 22 actual time interval for the circuit 29 to reach a count to 23 produce an output signal on the lead~i32 may be adjusted to satisfy 24 the particular requirements of operation of the system in which it 25 ~ iS used. Typically, a time of three or four seconds is used.
26 I When a signal appears on the lead 32, it is applied to the 27 ¦ relay latch and driver circuits 21 to reset the latches in the 28 ~ circuits 21 to a condition which ~auses the output signals from 29 the circuit 21 applied to the system~relays 22 to be such that all of the system relays are turned off or put in their normal standby 31 condition. ' ~

32 ~ Reference now should be made to Figures 2, 3 and 4 which .1~ l 1381~4 ~, 1 ¦together are a detailed circuit diagram of the system shown in 2 block diagram form in Figure 1, with;the exception of the computer 3 ¦1 10. Reference first should be made to Eigure 2.
4 In Figure 2, the polling signal input line 12, on which the serial polling signals are supplied from the computer 10, is 6 shown in the upper left hand corner. The polling signals typically 7 are encoded in ASCII code, with the l~onventional start and stop 8 bits preceding and following, respectively, each character of the 9j binary encoded serial signal train. A zener diode 35 is used to

10~1establish the range of the pulse voltage excursions. The signal

11 1input pulses are applied to the upper input of a two input NOR

12 gate 37, the lower input of which is an enable input obtained from

13 the "Q" output of a data latch control flip-flop 39.
4 ¦ For the purposes of this di$cussion, assume that the data 15 ll latch flip-flop 39 initially produces a low input to the NOR gate 6 1! 37. This is its normal or reset condition of operation, so that ~the NOR gate 37 is enabled to pass the pulse signal transitions of ! the serial input signal stream through to its output. The enabling ~of the gate 37 normally occurs ` in coincidence with an 20 1end-of-message ~EOM) signal from the poll decoder portion of the 21 ¦circuit. In this state, the system ~own in Figure 2 is in a 22 ~condition where it is ready and wa~t1ng for receipt of the first 231 character of a new input signal mess~ge.
24 ¦ The input signal messages applied to the line 12 from the 25~ computer 10 are in the form of two 1! character messages. In the 26l system shown and described, the irst four bits of the first 27 Ifl character are used to uniquely ldentify and activate the 28-lparticular card reader control con$ole, relay group, or fuel pump 29 1l island; and the next four bits of that same first character are 30¦¦decoded into one of eight possible decimal signals used to select 31¦~one of eight groups of eight relays associated with that card 321 reader station. The second charac~er is used to uniquely select ~ . g ~, ! ::~
.... , . , , . ,, .. ~

1138114 ~ i ,, 1 the individual relays out of a selected group. These relays may be 2 selected in any number in any pattern within the eight 31 possibilities for each group. Thus, each character of the 41 transmitted signal appearing on the data input line 12 is an eight character binary encoded signal precèded by a start transition and G terminated by a stop pulse transition of the type commonly used in 7 ASCII serial transmission.
8 The pulses passed by the NOR gate 37 are supplied through 91!an inverter 40, which in turn supplies the two character input messages to an output terminal 41 connected as the input to a two 11 Istage temporary storage shift register (Fig. 3) for further 12 ¦processing by the system. The operation of that register is 13 ~described subsequently in conjunction with Figure 3.

14~ The output of the NOR gate 37 also is supplied through a

15¦ differentiating circuit to the "set"~input of a start bit detector flip-flop 43 to cause the flip-flop to change its reset state to 7~¦its set state at the start of each received character, resulting 8 ! in a negative-going signal on its output on lead 44, and to cause 1s; a positive-going signal to appear on 1tS output lead 45.
The signal transition appearing on the output lead 45 of 21 the flip-flop 43 is applied through a differentiating circuit to a 221 reset input of a divide-by-ten cou~ter 48 and the output lead 49 23 ¦is applied directly to the reset input of a divide-by-ten counter 24~ 49 to release the counter 49 t~ commence operation of both 251 counters from their initial or zero counts. At the end of a full 26~ count, corresponding to one received character, an output pulse is 27¦!obtained from the counter 49 on a lead 50 and is applied to the 28 clock input terminal of the flip-flop 43 to reset the flip-flop 43 29 to its initial "reset" condition. The signal transition on lead 45 31 also resets the time-out counter 29 to a zero count.

32 I ~

-- . , ,, . . , . , , . __ .. .. .... ...... . .. ..

Clock pulses for operating the bit rate binary divider 48, land the character rate divider 49 are supplied by the clock 31 oscillator 30, as described previously in conjunction with Figure 4~ 1. The oscillator 30 preferably is a stable crystal oscillator, 5 ¦and a divider circuit 52 is connected to its output to produce G four different output signals at different frequencies. These 7 signals are applied to one of the terminals of a different one of 8 four switches in a switching circuit 54, having a common output 9 terminal. One of the switches in the switching circuit 54 is lo closed to select the desired baud rate of operation of the system.

2~ Typically these baud rates are 150, 300, 600 and 1200 pulses per second. The particular frequency of the clock pulses is selected 4 to coincide with the frequency of the data supplied to the system lSI over the lead 12. In any given system, once one of the switches in the switching circuit 54 is closed, it remains closed for the IG ¦I duration of the operation of the system.
7ll The pulses at the output of the switching circuit 54 are 8 ¦! applied to the clock input of the bit rate divider counter 48 ~91 which then supplies clock pulses at the desired bit baud rate on its various outputs. An output lead 56 is connected to the upper 21 input terminal of a two input NAND gat!e 57, the output of which is 2 used to supply shift pulses for t~q decoding shift register 80, 3 81. This output is applied over a lead 58. The NAND gate 57 is 24 prevented from passing clock pulses during the start bit of the characters of the incoming serial message by means of a control 26 input applied to its lower input from the output of a NAND gate 27l~61. The two inputs to the NAND gate 61 are obtained from the first 28~ and second stages of the divide-by~ten character counter 49; and 291 during the first two counts ~corresponding to the first two bit 30~ counts of the bit counter 48), the output of the NAND gate 61 311 prevents the NAND gate 57 from passing any clock pulses. Thus, 32 c1cck pulses are inhibited durin~ the start and stop bits; but . ~, llleach subsequent clock pulse occu~ring during receipt of the 2 lincoming serial data signal are passed by the NA~D gate 57 and are 31~centered on each of the corresponding incoming eight data bits.
4 At the end of each character, coincidence of outputs from 5 the dividers 48 and 49 at the inputs of a NAND gate 63 results in G the formation of a sampling clock p?lse. This pulse is inverted by 7 an inverter 64 and is applied to an~output lead 65 for use by the 8¦ poll decoding circuit of Figure 3. This output pulse occurs at the 9l end of the eighth data bit of the lncoming data character. The cycle then repeats. The flip-flop 4~3 is reset waiting for receipt 11 ~of the next start pulse. The time-out divider circuit 29 is reset;
l2 land the foregoing sequence of operation, commenced by the 13 Iresetting of the dividers 48 and 49 is repeated. A new character 14 then may be received by the system.~' 15j, The upper or clock input of the time-out circuit 29 is

16 ¦provided with pulses from one of the outputs of the clock pulse 7lldivider circuit 52. The number of st~ges of the divider circuit 29 8~lis selected to cause it to produce an output signal on its output 19l lead coupled to an inverter 68 if thère should be a failure of 20l activity on the polling signal lead 12 for some pre-established 21¦ time interval. Typically this time ii~n~erval is of the order of 22~ three or four seconds or the li~e~.~When the system is operating 23~ properly, serial polling input messages continuously appear on the 24l input lead 12. As a consequence, th~ flip-flop 43 is continuously 25~ set and reset to apply reset pulses~ to the reset input of the 261 time-out circuit 29 at regular inte~vals, which are less than the 271¦pre-established time-out period of the circuit 29.
28 ¦ If, however, serial data ishould cease to appear on the 29 lead 12 for any reason, even though all other parts of the system are operative and power is applied to it, the flip-flop 43 is not 3l set by start pulses applied to it from the output of the NOR gate 32 37. As a consequence, no reset pulses are applied to the time-out : ,~

113~3114 1 I circuit 29; and ultimately it reachqs a point where it supplies an 2 '! output signal to the inverter 68~ The inverter 68 in turn supplies 3 ~l its output to the upper one of two inputs of a NOR gate 70, which 4 is continuously enabled, to then produce a reset signal on the 5 lead 32. ~his signal is used to reset the relay latch and driver G circuits 21 (Fig. 1) in a manner described in greater detail in 7 conjunction with the circuit of Figure 4.
8 ¦ The reset signal on the ~'lead 32 also is applied to the 9 lower or reset terminal of the data latch flip-flop 39 (Fig. 2) to I cause its Q output to go low, therèby enabling the NOR gate 37 to 11 I continue to look for new incoming dàta applied to the system. This 12 is one of the ways in which the fli,p-flop 39 is set to enable the 13 system to respond to incoming polling input infomation. The other 14 I is that at the end of each message transmitted by the specific ~'5 i~ terminal under consideration, the flip-flip 39 is reset by an 16 1l end-of-message ~EOM~ pulse applied `to its clock input (CK) over a , ~,17 ¦1 lead 74 from the output of a isecond one of two cascaded 18 1 divide-by-ten binary dividers 75 and 76, respectively.
! Reference now should be made to Figure 3 which shows the 20 ¦ details of the poll decoder circult 20 of Figure 1. Whenever the 21 1 NOR gate 37 (Fig. 2l is enabled to pass the received serial data 22 ! signal stream, these signals, afte~r passing through the inverter 23 ~ 40, are applied to the lead 41 which serves as a data input to a 24 ¦ two-character shift register compri,`sing a pair of temporary 8-bit 25 ~I character storage registers 80 and 81, interconnected as a 16 bit 26 1l shift register. The shift pulses for operating the shift registers 27 ~ 80 and 81 (each of which is internally grouped into two groups of 28 ¦¦ four bits for purposes of description here) are obtained over the 29 ,, lead 58 from the output of the NAND gate 57 (Fig. 2) as described 30 above. Thus, the inputs to these registers cc~prise only the ùata 32 ,, ' -13-~,' I ~ ~

l~¦portion of the incoming message stream, in view of the fact that 2 1! the shift pulses on the lead 58 are inhibited from appearing 3 Iduring the start and stop pulse'i intervals of the received 4 Icharacters.
When a full 16 data bits have been sequentially shifted 6 into the registers 80 and 81, the right-hand four bits in the 7 register 81 then comprise the first four bits of the first 8 character. These bits are supplied to four inputs of a comparator 9 ¦circuit 84 for comparison with four /other pre-encoded reference 10 linputs which uniquely identify the particular terminal of the lllstation with which this control circuit is a part. The encoding of 12~ the reference inputs is accompli$hed by appropriate setting of 13~ four switches in a switch bank 86 to uniquely identify this 14 ! terminal to set it apart from alllother similar terminals which may be controlled by the same computçr 10.
16 j After each character has been received by the system, a

17 ¦¦ pulse is applied over the lead 65 fr~m the output of the inverter

18 ¦¦ 64 (Fig. 2) to an enabling input of the comparator 84. Upon

19 receipt of the pulse on the lead 65, the two sets of four inputs to the comparator 84 are compared. If they agree, a positive pulse 21 is applied over a start-of-message oitput lead 87. This pulse in 22 turn is applied to the set input ~f the data latch flip-flop 39 23 (Fig. 2) to cause the Q output of that flip-flop to yo high. This 24, disables the NOR gate 37, and n~ further polling input signal 25¦ pulses are passed by the NOR gate 37 t Thus, no further pulses' are 26l applied over the lead 41 to the shif~ register sections 80 and 81.
27 ¦1 At the same time since, this pulse occurs just after 28 ¦¦ receipt of character,~the flip-flo~ 43 is reset. Since no pulses 29 lare passed by the gate 37 for the du~ation of some further signal prl~cessing to be described subsequertly, the character 32 ... .

-14- !

_ , , , ~, _ _ , _ _ . _ _ _ , . .. , ,, . _ ,, . ,, ~ , . . . . .. .... , _ .

l counter 49 is disabled. As a res~llt, th~ r)7 ~n~ t~t 2I pass any further clock pulses over the lead 58; so that the 3 1l information for the two decoded characters in the shift register 4 ~80 and 81 is temporarily stored in th0 p(lsitiol~ it ~ )ie(l .~ tl-e time the comparator 84 produced the output pulse on the lead 87.
6 The second four bits of the!first character stored in the 7 section 81 occupy the left-hand four output positions of the 8~1register. The leftmost one of these bits is applied to the 9i~lowermost input of the NAND gate 92. This bit is always encoded O¦I"high", so that the pulse obtai!hed from the output of the 11 Icomparator 84, when a comparison is detected, is also passed by 12 the NAND gate 92 to its data clock output lead 90. This pulse 13 then is used to latch data into the four-bit latch circuits of 4¦ Figure 4 in a manner more fully described subsequently.
15l The other three bits of thisisecond portion of the first 16 1! character of the input message are applied to the three right hand 17 lower inputs of a binary to decima~ decoder circuit 93 which 181¦decodes the binary information coptained on these three outputs 9l into the corresponding one of eight different decimal outputs,

20~ SELA to SELH. The particular one of these outputs which is 2l¦ supplied with a positive or high out~ut potential by the decoder 22 93 designates the selection of the d~esired one of the eight groups 23 of relays identified by the encoding of the second four bits of 241 the first input message character. ~
The eight bits of the secondlmessage character storea in 2Gj the shift register section 80 each correspond to the selection of 27 1¦ the operating condition (on or off) Df the eight relays in the 28¦¦selected group of relays designate~ by the output of the decoder 29l circuit 93. None, or all, or any combination of the eight outputs 30¦ SELK 1 to SELK 8 may have a positive or enabling potential applied 31 to them from the outputs of the shif~ register section 80. Each of -15- ~

l l ,~

~38'114 1 I these outputs individually controls a selected relay through the 2 circuitry of Eigure 4.
3~j Reference now should be madq to Figure 4, which shows the 4~ relay driving circuitry and the verification circuit outputs from 5~ the relay drivers to the serializer circuit 25, descri~ed 6~ generally above in conjunction with Figure 1~ The circuit of 71 Figure 4 shows two of the eight relay groups which are selected by 8l the decoder 93 along with the relay driver circuits for the eight 9 relays of each of these groups (showing a total of 16 relay .
~I drivers in Figure 4). The other 9ix groups of eight relays each, 11 are all organized by pairs of groups in the same manner as those 12 ~ shown in Figure 4, but these additi~nal groups have not been shown 13 ! to avoid unnecessary repetition. It is to be understood, however, 4 I that each of the remaining six groups of relays are organized in S~¦ two group units identical to the unit shown in Figure 4 and are 611 similarly selected by different aqdress codes in accordance with '~ `r 17l~ the output of the decoder circuit 9~ (Fig. 3).
- ~ 18¦ The control of the turning on and the turning off of the 191 relays is effected by four-bit binary latch circuits 100, 101, 102 and 103. The latch circuits 100 and 101 each control four relay

21 ¦ driver amplifiers for a total of eight amplifiers in relay group

22 ¦ A. Similarly the latch circuit~02 and 103 control the eight

23 relay drivers for the relay group B.~ The selection leads SELA and

24 SELB from the output of the decod~ 93 (Fig. 3) are applied to a 2S~ respective pair of inverters 106.~ and 107 for enabling the 26 1! respective two groups of latch ci,,rcuits 100, 101 or 102, 103 in 27 1 accordance with the output of the decoder 93 of Fig. 3.
28 I The A and B selection inp~ts also each are applied to a 29 pair of two input NAND ~ates. THE SELA input is connected to the upper input of NAND gates 109 and 110. Similarly the SELB input is 31 connected to one of the inputs of each of the NAND gates 112 and ,~' ~
-16- ~

i 1138~14 l 113. The other input to the NAND gates 109 and 112 is the S3 2 output of the divide by 10 group selection divider circuit 76, and 3I the other input to the NAND gates 110 and 113 is the S4 output of ~¦ the divider circuit 76 of Figure 2. The operation of the NAND
5¦~ gates 109, 110, 112 and 113, in conjunction with a pair of dual G~ section gating circuits 120 and 121, is described subsequently in I conjunction with the operation of the system when it is supplying 8 ¦ a serial verification signal back to the computer 10.
,~ As is readily apparent from an examination of Figure 4, 0l the eight outputs from the second character storage stage 80 of 2 the shift register 80, 81, are applied to the respective latches I of each of the two groups shown in Figure 4 (similar connections 13 are made to the latches for the other groups of relays, which are ]4 !I not shown) No change in the status of any data stored in the ~latch circuits 100 to 103, however, is made unless these latch ;116 I circuits are specifically addressed or enabled by the outputs of 17jl their corresponding inverters 106 and 107. For example if the SELA
8 1¦ lead has a selection signal applied to it from the decoder 93 . (Fig. 3) the output of the inverter 106 is such that it enables the four bit latches 100 and 101 for operation upon receipt of the ! next data clock or data storage pulse on the lead 90. As described 22,l previously, this pulse is obtained from the output of the NAND
3~l gate 92 of Figure 3 when the particular control console with which 24 1l these groups of relays are associated is identified and selected

25 ~ by the poll decoding circuitry shown in Figure 3. When this pulse 2G 1il appears and is applied to the enabled binary latches 100 and 101, 27 Il, the latches are set to store selectively the relay operation (on 28 11 or off) information applied to them over the input leads SELK1 to 29l, SELK8. The outputs of the binary latches then either remain the 30~ same as they were previously, if there is no change in input data, 31 or they change to reflect the change in input data. These output 1138~14 1~lare applied to the corresponding bank of relay driver amplifiers 2I for the sel~,~cted relays shown on the right hand side of Figure 4.
31 The relay driver amplifiers then selectively operate or turn off 4 selected ones of the system relays 22 (Figure 1) in accordance with the system operation. The particular relays which are enabled 6 depend upon which one of the different groups of latch circuits is 7 selected by the selection signals ~rom the output of the decoder 8 93; and in addition, upon the status of the individual relay 9 Iselection information supplied to the latch circuits from the lol outputs of the shift register stage 80, connected in common to all 11¦ of the latch circits for all of the~eight groups of relays at the 121 particular station location involved~
13 The operation of the counters 75 and 76 shown in Figure 2 141 now should be considered. The counter 75 comprises a bit scanning 15l counter and, in conjunction with~ the operation of a character 16 1i scanning counter 76, determines the ~equence of the verification 17 !I data supplied back to the computer 10 over the lead 27. As 8¦ described previously, the counters 75 and 76 are reset by the 19 ! output of the data latch flip-flop 39 when it operates in response 201 to a start-of-message signal supplied to it from the output of the 21¦ comparator 84. The counter 75 then ls permitted to advance in its 221 count under control of the output of¦the bit counter 48 by pulses 23 applied to it over a lead 130. ~ ~
241 Initially, the counter 76 3also is set to supply an 25~ enabling output over its S1 lead. This lead is applied to the S1

26~1enabling input of a dual-section coincidence gating circuit 135

27,¦(Fig. 3) to cause the four parallel outputs of the gating circuit

28 ¦1 135 to correspond to the address or station identification

29 linformation set by the switches 86. This information is applied

30~ over the four output leads B1 through B4 to the lower inputs of 32 ~the serializing gating circuit 25 (Fig. 2). As the bit counter -18- l .~

1 ~divider circuit 75 is advanced in its count, it causes the gating 2llcircuit 25 to incorporate these four bits of information with 3Ijadditional bits of information (which are always constant) into 4~ serial ASCII encoded characters. The circuit 25 serially applies 51 the characters to a buffer amplifier output transistor 137, the G collector of which is connected to the verification signal output 7 lead 27. ;
8 After the first verification character has been 9 ~transmitted in this fashion, the counter 76 advances to its next lOIlcount and enables the S2 output. This output also enables the ~ lower section (section B) of the four input dual gating input 12l!circuit 35 to connect its output with the four inputs 13~lcorresponding to the relay group binary encoded information. This 14linformation then is supplied to `the leads B1 through B4 and 15~lencoded serially in the ASCII code in the same manner as the first ]G !group of four bits. ~
171¦ Similarly when the S3 step i~ reached by the counter 76, 18 ¦the gates 109 and 112 are enabled and, depending upon which group 19 of relays has been selected, one or the other of these gates (or a similar gate for one of the relay groups not shown) passes an 21 enabling signal to the "A" section o~ a respective dual section 221 coincidence gate 120 or 121. If re~ay group A has been selected, 23¦ the gate 120 interconnects the four outputs from the latch 100 241 with the gate outputs during thi$ time interval. These outputs 251 then are serialized as de~cribed aboye. After this character count 2G 11 has been completed, the divider 76 moves to its next count, 27 1! enabling output S4 The S4 output applied to the gates 110 and 113 ~8l¦of Figure 4 then enables the corresp~nding B section of one or the 29 i1 other of the gates 120 and 121 in iaccordance with which relay 30~¦group is selected. This then interconnects the binary latch

31 outputs for the second four relays of the selected groups to the ~2 outputs o~ he gate: and, for a s~lected group A, causes the . . ~/

113hll4 1¦~outputs of the latch circuit 101 to be interconnected by the qate 2~120 to the B1 through B4 outputs for serializing, as described 3Ipreviously.
4 After this character has been fully serialized under control of the counter 75, the character counter 76 then moves to 6 step 5 producing an output pulse on lead 74. This causes an 7 end-of-message (EOM) output pulse to be obtained from an inverter 8¦ 140 (Fig. 2) and this pulse is appli~d to a NOR gate 141 (Fig. 3) 9~ to reset or clear the shift registers 80 and 81 to an initial 10¦¦condition. Thus, all of the outputs which previously were used 11 from these registers to effect ~he relay group and individual 12 ¦relay selections, along with the poll decoding output are removed 13 ¦from the system. ~
14 At this time, it also should~be noted that when operating 15 ~power is first applied to the system, precaution must be taken to 16 linsure the system relays 22 are off or inoperative. This is 7l1accomplished through the signal applied on a "power up" (PWRUP) 8~¦lead 145 connected to the lower inpu~s of the gates 70 (Fig. 2) 19 and 141 (Fig. 3). This signal is delayed by an integrating circuit 146 to insure reset pulses are applied to the shift register 80, 21 81 and the reset lead 32 when the sy8tem initially is powered up.
22 The pulse appearing on the l~ad 74 also is applied to the 231 clock input of the data latch flip-flop 39 to cause it to change 241 state, thereby removing the inhibiti~g output applied to the lower 251 input of the NOR gate 37 to permit~the NOR gate 37 once again to 261 pass the serial data polling signals appearing on the polling 27l input lead 12 from the computer 10.'The system then processes the 28~1information in the same manner described above. If the polling 29~signal indicates some change in `the data for the particular ~V!¦control console or station involved,~,the changed data is stored in 31 ¦the shift register sections 80 iand 81 and is decoded to

32 Icorrespondingly change the state of the latch circuits of Figure 4 ''~,' ~20~
;~,: ll _ - $ ~

1138~14 i~ ' .;
11leither to turn on previously turned off relays or vice versa. The 2 1I system continuously operates in-this manner to update the state of 3 joperation as demanded in accordance with th~ n1ls a~>~liccl t~ it ~ over the polling signal input lead 12.
5 ~ Each time information is r decoded and updated by the 6 system, a full verification signal is sent back serially over the 7 ¦lead 27 under the control of the operation of the bit and 8 ¦character counters 75 and 76 of Figure 2. If there is a failure of 9 verification of the received data with the transmitted data at the 10 1computer 10, appropriate action can be taken automatically or by 11 manual intervention at the computer to correct the defect. This 12 1may be in the form of a set of signals sent over the polling 13 signal line 12 to turn off all of'the relays at the station for 14 which verification was not received. Another approach, which 151 optionally may be utilized, is to retransmit the original polling 16 linformation; and if verification then is obtained, to go ahead and ~¦operate in a conventional normal manner. If there is a second or a 18 ¦I third failure of verification, the system then can be placed in an 19 alarm mode to permit appropriate action to be taken.
Continuously during the above mentioned normal operation of the system, the time-out dividerl~ircuit 29 is reset each time 22 the start bit detection flip-flop 43j~s set after detection of the 23 presence of a start bit in the output of the data signal supplied 24 ¦through the NOR gate 37. The compute~ 10 operates continuously to 2S 1l poll and monitor the various station consoles in the system of 261 which the circuit shown in Figures 2; 3 and 4 is associated at 271 time intervals selected to be less than the time-out period of the 28 1 time-out divider circuit 29. If for ~ome reason there is a failure 2911at the computer 10 to transmit polling information at such regular 30~ intervals, the time-out divider c1rcuit 29 is permitted to 31 time-out and cause the application of a reset signal on the output 321 lead 32. Whenever this reset signal ~ccurs, it is applied to a ~, ~

~1 21 j 113~14 ., 1 reset input of each of the lat~h circuits 100 through 103 of 2 1I Figure 4. This places the latch circuits in a state to render 3 'inoperative or to turn off all of the relays operated by the relay 4 driver circuits connected to the outputs of the latch circuits.
This signal overrides the other signals applied to the latch 6 circuits 100 to 103, irrespective of the state of the operation of 7 the remainder of the system.
8 Even if the particular station which is illustrated in the 9~ drawings is not selected by the poll detector comparator 84 (Fig.
3~, the setting of the start bit qetector flip-flop 43 under 11 ¦control of the output signals f~om the NOR gate 37 and the 12 operation of the bit rate and character rate counters 48 and 49 13 ¦continuously resets the time-out circuit 29 to prevent any change 15 ¦in the status of the relays controlled by the particular station , ~ ~console shown. So long as there is polling activity on the polling lG linput line 12, the system operates in a normal fashion. Only if 17 Ithis activity fails to exist for a pre-established period of time, ¦¦is the time-out divider circuit 29 p~rmitted to operate to shut down or turn off the relays of the system in an alarm condition.
The system which has been described above in conjunction 21 with the schematic diagram of a preferred embodiment is to be 22 considered illustrative of the inve~tion and not limiting. It 23 operates to provide continuous verification of the polling signal 24 ¦data in a serial mode for the computer 10; so that the received 25 ¦information, as decoded by the sy~tem, is continuously compared 261¦with the transmitted information. If a discrepancy exists, 27 11 appropriate action can be taken.`Similarly even though a power Z8 1l failure may not occur at the l~cal station consoles being 291 controlled by the signals from ~he computer 10, the system 30~ operates to place all of the relays or utilization circuits 31 controlled by all of the consoles in a "fail safe" or "off"
32 condition of operation if activity from the computer is not . ;,,, -22- l 1138 ll4 1 continuously present for some mini~um time interval. The time 2 interval which is utilized in any particular system may be varied 3 in accordance with the desired oper~ating characteristics of the 4 system. Various modifications or v,ariations of the implementation 5 of the features of this invention w,hich have been described in conjunction with the above preferr~d embodiment will occur to thos~
7 skilled in the art without departing from the true scope of ~the inventio 12 .

.

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22 .~ t 2~

28 `

~2 ~ 3~ L

Claims (10)

1. An electronic control system having a central source of control and polling signals interconnected with a plurality of controlled terminal locations, the controlled terminal locations including in combination:
utilization circuit means at each controlled terminal location identified by a unique polling signal and having a control signal input terminal and responsive to signals applied thereon to be selectively rendered operative or inoperative thereby;
polling signal decoder means at each controlled terminal location for said utilization circuit means and having an input and at least one output terminal, and responsive to the unique polling signal identifying the controlled terminal location in which said polling signal decoder means is located when such unique polling signal is applied to the input terminal of said polling signal decoder means to produce an output signal on the output terminal thereof;
driver circuit means at each controlled terminal location connected between the output terminal of said polling signal decoder means and the input terminal of said utilization circuit means for such terminal location to selectively render said utilization circuit means operative or inoperative in response to the signals on the output terminal of said polling signal decoder means for such terminal location;
polling signal supply means coupled to the input termin-als of all of said polling signal decoder means for applying polling signals thereto from the central source; and separate control circuit means at each controlled termin-al location coupled to receive signals from said polling signal supply means and coupled to one of said driver circuit means and said utilization circuit means at such controlled terminal location for rendering said utilization circuit means at only such controlled terminal location inoperative in response to the absence of the receipt of polling signals by such control circuit means for a predetermined time interval from said polling signal supply means; each of said control circuit means at each of said controlled terminal locations operating independently of the control circuit means at other controlled terminal locations.

2. The combination according to claim 1 further including additional circuit means in each controlled terminal location, said additional circuit means coupled with at least said polling signal decoder means at the same controlled terminal location for supplying signals to the central source of control and polling signals indicative of the state of operation of said polling signal decoder means for such controlled terminal location.

3. The combination according to claim 2 wherein said additional circuit means is further coupled with the output of said driver circuit means for supplying signals representative of the state of the output of said driver circuit means to the source of control and polling signals.

4. The combination according to claim 1 wherein each of said control circuit means comprises a time-out circuit; and further including a source of clock pulses coupled to said time-out circuit for causing said time-out circuit to produce a reset signal on the output thereof after a predetermined time interval the output of said time-out circuit being connected to said one of said driver circuit means and said utilization circuit means at the controlled terminal location at which said control cir-cuit means is located for rendering said utilization circuit means inoperative whenever said reset signal appears, said time-out circuit having a reset input coupled with said polling signal supply means for resetting said time-out circuit in response to the presence of polling signals from said polling signal supply means to prevent reset pulses from appearing on the output of said time-out circuit.

5. The combination according to claim 4 wherein said time-out circuit is coupled with said driver circuit means.

6. The combination according to claim 1 wherein said polling signal decoder means at each of controlled terminal locations has a plurality of output terminals; and further including a plurality of utilization circuit means; and a plurality of driver circuit means, each driver circuit means comprising binary latch circuit means operated in response to signals appearing on different output terminals of said decoder means for selectively rendering operative and inoperative the utilization circuit means connected to said binary latch circuit means.

7. The combination according to claim 6 wherein said control circuit means comprises a time-out circuit means; and further including a source of clock pulses coupled to said time-out circuit means for causing said time-out circuit means to produce a reset output pulse on the output thereof after a pre-determined time interval, said time-out circuit means having a reset input coupled to said polling signal supply means to cause said time-out circuit means to be reset in response to the presence of polling signals which normally occur at time inter-vals less than said predetermined time interval; and means coupling the output of said time-out circuit means to said driver circuit means to render said utilization circuit means inoperative whenever said reset output pulse is produced by said time-out circuit means.

8. The combination according to claim 7 wherein the output of said time-out circuit means is coupled with reset inputs of all of said driver circuit means at only the controlled terminal location in which said time-out circuit means is located for causing the output of said driver circuit means to render all of said utilization circuit means at such controlled terminal location inoperative in response to the occurrence of a reset pulse from said time-out circuit, irrespective of the state of the signals applied to said binary latch circuit means by said polling signal decoder means.

9. The combination according to claim 8 further including additional circuit means coupled with at least said polling signal decoder means, and having an output connected to said source of polling signals, for supplying signals representative of the operation of said polling signal decoder means to said source of control and polling signals.

10. The combination according to claim 9 wherein said additional circuit means is further coupled with the output of said binary latch circuit means for supplying signals to said source of control and polling signals representative of the state of operation of said binary latch circuit means.