CA1135419A - Remote verification lockout system - Google Patents

Abstract

ABSTRACT

A remotely controlled verification lockout of the verification memory used in conjunction with fuel dispensing systems, service dispensing systems (such as automatic bank tellers), and the like is provided. At each user location, a verification memory is provided in which a single binary data bit is stored at each different verification address location. Each document or credit card used with the system has unique identifying information encoded on it for addressing a specific location in the memory which corresponds to the verification check for that credit card. Provision is made for automatically initializing the status of all of the information stored in all of the verification memories in the system by the transmission of an initializing signal to those memories from a central processor by way of suitable communications lines. In addition, on a periodic basis or at irregular intervals a change in the status of any address location in the verification memory may be effected by the central processor transmitting a control character which is decoded by logic at the fuel dispensing station to place the verification memory in its "write" mode of operation. This character then is followed by the addresses of the various memory locations which are to be changed or updated, and those addresses are changed accordingly. Thus, each of the different memory locations which are to be changed are individually addressed to establish the "valid" or "non-valid" binary data bit storage at the location corresponding to the different credit cards for which the verification memory status is being changed.

Description

~L13541~3 ca~e No. '124l.29 3 I Related Patent 4 I The subject matter of this application is related to the system disclosed in the patent to John Kubina, no. 4,114,140, 6 issued September 12, 1978 and assigned to the same assignee as the 7 present application.

9 IBackground of the Invention 101i The Kubina patent no. 4,114,140 is directed to a system for checking the validity of a credit document quickly and easily 12 11 at the location where the document itself is used and which 13~lfurther requires a minimum memory capacity in order -to effect the necessary document check. The system of the Kubina patent is used 15~ with an automated product dispensing system for dispensing products such a fuel for large fleet users or for priva-te owners.
17!¦SUch systems are also used for effecting bankin~ transactions 18 1I during hours when banks normally are closed and Eor other types of 1 19 ¦I credit card operated systems. ~enerally in such sys-tems, a card 20 1 reader control panel or control station is employed; and the 21¦ transaction is initiated by an insertion of an identified credit 22 ¦ card into a card reader by the customer or user of the system.
I 23 Such cards are uniquely encoded with indicia particularly 24 lidentifying the customer or user and, in many cases, include other 25 ¦ indicia to limit the type and quantity of product which may be 26l~lPurchased or withdrawn from the system in response to the use of 27l!the card.
28 11 In the system disclosed in the Kubina patent, at least 2g¦lsome of the data on the card used with the system is employed for ~verification of the validity for use of that card to conduct the 31 ~desired transaction. In the Kubina system, such veriEication is 32 ~
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1~35~L~9 1 done locally at the user terminal. Each card is uniquely

2 ¦identified with a verification binary word ~typically a four-bit

3 word) which identifies the card. This word then is compared

4 against the same word stored in a memory where it is then identified as being either "valid" or "non-valid" for conducting 6 the transaction. Often it is necessary for the status of a card 7 used with a system to be changed from a "valid" to a "non-valid"
8 status for various reasons. If a credit card is stolen, the 9 identity of that card must be changed in the verification logic of 10llthe system -to a "non-valid" status; so that it cannot be used to 11 ~carry out transactions with the system. Other situations arise 12 Isuch as where a customer falls behind in payments, so that it 13¦ becomes necessary to prevent that customer from using the system ~ luntil his account is satisfactorily brought up to date.
15~l The Kubina patent discloses a system for permitting the 16jl verification logic to be changed to indicate the "non-valid"
'71 status of specific cards or customers used with the system whenever desired. In the ICubina system, however, the status 191 change is effected by manually setting switches associated with 201 the verification memory at the fuel dispensing site or utilization 21~ site where the memory is located. If there are a large number or 221 potential sites at which the card which is to be "locked out" may 231 be used, it is necessary to manually effect the verification 24l lockout setting with the memory at each one of these different 25~l sites or locations. If changes in the status of cards used with 26j, the system occur infrequently, such an "on site" manual setting of 27 1l the verification logic is not particularly inconvenient.
28 ¦1 If the locations are widely dispersed, however, or if 29 1l frequent changes in the validity status of cards used with a 0 I system become necessary, it is desirable to effect a change in the 31 ~ verification lockout memory from a central location. Ideally, 32 ~

'I 1, 1 such a change in the lockout memory file should be effected 2 automatically on command from a central remote location as 3 frequently as becomes necessary during the use of the system.
4 1This is particularly desirable in conjunction with fuel dispensing systems where the fuel dispensing locations are scattered over a G large area and which may involve thousands of individual cards and/or customers using the system at any given time.

9l Summary of the Inventlon 101 Accordingly, it is an object of this invention to provide 11 ~an improved verification checking system.
12 j It is another object of this invention to provide an 1 13 1improved credit card verificatlon system ln which the veriEica-tlon lfi Imemory is easily updated.
It is an additional ob~ect of this invention to provide a 16,lsimplified credit card verifica-tion checking system in which the 17 11l verification memory may be remotely modified.
18 1¦ It is a further object of this invention to provide an 1911improved, remote updating of a verification memory used in conjunction with a credit document verification system for 21 effecting unattended business transactions.
22 In accordance with the preferred embodiment of this 23 invention, a verification checking system for providing a 24¦~verification check of uniquely encoded multi-bit binary words sllincludes a read/write verification memory. ~his memory has a 261 number of address locations in i-t for uniquely storing a "valid"
27 1 or "non-valid" indicia corresponding to each of the different 28 1I multi-bit verification words usecl in conjunction with the system.
2~ 1! A mode controlling switch and an address decoding circuit are 30 ¦1 employed in conjunction with the transaction verification memory 31 I and respond to verification updating messages transmitted from a ~3_ !l ~3~

remote central location to uniquely change the verification data of different address locations in the veri~ication memory.

More particularly, there is provided: :
A system for providing ~ veriication check of uniquely encoded multi~it binary words at a plurali~y of remote locations~ the system having a central station for supplying address signals and verification Uvalid/non-valid'' control signals through a transmission link interconnecting said central station with each o~ said plurality of remote locations t each of said re-0 mote locations including in combination:read/write memory means having a plurality of address locations therein, each address location storing a sinyle binary bit indicative of the "valid/non-valid" status of the item represented by each such address location, said memory means further having a single output on which an output signal is produced corresponding to the binary bit stored at the address location selected in said memory means;
lockout utilization means coupled to the output of said memory means and operated in response to output signals 0 appearing thereon;
address control means operated in response to addres-sing signals and coupled to said memory means for selecting particular address locations for the writing of bits into and the reading of bits from those address locations of said memory means;
read/write control means coupled to said memory means and further coupled with said transmission link and responsive to signals applied thereto from said central station over said transmission link for controlling the read/write mode of opera-tion of said memory means and for supplying said verificationcontrol signal~ to said memory means to selectively change the "valid/non-valid" status of the binary bits stored in said memory means when said memory means is in the write mode of operation;
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gating circuit means having a plurality of inputs and having ~utputs coupled with said address control means for supplying ~aid addressing signals thereto;
address decodiny means ~oupled to selected inputs of ~aid gating circuit means and further coupled with said trans-mission link and responsive to address signals supplied thereto from said central station over said transmission link for supplying address input signals to said gating circuit means;
further circuit means coupled to others of the inputs of said gating circuit means for supplying input addressing signals thereto; and selecting means coupled Wit]l said read/write control means and operated thereby and further coupled to said gating circuit means for causing the signals appearing on th~ out-puts of said gating circuit means to be selected from the input signals from said address decoding means or ~he input signals from said further circuit means~ thereby causing the signal on the output of said me~ory means to correspond to the binary bit stored at the address location selected by the addressing signals from said gating circuit mea~s.
Brief Description of the Drawings Figure 1 is a block dia~ram of a prererred embodiment of ~he invention; and Figures 2, 3, appearing with Figure l, and 4 are de-tailed block diagrams of a portion of the embodiment shown in Figure l.
Detailed Description The system shown in Figure 1 is a modification to the system shown in Figure 1 of the above mentioned ~ubina patent 4,114,140 which permits the validity che~k losic ~ortion OL the system of the ~ubina patent to be remotely update~ on demand from ~':
~4a-a central processor. The local operation of the system of the '140 patent is otherwise the same. Conse~uently, the system shown in Figure 1 adds additional flexibility to the system of the '14 patent, particularly where a large number of fuel dispensin~
l~cations, all programmed for use with the same set of customers, are employed.
In the system of Figure 1 all of the data from the different outlying fuel dispensing ter~inals are transmitted through a central processor modem 10 to a cen~ral processor ,1 which is conveniently located for ~athering in all of the accounting data, etc. from the various product dispensing terminals with which the system is used The central processor 11 may be any suitable printer with keyboard and/or ger.eral pur?ose computer and the necessary peripheral equipment, such as a keyboard and printer 12 shown ln Figur.e 1. Interaction betweer.
the keyboard and printer 12 and the centr.al processor 11 for the enterins of data into and the obtaining of data fro~ the central processor 11 is effected in a conventional manner. lhe modem 1~

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I then ma~ be ~sed in conjunction with a manual ~r automatic dialer 2 11 to dial a conventional telephone line or the like corresponding to 3 l any one or more of the outlying fuel dispensing system locations, 4 or to interconnect the central processor 11 with a specific fuel dispensing location by means of a dedicated line. Such modems and 6 dialers are conventional, and for that matter have not been 7 disclosed in detail in Figure 1.
8~ At each of the fuel dispensing terminals used with the 9il system is another modem 15 which similarly is used to interconnect 10ll the fuel dispensing terminal with which it is associated with the ll i modem 10 at the central processor terminal. The interconnections 12 between these modems 10 and 15 are indicated as two way 13 I interconnections, since data is transferred in both directions ~ between the modems 10 and 15.
15'l As is explained in the disclosure of patent number 16 ll 4,114,140, a transaction verification memory for determining the 17 1l "valid" or "non-valid" status of any card used with the system is ]~l employed for conducting a validity check on each carcl or set of 19 cards at the beginning of each transaction. This memory is indicated as the transaction verification memory 17 in Fi~ure 1.
21¦ Preferably the transaction verification memory 17 has a single bit 22¦ location corresponding to each 4 bit or multi-bit verification 23 ! word encoded on the cards used with the system. The memory 17, 24 however, also could store the entire verification designation, if 25 1I desired. This later approach, however, is wasteful of memory and 26 I generally is not likely to be employed.
27 ¦I For the purpose of updating the "valid" or "non-valid"
28 ¦I status of various credit documents or credit cards to be used with 29 I the system, the central processor 11 either periodically or on 30~ demand transmits a verification memory update to the desired 3I terminals or terminal for changing or upclating the verification

-5 113541g l! status of the validity chec]c information stored in the transaction 2~¦verification memory 17. When this information is received by the 3l modem 15 and translated through it, it is applied first to a mode 4~ control switching circuit 19 which places the transaction 51 verification memory 17 in its "write" mode of operation. The G ~address codes for the~addresses to be "locked out" or otherwise 7 modified in the transaction verification memory then are 8 Itransmitted sequentially from the central processor 11 -through the 9 Imodems 10 and 15 to an address decode logic circuit 20, which 1Oj specifically addr~sses the transaction verification memory 11 llocation corresponding to that address in a conventional manner.
12 IThe information then is written into the position of the 13 ¦I transaction verification memory 17 corresponding to the selected ]l~l address. The transaction verificat:ion memory 17 can either be selectively updated to change speciEic addresses of the "lock out"
16 I file, or the entire memory may be updated, dependin~ upon the 17 1! particular requirements of the system. The remainder of the system logic for operating in conjunction with the transaction 19¦ memory 17 is shown as a system logic bloc~ 25, and additional details of that logic are shown in Figures 2, 3 and 4. The system 21 logic interfaces with the transaction verification memory 17 and 22 also supplies the transaction information to the modem 15 for 23 transmittal to the central processor 11 in accordance with the 24 I particular system req~irements. The manner and times of 25 I transmission of this data are not important to an understanding of 2G the remote control of the lock out verification of the transaction 271 verification memory 17.
28l Reference now should be made to Figure 2, which 29 I illustrates the control portion of the validity and check logic 30 ~ circuit used in conjunction with the transaction verification 31 ¦ memory and which forms a portion of the system logic 25 of Figure

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1 1. This circultry is used to establish the different modes of 2~ operation of the validity check logic in conjunction with the 3 transaction verification memory 17. The system operating mode 4 primarily is controlled by the mode control switch 19, which is illustrated as a single-pole, double-throw switch 35. This is an 6 electronic switch "moved" to its upper or "set" position for

7 preparing the initial condition of operation of the transaction

8 verification memory 17 associated with the validity check logic

9 Icircuit portion of the system logic 25, and for subsequently

10 Isetting data into specific locations of addresses of the memory 17

11 ¦or for checking the status of the data stored at specific memory

12 laddresses. The mode of operation of the switch 19 is established

13¦ in conjunction with a mode control code transmitted from the I~l central processor throuyh the modem 15 and decoded by logic (not ` ~ 15l shown since it is conventional) in the mode control circuit 19 to :' ?6 11l operate the electronic switch 35, to the appropriate "set" or 17 1l "normal" operating position.
18jl ~hen the switch 35 is in its lowermost position as shown 191 in Figure 2, this is the normal operating position for the system 20 I and it is used to place the memory 17 used in the verification ~ 2l I circuit in a read only memory (P~OM) mode of operation. This is 1 22 ¦ accomplished by a pair of EXCLUSIVE OR gates 36 and 37, which are 1 231 cascaded to the upper terminal of the switch 35. The ~ate 36 has 24 ¦ one input connected directly to this upper terminal and the other 25 ¦ input obtained from the "Q" output of a control flip-flop 38.
26 I Normally this output is low; so that in the normal mode of 27 ¦1 operation both inputs to the EXCLUSIVE OR gate 36 are low, causing 28 ¦1 its output also to be low. This results in a high output from the 29 I gate 37 and the outputs of the gates 36 and 37, labeled ESET and 30 ! ENORM thus are low and high, respectively.
31 These outputs are applied to the "A" and "B" control _7_ inputs of four switch gates, 40, 41, 42 and 43 (Fig. 3), each of l~which functions as a four-pole, double-throw switch to 3 ~alterntively interconnect either the upper four inputs of each of 4 these switches with the four outputs thereof or the lower four inputs with the four outputs under control of the state of the 6 outputs of the gates 36 and 37. Whenever a high or positive 7 output appears on the ENOR~ input to the switch gates 40 to 43, 8 1the lower four inputs are connected with the respective outputs of 9 Ithe gates. Similarly whenever a high input is appliecl to the "A"
inputs (ENSET) of these four gates, the upper four inputs of the 11 ¦gates are interconnected with their respective outputs. Thus, for 12 Ithe normal mode of operation of the system, the lower four inputs 13 lof the switch gates ~0 to 43 are interconnected with their ~ outputs.
15 Il Now assume -that the system is first brought into If~loperation, requiring an initial set of condit:ions to be 17 ll established in the verification logic system to permit its ¦~programming for performing subsequent credit card verification Ichecks. The switch 35 then is moved from its lowermost (NOR~) operating position to its uppermost (SET) position (as shown in 21 Figure 2). This is accomplished in response to a transmitted 22 verification logic update mode control word from the central 23 processor ll. When the switch 35 is in this condition of 24 operation, a positive potential is applied to the upper input of 25 ¦1 the EXCLUSIVE OR gate 36 which initially reverses the condition of 26 !I the outputs of the gates 36 and 37 from that descrihed previously.
27 ¦I To "initialli~e" or set up these beginning operating 28 1I conditions a bank of ten read~write memories 45 through 54 (Fig.
29~ 4) are programmed to store the same binary condition at each 30 ¦address location in the memory. Each of these memories 45 through 311 54 comprises a l000 bit memory, and each bit is separately and ~135~i~

1 uniquely addressed by signals appearing on ten address leads 2 1l illustrated in Figure 4 in two sets, A0 through A4 and A5 through 3 11 A9, respectively. The signals on these address leads are supplied 41 to the memory from a BCD-to-binary converter 56 (Fig. 3), which in turn is provided with input signals from the twelve output leads 6 of the switch gates ~l, 42 and 43. The outputs of the 7 BCD-to-binary converter 56 are capable of lO00 different 8 combinations to uniquely address each of the lO00 memory positions 9 of each of the memories 45 through 54. Selection of the 101lparticular memory to respond to the addresses on the leads A0 111 through A9 is effected by the outputs of the switch gate 40 which 12¦ are applied to a BCD-to-decimal converter circuit 58 (Fig. 3).
13¦ The BCD-to-decimal converter circuit 58 has ten outputs, supplied

14 Ithrough buffer invertin~ amplifiers to provide a memory selection

15 'output on one of ten leads MO throuc~h ~19 at any given time, in ~response to the outputs of the gate 40. Thus, the combination of 17!¦the outputs of the BCD-to-binaxy converter 56 and the 1~ ¦BCD-to-decimal converter 58 are capable of uniquely selecting any 19 I one of the lO,000 aifferent address locations in the ten lO00-bit memory chips 45 through 54.
21 To ini~ially set the system to store all "valid" or all 22 "non-valid" verification information in all of the memory 231j locations in all of the memories 45 through 54, an initiallizing 24 1l switch 60, illustrated as a single-pole, double-throw switch 25~j (although ideally this is an electronic switch) is operated, in 261¦ response to an initializing signal received Erom the central 27 I processor ll through the modem 15, by moving from its normal 2~ ~ unconnected central location to momentarily contact either its 29 upper contact (initialize "valid") or its lower contact (initialize "non valid") to suppl.y a momentary positive pulse over 31 the selected lead. Whichever of these conditions is selected, a _g_ I' 11;~5q~

1 pulse is passed by an OR gate 61 to triyger the set input of the 2 ~ flip flop 38 to cause its "Q" output to go high. This then causes 3 the condition of the outputs of the EXCLVSIVE OR gates 36 and 37 4 to be low and high, respectively, which is the same condition of operation as exists for normal operation of the system, as 6 described previously.
7 The normal output condition of the flip-flop 38 is for lts 8¦ "Q" output to be low; so that when this output goes high, a clock 9 pulse is applied to the clock input of a one-shot multivibrator 65 10 I to trigger it to its astable condition of operation. This causes 11 a short duration positive pulse to appear on the "Q" output of the 12 I multivibrator 65; and this pulse is applied to the reset counter 13 ¦ input, RSCTR, of a jam input counter comprising four 4-stage I cascaded digital counters 66, 67, 6~ and 69 (Fig. 3) to set all Or 151 these counters to the zero count or zero state oE operation. In

16 1 other words, thc initial pulse from the output of the one-shot

17~ multivibrator 65 is used to cle~r the counters 66 to 69. These 181 counters normally are operated in a serial mode (jam inputs 19¦ disabled) since the jam enabling inputs ENTRA and E~TRB are at a 201 "low" potential.
21¦ This same pulse is applied to the set input of another 22l one-shot multivibrator 71 to trigger it to its astahle condition 23 f operation. This causes a short duration positive-going pulse 2~ to be applied through an OR gate 72 to a pair of NOR gates 73 ancl 74. At the same time Q output of the mode of the multivibrator 71 26 1l switches from its normally high output to a momentarily low output 27 1¦ pulse. At the end of the time out period of the multivibrator 71, 28 ¦I the Q output goes high to trigger a cascadecl one-shot 29¦¦ multivibrator 76 into its astable condition of operation. The Q
~,¦¦ output of the multivibrator 76 is connected to the cloc]c input of ~3~

1 the multivibrator 71, and together they function as a free runnlng 2 pair of multivibrators once the initial trigger pulse has been 3 ~applied to the multivibrator 71 from the mul-tivibrator 65.
41 Each time the multivibrator 76 is triggered into its 5 ¦1 astable state of operation, a high output pulse of short duration ~¦appears on the "Q" output of -the multivibrator. this comprises 7 the clock pulse (CLCTR) to the counter, and this pulse is applied 8 to all of the counters 66 through 69 to operate these counters as 9 la conventional BCD counter, with the counter 66 comprising the 10~1input stage since its signal input terminal is permanently grounded. Thus, the counters 66 though 69 operate to count the 12 ~ 10,000 pulses, corresponding to the 10,000 addresses for the 13 ¦memory units 45 through 54. The outputs of the counters 66 l4~ through 69 are applied to the switch gates 40 through 43 and are coupled to the outputs of these gates since the Olltput of the ]6li EXCLUSIVE OR gate 37 is high at this time and the output of the '7~1 gate 36 is low.

18¦ As described previously, the outputs of the switch gate 40

19 are applied to the BCD-to-decimal converter 58 to select one of the ten memories 45 through 54 (Fig. 4) to respond to signals on 21 the address leads. The outputs of the gates 41 through 43 are 22 applied to the 12 inputs of the BCD-to-binary converter circuit 56 23 which in turn produces the unique combinations of outputs 24 necessary to select any one of the 1,000 different address or 25 ¦ address locations ir. each of the memories 45 through 54.
26 ¦ The sequence of operation of the multivibrators 71 and 76, 27 ¦I which together constitute a free running multivibrator system, is 28 to first apply an output pulse from the multivibrator 76 to the 29 CLCTR counter advance input terminal of the counters 66 through 69. When this pulse terminates, the multivlbrator 71 is set to 3l its astable condition; and the pulse passed by the ~R gate 72 is 32 ~

1~L315~

1~ applied throucJh both of the NOR gates 73 and 74 to the memories 45 2ll through 54~ The output of the NOR gate 73 is a short duration 3 I negative going pulse which enables the "write" input (WREN) oE -the 4 memories 45 through 54. Data can only be written into the memories ~5 through 54 only when this pulse is present, otherwise 6 the memories operate strictly as read only memories. At the same 7 time, the address enable (ADDE~) for permitting the reading of 8 data out of or the reading o data into the memories 45 through 54 9 is obtained in the form of a negative going pulse from the output 10 lof the NOR gate 74. The other input to the NOR gate 74 is 11 !normally low, so that its output also is low at the time the 12 Ipositive pulse is obtained from the output of the OR gate 7 13 A particular memory tl1en is selected for addressing and 1~ Ifor writing of data into it when the WREN output o~ ~he NOR gate 151,73 is low and the ADDE~ output of the NOR cJate 7~ is low, G ! simultaneously wi.th the low ou-tput obtained from the selected 17~inverted output of the BCD-to-decimal converter 58 to select one ~ of the ten memory units 45 through 54. Only the selected one of 19 I the memory units is permitted to responcl to the ~riting of data

20 linto the address selected by the binary address signals on the

21 leads A0 through A9 at any given time. These addresses are changed

22 sequentially by the stepping of -the counters 66 through 69 under

23 the control of the clock pulses CLCTR appearincJ at the output of 24l the multivibrator 76.
25~¦ The particular data which is written into the addressed 26l,location of the selected one of the memories 45 through 54 at each 27 1I different step or cycle of operation of the multivibrator set 2a¦l71/76 is established by the particular direction of operation of 29 ¦I the switch 60. If the switch 60 is init-ially ope.rated to its ~,0¦~upper contact (initially "good"), a flip flop 80 is direct set to 31 Icause its "Q" output to go high. This output is applied to one f 1~5~19 1 two inputs of a NAND gate 81, the other input to which is obtained 2l¦from the "Q" output of the flip-flop 38~ As described prefiously 3 Ithe "Q" output of the flip-flop 38 also is high at this time.
4 This means that the output of the NAND gate 81 goes low, and this 5 output is applied to one of two inputs of a NOR gate 83~ The 6 other input of the NOR gate 83 is obtained from the output of a 7 NAND gate 84~ which has one input obtained from the ~IQll output of 8 a flip-flop 87 and the other input obtained from the Q output of ¦ i the flip-flop 38n Since the Q output of the flip-flop 38 is low 10¦lat this time, the output of the NAND gate 84 is high, irrespective 11¦ of the condition of the output of the flip-flop 87~ Thus, the NOR
12¦ gate 83 has one low input applied to it and one high input applied ¦ to it~ As a consequence, its output is "high", indicative of a t~L I binary "l" on the output terminal ~DI of the gate 33. This 15' constitutes the data input signal (shown on the r~ t hand side of 16l!Figure 4) applied in common to the data input terminals of all of 17¦the memory units 45 through 54. Thus, w~len the write pulse ~RE~I
18¦¦appears on the output of the N~R ~ate 73 this binary "l" is 91¦written into the selected address location in the selected memory unit.
21 I If, on the other hand, the initializing switch 60 was 22 ¦initially switched to contact its lower contact (initial "bad" or 23 I''non-valid''), the flip-flop 80 is set to its reset condition,

24¦1providing a low output on its "Q" output terminal. Under this condition of operation the output of the NAND gate 81 goes high;
261~so that both inputs to the NOR gate 83 are high. The output of 27~l'the NOR gate 83 then goes low, representing a memory data input 28 ~ IDI) for a binary "O". This then would constitute the data 29 ¦! stored in the selected address locations of the memory units 45 through 5~ so long as the system remains in this initializing mode 31 of operation. The selected data, either binary "l" ~valid) or ~13S41~

I binary "O" (non-valid) is written into each of the address 2l¦1Ocations of the memory 45 to 54 under the control of the system 3~iwhich steps the counters 66 through 69. 1^7hen 10,000 counts 4¦ representative of the 10,000 addresses for the memories 45 through 5 1 54 have been reached, an output is obtained from the last counter 6 ¦ stage 69 on an output terminal and constitutes a final count 7 (SPCNT) from the counter 69. This output is applied to the clock 8 input of the flip-flop 38 and causes the flip-flop 38 to be reset to its initial state of operation. Thus the "Q" output goes low 10 I and the Q output goes high. This in turn removes the enabling 11 ~ inputs to the one-shot multivibrators 71 and 76; so that the 12 , operation of the free running multivibrator 71/76 is terminated.
13 ~ Thus, no longer are any write enable (WR~N) pulses applied to the memories from the output of the NOR gate 73; and no lon~er is the 15l' address enable (ADDEN) control of the memories effected by the 1~1l output of the OR gate 72 through the NOR ~ate 74.
Once the initial claaring of the memories 45 through 5 l8 ¦ described above has been effected, individual ones of the memory 19 I address locations can be changed to store indicia opposite that which has been set into the memory initially for the purpose of 21 utilizing the system as a verification check system or a 22 "lock-out' system. For example, if all of the memory address 23 locations were initially set to store a binary "1" (valid) this 24 I means that uniquely encoded verification data on the credit cards

25 ¦ used in the system is assumed to be "valid". If it is desired to

26 ¦I prevent the use of any particular credit card in the system, it is

27 1l necessary to change the binary "1" to a binary "0" at the address

28 ¦1 location corresponding to the validity data encoded on that card.

29 I To do this, the validity identification word or data for such a card or customer is transmitted from the central processor 11 31 ~ through the modems 10 and 15 preceded by a mode con-trol binary 11 ~35~

1 encoded word which is decoded by the mode control circuit 19 to 2 place the switch 35 in its upper or "set" position, as shown in 31 Figure 2. The initializing switch 60, however, is not operatecl 4 since no initializing code is transmitted at this time.
Consequently the outputs of the ~XCLUSIVE OR gates 35 and 37 are 6 reversed from the conditions described previously. That is, the 7 output of the gate 36 is high and the output of the gate 37 is 8 low. This causes the switche gates 40 through 43 to be operated g to connect the upper four inputs of each of these gates with their respective outputs As a result, the ouputs of the counters 66 11 through 69 no longer control the address selection of the various 12 ~memories. Instead, control of the address selection is effected 13 ~by the address decoding circuit 20 which decodes the address 1~ Isupplied to it from the central processor ll throu~h the modem 15 15!lto a uniquely encoded ~CD word corresponding -to the selected credit card (either individual carcl or customer identification) 17 1I which is to be prevented or locked out from functioning to operate 18 ¦I the system with which the verificat:ion logic of Fi~ures 2, 3 and 4 19 1is associated.
20 I The address decodiny circuit 20 has a capability of 21 ~decoding any one of the lG,000 different addresses which can be 22 1located and stored in the memory units 45 through 54. The unique 23 ¦combinations of BCD words corresponding to these addresses are 24~1 applied through the switch gates 40 to 43 to selected a particular 25~1address corresponding to the desired card which is to be locked 26~1out of the system. If the system previously had all of the memory 27 ¦1 locations set "valid", that is storing a binary "l", a subsequent 2~ ¦I control signal transmitted from the processor ll is supplied 29 1I through the mode control circuit l9 produce a positive pulse

30 I through an OR gate 96 to the clock input of a one-shot 3l ~ multivibrator 97O This is accomplished electronically by the mode l ll ~ -15- 1 l I

1 ~control circuit 19 and is indicated in Figure 2 by momentarily 2llmoving the switch contact of the switch 95 to its lot~er positlon.
3j~ This same pulse is applied to the reset tcrminal of a 41 flip-flop 87 to cause its "Q" output to ~o low, if this output 51 already was not low~ Since the flip-flop 38 already is in its 6 reset condition of operation (with its "Q" output low), the result 7 of this operation is to cause the output of the NO~ yate 83 to go 8 low. This means that the memory data input signal (MDI) is 9 repesentative of a binary "0" or "non-valid" indicia for the 10lselectred address. The pulse produced by the one-shot 11¦ multivibrator 97 is applied through the OR gate 72 in the same 12 Imanner described previously to cause the writing of the data 13 ¦information appearing on the terminal MDI in-tG the selected l4 laddress of the memory. At the termination of the pulse from the 51one-shot multivibrator 97, no Eurther operation of the circuit takes place until the switch 95 is again pulsed -to apply a 17j~positive going pulse to either one of its two output -terminal as l8¦1indicated in Figure 2.
19 In the event that the initializing of the data storage in all of memory units 45 through 54 was to cause them to store a 21 binary "zero" the system can be individually operated to store a 22¦ binary "l" in each of the selected address locations in the same 23¦ manner described above for an initial initialization of binary "l"
24 11 in the system. This merely reverses the outputs of the NOR gate 83 to a high or binary "l" output from that described above by a 26 ¦I reversal of the state of the flip-flop 87. The operation of the 27~lone-shot multivibrator 97 is the same. Thus, for each different 28 11 address location selected by the operation of the address decoding 29¦lcircuit 20, a different selection of an address or binary bit 30¦¦location in the memories 45 through 54 may be made to change or

31 store the desired data at that address location in the same manner

32 1 I described above.
2 If it is desired merely to chec~ the condition of an 3 jaddress location without writing new data into the memory, the 4 ¦switch 95 is not operated in response to any signal applied to the mode control circuit l9. Instead, a signal is applied to the mode G control circuit l9 to cause it to connect the switch 35 to its 7 upper "set" position as shown in Figure 2. The condition of the 8 switch gates 40 through 43 then remains as described above for the 9 setting of information from the address decoding circuit 20 into l0¦lthe memory. A check switch 99 is operated in response to a 11 1verification chec]~ control signal transmitted from the central 12 1processor and decoded by the circuit 19 to move it Erom a normally 13 ¦unconnected position, as shown in Figure 2, to its lowermost 14 ¦position. This triggers a one-shot multivibrator l00 into 15 ~operation to produce a pulse throu~h an OR ~ate l0] to the lower lG 11l input of the NOE~ gate 74. Since the upper input of this NOR gate 171¦is low at this time, the positive going pulse supplied to the lower input produces a short duration negati~e pulse on the output 19~ of the NOR gate ~4. The output of the NOR gate 73, however, 20 Iremains high at this time; so that the address location which has 21 ¦been selected by the address decoding circuit 20 may be used to 22 produce a read out on the conmon output terminal rlDO from the 23 memory units. This output then is representative of the data 24 ¦stored at that address location in the memories ~5 through 54, effectively causing the system to be operated as an ROM memory 261lsystem (read only memory).
27¦1, Data read out of the memory is applied through a first 28~inverter 103 to the base of an NPN transistor 105 connected in 29 1I series with an indicator lamp 106 between the switch 35 and 30 ¦ground. The output of the inverter 103 is supplied ~hrough a 31 1second inverter 107 to the base of a second NPN transistor l0~, 32 ,which in turn is connected in series circuit with a second 1135~

1~ lndicator lamp 109 and ground. Thus, one or the other o the lamps 106 or 109 is illuminated depending upon whether a binary 3~ "1" or a binary "0" was stored at the selected address location in 4 j the memory. Typically, the lamp 106 is a red lamp indicative of S ¦ "bad" or "non-valid" status and the lamp 109 is a green lamp ~ indicative of "good" or "valid" status of the selected address.
7~1 This provides users of the system with a ready visual reference of 8I the status of the selected addresses.
9l Assume now that the system initially has been set up and that some selected address locations of the memory units 45 through 54 have been set to store a binary digit representative of 12 1 a "non-valid" credit card which is to be locked out of the system 13l or prevented from using the system to obtain products or services lill in response to use of the card. As described previously, the normal operation of the system other than the initializing operation or -the setting of the memory for specific address 7 l locations or checking of specific address locations by way of the switches 90 through 93, is for the switch 35 to be placed in its lowermost (NO~M) position. In this position, the various other 20ll circuit swltches of Figure 2 which have been described above are 21¦l rendered inoperative. Particularly, no writing of data into the 22l~ memory can be obtained from the output of the ~lOR gate 73 since 23l its output continues to be high at all times when the switch 35 is 24l in its lowermost or "NOR~" position. In the normal condition of -5l operation of the system, the addressing of the memory is effected 26, through the counters 66 through 69 which now are operated as jam 27~ input counters. With the switch 35 in its low~rmost position, the 28, output of the EXCLUSIVE OR gate 37 is high and that of the 29 EXCLUSIVE OR gate 36 is low; so that the switch gates 40 through ¦' 43 are enabled to supply the information connected to the 'l lowermost four leads of each of these ga-tes to the outputs of the :

, 1 ~3! 3~ L~

1 gates. This means that the counters are in control, and the 2 address decoder circuit 20 is prevented from having any effect on 3 ¦the operation of the system~
4 Various types of data are encoded on the credit cards or document cards inserted into the card reader 25. Some columns of 6 this data include the unique information used to identify the 7 vehicle and/or customer~ This is the information which is checked 8 in the verification circuit of Figures 2, 3 and 4 to determine g~¦whether that card is one which is valid for use in the system, lol,that is, whether that particular card can be used to obtain 11 ~products from the system controlled by the verification logic and 1 12 the circuitry descrihed previously~ This data is checked during 13 Iclock pulses 5, 6, 7 and ~ (from a clock, not shown here, but 14 ¦I corresponding to the clock 27 of the Kubina '140 pa-tent) and the 15l' terminals to which these clock pulses are applied are shown in the lG I lower lefthand corner of Figure 2. The eight rows of data in any 17 1l column of a card inserted into the card reader of the sys-tem l~ j described in the Kubina patent 4,114,140 are applied in tw~ groups 19¦~ of four to the jam input counters 66 through 69. For example, 20~l rows 1 throu~h 4 are connected in parallel to the inputs of the 21l¦ counters 67 and 69, while rows 5 through 8 are connected in 22 1I parallel to the inputs of the counters 66 and 68. To provide 23 ¦ additional security and additional flexibility in the programming 24 ¦1 Of the system, the data on these rows is alternately read 25 1I simultaneously into the counters 68 and 69 and simultaneously at a 26 1' different time into the counters 66 and 67. Thus two different 27¦¦ columns of data each comprising 8 rows of binary information are 28 1¦ stored in the counters 67 through 69 to select the one oE the 29¦¦ 10,000 address locations in the memories 45 through 54 (Figure 4) 30 ¦¦ which corresponds to the data read from the cards.
31 To control which of the columns on the cards are used to 1~L35~

1 enter this data, a manually operated preset switch bank 115 is 2!l provided. This switch bank includes a first pair o~ switches 116 3 I and 117 connected to one input of an AND gate 120. A second pair 4 of switches 121 and 122 are connected to one lnput of a second AN~
124. The other inputs to the gates 120 and 124 are obtained in 6 common from the output of an AND gate 126 which is provided with 7 two inputs, the STRB and the ENGD inputs. These inputs correspond 8 to the similarly identified inputs of the system disclosed in 9 Patent Number 4,085,313. All that is necessary for the purposes 10~ of this disclosure is that the output of the ~a-te 126 is high at ll ~ the time the clock pulses CL5, CL6, Cl,7, and CL8 occur. Only one 12 I of the two switches 116 or 117 is closed and only one of the two 13 ¦I switches 121 or 122 is closed to control the particular time of ~ occurance of the clock pulse which is applied to each of the gates 120 and 124. These clock pulses are applied to read different IGjl columns of information from the card reacler; so that by grouping l7~ the pulses in this manner different groups of data may be used for 1~1 verification purposes. In addition, the arrangement of closure of 19li the switch combinations 116/117 and 121/122 can be varied at any 201 time the programming for the system is to be changed.
21~ The counters 66 and 67 are enabled to respond to the data 221 appearing on their inputs as jam input data whenever a positive 23 ¦1 output (EN-B) is obtained from the AN~ gate 124. Similarly the 24~l counters 68 and 69 are enabled to store, as jam input counters, 25 ¦I the data appearing on the inputs supplied to them whenever a 26 1I positive output (EN-A) is obtained from the gate 120.
27 1i At the time the subsequent ninth clock pulse, CL9 occurs, 28 1l it is applied to one input of an ANn gate 131, which is enabled on 29 I its other input from the ENGT signal of Figure 1. This produces a 3l¦ p~sitive output through the OR gate 101 which ~s applied to the I

113~i~19 1 NOR gate 74 to create a negative going address enable pulse to the 2 memories 45 through 54. This permits the memories to be read for 3~ the selected address to produce an output signal on the output 4 lead MDO corresponding to the "valid" or "non-valid" binary bit indicia which is stored at that address. This binary output G signal from the memories is applied to the lower one of two inputs 7 to a negative logic N~ND gate 133, the upper input to which is 8 obtained from the output of a positive logic NAND gate 135.
9 Whenever a clock pulse CL9 occurs, the upper input to the NAND
gate 133 goes low; and this gate is used to sample the data on the 11 ¦ common output MDO from the memories. The output of the NAND gate 12 1 133 ~hen is passed through an inverter 136 to constitute the 13 ~ output signal to the rest of the system to signify whether the 14 ¦ validity check logic found the card being checkecl to be "valid" or 151~ "non-valid". If the card is "non-valid", the MDO signal is used 16~l by the system to prevent operation of the system to withdraw 17¦~ products or to obtain services. If the card checks out "valid"
18 ¦I normal use of the system for its designated function is permitted.
19 I Any "valid" card subsequently can be locked out of the system by encoding its identifying BCD word ~or words) by 21 transmitting a si~nal for the corresponding address indicative of 22 a "non-valid" status through the address decoding circuit 20 23 during the updating of the validity memory 45 through 54. At the 24 I end of such an updating, the stored binary bit for such a card at 25 I the address location for that card in the memories 45 to 54 is 26~i changed from "valid" (binary "1") to "non-valid" (binary "0").
27ll Similarly, any bit stored for a locked out or "non-valid" card can 28l be changed back to "valid" whenever the credit status for that 29 , card changes to an acceptable status. By utili~ation of the central processor 11 to transmit updated information for the 31 lockout or transaction verification memory 17 on a regular l l ~21- 1 113S41~

1 periodic basis or as the necessity for a change in the sta-tus of 2 the verification memory 17 occurs, a highly flexible system is 3 lobtainedO Thus, it is no longer necessary to physically visit 4 each of the remote locations at which card readers or business transaetions are to take plaee in the system to set or update the 6 transaetion verification memories. Instead, the updating of the 71 memory is aecomplished automatically from the central processing 8 ¦ station associated with all of the outlying re~ote locations. In 9¦l~all other respects the system functions at the utilization point llin the same manner as the system of the patent ~,114,140.

l4 1~
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Claims (5)

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE PROPERTY
OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:

1. A system for providing a verification check of uniquely encoded multibit binary words at a plurality of remote locations, the system having a central station for supplying address signals and verification "valid/non-valid" control signals through a transmission link interconnecting said central station with each of said plurality of remote locations, each of said re-mote locations including in combination:
read/write memory means having a plurality of address locations therein, each address location storing a single binary bit indicative of the "valid/non-valid" status of the item represented by each such address location, said memory means further having a single output on which an output signal is produced corresponding to the binary bit stored at the address location selected in said memory means;
lockout utilization means coupled to the output of said memory means and operated in response to output signals appearing thereon;
address control means operated in response to addres-sing signals and coupled to said memory means for selecting particular address locations for the writing of bits into and the reading of bits from those address locations of said memory means;
read/write control means coupled to said memory means and further coupled with said transmission link and responsive to signals applied thereto from said central station over said transmission link for controlling the read/write mode of opera-tion of said memory means and for supplying said verification control signals to said memory means to selectively change the "valid/non-valid" status of the binary bits stored in said memory means when said memory means is in the write mode of operation;

gating circuit means having a plurality of inputs and having outputs coupled with said address control means for supplying said addressing signals thereto;
address decoding means coupled to selected inputs of said gating circuit means and further coupled with said trans-mission link and responsive to address signals supplied thereto from said central station over said transmission link for supplying address input signals to said gating circuit means;
further circuit means coupled to others of the inputs of said gating circuit means for supplying input addressing signals thereto; and selecting means coupled with said read/write control means and operated thereby and further coupled to said gating circuit means for causing the signals appearing on the out-puts of said gating circuit means to be selected from the input signals from said address decoding means or the input signals from said further circuit means, thereby causing the signal on the output of said memory means to correspond to the binary bit stored at the address location selected by the addressing signals from said gating circuit means.

2. The combination according to claim 1 wherein said gate means comprises a multiple-pole, double-throw switching circuit means.

3. The combination according to claim 1 further including initializing circuit means coupled with said read/
write control means and operated thereby and coupled with said address control means for initially causing said memory means to store binary bits of the same type in all of said plurality of address locations.

4. The combination according to claim 3 wherein said system further includes "set" control means coupled with said read/write control means and said selecting means for causing said memory to be placed in its "write" mode of opera-tion and for causing said gate means to supply addressing signals to said address control means from said address de-coding means; and means for causing binary bits having a pre-determined binary characteristic to be stored in said memory means at the address location selected by said address decoding means.

5. The combination according to claim 4 wherein said selecting means further includes means for causing said memory means to operate as a read-only memory means when said select-ing means causes said gating circuit means to provide addressing signals on the outputs thereof in response to input signals applied thereto from said further circuit means.