CA1134058A - Method of fabricating semiconductor device by bonding together silicon substrates - Google Patents
Method of fabricating semiconductor device by bonding together silicon substratesInfo
- Publication number
- CA1134058A CA1134058A CA396,119A CA396119A CA1134058A CA 1134058 A CA1134058 A CA 1134058A CA 396119 A CA396119 A CA 396119A CA 1134058 A CA1134058 A CA 1134058A
- Authority
- CA
- Canada
- Prior art keywords
- semiconductor device
- bonding surface
- fabricating
- recesses
- silicon substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
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- Electrodes Of Semiconductors (AREA)
Abstract
Abstract:
There is provided a method of fabricating a semi-conductor device wherein in a bonding surface of a silicon substrate of n-type conductivity are formed recesses having each a bonding surface of a higher order plane index than that of the bonding surface of the silicon substrate, and the substrates are bonded together with an aluminum solder so as to decrease a forward voltage drop FVD. After forming the recesses but prior to the bonding with the aluminum solder, phosphor is diffused into a region ranging from the bonding surface to a depth of 20 microns, thereby further decreasing the forward voltage drop FVD.
There is provided a method of fabricating a semi-conductor device wherein in a bonding surface of a silicon substrate of n-type conductivity are formed recesses having each a bonding surface of a higher order plane index than that of the bonding surface of the silicon substrate, and the substrates are bonded together with an aluminum solder so as to decrease a forward voltage drop FVD. After forming the recesses but prior to the bonding with the aluminum solder, phosphor is diffused into a region ranging from the bonding surface to a depth of 20 microns, thereby further decreasing the forward voltage drop FVD.
Description
-q~
Method of fabricating semiconductor device b~ bonding together silicon substrates This invention relates to a method of fabricating a semiconductor device and more particularly to an improve-ment in bonding together silicon substrates with aluminum.
It is general practice to bond a silicon substrate to a silicon substra~e with an aluminum solder Eor the purpose of establishing the electrical connection. In some applications, the aluminum solder is also used to bond one silicon substrate to another.
With respect to contacts to silicon substrate using aluminum, one may reter to the Matlow et al article "Ohmic ~luminum-n-Type Silicon Contact", Journal of Applied Physics, Vol. 30, No. 4, (1959) pp. 541-543; the Roberts et al article "The Controlling Factors in Semiconductor Large Area Alloying Technology", Journal of Materials Science 3 tl968) pp. 110-119; or the Roberts et al arti-cle "The Effects of Alloying Material on Regrowth-layer Structure in Silicon Power Devices", Journal of Materials Science 6 ~1971), pp. 189-198.
Aluminum is used as a solder because in one respect, it has superior electrical conductivity and bonding ability to the other brazing materials and in another respect, it belongs to a hard solder which is economical.
Where the bonding surface of the silicon suhstrate ' has in part n-type conductivity, heat for bonding together silicon and aluminum causes silicon to react with aluminum and accordingly, a regrowth layer of p-type conductivity is formed on the n type conductivity surface, resulting in unwanted increase in a forward voltage drop FVD of the semiconductor surface.
One conventional countermeasure for preventing the p-type regrowth layex includes decreasing the thickness of the aluminum solder. Another countermeasure includes providing a foil of five-valence element such as antimony between the silicon substrate and an aluminum foil serving as aluminum solder. Still another counter-measure includes diffusing into the n-type surface a large amount of phos-phor which is chosen because of not only being a five-valence element but also being effective to prevent theformation of the regrowth layer. However, these counter-measures are unsatisfactory.
With increased forward voltage drop Fvn~ the silicon substrate generates a correspondingly large amount of heat when conducting and becomes difficult to cool. Therefore, the amount of current to be passed through the silicon sub-strate must be suppressed.
It is therefore an object of the invention to provide a method of fabricating a semiconductor device which can ensure that silicon substrates can be bonded together with aluminum without causing increase in a forward voltage drop.
Another object of the invention is to provide a method of fabricating a semiconductor device which can decrease the forward voltage drop so that heat generated in the semiconductor device can be decreased and a correspondingly large amount of current can be passed therethrough.
Still another object of the invention is to provide a method of fabricating a semiconductor device which can decrease the forward voltage drop FVD without degrading characteristics of the silicon substrate.
[~
According to the invention, there is provided a method of fabricating a semiconductor device comprising the steps of: forming~ in a bonding surface of a silicon substrate of n-type conductivity, recesses each o~ which has a bonding surface of a higher order plane index than that of the bonding surface of said silicon substrate; and integrating at ]east two silicon substrates formed with the recesses and an aluminum solder interposed between them by heating.
The above and other objects and features of the invention will be better understood when reading the following detailed description in conjunction with the accompanying drawings, in which:
FigO 1 is a longitudinal sectional view of a semi-conductor device in which silicon substrates and electrodes are bonded together with an aluminum solder;
Fig. 2 is a graphic representation showing the relation between heating temperature and discontinuity ratio in accordance with the conventional method and the fabricating method of the invention;
Fig. 3 is a graphic representation showing the relation between discontinuity ratio and increment of forward voltage drop;
Fig. 4 is a graphic representation showing phosphor concentration profiles in the depth direction of a silicon substrate of a semiconductor device in accordance with the conventional method and the fabricating method of the invention;
Fig. 5 is a graphic representation showing the rela-tion between discontinuity ratio and increment of forwardvoltage drop in semiconductor devices fabricated in accordance with the conventional method and the fabri-cating method of the invention; and Fig. 6 is a micro-photograph of a silicon substrate surface taken after an etching process in the fabricating method of the invention.
. .
L~
Fig. 1 shows a glass-molded type high voltage diode 30 wherein a pair of molybdenum electrodes 31 and 32 are spaced apart, conductive spacers 33a and 33b adjoin the electrodes 31 and 32, and silicon pellets (silicon sub-strates) 34a, 3~b, ...~, 34n having p-n junctions are laminated between the spacers 33a and 33b s~ch that their rectifying polarities are aligned in one direction, the electrodes 31 and 32, the spacers 33a and 33b, and the silicon~ pellets 34a, 34b, ...., 34n being bonded together with aluminum solders 35a, 35, ... 35n~1, 35n. The resulting assembly is molded with a %nO-B2O3-SiO2 system glass mold 36 which bridges across the electrodes 31 and 32.
The glass mold 36 serves not only as a surface stabi-lizer for the exposed ends of the p-n junctions of the silicon pellets 34a, 34b, ...., 34n but also as a pro-tector against an external stress. Copper lea~s 37 and 38 containing a small amount of zirconium are connected to the electrodes 31 and 32 by percussion welding.
When bonding together the silicon pellets 3~a, 34b, ...., 34n with the aluminum solders 35b, ...., 35n-1 in the case of Fig. 1 diode, a fabricating method according to the invention is applied~
~ore particularly, the silicon substrate has a bond-ing surface in the form of an n-type conductivity (111) crystallized surface, and the bondin~ surface is etched with an aqueous solution mainly containing 5% sodium hydroxide to form therein recesses. Thereafter, phosphor is diffused into the bonding surface at a high concentra-tion (1.08 atomic %; 1 atomic ~ = S ~ 102 atoms/cc) toconvert it into an n+-type conductivity bonding surface.
A micro-photograph of the thus prepared n+-type conductivity bonding surface is shown in Fig. 6. ~t is to be noted that the diffusion of phosphor at the high concentration is to suppress increase in the forward voltage drop by virtue of the ablity of phosphor to .. . . . . . .
prevent the formation of regrowth layers and this dif-fusion is not an indispensable condition for achieving the invention. When observing the n -type conductivity bonding surface, it was proved that there were formed a great number of recesses in which isolated segmental bonding surfaces were exposed having a higher order plane index than the plane index (111) of the original bonding surface.
Subsequently, one high concentration phosphor diffused n+-type conductivity layer is removed by polishing or etching whereas the other high concentration phosphor diffused n+-type conductivity layer serving as the bonding surface is masked with a diffusion mask through which p-type conductivity impurity (acceptor) such as boron, gallium or the like is diffused to form a p-n junction. Since heating temperature for the formation of the p-n junction is below the melting temperature of the silicon, the great number of recesses formed in the n~-type conductivity bonding surface will not distort during the heat treatment.
Then, the diffusion mask and a silicon oxide film formed on the silicon substrate diffusing acceptor are removed.
In the next step, the n+-type conductivity bonding surface formed therein wiLh the recesses of the high order plane inde~ is deposited with aluminum in a predetermined thickness by well-known technique such as vapor deposition.
In the next step, the spacers 33a, 33b and the silicon substrates are laminated as shown in ~ig~ 1, and is heated at a temperature above the melting point of aluminum for a predetermined time and thereafter subjected to cooling, thereby bonding the spacers and the silicon substrates to each other.
Further increased discontinuity ratio of the regrowth layer attributable to the longitudinal growth of the regrowth layer can afford to suppress increase in the forward voltage drop FVD.
"Discontinuity ratio" referred to herein defines a ratio Q/L ~Q being the length of a portion at which a cross-sectional area of the crystallized regrowth layer is not present after bonding, and L being the entire bonding length). This rate is equal to a ratio q/Q (~
being the area at which the regrowth layer is crystal-lized, and Q being the area of the bonding surface).
Fig. 2 shows the relation between heating temperature for bonding and discontinuity ratio of the regrowth layer, where curve A represents results of the invention and curve B results of the conventional method wherein any recesses of the high order plane index are not formed.
As will be seen from Fig. 2, the number of crystallized regrowth layers increases as the heating temperature increases so that the discontinuity ratio is decrased, and the discontinuity ratio is improved according to the invention as compared to the conventional method.
Fig. 3 shows the relation between discontinuity ratio and increment ~FVD of the forward voltage drop due to the regrowth layer. As will be seen from Fig. 3, the forward voltage drop FVD is decreased as the discontinuity ratio increases, as described in the foregoing.
Thus, Figs. 2 and 3 teach that according to the invention, the discontinuity ratio is increased as compared to the conventional method so that the forward voltage drop can be decreased.
Fig. 4 shows phosphor concentration profiles within a region ranging from the n+-type conductivity surface of silicon substrate of the semiconductor device to a depth of 20 microns, where curves ~ and ~ represent profiles in the silicon substrate according to the conventional method and curves ~ and ~ profiles in the silicon substrate of the semiconductor device according to the invention.
In'the case of curve ~ , the phosphor concentration C3~
at the surface is 1.8 x 1021 atoms/cm3 and about 9 ~ 102 atoms/cm3 at a depth of 20 microns. In the case of curve ~ , the phosphor concentration is 4.0 x 102 atoms/cm3 at the surface and 1.5 x 10 atoms/cm at a depth of 20 microns. In accordance with the invention, the phosphor concentration is 3 to 7 x 102 atoms/cm3 de-pending on a depth ranging from the n+-type conductivity surface to 20-micron depth.
Silicon substrates corresponding to curves ~
~ and ~ were each bonded to a metal plate of molybdenum with aluminum solder to complete a glass-molded diode~ The products or samples ~ to ~ thus prepared were sheared, and cut surfaces were polished and immersed in a Sirtl etchant (solution of 10 cc water and 5 gram CrO3:
HF = l : l) to form regrowth layers which were observed by means of an optical microscope. With these samples, increments ~FVD of the forward voltage drop FVD due to the regrowth layer were measured, and discontinuity ratio were also measured from the regrowth layers formed in the cut surfaces. Results are shown in Fig. 5, from which it i9 to be noted that a discontinuity ratio of more than 10~
and an increment of less than 0.2 ~olts are obtained only with samples ~ and ~ , and that the increment aFVD of samples ~ and ~ exceeds 0.4 volts and the discontinuity ratio thereof is l to 2%.
As described above, it will be appreciated that when phosphor is diffused into a region ranging from the n~-type conductivity bonding surface to a depth of 20 microns at a concentration of 3 to 7 x 102 atoms/cm3, the forward voltage drop FVD can be decreased.
The bonding surface subjected to the phosphor diffusion is formed with other recesses than those created by etching when undergoing bonding with aluminum. The additional recesses due to phosphor diffusion contribute to increase in the discontinuity ratio.
According, when the phosphor concentration is less than 3 x 102 atoms/cm3, the formation of additional recesses is insufficient, resulting in a large increment QFVD. Conversely, when the phosphor concentration is more than 7 x 102 atoms/cm3, the additional recesses may be created excessively and it follows that the bonding surface becomes excessively irregular, resulting in the same surface condi~ion as that of the conventional bonding surface not formed with recesses and consequent increase in the increment ~FVD.
Where the spacers 33a, 33b and the sil;con pellets 34a, 34b, ...., 34n are bonded together with the aluminum solders 35a, 35b, .... 35n to form a lamination as in the glass-mold type high voltage diode 30 of Fig. l, the pro-vision of the recesses of high order plane index in the n-type conductivity surface can ensure that the discon-tinuity ratio is sufficiently increased and consequently the forward voltage drop is decreased, as shown in Figs.
Method of fabricating semiconductor device b~ bonding together silicon substrates This invention relates to a method of fabricating a semiconductor device and more particularly to an improve-ment in bonding together silicon substrates with aluminum.
It is general practice to bond a silicon substrate to a silicon substra~e with an aluminum solder Eor the purpose of establishing the electrical connection. In some applications, the aluminum solder is also used to bond one silicon substrate to another.
With respect to contacts to silicon substrate using aluminum, one may reter to the Matlow et al article "Ohmic ~luminum-n-Type Silicon Contact", Journal of Applied Physics, Vol. 30, No. 4, (1959) pp. 541-543; the Roberts et al article "The Controlling Factors in Semiconductor Large Area Alloying Technology", Journal of Materials Science 3 tl968) pp. 110-119; or the Roberts et al arti-cle "The Effects of Alloying Material on Regrowth-layer Structure in Silicon Power Devices", Journal of Materials Science 6 ~1971), pp. 189-198.
Aluminum is used as a solder because in one respect, it has superior electrical conductivity and bonding ability to the other brazing materials and in another respect, it belongs to a hard solder which is economical.
Where the bonding surface of the silicon suhstrate ' has in part n-type conductivity, heat for bonding together silicon and aluminum causes silicon to react with aluminum and accordingly, a regrowth layer of p-type conductivity is formed on the n type conductivity surface, resulting in unwanted increase in a forward voltage drop FVD of the semiconductor surface.
One conventional countermeasure for preventing the p-type regrowth layex includes decreasing the thickness of the aluminum solder. Another countermeasure includes providing a foil of five-valence element such as antimony between the silicon substrate and an aluminum foil serving as aluminum solder. Still another counter-measure includes diffusing into the n-type surface a large amount of phos-phor which is chosen because of not only being a five-valence element but also being effective to prevent theformation of the regrowth layer. However, these counter-measures are unsatisfactory.
With increased forward voltage drop Fvn~ the silicon substrate generates a correspondingly large amount of heat when conducting and becomes difficult to cool. Therefore, the amount of current to be passed through the silicon sub-strate must be suppressed.
It is therefore an object of the invention to provide a method of fabricating a semiconductor device which can ensure that silicon substrates can be bonded together with aluminum without causing increase in a forward voltage drop.
Another object of the invention is to provide a method of fabricating a semiconductor device which can decrease the forward voltage drop so that heat generated in the semiconductor device can be decreased and a correspondingly large amount of current can be passed therethrough.
Still another object of the invention is to provide a method of fabricating a semiconductor device which can decrease the forward voltage drop FVD without degrading characteristics of the silicon substrate.
[~
According to the invention, there is provided a method of fabricating a semiconductor device comprising the steps of: forming~ in a bonding surface of a silicon substrate of n-type conductivity, recesses each o~ which has a bonding surface of a higher order plane index than that of the bonding surface of said silicon substrate; and integrating at ]east two silicon substrates formed with the recesses and an aluminum solder interposed between them by heating.
The above and other objects and features of the invention will be better understood when reading the following detailed description in conjunction with the accompanying drawings, in which:
FigO 1 is a longitudinal sectional view of a semi-conductor device in which silicon substrates and electrodes are bonded together with an aluminum solder;
Fig. 2 is a graphic representation showing the relation between heating temperature and discontinuity ratio in accordance with the conventional method and the fabricating method of the invention;
Fig. 3 is a graphic representation showing the relation between discontinuity ratio and increment of forward voltage drop;
Fig. 4 is a graphic representation showing phosphor concentration profiles in the depth direction of a silicon substrate of a semiconductor device in accordance with the conventional method and the fabricating method of the invention;
Fig. 5 is a graphic representation showing the rela-tion between discontinuity ratio and increment of forwardvoltage drop in semiconductor devices fabricated in accordance with the conventional method and the fabri-cating method of the invention; and Fig. 6 is a micro-photograph of a silicon substrate surface taken after an etching process in the fabricating method of the invention.
. .
L~
Fig. 1 shows a glass-molded type high voltage diode 30 wherein a pair of molybdenum electrodes 31 and 32 are spaced apart, conductive spacers 33a and 33b adjoin the electrodes 31 and 32, and silicon pellets (silicon sub-strates) 34a, 3~b, ...~, 34n having p-n junctions are laminated between the spacers 33a and 33b s~ch that their rectifying polarities are aligned in one direction, the electrodes 31 and 32, the spacers 33a and 33b, and the silicon~ pellets 34a, 34b, ...., 34n being bonded together with aluminum solders 35a, 35, ... 35n~1, 35n. The resulting assembly is molded with a %nO-B2O3-SiO2 system glass mold 36 which bridges across the electrodes 31 and 32.
The glass mold 36 serves not only as a surface stabi-lizer for the exposed ends of the p-n junctions of the silicon pellets 34a, 34b, ...., 34n but also as a pro-tector against an external stress. Copper lea~s 37 and 38 containing a small amount of zirconium are connected to the electrodes 31 and 32 by percussion welding.
When bonding together the silicon pellets 3~a, 34b, ...., 34n with the aluminum solders 35b, ...., 35n-1 in the case of Fig. 1 diode, a fabricating method according to the invention is applied~
~ore particularly, the silicon substrate has a bond-ing surface in the form of an n-type conductivity (111) crystallized surface, and the bondin~ surface is etched with an aqueous solution mainly containing 5% sodium hydroxide to form therein recesses. Thereafter, phosphor is diffused into the bonding surface at a high concentra-tion (1.08 atomic %; 1 atomic ~ = S ~ 102 atoms/cc) toconvert it into an n+-type conductivity bonding surface.
A micro-photograph of the thus prepared n+-type conductivity bonding surface is shown in Fig. 6. ~t is to be noted that the diffusion of phosphor at the high concentration is to suppress increase in the forward voltage drop by virtue of the ablity of phosphor to .. . . . . . .
prevent the formation of regrowth layers and this dif-fusion is not an indispensable condition for achieving the invention. When observing the n -type conductivity bonding surface, it was proved that there were formed a great number of recesses in which isolated segmental bonding surfaces were exposed having a higher order plane index than the plane index (111) of the original bonding surface.
Subsequently, one high concentration phosphor diffused n+-type conductivity layer is removed by polishing or etching whereas the other high concentration phosphor diffused n+-type conductivity layer serving as the bonding surface is masked with a diffusion mask through which p-type conductivity impurity (acceptor) such as boron, gallium or the like is diffused to form a p-n junction. Since heating temperature for the formation of the p-n junction is below the melting temperature of the silicon, the great number of recesses formed in the n~-type conductivity bonding surface will not distort during the heat treatment.
Then, the diffusion mask and a silicon oxide film formed on the silicon substrate diffusing acceptor are removed.
In the next step, the n+-type conductivity bonding surface formed therein wiLh the recesses of the high order plane inde~ is deposited with aluminum in a predetermined thickness by well-known technique such as vapor deposition.
In the next step, the spacers 33a, 33b and the silicon substrates are laminated as shown in ~ig~ 1, and is heated at a temperature above the melting point of aluminum for a predetermined time and thereafter subjected to cooling, thereby bonding the spacers and the silicon substrates to each other.
Further increased discontinuity ratio of the regrowth layer attributable to the longitudinal growth of the regrowth layer can afford to suppress increase in the forward voltage drop FVD.
"Discontinuity ratio" referred to herein defines a ratio Q/L ~Q being the length of a portion at which a cross-sectional area of the crystallized regrowth layer is not present after bonding, and L being the entire bonding length). This rate is equal to a ratio q/Q (~
being the area at which the regrowth layer is crystal-lized, and Q being the area of the bonding surface).
Fig. 2 shows the relation between heating temperature for bonding and discontinuity ratio of the regrowth layer, where curve A represents results of the invention and curve B results of the conventional method wherein any recesses of the high order plane index are not formed.
As will be seen from Fig. 2, the number of crystallized regrowth layers increases as the heating temperature increases so that the discontinuity ratio is decrased, and the discontinuity ratio is improved according to the invention as compared to the conventional method.
Fig. 3 shows the relation between discontinuity ratio and increment ~FVD of the forward voltage drop due to the regrowth layer. As will be seen from Fig. 3, the forward voltage drop FVD is decreased as the discontinuity ratio increases, as described in the foregoing.
Thus, Figs. 2 and 3 teach that according to the invention, the discontinuity ratio is increased as compared to the conventional method so that the forward voltage drop can be decreased.
Fig. 4 shows phosphor concentration profiles within a region ranging from the n+-type conductivity surface of silicon substrate of the semiconductor device to a depth of 20 microns, where curves ~ and ~ represent profiles in the silicon substrate according to the conventional method and curves ~ and ~ profiles in the silicon substrate of the semiconductor device according to the invention.
In'the case of curve ~ , the phosphor concentration C3~
at the surface is 1.8 x 1021 atoms/cm3 and about 9 ~ 102 atoms/cm3 at a depth of 20 microns. In the case of curve ~ , the phosphor concentration is 4.0 x 102 atoms/cm3 at the surface and 1.5 x 10 atoms/cm at a depth of 20 microns. In accordance with the invention, the phosphor concentration is 3 to 7 x 102 atoms/cm3 de-pending on a depth ranging from the n+-type conductivity surface to 20-micron depth.
Silicon substrates corresponding to curves ~
~ and ~ were each bonded to a metal plate of molybdenum with aluminum solder to complete a glass-molded diode~ The products or samples ~ to ~ thus prepared were sheared, and cut surfaces were polished and immersed in a Sirtl etchant (solution of 10 cc water and 5 gram CrO3:
HF = l : l) to form regrowth layers which were observed by means of an optical microscope. With these samples, increments ~FVD of the forward voltage drop FVD due to the regrowth layer were measured, and discontinuity ratio were also measured from the regrowth layers formed in the cut surfaces. Results are shown in Fig. 5, from which it i9 to be noted that a discontinuity ratio of more than 10~
and an increment of less than 0.2 ~olts are obtained only with samples ~ and ~ , and that the increment aFVD of samples ~ and ~ exceeds 0.4 volts and the discontinuity ratio thereof is l to 2%.
As described above, it will be appreciated that when phosphor is diffused into a region ranging from the n~-type conductivity bonding surface to a depth of 20 microns at a concentration of 3 to 7 x 102 atoms/cm3, the forward voltage drop FVD can be decreased.
The bonding surface subjected to the phosphor diffusion is formed with other recesses than those created by etching when undergoing bonding with aluminum. The additional recesses due to phosphor diffusion contribute to increase in the discontinuity ratio.
According, when the phosphor concentration is less than 3 x 102 atoms/cm3, the formation of additional recesses is insufficient, resulting in a large increment QFVD. Conversely, when the phosphor concentration is more than 7 x 102 atoms/cm3, the additional recesses may be created excessively and it follows that the bonding surface becomes excessively irregular, resulting in the same surface condi~ion as that of the conventional bonding surface not formed with recesses and consequent increase in the increment ~FVD.
Where the spacers 33a, 33b and the sil;con pellets 34a, 34b, ...., 34n are bonded together with the aluminum solders 35a, 35b, .... 35n to form a lamination as in the glass-mold type high voltage diode 30 of Fig. l, the pro-vision of the recesses of high order plane index in the n-type conductivity surface can ensure that the discon-tinuity ratio is sufficiently increased and consequently the forward voltage drop is decreased, as shown in Figs.
2 and 3~
The formation of the recesses of high order plane index does not rely on etching a:Lone. But, if the recesses are formed mechanically, the working stress persists in the surface of silicon substrate and tends to adversely affect electrical and mechanical charac-teristics of the silicon substrate. Therefore, it is desirable to employ such a process as etching which is free from working stress and is of high workability.
As an etchant, an alkaline aqueous solution is preferred. Especially, an aqueous solution containing sodium hydroxide or potassium hydroxide is effective.
As the forward voltage drop is decreased, the amount of heat generated in the semiconductor device of the invention during conduction can be decreased corres-pondingly. Further, the decreased heat generation can increase the amount of current correspondingly.
The formation of the recesses of high order plane index does not rely on etching a:Lone. But, if the recesses are formed mechanically, the working stress persists in the surface of silicon substrate and tends to adversely affect electrical and mechanical charac-teristics of the silicon substrate. Therefore, it is desirable to employ such a process as etching which is free from working stress and is of high workability.
As an etchant, an alkaline aqueous solution is preferred. Especially, an aqueous solution containing sodium hydroxide or potassium hydroxide is effective.
As the forward voltage drop is decreased, the amount of heat generated in the semiconductor device of the invention during conduction can be decreased corres-pondingly. Further, the decreased heat generation can increase the amount of current correspondingly.
Claims (6)
1. A method of fabricating a semiconductor device comprising the steps of:
forming, in a bonding surface of a silicon substrate of n-type conductivity, recesses each of which has a bonding surface of a higher order plane index than that of the bonding surface of said silicon substrate; and integrating at least two silicon substrates formed with the recesses and an aluminum solder interposed between them by heating.
forming, in a bonding surface of a silicon substrate of n-type conductivity, recesses each of which has a bonding surface of a higher order plane index than that of the bonding surface of said silicon substrate; and integrating at least two silicon substrates formed with the recesses and an aluminum solder interposed between them by heating.
2. A method of fabricating a semiconductor device according to Claim 1, wherein at least one of said silicon substrates has one surface in contact with the aluminum solder which is formed with the recesses.
3. A method of fabricating a semiconductor device according to Claim 2, wherein said recesses are formed by etching.
4. A method of fabricating a semiconductor device according to Claim 3, wherein said etching is effected with an etchant of alkaline aqueous solution.
5. A method of fabricating a semiconductor device according to Claim 1, wherein after forming said re-cesses, an acceptor is diffused into said silicon substrate to form a predetermined p-n junction.
6. A method of fabricating a semiconductor device according to Claim 1, wherein after forming said re-cesses, phosphor is diffused into a region ranging from the bonding surface to a depth of 20 microns at a concentration of 3 to 7 x 1020 atoms/cm3.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA396,119A CA1134058A (en) | 1978-04-28 | 1982-02-11 | Method of fabricating semiconductor device by bonding together silicon substrates |
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP53049971A JPS5946415B2 (en) | 1978-04-28 | 1978-04-28 | Manufacturing method of semiconductor device |
| JP49971/78 | 1978-04-28 | ||
| CA325,856A CA1127322A (en) | 1978-04-28 | 1979-04-19 | Method of fabricating semiconductor device by bonding together silicon substrate and electrode or the like with aluminum |
| CA396,119A CA1134058A (en) | 1978-04-28 | 1982-02-11 | Method of fabricating semiconductor device by bonding together silicon substrates |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1134058A true CA1134058A (en) | 1982-10-19 |
Family
ID=27166193
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA396,119A Expired CA1134058A (en) | 1978-04-28 | 1982-02-11 | Method of fabricating semiconductor device by bonding together silicon substrates |
Country Status (1)
| Country | Link |
|---|---|
| CA (1) | CA1134058A (en) |
-
1982
- 1982-02-11 CA CA396,119A patent/CA1134058A/en not_active Expired
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