CA1132711A - Pcm codec using common d/a converter for encoding and decoding - Google Patents

Abstract

PCM CODEC USING COMMON D/A CONVERTER
FOR ENCODING AND DECODING
Abstract A codec (coder/decoder), having particular utility in a pulse code modulation (PCM) communications system employing per-line coding and decoding, employs a common digital-to-analog (DAC) converter. A PCM signal to be reconstructed is decoded at two points of time within the basic sampling interval, preferably at twice the basic sampling frequency.
In order to realize the desired analog reconstruction level, the PCM signal is first decoded at a first decision level lying on one side of the desired reconstruction level;
then modified and again decoded at a different decision level lying on the other side of the desired reconstruction level.
The average of the two decoded analog signals then lies on the desired reconstruction level. In a conventional PCM
system, the two PCM samples differ by only one least signi-ficant bit (LSB) in the PCM word used in setting the common DAC. In a preferred embodiment of the invention, separate storage registers are respectively employed for the encoding and decoding, together with a selector for switching between the two registers during the two desired decoding intervals.
In this way, the encoding operation may be carried on during a substantial portion of the basic sampling cycle, being interrupted only for generation of decoded samples. The invention is applicable to PCM systems generally t including compressed pulse code modulation (CPCM) systems operating in accordance with the U-law or the A-law.

Description

BACKGROUND OF THE I~ENTION

My invention relates to codecs (coder-decoders), primarily intended for encoding and decoding of analog sig-nals, e.g., sp~ech o~ similar signals, in Puls~ Cod~
Modulation (PCM) systems, and is par~icularly applica~le to so-called per-line codecs which are not time-shared by several PCM channels.
A particular and commonly~used category of such codecs relies on so-called digital-to-analog converters (DAC's) for encoding and decoding. The DAC usually comprises a resistor network in combination with a number of electronic switches which are set by the digital code to be converted.
m e analog output signal from the combination network will then be related to a reference input signal according to the set~ing of the switches and the desired transfer character-istic. This reference signal is usually a fixed voltage of selectable polarity.
In order to accommodate great variations in th~ signal levels to be encoded, while yet maintaining an accepta~le signal-to-quantization-noise ratio, compressed pulse code modulation (CPCM) employing companding is customarily used.
This may follow one of the companding laws accepted as standard in the communications industry, e.g., the so-called U-law or the so-called A-law. As is well-known, companding requires a nonlinear transfer characteristic between the input signal

- 2 -and the resulting CPCM code. An inverse transfer character-istic is applied in the decoding process in order to provid~
an overall transfer characteristic that is linear after the speech signal has been hoth coded and decoded. This requirement can be me~, at least approximately, by using identical DAC's for both encoding and decoding. Since the DAC is one of the most complex and costly components of a PCM system using per-line codecs, such standardization of the DAC for both the encoding and the decoding processes is highly desirable.
Even more desirable from the standpoints of econom~
and circuit simplification would be the use of a single DAC
for both encoding and decoding in each line. However, upon closer examination of such multiple use of a DAC in a codec, one encounters a dilemma. Regardless of whether companding is used or notf the decision levels during encoding and the reconstruction levels during decoding do not coincide. As a matter of fact, in order to achieve minimum overall sig-nal degradation in an end to-end connection, the reconstruc-tion levels during decoding should be exactly midway between the corresponding decision levels during encoding. Thus, it has previously been considered necessary to use separate DAC's for encoding and decoding, or else to add complexity to the DAC so that its transfer characteristic can be modified by a control signal between the encode and decode modes.

S~ARY OF THE I~ENTION

My invention ofers a simple solutlon to the abo~e dilemma so that the same DAC can be used for ~oth encoding and decoding without the necessi~y o~ addina circuit com~
plexi~y to the DAC. The basic principle, according to the invention, is to genexate ~wo sample~ in the decoding for each received PCM word, in contrast to the normal procedure of generating only one sample for each PCM word.
In conventional PCM systems, the samples are generated at a rate of 8 KHz, i.e., at 125 ~s intervals. According to my invention, during decoding, samples are genera~ed at twice this rate, i.e., at 16 KHz, preferably at 62~5 ~s intervals. The first of the two samples per received PCM
woxd is generated by setting the DAC to the nearest decision level a~ove the desired reconstruction level. The second sample is generated by setting the DAC to the nearest decision level below the desired reconstruction level. The second sample is then applied to the output of the codec 62.5 ~s later, assuming an 8 KHz basic sampling rate in the system.
Qf course, the order of the samples may be reversed, i.e., the lower amplitude sample may be generated first and the higher amplitude sample may be generated 62]5 ~s later. The choice is a matter of practical implementation. Since the two samples differ by only one least significant bit (LSB~
in the PCM word used for setting the DAC, it takes only simple additional digital circui~ry in the control logic for the DAC to modify the incoming PCM word between the two samples. Included in the modification o the control logic necessary to implement the in~ention are also timing arranyements to generate two samples, equally separated, p~r basic decoding interval, rather than one sample~ With modern large-scale-integration (LSI) technology developed by the semiconductor industry, such modifications or additions of circuitry can still be made at much lower cost than the cost of providing separate D~C's for encoding and decoding or the cost of modifying a single DAC to provide different levels during encoding and decodins.
The result of providing two samples during a hasic sampling interval, e.g., an interval of 125 ~s~ is that the average signal value received during ~he interval will lie midway between the two yenerated signal levels. This is exactly what is desired in order to arrive at the proper reconstruction level. A conventional filter that receives the decoded output signal can then provide at its output the proper average signal corresponding to the desired recon-struction level.
Two such samples, differing in amplitude by one LSB
and generated at twice the conventional sampling rate, may be regarded as amplitude modulation signals of square wave-form having a basic modulation frequency equal -to the conventional sampllng rate, e~g., 8 KHz. In such a square . : .
.
:

waveform, there wi:Ll also be unwanted odd harmonics but since their amplitudes are much lower than -the amplitude of the fllndamental, -they can be adequately attenuated hy any filter ~hat is suitabl~
for conventional types of PCM decoders. It can readily be sho~n, for example, that they may be adequately attenuated by a low-pass filter having a high rejection of 4 KHz a.nd hiyher frequencies in a communication system conventionally having signal frequencies lying in the 300-3400 KHz band. Furthermore, the degree of modulation at harmonic frequencies is very low for all signal levels of concern, i.e., for signal levels higher than appro~imately 40 dB below ma~imum signal level.
In accordance with -the present invention, there is provided in a communication coding and decoding system for encoding incoming analog signals into outgoing PCM signals and also decoding incoming PCM signals into outgoing analog signals, all within a selected time period corresponding to one cycle at a basic sampling frequency, the combination comprising. means to receive a multi-bit incoming PCM character signal within a first predetermined portion of said time period; decoding means comprising a common digital-to-analog converter (DAC) for decoding said incoming PCM
signal; control means for setting said DAC to a first decision level ad~acent to one side of a desired analog reconstruction level; means for modifying said incoming PCM signal within a second predetermined portion of said time period and for utilizing said modified PCM signal to reset said DAC to a second decision level adjacent to the opposite side of said reconstruction level;
encoding means comprising said ~ommon DAC for encoding an incoming analog signal into an outgoing PCM signal during a third pre-E~

~32~

determined portion of said time period; means for sequentially reading out resul-tant analog signals from said DAC eorrespondiny to said first and second deeision levels; And means for averaging said resultant siynals to provide a decoded analog signa], ~aving a value intermediate said decision levels.
In accordance with the present invention, there is also provided a per-line eodec for a PCM eommunication channel, said ehannel having PCM input and output buses and analog input and output eircuits, comprising in combination: means comprisiny eontrol logic and timing circuits for sampling incoming PCM
character signals and deliveriny outgoing PCM signals within each basic sampling period; means comprising input sample-and-hold eircuits and output sample-and-hold circuits for respeetively sampling incoming analog signals and deeoded analog output signals;
means comprising a signal comparator energized by said incoming and decoded analog signals, a register set by said logie and timing eircuits, and a common digital-to-analog converter (DAC) for deeoding said incoming PCM signals and generating decoded analog signals during first and seeond decoding time intervals lying with-in each said sampling cycle, said eomparator being set during saidfirst time interval to a first deeision level adjaeent one side of a desired reconstruction level for said decoded analog signals;
means controlled by said logie and timing circuits for modifying said incoming PCM signals by one least-significant-bit between said first and seeond time intervals, thereby to reset said comparator during said second time interval to a second decision level adjacent the opposite side of said desired reconstruction level;
means eontrolled by said logic and timing circuits, by said compar-''~i'` - 6a -.

ator, and by said common DAC for encodiny said incorning analoy siynals into ou-tyoing PCM siynals ~uring one or more time intervals of said cycle interspersed with said first and second time intervals;
and means for averaging the decoded analog signal.aJ supplied from said DAC, thereby to yield a desired reconstruction level inter-mediate said decision levels.
BRIEF DESCRIPTION OF THE DRAWING
In the accompanying drawing:
Fig. 1 is a simplified schematic diagram illustrating one form of codec using a common DAC for encoding and decoding a PCM signal in accordance with my invention;
Fig. 2 is another similar schematic diagram illustrating a modified form of codec with a common DAC embodying the invention; and Fig. 3 is a timiny diagram comprising a set of exemplary waveforms which will be particularly referred to in connection with the description of the codec of Fig. 2.

~ - 6b -Description of the _ erred Embodiments In t.he codec represented schematically in Fig. 1, one-line connections have been shown between rnajor components to simplify the drawing. It will be apparent to those skilled in the art that each line may represent several conductors or control pa~hs. The major components of this version of my improved codec comprise an Input Sample-and-~old Circuit (Inpu~ S/H Circuit) 100, a Comparator 101, Control Logic and Timing Circuit~ 102, and 8-bit Regi~ter 103, a common Digital-to-Analog Converter(DAC) 104/ an Output Sample-and-Hold Circuit (Output S/H Circuit) 10S, an Output Low-Pass Filter 106 and a Clock 107.
Analog signals to be encoded are supplied over Input Path 110 and the sampled signal level to be encoded is supplied over a path 111 to Comparator 101. The Control Logic and Timing Circuits 102, which receive the output of Compara-tor 101 over a path 112, are controlled by clock pulses over a path 113 and by conventional S~art or Strobe pulses from suitable circuits (not shown) over a path 114. Input PCM signals are also supplied over a Bus 115. The outputs of the Control Logic and Timing Circuits 102 comprise the 8-bit leads 116 to the 8-bi~ register 103 and a Read-Out Control path 117. Outputs from the 8-bit Register 103 comprise the 8-bit Leads 118 interconnecting it with the common DAC 104. The PCM Output Bus is represented conven-tionally by reference numeral 119. An output pa~h 130 from .

3'~
the DAC 104 supplies signals both to Cornparator 101 over path 131 and to Output S/~ Circuit 105 over a path 132.
Finally, the decoded analog output signals are suppl;ed over a path 133 and through Low-Pass Filt~r 10~ to the Output Path 134. Sample-and-~old circuits 100 and 105 are also controlled from the Control Logic and Timing Cixcuit 102, as indicated schematically by control paths 150 and 151, respectively.
The procedure for encoding in the system of Fig. 1 will no~ be briefly described. Ass~ne that an 8 KHz sampling rate is used so that the basic sampling cycle occupies a time interval of 125 ~s. The input analog signal on path 110 is then samplad by Input S/H Circuit 100 at the beginning of Pach sampling cycle and is held there for the balance of the 125-~s interval. This analog signal level, supplied over path 111, is compared in Comparator 101 with the analog output on paths 130-131 from the DAC 104. The output of Comparator 101 on path 112 causes the Control Logic and Timing Circuits 102 to vary the output from the 8-bit Register 103 in a direction tending to make the analog output from DAC 104 match the analog input signal from the Input S/H
circuit 100.
For this matching process, many alternative strategies or algorithms may be used. The most efficient, from the standpoint of speed of response, is to approach the final value by conventional successive approximation techniques.

Regardless of the method used~ final result of the manipula-~ions of ~he bits controlliny DAC 104 should be a setting (iOe., a PCM word) which corresporlds to an analog output on paths 130-131 which differs from the sampled input signal on path 111 by less than 1 step, corresponding to one least significant bit (LSB), from the output o 8-bit Register 103. Stated another way, the output from Comparator 101 on path 112 should change in response to a change in the LSB only.
A logic signal level supplied over path 150 determines whether the Input S/H Circuit 110 is tracking the analog input signal (i.e. sampling this siynal) or whether it is holding the value of this input signal as it existed at the start o~ the holding interval. The Output S/H Circuit 105 is similarly controlled by a logic signal level over path 151.
By convention, the setting of the 8-bit Register 103 is used as the outgoing PCM word on the PCM Output Bus 119.
With the conventional D2/D3 format used in the United States, the magnitude bits of the outgoing PCM word are actually com-plements of a con~entional binary word which expresses the amplitude o~ the sampled level on an approximately logarithmic basis. Accordingly, the lower bound of a step on the transfer characteristic corresponds to the conventional "higher value' of the binary word, or vice versa. Accordingly, thi.s is the word which, together with the sign bit, (i.e., the most significant bit (MSB~, is transmitted to the PCM output ~3~
bus 119 as representi~g the encoded signal. Hence, when the content of the 8-bit Registe~r 103 is such that a difference of only one LSB will change the logic output of the Cosnpara-tor 101, it represents the desired PCM word which is now taken out on the Output Bus 119 at a time de~ermined by the Control Logic and Timing Circuits 102. It will be appreciated by those skilled in the art that this word can be transmitted in either parallel or serial form, as the particular application dictates.
The frequencies supplied by the Clock 107 and the para-meters of the Control Logic and Timing Circuits 102 must be so chosen that the complete encoding operation will be completed during a first poxtion of the 125-ys cycle such that the remaining time in the cycle will be sufficient ~or the circuit to perform the decoding operation by use of the common DAC 104.
The decoding process in the system of Fig. 1 requires consiaerably less time than the encoding process. In principle, ~ecoding only requires that the incoming PCM
code on the Input Bus 115 be applied to the common DAC 104 through the 8-bit Register and that thereafter the Output S/H Circuit 105 be ~witched to "sample" for a time period within the 125-1ys interval such that the analog output signal on path 130 can be acquired and stored. The Output S/H Circuit 105 may thereafter be switched to "hold'`, freeing DAC 104 for a subsequent encoding operation.

According to a preferred form of my invention, decoding is executed in two similar steps at 62.5-~s interval~. Thi5 means that the encoding must take place within one o~ ~he two 62.5-~s intervals or that it must be in-terrupted during the second decode samE~ling. ~he latter method makes the control logic and timing circuitry somewhat more cornplex but it has the advantage that more total time is available for encoding. This in turn improves the accuracy and imposes less stringent speed requirements on Comparator 101 or com-mon DAC 104, or both. This preerred embodiment is illus-trated in the schematic block diagram shown in Fig. 2. In analyzing the operation of this embodiment, reference will also be made to the timing diagrams of Fig~ 3.
Referring now to Fig. 2, many of the components may ~e essentially the same as components in the circuit of Fig. 1 and will therefore not be described ayain in detail. Such similar components include t~e Analog Input Path 210, Input S/H Circuit 200, Comparator 201, common Digital-to-Analog Converter (DAC) 204, Output S/H Circuit 20S, Output Low-Pass Filter 206, and Clock 207. Various other input signal path~s also correspond to those o Fig. 1 and will not be described in detail: for example, paths 210 and 211. Various control paths also correspond to those o~ Fig. 1. such as the Start or Strobe path 214, logic control path 250 to the Input S/H
Circuit 200 and logic control path 251 to the Output S/H
Circuit 205, as well as clock pulses supplied over path 213.

Similarly, many of the output pat~ correspond to those of Fig. l including pa~hs 230-231, 232t 233, and 234. The principal differences, as compared to ~imilar elements of Fig. l, are that the Control I.ogic and Timing Circuits 102 and 8-bit Register 103 of Fig. l have now been replaced hy master Control Logic and ~iming Circui~s Z60, a Successive Approximation Register Control circuit(SARC) 261, including an associated Register R which provides the PCM output over Output Bus 219, a separate Register R which receives the PCM input over Input Bus 215 and a common Selector 262 receiving inputs from Registers ~ and R ovex 8-bit leads 218~ and 218~, respectively. Finally, Selector 262 is interconnected with the common DRC 204 by a set of 8-bit leads 218C.
In order to simplify the schematic diagram of Fig. 2, only one control path 263 is shown between the Control Logic and Timing Circuits 260 and the SARC 261. Likewise, only one control path 264 is ~hown between the Control Logic and Timing Circuits 260 and the Register R . In actual practice, several paths will be required for each indicated control connection, as will be understood by those skilled in the art.
For example, the control o SARC 261 and its associated Register R will require interconnections with the Control Logic and Timing Clrcuit 260 to accomplish at least the following functions: (a) to read out the contents o R , either serially or in paral]el, (~) to operate the SARC 261 a~ an appropriate secondar~ clock rate adequa~e to complete the encoding cycle in available encoding time (as will be described shortly in greater detail) and (c~ to zero-set the Register ~ . Similarly, ~ontrol of register R requires interconnections with the Control Logic and Timing Circuit5 260 to accomplish the following function~: (a) to read in a received PC~ word, either serially or in parallel, during the appropriate time interval, and (b) to alter the content5 of Register R at an appropriate point o time, to be dis-cussed below~ The Selector 262 is also indicated schematically as being controlled from the Control Logic and Timing Circuits 260 over readout control path 217 so as to de-termine which of the two registers Rl and R2 i5 alternati~ely connected to the common DAC 204.
The basic encoding and decoding ,unctions of the circuit of Fig. 2 will now be described in greater detail. In this connection, reference will also be made to the illustrative waveforms in the timing diagram of Fig. 3. As previously mentioned, i~ is preferred that the decoding be executed in two similar steps at 62.5-~s intervals, which means that the encoding must either be accomplished within one of the two 62.5-~s intervals or that the encoding process must be interrupted during the second decoding interval. In the illustrative embodiment shown in Fig. 2, and as shown in the waveforms of Fig. 3, a serial PCM output has been assumed -~

~ .

with 8 bit positions, within approximately 5.2 lJS intervals, corresponaing to a bit rate of 1.544 Mb/s. This in turn corresponds to the basic ~ KHæ sampling rate. One complete 125-~s cycle is represented duriny the time inter~al t t ' in Fig. 3, with certain points o~ time, referred to below, indicated by to-t8 The clock pulses ~not precisely tv scale) are indica~ed by waveform A in Fig. 3. These may, for example, recur at a frequency of 128 KHz.
On occurrence of a Start or Strobe pulse over path 214 at time t , represented by waveform B in Fig. 3, the Control Logic and Timing Circuits 260 activate the Regi~ter R
through the SARC 261 and control path 263. At the same time, the Register R is enabled over control path 264x to receive the PMC input signal on Input Bus 215. During the first 5.2 ~s (approximately), the PCM word residing in register Rl , as a result of encoding an analog input sample during the pre ceding 125-~s cycle, is read out to ~he PCM Output Bus 219~
Simultaneously, a new incoming PCM word is read into register R2 from the PCM Input Bus 215. These operations are repre-sented by the waveform C in Fig. 3. Within the time period to-t3, as represented by waveform D, the Input S/H Circuit 200 is set into its l'sample" mode to accept a new input analog sample from input path 210. This sampling period is not critical and may for example be of the order of 15~s or more, as this sample cannot be used before the common .
. .

,~
.

DAC 204 is ag~in available. This relatively lor,g sampling time helps to improve the precision of the sample and to reduse the speed requirements on the Input S/H Circuit 200.
At time t , immediately aft~r reception of the input PCM word, the Selec-tor 262 i5 set to receive ~ignals from the Register R so that i~s content defines the analog output from the DAC 204. This is represented by waveform E.
After a short time, tl-t , to allow DAC 204 to settle, the Output S/H Circuit 205 is set to its "sample" mode so that it acquires the analog signal from DAC 204. This is repre-sented within the interval t -t3 by ~aveform F. The sampling time must be determined from the acquisition time o the DAC 204 and by the required accuracy. A time interval t -t of the order of 10 ~s may be adequate in a practical system.
After completion of the output sampling interval within t2-t3, the Output S/H Circuit 205 is set to its "hold"
mode and the Selector 262 is set to receive the 8-bit sig-nals from Register Rl. This then prepares the codec for the encoding process which will be initiated just after time t , by control of the SARC 261 from the Control Logic and Timing Circuits 260 over path 263. The encoding intervals are represented by waveform H. For this first encoding interval within t3-t5, according to the assumptions made above, a time frame o~ the order of 40-45 ~s is available before it is again interrupted at time t5. Then immediately thereafter, during the time interval t6-t7, the SARC is interrupted so "1~13'h7i~
that the DAC 204 may be "borrowed" ~ithin the time interval t6-t7 to de~ode the modified input PCM word in order to provide the second output sample approximately one-half frame later (e.g., at time t which is about ~5 ~s from the start of a cycle~. As represented in Fig. 3, the output sampling interval of waveform F is preferabLy terminated just before the start of the encoding intexval of waveform H to àllow the circuits to settle, e.g., just before and just after time t , respectively.
During this first encoding interval between t3 and t5, an extra reset pulse, represented by waveform G, is sent to Register R at time t4 to modify its content in accordance with the principles of my invention. If, according to the preceding description, the so~called D2/D3 code format is used, this modifica~ion will consist of adding one bit to the code word in the least significant bit (LSB) position.
Of course, by logic addition, this may also result in a change of the "higher order" bits in the code word. For example, there is one special case where the original unmodified code word has l's in all magnitude - bit positions~
In this case, the modification should result in a change in the most significant bit ~MSB) position with all seven "amplitude bits" left unchanged as l's. This special case can easily be handled by proper digital logic techniques familiar to those skilled in the art.

~ . ' 3ifZ7~3_ The overall result of this addition should be that the absolute output level of the DAC 204 is reduced b~ one step size. This step si~e depends on the level being sampled, as determined by the position of the chord on which this sample ls located. ~he exact point of time t4 for modii-cation of the P2 ls not critical, as will be evident from the timing diagram.
As previously stated, approximately 62 5 ~s after the start of the cycle, ~he operation of the SARC 261 is inter-rupted within the time interval t -t . After a suitable guard time, t5-t6, Selec~or 262 is again set to receive the 8-bit sample during interval t6-t7 from Register R2 (per waveform E~. Output S/H Circuit 205 is concurrently set to its "sample" mode within the interval t6-t7, as illustrated by waveform F, thereby acquiring the second analog signal level, which is one LSB lower in amplitude, from the DAC 204.
As previously mentioned, the sampling time must be determined from the acquisition time of DAC 104 and by the required system accuracy. A decoding time of the order of about 10 ~s may be adequate in a particular system, as previously men-tioned. As only a relatively small shift in level is imposed on Output S/H Circuit 205, this second sample interval t t7 may be made shorter than the first output sample interval t -t if total available time in the cycle becomes critical.

After restoring Output S/H Circui~ 205 to "hold"
condition and resetting Selector 262 to receive pulses from Register Rl, the encoding process m~y be reswned, as previously described, ~y opera~ion o S~RC 261. Accordingly, an additional encoding time of the order of about 40 ~s is now available for encoding from time t7 up to the time t~
near the end of the sampling cycle.
The interrupt arrangement just described provides almost twice the total time for encoding as compared to the system of Fig. l (e~g., within time interval t3-t plus time interval t -t .). This is a significant advantage as the speed requirements for the encoding circuits can there-by be reduced to a minimum.
While I have described certain prefexred features and embodLments of my invention with reference to the encoding and decoding laws and speeds typically used in the United States, it will be apparent to those skilled in the art that the basic principles are generally applicable to systems having other types of encoding and decoding laws and speeds, such as the European CCITT telecommunications systems with companding according to the A-law. For a general discussion of industry standards applicable to digital transmission systems and recommendations for encoding and decoding, reference may be made to the so-called "Green ~ook" of the CCITT, reporting on the "Fifth Plenary Assembly", Geneva, ':

, ~ ,

4-15 December 1972, Vol. III-2, Section 7 (ancl especially pages 372-377), published by the International Tele-communication Union, 1973. My invention is also applicable to systems with other sampling frequencies and other channel si~es (numbers oE channels). The speci~ic ~iming arrangements shown for purposes of illustration may also be modified, if desired, e.g~, for plesiochronous operation, where the encode and decode operations are not in full synchronism. The invention mas~ also ~e used in PCM systems which employ linear encoding, rather than companded encoding, although in the latter case the advantages obtained by use of my invention may be less outstandingO
While I have disclosed certain ~specific embodiments of my invention, it will be understood that these are purely exemplary and that I intend to be limited only by the scope and spirit of the appended claims.

I-cl~im:

Claims (6)

What is claimed is:

1. In a communication coding and decoding system for encoding incoming analog signals into outgoing PCM signals and also decoding incoming PCM signals into outgoing analog signals, all within a selected time period corresponding to one cycle at a basic sampling frequency, the combination comprising:
means to receive a multibit incoming PCM character signal within a first predetermined portion of said time period;
decoding means comprising a common digital-to-analog converter (DAC) for decoding said incoming PCM signal;
control means for setting said DAC to a first decision level adjacent to one side of a desired analog reconstruction level;
means for modifying said incoming PCM signal within a second predetermined portion of said time period and for utilizing said modified PCM signal to reset said DAC to a second decision level adjacant to the opposite side of said reconstruction level;
encoding means comprising said common DAC for encoding an incoming analog signal into an outgoing PCM signal during a third predetermined portion of said time period;
means for sequentially reading out resultant analog signals from said DAC corresponding to said first and second decision levels; and means for averaging said resultant signals to provide a decoded analog signal having a value intermediate said decision levels.

2. A system according to Claim 1 further comprising timing means for initiating said first and second time intervals at twice the basic sampling frequency, the second interval beginning substantially at the midpoint of said time period, whereby said output reconstruction level lies midway between said decision levels.

3. A system according to Claim 2 wherein:
said encoding means further comprises a first digital register for storing said encoded outgoing PCM signal;
said decoding means further comprises a second digital register for storing said incoming PCM signal; and selector means controlled by said control means for alternately gating said registers to said common DAC during the encoding and decoding portions of said time period.

4. A per-line codec for a PCM communication channel, said channel having PCM input and output buses and analog input and output circuits, comprising in combination:
means comprising control logic and timing circuits for sampling incoming PCM character signals and delivering outgoing PCM signals within each basic sampling period;
means comprising input sample-and-hold circuits and out-put sample-and-hold circuits for respectively sampling incoming analog signals and decoded analog output signals;

means comprising a signal comparator energized by said incoming and decoded analog signals, a register set by said logic and timing circuits, and a common digital-to-analog converter (DAC) for decoding said incoming PCM
signals and generating decoded analog signals during first and second decoding time intervals lying within each said sampling cycle, said comparator being set during said first time interval to a first decision level adjacent one side of a desired reconstruction level for said decoded analog signals;
means controlled by said logic and timing circuits for modifying said incoming PCM signals by one least-significant-bit between said first and second time intervals, thereby to reset said comparator during said second time interval to a second decision level adjacent the opposite side of said desired reconstruction level;
means controlled by said logic and timing circuits, by said comparator, and by said common DAC for encoding said incoming analog signals into outgoing PCM signals during one or more time intervals of said cycle interspersed with said first and second time intervals; and means for averaging the decoded analog signals supplied from said DAC, thereby to yield a desired reconstruction level intermediate said decision levels.

5. A system according to Claim 4 further comprising:
timing means for initiating said first and second time intervals at the beginning and midpoint of each said basic sampling period; and selector means for interrupting the operation of said encoding means during said decoding time intervals and for enabling said encoding means during said interspersed time intervals.

6. A system according to Claim 4 wherein.
said encoding means further comprises a first digital register for storing said encoded outgoing PCM signals;
said decoding means further comprises a second digital register for storing said incoming PCM signals;
and selector means controlled by said logic and timing circuits for alternately gating said registers to supply said incoming and outgoing PCM signals to said common DAC during the encoding and decoding portions of said basic sampling period.