CA1129973A - Integrated logic circuit - Google Patents

Abstract

ABSTRACT
An integrated logic circuit having a signal input which is formed by a base of a bipolar transistor and having a plurality of signal outputs which are each coupled, via a diode. to the collector of the bipolar transistor. This bipolar transistor has additional means by which an effective complementary auxiliary transistor is incorporated which dissipates a considerable part of the base current in the case the bipolar transistor is overdriven. The storage of mobile change carriers in the overdriven bipolar transistor can be considerably restricted and controlled and this avoids the need for a Schottky clamp diode across the base-collector junction of the bipolar transistor.

Description

~12~973 .

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2-7-1~78 1 PHN 9006 "Integrated logic. circuit".

. The invention relates to an integrated logic circuit having a signal input which is formed by a base of a bipolar transistor and having several signal outputs which are each coupled, via a diode, to the collector of 5 the bipolar transistor, the signal input comprising mean~
to supply current and the integrated circuit comprising a semiconductor body having a major surface to which several surface regions of a first conductivity type adjoin which are situated on a common substrate region of a second con-ductivity type opposite to the first, at least one of the said surface regions beIonging to a collector region of Z the first conductivity type which forms part of the bipolar transistor~ said collector region having a high-ohmic and -- a low-ohmic part, the low-ohmic part extending at and along the interface between the collector region and the . substrate region, the bipolar transistor furthermore com-:~ prising a major surface-adjoining emitter zone of the first ; conductivity type which in the semiconductor body is scparated from the collector region by a base zone of the second conductivity type extending up to the major surface, an electrically isolating layer being present on -the major surface and havi.ng a first aperture which overlies the emitter zone, a second aperture which is situated be-side the emitter zone above the base zone, and several ~5 third apertures which are situat:ed beside the base æone .. . . . ......

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12-7-19~8 -2- PH~ 9006 above the collector region, the insulating layer separating conductor tracks from the semiconductor body which extend into the first, the second and the third apertures for electric connection, the conductor tracks extending into the third apertures being each coupled to the collector region via a rectifying junction which adjoins the collector region, said rectifying junctions forming the said diodes, the bipolar transistor at the major surface being surrounded by an isolation zone by means of which the bipolar trans-s-10 tor is isolated electrically, at least during operation,from adjacent surface regions of the first conductivity type.
- Said circuit is known from n 1975 IEEE ~nterna-tional Solid State Circuits Conference", Digest of Technical Papers, Frebruary 1975, pp 168 and 169 and is described as being very attractive for large scale integration (LSI). The base cell is a NAND gate in which the coupling diodes at --the signal outputs are provided as Schottky diodes. In addi-tion the cell also comprises a Schottky diode which is connected parallel to the collector-base junction of the transistor. Said Schottky diode (clamp diode) has a larger diode forward voltage than the coupling diodes. The swing of the logic signal, that is the voltage difference between the signals representing a logic 1 and a log c 0, respecti-vely, is equal to the diffarence in diode forward voltageof the two mutually different types of Schottky diodes. As a result, said swing can be comparatively small, which im-~- proves the switching speed of the cell. The minimum delay ! : time of the cell is comparable to that of the version of TTL with Schottky diode and low dissipation which is some-times referred to by the abbreviation LS TTL. ~urthermore, the cell is particularly compact and the product of delay time and power dissipation is also attractively low.
Although said attractive LSI logic was announc-ed nearly three years ago now, it has up till now not resul-~! ted in commercial products ~hich have found acceptance on - the mar~et, at least~ in as far as the inventor is aware.
It is the object of the present invention to .

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provide measures to arrive at a modification of the inte-grated circ~lit described, starting from said known LSI-logic, which modification can be manufactured in a simpler and cheaper manner, while at the same time the attractive elec-trical properties and the high packing density desired forintegration are maintained for the greater part.
Surprisingly it has been found in experiments conducted in connection with the invention that, by means of special ~easures in the semiconductor structure which do 10 not require any extra operations during the manufacture, an auxiliary transistor coupled to the bipolar switching transistor can be realised which makes it possible to omit the clamp diode without thereby the switching time of the cell being increased inadmissi.bly.
According to the invention, an integrated logic circuit of the kind described in the preamble is character-. ized in that a further surface zone of` the first conducti- -vity type is incorporated in the se~iconductor structure of the bipolar transistor and is separated from the said col-lector region by the base ~one and has an electric connect-ion, the collector region, the base zone, and the further surface zone of the first conductivity type serving as emit-ter, base, and collector, respectively, of an auxiliary transistor so that, if the bipolar transistor is overdriven, ~5 a considerable part of the current flowin.g through the base connection of the bipolar transistor can be dissipated in the auxiliary transistor and the storage of mobile charge : carriers in the overdriven transis-tor can be reduced con-siderably.
l`he current dissipated by the auxiliary transis-tor reduces the current flowing through the base connection so that the base current available for the ac*ual inverter transistor is reduced.
: The proposed integrated logic circuit with an inverter transistor having coupling diodes integrated on or in the collector region and an effective bui.1.t-in I ::.......... auxiliary transistor enables switching speeds which are equal to or are better than those of LS TTL, while the ,.. , , , -, ' ' '' .

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g~3 dissipated power is considerably smaller. In addition, the pac~ing density is easily a factor two to six larger than for LS TTL. The electric connection of the further surface zone of one conductivity type is preferably formed by the conductor track which extends into the second aperture situated above the base zone of the bipolar transistor. At the major surface substantially no extra space is necessary for the further surface zone of the first conductivity type - when it is provided below the base contact in such manner 10 that the p-n junction formed between said further zone and --; the base zone in the second aperture extends up to the major surface and is short-circuited at that'area by the electrio connection of the base zone.
In an important preferred embodiment the iso-lation zones comprise zones of insulating material extend-ing from the major surface down to a larger depth in the semiconductor body than the base zone of the bipolar transis-tor and in which the base zone adjoins the insulating material at least over a considerable part of its periphery.
In this manner small bipolar transistors having small capacitances and a low charge storage can be obtained in which the auxiliary transistor further reduces and con-; trols the storage of charge. ~
In a further important preferred embodiment of the integrated circuit according to the invention a com-plementary auxiliary transistor is also incorporated~ The extent of the low-ohmic part of the collector regicn of the first conductivity type in a direction substantially parallel to the major surface is preferably restricted, said par-t extending on the one hand below the emi-tter zone ~ and below the rectifying junctions and on the other hand ; exposes, below the base zone and the overlying second aper-ture in the insulating layer~ a regioll in which the high-ohmic part of the collector region directly adjoins the

3~ substrate region while forming a ~-n junction, the part of the substrate region adjoining the high-ohmic part of the collector region cooperating as collector of the auxiliary transistor with the adjoining collector region and the base , .
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12~7-i978 -~- PHN 9~o6 zone of the bipolar transistor. In this embodiment the thickness of the high-ohmic part o~ the collector region measured between the second and the third ~-n junction pre~erably is smaller than 5 /um.
, In another important preferred embodiment of the integrated circuit according to the invention in which a complementary auxiliary transistor is also incorporated, a ~urther .surface zone of the second conductivity +ype - adjoining the collector region o~ the ~irst conductivity type is present at t~e major sur~ace beside the base zone and extends into the semiconduc-tor body from the major surface down to substantially the same depth as the base zone~ said ~urther zone serving as collector of the com-plementar~ au~iliary transistor and being connected to the substrate region.
Said further sur~ace zone o~ the second conduc-tivity type can simply be provided simul-taneously wi-th the base zone so that the distance between said zones can be comparatively small. Pre~erably the distance at th,e major 20- surface between the base zone and the ~urther sur~ace zone of the second conductivity t~pe is at most 5 /um.
, The vertical and the horizontal complementary au~iliary transistors may also be combined advantageously in the same integrated circuit according to +he invention.
The invention will now be described in greater detail 7 by way of example, with re~erence to a ~ew embo-diments and the accompanying drawings, in which Fig. 1 shows the electric circuit diagram o~
the known NAND gate.
~ig. 2 is a part o* a diagrammatic plan view of a ~irst embodimen-t o~ the integrated circuit according to the invention.
Fig, 3 is a diagrammatic cross-sectional view o~ this part o~ the ~irst embodiment taken on the line ,,' 35 III-III of ~ig. 2, ; ; ~ig. 4 shows diagrammatically a part o~ a ,,,, second embodiment o~ the integrated circuit'according to the invention, and .
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Fig. 5 is a diagrammatic cross-sectional vie~-associated with the said second e~ample and taken on the line VI-VI of Figure 4.
The electric circuit diagram of the above-men-tioned known NAND gate, shown in Fig. 1, has a signal input 1~hich is formed by the base of a bipolar transistor T and several signal outputs 2, 3, 4 and 5 which are each coupled to the collector of the bipolar transistor T via a diode 6.
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- The signal input 1 has means to supply current, which means are denoted by the current source I.
- The transistor T is a planar transistor, the collector-base junction of which is shunted b~r a Schott~y diode 7. Due to said clamp diode the transistor has the high switching speed whi-ch is desired nowadays ~or logic circuits. If the clamp diode 7 were omitted, the transis-tor in the conductive state will become highly saturated.
The transistor then contains a large amount of stored ; chargc, mainly in the form of minority charge carriers, which are situated in the collector region. The switching 20 off of the transistor occuxs accordingly slowO The clamp diode 7 prevents the transistor from becoming saturated so that the said charge storage is avoided~
If during operation the signal input 1 is not connected, the signal input 1 will be charged by the sup-25 plied current I to the emitter-base voltage of the transis-tor T associated with to the conductive state. Said diode , .
forward voltage or junction voltage VBE is, for example, approximately 7OO to 7~O mV for a silicon -transistor.
When -the voltage at the signal input reaches 30 the diode ~orward voltage ~E~ the transistor T becomes conductive and the current I is used as a base current.
The current available at one or more of the signal outputs is then dissipated via transistor T, the voltage at the relevant signal output baing equal to the diode forward 35 toltage VD1 of the coupling diodes 6 augmented by the collector-emitter voltage of the conductive transistor T.
~- Said collector-emitter vo3tage is equal to the voltaga VBE reduced by the diode forward voltage VD2 of the clamp ', .
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12-7-1978 -7~ PHN 9OO~
, diode 7. If the voltage VD2 is larger than the voltage VD1, the signal output voltage ls smaller than VB~ and the tran-sistor of a subsequent N~ND gate connected to the relevant signal output will be kept in the non-conductive state.
The swing of the logic signal, that is the difference between the high and the low signal level, is equal to the difference between the diode forward voltages VD2 of the clamp diode 7 and VD1 of the coupling diode 6.
The Schottky clamp diode 7 is a PtSi-Si contact 10 with a diode forward voltage VD2 of appro~imately 5OO mV.
The Schottky coupling diodes 6 are Ti-Si contacts with a diode forward voltage of approximately 35O mV. The loglc swing then is appro~imately 150 mV. This comparatively small logic swing has a favourable effect on the delay time of the gate circuit. When switching from the high to the low signal state, or conversely, only a small voltage difference need be bridged. So the switching can be realised in a correspondingly short period of time.
So the described known logic circuit owes its ¦ 20- attractive circuit properties to two things. In the first place there is the use of a high speed planar -transistor T
which is freed from saturation by means of the Schottky diode 7, and in the second place there is a suitably chosen metallisation with metal-to-semiconductor contacts of different compositions which provide ~chott~y diodes wi$h a favourably small difference in diode forward voltage of approximately 150 mV. Hence both in the switching transis-tor T and in determining the desired logic swing the metal-. lisation chosen plays an essential and decisive part.
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,~ 30 The present invention makes it possible to use, instead of this decisive complex metallisation which ne-cessarily is constructed from conductive layers of different materialsJ a much simpler metallisation which, for e~ample, has also been used already in e~isting products.
i 35 The first embodiment which wili be described .
further with reference to Figs~ 2 and 3 has a semiconductor ~ body 20 having a major surface 21 to which several surface ;1 regions 22~ 23 and 24 of a flrst conductivity type adjoin .

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12-7-1978 -$- PHN 9006 and which are'situated on a common substrate region 29 of a second conductivity type opposite to the first. The sub-strate region 29 may be a common semiconductor layer which is provided, for example, on any suitable substrate. In the ' 5 present example a ~-type semiconductor substrate of silicon is used having a resistivity of, for example, 10 to 15 Ohm.cm.
At'the major surface 21 the surface regions 22, 23 and 24 are each surrounded by an isolation zone 30 by 10 means of which the surface regions are isolated electrical-ly from each other at least during operation. In this example the isolation zones consist entirely of insulating material. Alternatively, p-type zones may be used extending ' from the major surface 21 into an n-type surface layer. The isolation zones 30 extend over a part of the thickness of the surface layer or penetrate through the surface layer entirely so that they reach down into the substrate 29.
By applying a voltage in the reversa direction across the p-n junctions formed between -the ~-type isolation zones and 20- the surface regions 22, 23' and 24 and/or between the sub-strate 29 and the surface regions 22, 23 and 24, electric isolation between the surface regions 22, 23 and 24 can be ensured in the usual manner during operation. Alternatively, the isolation zones;may consist partly of insulating ma-terial and partly of ~~type semiconductor material.
At least one (22) of the surface regions 22, 23 ' and 24 serves as a collector region of a bipolar transis-tor, Said collector region 22 has a high-ohmic part 31 and ' a low-ohmic part 32, the low-ohmic part 32 extending at and along the interface between the collector regi~n 22 ~ and the substrate region 29.
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Thc bipolar transistor f'urthermore has an emit-ter zone 33 of the first conductivity type which adjoins the major ~ur~ace 21 and which is separated in the semi-conductor'bod~ 20 from the collector region 22 by a base l zone 34 of the second conductivity type extending up to the ;~ ~' major surface 21. The n-type emitter zone 33 forms, with the p-type base zone 34, a first ~-n junction 35'having a first , ' ~ .,.. , .. .... ,,, , . , , ,: ~ ' :, ' _9- PHN 9006 diode forward voltage VBE, and the p-type base zone 34 forms, with the _-type collector region 22, a second p-_ junction 36.
Present at the major surface 21 is an electric-ally insulating layer 37 which in the plan view shown in Fig. 2 is considered to be transparent. The layer 37 con-sists, for example, of an insulating material, for example silicon dioxide or silicon nitride or a combination thereof.
A first aperture 38 in the insulating layer 37 is situated above the emitter zone 33. A second aperture 39 is situ-ated beside the emitter zone 33 above the base zone 34. In addition, beside the base zone 34 above the collector region 22 several third apertures 40 are present. In Fig. 2, the apertures shown in the insulating layer 37 are illustrated in broken lines.
The insulating layer 37 separates conductor tracks 11, 12, 13, 14, 15 and 41 from the semiconductor body 20, which tracks extend into the first, the second and the third apertures 38, 39 and 40, respectively, for electric connection. For clarity, not all conductor tracks of the integrated circuit are shown i~ Fig. 2. Those conductor tracks which are shown are shadedO
The conductor tracks 12, 13, 14 and 15 extending into the third apertures 40 are each coupled to the collec-tor region 22 via a rectifying junction 16 which adjoins said collector region. In this example the rectifying junctions 16 are metal-to-semiconductor junctions orSchottky -~
junctions, and may comprise platinel silicide contacts as described in United Sta-tes Patent 3,855,612 - Signetics Corporation - Dec. 7, 1974. The rectifying junctions 16 have a diode forward voltage VDl. For the operation of the circuit it is desired that junctions 16 be used having a diode forward voltage VDl which is smaller than the diode forward voltage VBE of the emitter-base ~-n junction 35 of the transistor.
In a direction substantially parallel to the major surface 21, the low-ohmic part 32 of the collector region 22 extends from below the emitter zone 33 to below the rectifying junctions 16.

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~9~73 12-r~'-1978 -10- PHN go~G

J According to the invention, a further surface ! zone 80 of the first conductivlty type is incorporated in the semiconductor structure of the bipo]ar transistor 33, 34, 22 and is separated from the collector region 31, 32 by the base zone 31~. The collector region and in particular the low-ohmic part 32 thereof, the base zone 34 and the _-type further surface zone 80 serve as emitter, base, and : collector, respectively, of an auxiliary transistor. This auxiliary transistor is of the same type as the bipolar switching or inverter transistor. In this example the in-verter transistor and the auxiliary transistor are both npn-transistors.
The further surface zone 80 is preferably pro-vided simultaneously with th0 0mitter zone 33 so that the 15 depth of penetration into the base zone 3~ and the profile in doping concen-tration of the zones 80 and 33 are the same The further surface zone 80 which serves as collector of the auxiliar~ transistor comprises an electric ~ connection. This connection may be a separat0 co~nection to which a suitable reference po-tential can be applied during operation. Preferably, however, as in the example, this connection is combined with the connection for the base zon0 34. The ~-n junction 81 between the further zone 25 80 and the base zone 3~ extends in the second aperture 39 up~to the semiconductor surface 21 and is shor~circuited in said aperture by means of the conductor track 11. The -~ conductor tracX 11 is connected both directly to the base zone 3~ and directIy to the further surface zon0 80.
In the circuit described, the auxiliary tran-sistor 32, 34, 80~proves to be a means to improve the s~itching speed, whlch is surprisingly effective. Minimum delay times of a few nsec. can be realised with the inte-grated logic gate circuit according to the invention. Henoe the minimum delay time is comparable with or more favourable than that of the conventional LS TTL. The packing density ------ and the product o~ delay time and power dissipation are both more favourable than for LS TTL. These favourable .

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1~ 73 12-7-1978 ~ PHN 9006 properties of the integrated circuit according to the in-vention are also remarkable in particular because in con-trast wiGh LS TTL in which the inverter transistor in the conductive state is not saturated, the inverter transistor in the present c:ircuit is saturated indeed. ~owever, as soon as the base-collector jul~ction 36 becomes biased in the forward direction, a part of the base current of the overdriven inverter transistor will be used as a base cur~
rent for the auxiliary transistor. In addition, when the surface zone 80 is connected to the base zone 34, a usually considerably larger part of the base current will be able to flow through the maln current path of the auxiliary transistor directly to the collector of the inverter tran-sistor.
~linority charge carriers are collectod from the base zone 36 across the rectifying junction $1 which does not come in the forward direction~ As a result of this the storage of ~aid charge carriers in itself is already re-duced. An important effect, however, is also that, since 20 a considerable part of the current flowing through the con--nection 11 is dissipated in the auxiliary transistor, less base current is available for the inverter transistor it-self. As a result of this the inverter transistor is less overdriven so that the base-collec-tor junction 36 is 25 polarized less I`ar in the forward direction and the voltage across the emitter-base junction 35 will also be smalIer.
As a result of this the storage of minority charge carriers ill the inverter transistor as a whole is also accordingly smaller.
As in the present example, the isolation zones 30 preferably comprise~insulating material, said insulating material extending ~rom the major surface 21 down to a - larger depth into the semiconductor body 20 than the base zone 34 of the bipolar inverter transistor. The base zone 3~ adjoins the insulating material at least over a considerable part of its periphery. In the example the base zone 34 on thre0 sides adjoins the isolation zone 30 which separates the transistor from the other transistors. A zone S2 of .... . ..... . . . ...... ......
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~73 12-7-~978 -12- P~ gOO~

insulating material is also present on the fourth side, the side of the base zone 34 facing the coupling diodes. Said part 82 of` the pattern O:r insulating material does not ser-ve for eleotric isolation of the transistor but serves to limit the base zone 31~. By using the pattern of insulating material the surface of the base-co]lector junction 36 is kept comparatively small and the possibility of storage of charge carriers in the collector region 22 is restricted and the storage of charge carriers in the high-ohmic part 10 31 of the collector region 22 situated beside the base zone 34 is avoided.
It is to be noted that, although the zone 82 of insulating material is preferably present, said zone is not necessary. The zone 82 may be omitted entirely so that the high-ohmic part 31 of the-collector region adjoins the base zone 34 àt that area. In that case also the storage of charge carriers in the collector region will be compara-tively small due to the suct1onal effect of in particular the coupling diode situated nearest. Said suc-tional effect 20 will be further described with reference to the second example.
Fur-thermore~ instead of the zone ~2 o:~ insu-lating material, a highly doped n type zone may be used which restricts the injection of holes from the base zone 34 in the lateral direction substantially parallel to the major surface.
In the example the base zone 31~ of the inverter transistor reaches down to the low-ohmic part 32 of the collector region 22 and said base zone is separated from the substrate region 29 by said part 32. The doping con-centration on the collector side of the junction 3O will hence -be comparatively~hlgh so that the depletion capacity of said junction is comparatively large. It is more impor-` ~ tant, however, thatS due to s~id comparatively high con-centration, comparatively little s~rage of minority charge carriers will occur in the collector region.
The emi-tter zone 33 adjoins the insulating ma-terial 3O only on two sid~s. This has ~or its advantage ., .. .. ... ,,, .... . . . ~ . ............ . . .. . . . . .. ... .... . . . .

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that the surface area of the emitter zone 33 is not so de-pendent on deviations in location which may result from tha non-ideal alignment of masks dur.ng the manufacture. In applications in which the si.ze of the surface area of the S emitter zone is not very critical, however, the emitter zone : may also be provided against the insulating material 82 so that the emitter is bounded by insulating material on three sides, In that case the inverter transistor may be smaller.
- Fig. 2 also shows surface regions 23 ancl 24 10 which comprise identical, or at least similar, circuit elements. Thus these regions 23 and 24 each serve as a collector region of a planar npn transistor having a number : of signal output tracks which are coupled to the relevant collector region via a diode. The number of diodes may vary for each individual transistor between one and, for example, four or five and will depend on the logic function to be generated by the integrated circuit.
The collector.regions or islands 22, 23 and 24 are arranged beside each other along an elongate surface ~0 region 28 ~rom which the signal inputs 11 are provided with current. In said region 28 a number of lateral pn~ transi.s-: tors are provided which ha.ve a common ~-type emitter zone :~ 43. The regi.on 28 serves as a common n-type base zone. The pnp transistors each have a separate ~-type collector zone .
44 which is connec-ted to a signal input 1i via an aperture 45 in the insulating layer 37. The common emitter zone 43 is connected, via an aperture 46, to a conductor t.;ack 47 :: : which has a diagrammaticaIly shown connection 48 for a ; : supply source.
The common base zone 28 has a high-ohmic part 49 and a low-ohmic part 50 in the :form of a buried layer.
Furthermore~ a low-oh.mic n-type surface region 51 is pre-sent in the base zone 28 whi.ch may be provided, for example, simultaneously with the emitter zone 34. The buried layer 50 and the surface region 51 serve to reduce the base :: series resistance. The buried layer 50 also serves to -- suppress parasitic transistor action to the ;substrate.
, Above the surface region 51 an aperture 52 in the insulat-, :
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12-7-1978 ~ - PHN 90~6 .

ing layer 37 is ~resent through which the common base zone 2~ is connected to a conduc-tor track 53.
The integrated circuit is constructed with a metallisation which is divided over several layers and without which complex LSI circuits are substantially not realisable nowadays. For that purpose, the insulating layer 37 consists of a first or lowermost layer 55 having the , apertures 38, 39, 40, ~5, 46 and 52 and a second o,r upper-most layer 56. A first level o~ conductor tracks which com-10 prises inter alia the conductor tracks 12 to 15~ 47 and53 is situated,on the lowermost layer 55. The conductor tracks 11 consist of two parts of which ~irst parts 57 lie at the first level and extend into the apertures 39 and 45 and of which a second part 58 lies at a second level which is separated from the first level by'the uppermost layer 56; the second part 5~ is directly connected to the first parts 57 via apertures 59.
~onnections between signal inputs 11 and signal ~ outputs 12 to 15 can also be realised by means of the : 20 second level of` conductor tracks~ For example, the base zone of the inverter transistor in the island 24 may be connec-ted to the conductor track 12. The second part 58 ~ of the conductor track.11 then extends in the direction : shown horizontally in ~ig. 2 from the coIltact with the base zone across the emitter zone of the inverter transistor and the conductor track 41 to above the conductor track 12 and at that area it is connected through an aperture 59 (not shown) in:-the second insulating layer 56 to the end shown of the conductor track 12 a In a modified embodi.ment of this example the : conductor track which interconnects the e.mitters has been moved to the second level of conductor tracks and the ~, intermediatecpaces between the inverter transistors are ~: .
` slightly enlarged so that the first parts 57 of the con-ductor tracks 11 can be connected to the conductor tracks . 12 to 15 at ~he first level via conductor tracks situated ,; ',' , ~ at the ~`irst level and extending between the inverter ,~' transistors. T:he conductor track 5~ may be connected to a .
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: , : ' ' , ~29~73 connection 54 which is shown diagrammatically.
The conductor tracks 12 to 15, 47 and 57 of the first level may be, ~or example, aluminium or another suitable conductive material. If desired, a barrier layer may be used to avoid direct contact between the aluminium and the plantinel silicide formed in the apertures in the insulating layer. As a barrier layer may be used, for example, titanium-platinum or titanium-tungsten or rhodium.
The conductor tracks 58 of the second level 10 are, for example, of aluminium or titanium-platinum-goldT
Preferably, the same material is in direct con-tact with the semiconductor body in ail apertures 38, 39, 40, 45, 46 and 52 in the first insulating layer 37 and notably in the first, the second and the third apertures 15 38, 39 and ~0. In the present example this material is the said platinel silicide which in the apertures 40 forms a Schottky diode and which, in the other apertures, forms a readily conductive junction betwe~n -the conductor tracks and the semiconductor regions adjoining same in said aper-20 tures.
The conductor track 41 connected to the emitterzone 33 is provided wi-th a connection 60, shown diagram-matically, and the substrate region 29 has a connection 61 which may be connected to the connection 60 to form a com-- 25 mon connection 62 for a supply source.
The connection 62 may be connected to a suitable reference potential, for example ground potential. A
suitable current or voltage supply source is connected be-tween the connections 62 and 48. The connection 54 is connected to a suitable reference potential, the pn~
transistors being conductive. The integrated circuit further-more has one or more signal inputs~ not sho~n, via ~hich input signaLs can be supplied to one or more conductor ~ ~ tracks 11, and one or more signal outputs, not sho~n, via; 35 which output signals generated by the integrated circuit can loe derived~ For completeness~ sake it is to be noted that the second level of conductor track~ may ~e covered entirely or partly with a further insulating layer, i~ so ' ,.
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desired.
The embodiment described can be manufactured entirely by means of methods known in semiconductor tech-nology. For example, the method may be used which is des-cribed in United States Patent 4,199,378 - Signetics Corporation - April 22, 1980. This method is of advantage inter alia when the current supply to the base zones of the inverter transistors is realised by means of lateral complementary transistors.
A second embodiment will be described with reference to Figs. 4 and 5. In this embodiment, the same reference numerals are used as in the first example for corresponding components of notably the inverter transis-tor and the coupling diodes.
In the plan view shown in Fig. 4 the conductor tracks at the first level are shown only partly. This concerns inter alia the conductors 11, 12 and 57. For clarity, the conductor tracks shown are shaded in this figure also.
The second embodiment comprises a number of n-type surface regions 22 to 26 and 72 which are separated from each other in the usual manner by means of p-type isolation zones. The surface regions 22 to 26 serve as collector regions of bipolar inverter transistors. The transistor in the collector region 22 will be described in greater detail specifically hereinafter.
Said transistor comprises an emitter zone 33 and a base zone 34 which form a first _-_ junction 35.
The base zone 34 furthermore forms a second junction 36 with the collector region 22. A further n-type surface zone 80 which is connected to the conductor track 11 is provided in the base zone. This transistor also comprises a vertical auxiliary transistor 22j 34, 80 which is of the same type as the inverter transistor. Both transistors are npn trans~stors. In this example a few further meas-ures are taken in addition to improve the switching speed.
In this embodiment, the low-ohmic part 32 of :

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,. . .
the collector region 22 in a direction substantially parallel to the major sur*ace 21 has a restricted extent, in which said part 32 on the one hand is situated below the emitter zone 33 and below the recti*ying Junction 16 and on the other hand does not extend in a reg:ion belo~ the base zone 34 and the overlying second aperture 39 in which region the high-ohmic part 31 of the collector region directly adjoins the substrate region 29 while *orming a third p-n junction 42. The thic~ness of the high-ohmic part 31 of the collector 10 region 22 measured between the second and the third ~-n-junctions 36 and 42~ respectively~ is preferably smaller than 5 /um. As a result o* this additional measure, by which : below the base contact the substrate region extends up to a ; comparatively small distance *rom the base-collector junction 15 36, the relevant part o* the substrate region 29 cooperates effectively as a collector of a complementary auxiliary transistor with the adjoining hig-ohmic part 31 which is situated between the two ~-n junctions 36 and 42, and with the baee zone 3L~. A vertical complementary auxiliary transi~
20 tor 34, 31, 29 is thereby incorporated in the npn transistor structure ill an effective manner and substantially without this requirin~ rnore semiconductor sur*ace area for the transi.stor. As a result of this~ when the inverter transis tor is overdriven, a part of the current flowing in the 25 base zone 3~ flows through the complementary auxiliary transistor 34~ 31, 29 so that -the storage of mobile charge carriers in the overdriven inverter transistor is further restricted. ~ : .
-~ In the present example the emitter zone 33 is, ~; 30 for example~ 12 /um x 12 /um. The associated contact aper-; ture 38 is approximately 6 jum x 6 /um and for .the ~istance :. at the semiconductor sur*ace between the emitter base junction 3~ and the base-collector junction 36 a minimum value of 3 /um is used. The active part of the base zone 35 required for the emi.tter zone is 18 /um x 18 /um. However~
~ at least one contact aperture *or contacting the base is : .. necessary beside the emitter zone.
~ ln this connection~ the active paxt of the base ' .
' ' ''' ' ' "'' ' ' ' ' - ,.... .. ..

-~ !

95~73 12-7~19~8 -18~ -P~N 9006 zone 34 is to be understood to mean that part whicll is necessary to be able to accommodate an emitter zone 33.
~djoining said active part a non-active part of the base (,,t zone 34 is necessary for electric col~lection of the conduc-tor track 11.
The dimensions of the base zone 34 are, for example, 37 /um x 18 /um. The size of the non-active part in this case is 18 /urn x 19 /um and it thus has a larger area -than the active part. Within the scope of the present 10 invention the non-active part of the base zone 34 which comprises the, emitter of the ver-tical complementary auxilia-ry transistor is preferably at least equally large as the active part.
The comparatively large non-active part of the 15 base zone 34 iIl this example facilitates the placing of the further surface zone 80 and the shortcircuit of the ~-n junction 81 in the aperture 39. The aperture 39 is, for example~ 10 /um x 12 /um and the surface zone 90 is approxi-mately 6 /um x 12 /um. The area occupied at the major sur-20, face 2'l by the surface zone 80 is preferably at least onethird of that of the emitter zone 33 and the surface zone 80 is at most two to three times as large as the emitter zone 33~ Good'results were obtained in particular with a surface zone 80 which is at least half as large as the emitter zone 33.
Since the non-active part of the base zone 34 ' in, this example is comparatively large and the low~ohmid part 32 of the collector region 22 does substantially not ' reach further than -to below the emitter zone 33, the oppo-,~ 30 sitely located parts of the ~-n junctions 36 and 42 also have a comparatively large area. This means that the in-corporated vertical ~ auxiliary transistor is cornparati-vely large. According as the _~ auxiliary transistor and/or , the ~'auxiliary transistor is larger, excessive base ,~ 35 current of tlle conductive inverter transistor is dissipated '~ ; more effectively and at a lower forward voltage across the - ~-n junction 36. 'L`he conductive inverter -transistor is then less overdriven and the charge storage in said transistor '''~ '"'' ' '~'''' ''" ' ~i t .. , . . . . , ~

12-7~1978 -19- P~N 9006 , is correspondingly reduced.
I The apertures l~o have dimensions of, for example~ 5 /um x 22 /um-For cornpleteness~ salce it is to be noted that 5 the above-given dimensions sirnply relate to the masks which are necessary for the various photolithographic treatments during the manufacture. In the integrated circuits them-selves the actual dimensions, as is known, slightly differ ; inter alia because upon exposure and development of the 10 photosensitive lacquer an exact reproduction of the masks is not obtained, because during the etching treatments ; undercutting often occurs and because upon diffusion of - impurities lateral diffusion also occurs.
In the above description it is assumed -that the 15 inverter transistor has a single emit-ter zone 33 and a ; single base contact aperture 39. Alternativel~-, for example, two conductively interconnected emitter zones may be used dependent înter alia on the desired current level. Several base contact apertures may also be present, for example, 20 two base contact apertures on oppositely located sides of a single emitter zone. 1~len several base contact apertures are used it is not necessary to incorporate an auxiliary transistor below each of the base contac-ts. The collector region 22 of the inverter transistor preferably is sub-25 stantially rectangular and the aper-tures 38~ 39 and l~o i~
the insulating layer are situated beside each other in the same direction, the emitter contact apertur~ or apertures 38 and the associated emitter zone or zones 33~eu~situated between the apertures 40 for the coupling diodes on one 30 side and the or at least one of the apertures 39 for the base contact on the other side. The incorporated vertical compIementary auxiliary transistor is preferably situated below the last-mentioned outermost base contact aperture.
T~e buried layer 32 preferably continues uninterruptedly , ~
?5 from below the emitter zone 33 to below the coupling diodes 16. A f`urther surface zone 80 is preferhbly ~I situated at least near said outermost base contact aper~
ture~ Because in this place 'he vertical complementary ~,s~: ~ '' .
: '1 ~,: :' ' . .~ " . '. ' '.
~ ~.,;.. ,..--' ~ ~

- ~29~73 ..

12-7-1978 _20- PH~ 9006 auxiliary transistor is incorporated, the space available for the further surface zone 80 usually is comparatively large. lf other second apertures 39 are also present above the base zone 34, surface zones 80 may also be provided advantageously near said base contact apertures. In this connection it is to be noted that by incorporating a ver-tical complementary auxiliary transistor below a surface zone 80, the favourable effect of the surface zone 80 in - itself can be reduced. The fact that in that case the low~ ohmic part 32 of the collector region 22 does not extend to below the surface zone 80, may have for its resul-t that the collector region 22 constitutes a less ef`ficient emit-ter for the n~ auxiliary transistor. The overall favour--able efect of the two auxiliary transistors together (npn and pnp), however, will be larger than that of a single auxiliary transistor.
Ar.other measure to improve the swltching speed is that an improved lateral complementary auxiliary tran-sistor is incorporated by the addition of a further sur-face zone ~1 which during the manufacture can be obtained . . .
simultaneously with the base zone 34. In contrast with thesurface zone 80~ the zone 71 has-the same conductivity type as the base zone 34 and as the isolation zone 30. ~t the semiconductor surface the zone 71 coincides partly with the isolation zone 30. The zones 71 and 30 overlap ~` ~ each other. It is of importance~that the base zone 34 and the isolation zone 30 are obtained with different dif-fusion treatments. ~s a resu]t their mutual distance at the semiconduc~r surface must be comparatively large. The base zone 34 and the zone r~ 1 on the contrary are obtained si-multaneously with the same diffusion $reatment so that ~`~ their mutual distance can be comparatively small. They have substantially~the same depth of penetration in the semiconductor body and they have suhstantially the same profile in doping concentration in a direction transverse to the major surface. ~ usual distance between the base - zone 34 and the isolation zone 30 would be, for example, approximately 10 junl. The dlstance betwe-n the base zone , ' ' '' ': ' ' .. . .. ..

~ ~9~3 34 and the further surface ~one 71 need not be more than 5 1um. The zones 34 and 71 constitute the emitter and the collector of a~ effective lateral complementary auxiliary transis-tor the base thickness of which is 5 /um or less.
If -the inverter transistor is conductive, said auxiliary transistor also dissipates current so that the inverter transistor is less overdriven.
~s stated, the base width of the lateral com-plementary auxiliary transistor is preferably at most 5 /urn~
In the present example the indicated distances of 10 and5 /um apply to the masks to be used in the manufacture and the corresponding dimensions in the integrated circuit are sma].ler, in particular due to the occurrence of later-al diff`usion. The distance between the base zone ~ and the isolation zone 30 will on an average be approximately 7 /um. The base thickness of the lateral auxiliary transis-tor actually is approximately 3 /um.
In this embodi.ment having a la-teral complemen-tary auxiliary transistor the additional surface zone 71 20. const:itutes the region of the second conductivity type which effectively serves as collector of the complementary auxiliary tran.sistor.
The further surface zone 71 may have a closed geometry and surround the base zone 34 as a ring, which : 25 extends between the base zone 34 on the one side and the coupling diodes 16 on the other side. Preferably, however, tae further zone 71 is open on the side of` the coupling diodes 16 and. sùrrounds the base zon.e 34 only at the part of the edge of the base zone not facing the coupling diodes. Therefore in the present example the zone 71 is in the form o.~ a.U
The use.of a zone 71 having a non-closed geo-: metry is based on the recognition of th.e fact that such a zone is substant;.al.ly superfluous on the side of the base ~5 zone 34.facing the coupling di.odes 16. Notably~ if the coupling diodes are Schottky diodes, the lifet;.me of the - minority charge carriers in the coll.ector region 22 a~
the rectifylng junctions iO is very small. In particular , .;.. .. . , , ............. -. - .. - .
.

:

3L~ 73 ' .

12-7-1978 ~22- PIIN g~o6 '. . . .
the first coupling diode situated nearest to the base-zone 34 will draw minority charge carrlers from the collector region and thus fulfils substantially tne same function as the zone 71. As a resul-t of this, a slightly larger current will ~low through the first coupling diode than through the remaining coupling diodes which are situated farther away.
This dif`ference in current level, however, is so small that the proper electrical operation of the ci~cuit is by no means endangered by it. The inverter transistors have amply sufficient gain to be able to absorb said current differenc-es. The above-described ef`fect of the coupling diode on the storage o:f` minority charge carriers will also occur in the first example if the zone 81 of insulating material between the base zone 34 and the coupling diodes 16 is omitted.
The U-shape selected for the further surface zone 71 has the important advantage that no extra area is necessary at the semiconductor surface. A closed shape or ring surrounding the whole collector region would restrict the area available for the coup:Ling diodes. A closed shape or ring surrounding the base zona 34 and extending between the base ~one 34 and the first coupling diode 16 would necessi-tate a larger distance between said base zone 34 and the first coupling diode l6. ---Another measure by which the switching speed can be increased is to replace the lateral ~ transistor43, 28, 44 of the first example used for the suppl~ of current by a resistor in combination with a lowest pos~
sible supply voltage of 1 V or less. The supply voltage pre~erably is at most equal to the sum of the diode forward voltage VBE of` the inverter transistor and the swing of the logic signal, or in other words, at most e~ual to approxima-tely 2VBE ~ ~D1 9 ~ere VD1 is the diode forward voltage of the coupling diodes.
The last-mentioned measure has also been rea-lised in the second example. rhe collector regions 22 to 26 o~ the inverter transi.stors are arranged on the opposi-tely located sides of a common surface region or island 72.
Said i~and 72 com~rises a number of resistors 73 which are .
~ ~ , ` ` `'' ' .
.
..
.~.. ~.... .

.
.

, .

each connected to a signal input conductor 11. The resis-tors 73 furthermore comprise connection contacts in the form of a conductive layer 74 which, as the conductor layers 82 connected to the emitter zones 33, belong to the first level of conductor tracks. The conductive layers 74 serve for the connection to a supply line 75 which is not shown in Fig. 4 and e~tends horizontally in the plane of the drawing of Fig. 4 substantially centralLy above the ~- resistors 730 Said horizontal supply line 75 belongs to the conductor tracks of -the second le~el and has projections which in the planc of Fig. 4 are directed alternately up-wards and downwards and which are connected to the layers 74 through an aperture in the incula-ting layer 56 which separates the conductor tracks of different levels from each other.
The second supply line 83 also belongs to the conductor tracks of the second level and is not shown in the drawing of Fig. 4~ The supply line 83 extends sub-stantially parallel to the supply line 75 and overlies the emitter zones 33.
Fig. 4 finally shows a few signal input conduc-~
.
tors 11 and signal output conductors 12 which belong tothe first level of conductor tracks. In so ~ar as signals of other parts of the integrated circuit situa-ted farther away a~e to be supplied to the inverter transistors shown, at least two positions situated between the electric con-nections of the resistors 73 in a direction p~rallel to the supply lines are available. In addition, a position may sometimes be used between the resistors and the in-verter transistors as is shown at the bottom of Fig~ 4.Furthermore, signal conductors crossing each other can also be reallsed by means o~ the second level o:~ conductor ~; trac~s.
- The resistors 73 ha~e a structure which is usual for inte~rated circuits. They are ~--type zones Wl.liC~
can be obtair~ed simultaneously with the base zones 34. ~aid zones 73 are situated in the common island 72 above a ~- buried layer 76 belongin~ to the island 72. A Inore highly : ~ .
.

" ' : -i ~.~.2~9~3 -12-7-1978 _24- PHN goo6 doped n-type surface zone 77 is provided at the-end of the resistors 73 connected to the supply line 75, simultaneous-ly with the emitter zones 33. The p-n junction 78 forme~ at the boundary of the zones 73 and 77 is short-circuited by the overlying conductive layer 74. The supply line 75 is connected directly to the common island 72 via the surface zones 77.
It will be clear that not all resistors need be connected on one side to the common island 72 via an ad-joining surface ~one 77 and a shortcircuited ~-n junction 78. For example, one single connection between the supply line 75 and the common island 72 will in itsel~ often suffice. Only the leakage currents of the various ~-n junctions need be-dissipated vla the connection to the sup-ply line, so that -the current through sa~d connection is comparatively smalll.
The sheet resistance of the zones 73 is, for example, approximately 200 Ohm. The resistors each have ` a value o:~, :for example, approximately 800 Ohm.
~he supply line 75 is connected to a connect-ion 48; the supply line 83~ as well as -the substra-te region 29, is connected to the connection 62. Between the con-nections 48 and 62 a supply voltage can be applied of, for example~ approximat~Iy 920 mV. Said supply is shown diagramrnatically in~Fig. 5 by the voltage source 79.
- The~selected supply voltagé is equal to the sum of~ the dlode~ forward ~oltage VB~ of the inverter transis-tor and the logic swing. The logic swing is equal to the voltage VBE~decreased by the diode forward voltage VD1 30 ~ and the oollector-emit-ter voltage VcE of the conductive inverter transistor.~
During operation,~the output of a first gate circuit~ having a co~ductive inverter transistor is con- -nected to the input of a second gate circuit whose inver-ter trarlsistor then is non-oonductive. A voltage drop equal to the logic swing will occur across -the resistor associat-e~ with the firs-t gate circuit. In :~act, the input signal is high a-nd equals the base-emitter forward vo:Ltage V~E.

. . . .
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"1, ~ ' ' , LZ~73 . .
, , .
12 7_1978 -25- P~N 9O~6 A voltage drop which is tw~ce as large as the logic swing will occur across the resistor associated with the second gate circuit. In this case the input si~nal is low and is approximately equal to the sum of the diode forward voltage VD1 and the voltage ~CE of the conductive transistor.
The current which flows through the second resistor and which is dissipated via the collector of the conductive - -A . . transistor thus is approxima-kely twice as large as the current which flows through the I`irst resistor and which is supplied to the conductive transistor as a base current So the conducti~Te transistor clearly is less overdriven than would have been the case with a more ideal current supply source. In the latter case the base and collector currents would have been substantially equally large while in this example as a result of the low supply voltage in combination with the resistors 73, a factor of two differen-ce occurs. The charge storage in the inverter transistor is decreased accordingly.
Also when a higher supply voltage is used it 20- may be o* advantage to supply -the currents via resistors -to the bases of the inverter transis-tors. The resistance values o~ the resistors will then have to be large I~
necessary, the resistors may be manu~actured in known manner by means of` ion implantation. In that case resis-tance zones having a shee-t res~stance of, for example9 approximately 2 l~Ohm can simply be obtained. Alternative-ly, the resistors may be provided, on the semiconductor body instead of in the body, for example, with a layer of . resistance material~ such as titanium9 tantalum or poly-crystalline semiconductor material, ob-tained by deposition or otherwise.
In the second example described, cu:rrent is dissipated to the connection 61 via the vertical and/or the horizontal complementary auxiliary -trans:istor. Said 3~ electric connection 61 constitutes the connection of the collector of` the auxiliary transistor. In order to reduce the series resls-tance i-t may be favourable in this con-nection no-t to contact the substrate 29 at the lo~er side "

` ~lZ9~73 . .
.
` 12 7-197S -26 P~IN 9006 or to co~tact it not only at the lower side, but to con~
nect the deep ~-typc zones 30 to a conductor tr~ck ~nct, :~or example, to the supply line 83 on the upper side o~ tho semiconductor body at locations pre~erably situated at regular mutual distances. If the isolation zones consist of insulating material throughout their depth or over a part - of their depth, and a complemen-tary auxiliary ~ransistor is used, it is recommended to provide deep semiconductor zones at locations regularly arranged between or beside the gate circuits, which zones extend from the semiconductor sur~ace down to the substrate region and are connec-ted at the semi-conductor surface to a conductor track 30 that in this man~
ner they may serve for the desired dissipation of current.
The integrated circuit according -to the second ~5 embodiment can also be manufactured entirely in -the usual manner by means of methods known in semicouductor tech nology.
; The embodiments described have a combination of properties which are particularly suitable for ISI cir-cuits. First of all, the manufacturing process necessary for said integrated circuit is considerably simpler than for the described known circuit. The integrated circuit according to the invention can be manufactured wi-th the same available process in which, ~or example, LS TTL and I L c,an also be manufactured. In contrast with the l~no-~n circuit described~ LS TTL and I L are botll on the marke-t as comlllercial products.
In the second example an n-type epitaxial layer was-used in a thickness of approximately 3 /um and a resistivity of approximately 0.7 Ohm.cm~ As stated, the Scho-t-tky coupling diodes were of a type which is also usual in LS TTL having a plantinel silicide junctio~. The diode forward voltage of said diodes was appro~imately 0.~8 ~t.
As is known, the conventional L L is compara~
tively slow as compared with LS TTL. The minimum delay time of an I L inverter having a s~ingle outpu-t is approxi-mately 10 to 20 nsec., wherea5 ~or LS T'rL the minimum .
delay time ls in the proximately o~ approximately 5 to 7 - -~ 9~73 12-7-1g78 -27- PHN 9006 nsec. The switching times given here are ~alised in I L
and LS TTL integrated circuits, respectively, with an epitaxial layer having a thickness of approximately 3 /um.
The resistivity of the epitaxial layer for I L circuits is approximately 0.7 Ohm Ctn ~ ~rhereas for LS ~TL circuits a value of approxilnately 0.3 Ohm.cm has been assumed.
It is very surprising that the minimum delay time for the circuit according to the invention in the second embodiment described may be approximately 2 to 3 nsec. ~t a current level of, for example, approximately 400 /uA the emitter-base diode forward voltage is, for example, approæimately 760 mV and the collector-emitter voltage V~E of the conductive inverter transistor may be approximately 60 mV. The swing of the logic signal then is approximately 220 mV.
In spite of the fact that the inverter transis-tor in LS TTL is kept from saturation by means of a Schottky clamp diode and the inverter transistor in the circuit according to the invention does become saturated, the latter circuit nevertheless has a delay time which is approximately two times smaller. The comparable I L in-verter which also becomes saturated, on the contrary has a 3 to 6 times larger delay time. Apparently, the incorporat-ion of`one or more auxiliary transistors as indicated is ~- 25 an unexpectedly effective means in which the consequences of the fact that the inverter transistor becomes satllrated -are drasticaliy restricted and in which the extent to which the inverter transistor ~ecornes sa-turated is re~lily controlled. ~ ~
For LS rTL the ~ D product, that is the pro-duct of the delay time r and the power dissipation D
; associated with said delay time i-n a usual construction is approximately 19 pJ~ For I2L and the circuit according to the invention the r D product is o~ approximately the sarne value, namely 0.3 to 2 pJ.
~ A third quanti-ty which is extremely important u~ for LSI circuits is the packing density or the num~er of gate circuits which can be realised on an average per mm , , . ... . - `
. , " ~.:.. , , : . :

~; ~

`` 3L~9973 , 12-7-1~78 -28- , PH~ 900 of semiconductor surface area. In this respect, as is known, l L with a packing density of approximately 200 to 250 gates/mm is superior to LS TTL which has a packing density of 15 to 20 gates/~nm . The packing density of -the ' integrated circui-t according to the invention is for the second embodiment 120 to 180 gates/mm . So this is approxi-mately a factor of ~ more favourable than for LS TTL and less than a factor of 2 worse than for I L.
So the present inven-tion provides a cons'iderable improvement with respect to LS TTL and notably i9 signi-ficantly competitive with respect to I L for applications in which a switching speed is necessary which is too high for conventional I L.
'It will be apparent that the invention is not res~r,i~ted to the embodiments described but that many variations are possible to those skilled in the art with-,out departing from the scope of -this invention. For example, other semiconduc-tor materials, such as germanium or AIIIBv compounds, may be used. Furthermore, the conductivi-- 20 ty types in the examples may be interchanged, the electric voltages and current directions being adapted accordingly.
In the first embodiment -the -thickness of the n-type surfac'e layer is preferably not lar~ger than appro-xima-tely 2 /um. An ~-type epitaxial Iayer is preferably used and -the base zone 34 preferably is obtained by locally conver-ting the epitaxial layer into ~-type b,y diffusion and1or 'ion implantation by overdoping up to the more high-, ly doped n-type buried layer~
Other forms of dielectric isolation, for example ~r grooves or polysilicon-filled grooves may alter-na;tively be us'ed.
~' In the second embodiment the thicl~ness of the - , surface layer is preferably not larger than approximately 6.5 /urrl. ~dvantageously a thickness of at most approxima-~; 35 tely 3.5 /um is used. The surface layer will usually be an epitaxial layer5 but may also be obtained differen-tly, for example, by diffusion or iOll implantation. The collec-~or regio~s can also be provided as separate regions by ' . ,,., ' ' ., ---- -~

,:' ` ~; .

Z~973 12-7-l978 -29- PHN 90~6 doping in a substra-te of the oppo~ite conductivity type.
The resistivity or in general the doping concentration oP
the surface layer may be adapted within wide limits. For example, instead of the epitaxial layer of 0.7 Ohm.cm an epitaxial layer of approximately 0.3 Ohm.cm may alternatl-vely be used readily. Said resistivity lnfluences inter-alia the series resistance of the coupling diodes.
Both for the vertical and for the lateral com-plementary auxiliary transistor it holds that the base width of the aux~iary transistor between the emitter and the collector is preferably approximately 3 /um or less.
The inverter transistor may alternatively be constructed so as to be symmetrical with respect to the non-active part of the base zone. In tha-t case the base contact which comprises the emitter of the auxiliary tran-sistor will, for example, be situated centrally, an emitter zone and one or more coupling diodes being present on two opposite sides of said contact. On each of the said sides a buried layer will be present which continue uninterrupted-ly from below the emitter ~one to below the couplingdiode(s). lf a lateral complementary auxiliary transistor i is incorporated in such a symmetrical transistor, the re~on hich serves as collector thereof will consist of two parts which are situated beside the two other opposite 2S sides of the ba~e zone not facing coupling diodes.
The activator concentration in the par-t of the subs*rate region which is situated as collec-tor of -the vertical complementary auxiliary transistor opposite to the base zone of the inverter transistor is preferably at least ~o a factor of 10 and advarJtageously a-t lcast a fa~tor of 100 lower than the activator concentration in -the low-ol~mic part of -the collector re~ion of -the inverter transistor.
A]te~rnatively, -the coupling diodes 16-may be obtained by means of ma-terials other than the said platinel silicide~ ~or example, aluminium, platinum silicide, cobalt silicide or ti-tanium may be used. This material may be present onlr in the apertures in thc insulatirlg layer, as - -- - , with the described plantinel silicide junctions, or ma~
:` :
,, ' .
, ~ - - - , .......... .

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Z~973 .

12-7-1978 -3- P~N 9OO~

form a layer as part of the conductor tracks, as is often the case ~ith titanium. l`he layer of titanium is then coated ~ith a readi:Ly conductive layer of, for example, gold in ~hich, if` necessary, a barrier layer of, for example, platinum may be interposed between the titanium and such a gold layer.
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Claims (15)

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS

1. An integrated logic circuit having a signal input which is formed by a base of a bipolar transistor and having a plurality of signal outputs which are each coupled, via a diode, to the collector of the bipolar transistor, the signal input comprises means to supply current, the integrated circuit comprising a semiconductor body having a major surface to which several surface regions of a first conductivity type adjoin which are situated on a common substrate region of a second con-ductivity type opposite to the first, at least one of the said surface regions belonging to a collector region of the first conductivity type which forms part of the bi-polar transistor, said collector region having a high-ohmic and a low-ohmic part, the low-ohmic part extending at and along the interface between the collector region and the substrate region, the bipolar transistor further-more having a major surface-adjoining emitter zone of the first conductivity type which in the semiconductor body is separated from the collector region by a base zone of the second conductivity type extending up to the major surface, an electrically insulating layer being present at the major surface and having a first aperture which over-lies the emitter zone, a second aperture which is situated beside the emitter zone above the base zone and several third apertures which are situated beside the base zone above the collector region, the insulating layer separat-ing conductor tracks from the semiconductor body which conductor tracks extend for electric connection into the first, the second and the third apertures, each of the conductor tracks which extends into a third aperture being each coupled to the collector region via a rectifying junction which adjoins the collector region, said rectify-ing junctions forming the said diodes, the bipolar trans-istor at the major surface being surrounded by an isolation zone by means of which the bipolar transistor is isolated electrically, at least during operation, from adjacent surface regions of the first conductivity type, character-ized in that a further surface zone of the first conduc-tivity type is incorporated in the semiconductor structure of the bipolar transistor and is separated by the base zone from the said collector region and which has an elec-tric connection, the collector region, the base zone and the further surface zone of the first conductivity type serving as emitter, base and collector, respectively, of an auxiliary transistor so that, if the bipolar transistor is overdriven, a considerable part of the current flowing through the base connection of the bipolar transistor can be dissipated in the auxiliary transistor and the storage of mobile charge carriers in the overdriven bipolar trans-istor can be considerably restricted.

2. An integrated circuit as claimed in Claim 1, characterized in that the electric connection of the fur-ther surface zone of the first conductivity type is formed by the conductor track which extends into the second aper-ture overlying the base zone of the bipolar transistor.

3. An integrated circuit as claimed in Claim 1, characterized in that the isolation zones comprise zones of insulating material extending from the major surface down to a larger depth in the semiconductor body than the base zone of the bipolar transistor, the base zone adjoin-ing the insulating material at least over a considerable part of its circumference.

4. An integrated circuit as claimed in Claim 1, 2 or 3, characterized in that the base zone of the bipolar transistor extends down to the low-ohmic part of the col-lector region and is separated from the substrate by said low-ohmic part.

5. An integrated circuit as claimed in Claim 3, characterized in that the base zone of the bipolar trans-istor at the major surface is surrounded entirely by and adjoins the insulating material.

6. An integrated circuit as claimed in Claim 1, characterized in that in the semiconductor structure of the bipolar transistor additional measures have been taken so that a region of the second conductivity type cooperates effectively with the said base zone of the second conduct-ivity type and the said collector region of the first con-ductivity type so that a complementary auxiliary transistor is incorporated which has the said base zone as emitter, has the said collector region as base, and has the said region of the second conductivity type as collector, the last-mentioned region being provided with an electric connection as a result of which, if the bipolar transistor is over-driven, a considerable part of the current flowing in the base zone of the bipolar transistor can flow through the complementary auxiliary transistor and the storage of mobile charge carriers in the overdriven bipolar transis-tor can be restricted considerably.

7. An integrated logic circuit as claimed in Claim 6, characterized in that the low-ohmic part of the collec-tor region in a direction substantially parallel to the major surface has a restricted extent, said part extending on the one hand below the emitter zone and below the rect-ifying junctions and on the other hand exposes, below the base zone and the overlying second aperture in the insulat-ing layer, a region in which the high-ohmic part of the collector region directly adjoins the substrate region while forming a p-n junction, the part of the substrate region adjoining the high-ohmic part of the collector reg-ion cooperating as collector of the complementary auxiliary transistor with the adjoining collector region and the base zone of the bipolar transistor.

8. An integrated logic circuit as claimed in Claim 7, characterized in that the base zone of the second con-ductivity type has an active part which surrounds the emitter zone of the first conductivity type and an adjoining non-active part which serves for the electric connection of the base zone and above which a second aperture is present, which adjoining non-active part is at least equally large as the said active part, adjoins the said further surface zone of the first conductivity type and comprises the emit-ter of the complementary auxiliary transistor.

9. An integrated logic circuit as claimed in Claim 6, 7 or 8, characterized in that, viewed on the major sur-face, the first, second and third apertures are arranged in a row in which between one or more third apertures on the one hand and a second aperture which overlies a part of the base zone which comprises the emitter of the complementary auxiliary transistor on the other hand, at least a first aperture overlying an emitter zone is present.

10. An integrated logic circuit as claimed in Claim 6, characterized in that at the major surface beside the base zone a further surface zone of the second conductivity type adjoining the collector region of the first conductiv-ity type is present which from the major surface extends down to substantially the same depth in the semiconductor body as the base zone, said further surface zone of the second conductivity type serving as collector of the com-plementary auxiliary transistor and being connected to the substrate region.

11. An integrated logic circuit as claimed in Claim 10, characterized in that the distance at the major surface between the base zone and the further surface zone of the second conductivity type is at most 5 µm.

12. An integrated logic circuit as claimed in Claim 10 or 11, characterized in that the isolation zones are surface zones of the second conductivity type which extend from the major surface down to a larger depth in the semi-conductor body than the said further surface zone of the second conductivity type and in which the further surface zone of the second conductivity type is connected directly to the isolation zone adjoining the collector region of the first conductivity type in that the said two zones overlap each other at the major surface.

13. An integrated logic circuit as claimed in Claim 10, characterized in that the base zone of the second con-ductivity type at the major surface is surrounded only partly by the said further surface zone of the second con-ductivity type, the periphery of the said base zone at the major surface is situated partly opposite to one or more third apertures and for the whole remaining part is situ-ated opposite to the said further surface zone of the second conductivity type.

14. An integrated logic circuit as claimed in Claim 13, characterized in that the base zone of the second con-ductivity type is substantially rectangular, the said fur-ther surface zone of the second conductivity type is sub-stantially U-shaped and surrounds the base zone on three sides, and the third apertures in the insulating layer are arranged beside the fourth side of the base zone.

15. An integrated circuit as claimed in Claim 1/ 5 or 6, characterized in that the said further surface zone of the first conductivity type at the major surface occupies an area which is at least one third of the area occupied by the emitter zone.