CA1127771A - Electronic data processing coded signal converting means - Google Patents

Abstract

ABSTRACT
Data processing information storage and retrieval system having a memory. A number of modules are inter-connected with the memory. Encode and decode modules operate in conjunction with the memory for compacting and expanding data. A revolve module in association with a delta module and a memory enable coded signals to be transferred into a number of unique but equivalent and related signals. A seed module enables the shortest of the equivalent signals to be located. A change module enables any one of the equivalent signals to be updated.
An output module causes an equivalent signal to be converted back to the original signal representation.
Pipe and brightness modules perform a discrimination function on stored information. The data processor includes programs which by unique means and methods structure and retrieve data from the data base. The retrieval may be based on an inexact match between events and entries of a request and the structured data base.

Description

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BACKGROUND OF THE INVENTI~N
This invention relates to information storage and retrieval systems.
~.
Distinguishing the present~invention from the prior z~
art there are certain characteristics that are generally b applicable to prior art information storage and retrieval systems in existence today. These features are as~follows: i.
1. As the size of a stored data base increases, the s average time required to retrieve data therefrom increases.
30 '

2. Data compressed in a storage and retrieval system a i i . , ..._ .... __ _.. .. _.._. _...._.._ _.._...._ ....____ .
_......_.___..._._..____~_.... ._ ._._ _ ___._~:~_.._..._i f ~~z~7~~2 must be expanded before it can be operated on.

3. If another element is added to a data base (for example, a record is ad~iect to a ~ile), the amount of space required to store the updated base always increases.
Some inquiries will be rejected by a retrieval system because they are not stated or formated correctly.
5. As the size of a random access data base increases, the efficiency of storage decreases (due to the. requirements for indexing tables, pointers, etc.).
An embodiment of the present invention does not have any of the above features.
An embodiment of the present invention involves a method and apparatus of restructuring digital information to produce iso-entropicgrams and seeds. To be explained in more detail, a seed is an optimum way of representing a particular piece of informat:i.on with minimum storage.
Stored information is retrieved, not by searching the data base, but by a generation process. During the generation process a data request, along with stored iso-entropicgram 20II seeds, are fed as parameters to an output generator.

In summary, some of the advantages gained from using the techniques according to the present invention may be achieved as follows: ..(1) J.ess physical storage is required,.
(2) fast retrieval time, (3) ease of restructuring and up-Z:~ dating a data base, (4) ease of specifying a new retrieval crit-aria, and (5) ease of specifying and carrying out a process.
The information storage and retrieval system described in the present patent application is a new class of machine, 30 based on an entirely new technology. Since it is based on I a new technology, a new word has been coined to describe this technology, the word being "holotropic°'.
The holotropic information storage and retrieval system is not based upon a new component nor merely upon a . 10 '~

3Oi il ~~ rearrangement of erisring components, but instead is based upon new methods and apparatus for building a whole new class of information processing machines.
Some superficial similarities will be found between presently available techniques and the class of new machines disclosed herein, lios~ever_ the cl3ff~rt~ne>sae ar~~~.r,".ot-~ ."..,.e, significant then the similarities, making it ~kward to describe the new technology in existing terms. Four example, one aspect of the invention resembles holography in the sense that information pertaining to an item is not stored in one place, however, to ts~ the word "holographic" to describe this new technology would convey the totally incorrect impression that it is optical in nature and, at th a same time, the terea fails to refer to this technology's other character_ istics. By way of further example, this aspect of the invention may behave in some x°espe~ts like an associative memory. However, here again, the diffwrences outweigh the similarities and the use of a descriptor like "associative"
generateswmore confusion,that it does clarification. For 2~ this reason, the term holotropic is used t~ identify the technology involved.
~ne applibation of the holotropic method and apparatus is fox information storage and retrieval. However, in des_ cxibing the functioning of a holotropic memoxy system, care m~ t be taken in using the terms used for previous techniquesa 25 , The mechanisms by which holotropic memory systems store and .
retrieve information are totally different from the mechanisms associated with terms like "search", "scan", "match", °'point"y "link°', or °'thread", Thus according to are embodiment of the present invention, instead of searching for the presence of stored data on the basis of matching an inquiry, the

-4-. n , holotropic memory system use;; the inquiry to invoke parameters which define both the applicable pieces and any relations between these pieces and the rest of the information. Those parameters then produce the information requested in the inquiry, not by reading it out of storage, but by recomposing' it.
In a holotropic memory system, the information itself is not found, it is generated.
From the user's point of view, there..are txoo character-istics of hoiotropic techniques which profoundly change conventional modes of dealing with an information storage and retrieval system. one characteristic concerns the absence of the need for descriptors, and another concerns file compression.
Attention will now b~ directed to descriptors and 13 exactness as it applies to an embodiment o~ the present invention. The data which is to be entered into the holotropic system for later retrieval need not b~ categorized, indexed, described, or even format~d for thevpurpose of retrieval. Should the user wish to set up a structure 20 of categories containing descriptors ox indices because it makes it easier for him, he may of course do so. An important distinction here is that a holotropic memory system never imposes such,structures upon the process. Even though the holotropic memory syste~ can accommodate such structures, it does not require them.
The same flexibilities characterize the making of inquiries of a holotropic memory system. The inquirer can simply ask questions in whatever form, using whatever words occur to him. Usually the person attempting to use an information storage and retrieval system has no trouble _ 5_ '"'"'y sc:,~t-.ia~g, his inquiry in such a c~aay that he understands it, rind in such a way that other people understand it. The difficulty arises when he tries to translate his inquiry into an equivalent question which meets the acceptance requirements imposed icy conventional information storage and retriefJal systems.
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~ prior information storage and retrieval systems, limits have to be set on the inquiry process. Since a holotropic memory system does not impose any requirements on the inquiry process, necessary control is vested where it belongs, namely, with the user. The most important control the user exercises concerns the degree of exactness of tha match between his inquiry and the contents of the data base.
The maximum setting on his "degree of exactness" control would be that for an exact match. Should an exact match not be found, the holotropic memory system enables it to tell the user that the situation exists and indicates that change must be made in the exactness setting so that the inquiry will retrieve at least one relevant item.
The exactness contxol setting has no effect whatsoever on the search time of the holotropic memory system. FIowever, since it indirectly controls the amount of data retrieved, it does effect the total response time in the sense that more retrieved data will tales longer to display in print.
2~ Because of the differences in the techniques of the inquiry process in traditional and in holotropic information storage and retrieval systems, the structure of the latter may be Vastly different, In traditional retrieval information storage and retrieval systems, an inquiry can be rejected becau3e it contains an unallowable descriptor, or because something is misspelled, or because the arts are ordered imp~'operly, or because the inquiry is not framed according to the speciFications ~ '.thus, an inquiry can be rejected _w 1 regardless of whether the information it asked for is actually in the data base, In a holotropic data storage and retrieval system, no inquiry need ever be rejected for such reasons.
The only sense in which an inquiry needs to be "rejected"
at all by a holotropic information storage and retrieval system is that~it fails to retrieve. In other words, the data base does not contain anything which matches the inquiry at the specified_level of exactness. If this happens, the user is told whether or not a change in exactness will retrieve an item, and if so, the setting.
Another consideration for holotropic information storage and retrieval method and apparatus is file compression.
The nature of the holotropic system is such that the stored data is compressed into less space than would be used to store the data with pvresently available techniques.
This is true even if it were centered as a linear string, that is, as a single record. The degra~ to which ar~y particular data sample is compressed in a holotropic system is a function of two independent processes.
20 The first process is fairly easily described, and its effects are relatively predictable. The holotropic storage and retrieval system compresses input data by automatically taking advantage of any redundaa~cy. In one test, a 10,000-word sample of ordinary English prose was compressed to approxi-2~ mately one-half the space which would have been required had the sample (without any index tables, pointers, or other artifacts) been stored as a single record in a traditional information storage and retrieval system. The exploitation of these redu~adancies occurs at all levels. Once a character, a word, a sentence,,a paragraph, or any other n ~~
1 arbitrarily specified input element has been encountered, no subsequent occurrences of that same element need be stored in their original form, Instead, the holotropic system notes that a previously encountered element has occurred again, in a manner which permits reconstitution of any or every one of the multiple input elements in its original conte~;t.
The second process contributing to data compression in a holotropic memory system is more difficult to predict.
' 101 It is more difficult to predict as it is a function of the relatedness of elements which are part of a data base.
As each new input element is added to the data base, it is automatically correlated with every otfaer appropriate element already stored. Since this process operates on the 1~ data base in its comtaressed form, it does not adversely affect storage time. One possible result of tt~iis correlation is that the content and structure of a new input element shay reveal a relationship between itself and a nuz~ber of already stored elements which peru~its a1.1 of the related elements 20 to be treated as a single entity and stored together. Thus, a number of elements which at one time were stored separately, can be collapsed on the basis of their relationship with a subsequent input element, trith results that the updated file can require less total storage space than it did prior 25 to the addition of the new input element.
Another characteristic which is also very different in a holotropic system from traditi~nal information storage and retieval systems is that in a holotropic system both the degree of compression and the relative speed of retrieval 30 may increase as the size of the data base increases.
_g_ n , ~.~.2''J'~'~~.
1II A derivative feature of compression in a holotropic system is that certain processing or manipulation of the stored data is done in its compressed form, thus permitting higher processing speeds than systems~which must first expand the data, Although the above discussion has been directed primarily to holotropic information storage and retrieval systems, specific holotropic method and apparatus .techniques may be applied in other areas.
~ne area is in digital comm~xnications, where band taidth limitations place an upper bound on speed of transmission.
Here, a holotropic system can be used to encode the digitized data, and th a speed of transmission of any message will be increased as a function of the degree of compression as 1S discussed With respect to information storage and retrieval applications. $t is important to remember that the information thus cr~mpressed and transmitted can represent anything whatsoever, _from a payroll file to a digitized pictorial image.
Significantly, other systems can be used to efficiently 2~ compress and transmit data, However, one thing which makes the holotropic approach unique 3s the, aince holotropic compression is a function of the redundancy of the message, compression and error correction are one and the same mechanism.
Significantly, holotropic techniques can be implemented ~S in software, but some or all are much more efficient when implemented in microcode, and are maximally efficient when implemented directly in hardwaxe. However, even where holotropie techniques are implemented in software or microcode, holotropic memory systems car,,perform more .
S~ efficiently in terms of storage, speed, e~tc, than presently known~techniques, A,t the hardware level, holotropic _9_ i I

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technology can take full advantage of the unique properties ' of the latest components, such as, charge couple devices, magnetic-bubble logic, and memory, etc.
The technology described herein is applicable alike to large computers (for example, information storage anal retrieval systems), to subsystems (for example, intelligent disk storage devices), or to very small stand-alone machines (for example, battery-driven calculators)...
sur~r~~~ o~ TuE mv~z~Taorr t One aspect of the present invention concerns novel method and means invo~.va.ng a digital data processor for creating or structuring a unique digital coded data base in a memory of the data processor. briefly, a method is disclosed for forming, in a desired order of occurrence, and as input, a plurality of coded event signals. At least some of the event signals represent the same event and at least one signal represents a different event. The event signals together represent plural entries. An event-time indication is formed far each; event signal representing the order of occurrence thereof. In the memory, a stored data base is formed which comprises a.separately retrievable event vector signal for each diffegent event and includes the step of forming in each retrievable event vector signal 2~ a representation of those event-time indications Which represent the order of occurrence of the corresponding event. Preferably, the event-time indications are formed by counting the event signals as they are formed.
The vector signals are referred to herein as being 3p retrievable because the vector signals need not be stored _la-~~v, M
io :~c~~>c~rate memory locations as separate signals but may !~~ iii a special form called a seed or may be combined with other seeds which may be retrieved to separate vector signals as required.
Also disclosed is a method and means utilizing a~data processor having a memory for creating or structuring a multiple layered data base in the memory. The method involves the steps of forming, in a desired order of ..
occurrence, and as input, a plurality of coded event signals;
~~ at least some event signals represent the.same event and at least one event signal represents an event which is different from another one. The event signals, together, represent a sequence of entries. Some of the entries are the same and at least one is different. A first event-tune indication is formed for each of the event signals. A second event-time indication is formed for each of ~t~he entries. The event-times represent the order of occurrence of the respective events and entries, representing the input.
The first data base layer is entered in the memory and 20 involves the steps of storing in the memory a retrievable first layer vector signal corresponding to each different valued event signal and the step of forming in each of the first layer vector signals a representation of those first .
event-time indications ~rhich represent the order of occurrence 25 of the corresponding valued event signals. The second data base layer is entered in the memory and involves the step of storing in the memory a plurality of retrievable second layer vector signals. Those entries which are the same have a corresponding second layer vector signal and those entries 3Q which are different each have a different second layer vector s signal. .Also included in the step of forming the second layer is the step of forming in each second layer vector signal a representation of those second event-time indi-cations which represent the order of occurrence of the corresponding entries.
Preferably, redundancy is eliminated in the first data base layer. According to a preferred method, a test is made to determine if a newly formed input entry is already represented in the first database layer. If the entry is not represented, the raewly formed entry is added to the first data base layer, utilizing the step of storing.
If the entry is already represented, then it is not added t~ the first layer a second time. However, the entry is added on the second layer.
According to a further preferred embodiment of the invention, method and means are provided for storing delimiter events in one or the other ox° both of the layers.
Hriefly, a method is, disclosed wherein the event signals of the input comprise at least one representing a delimiter.
At least one such delimiter event signal is formed in each of the entries and in the order of occurrence of the entries so as to define the boundaries of the, entries. The first event-time indications also identify the order of occurrence of each delimiter. A separately retrievable vector signal 2~~I is provided for the first event-time indications which .represent the order of occurrence of the delimiter event signals. A similar method is provided for forming a delimiter event signal in the second layer identifying the bounds of entries in the input.
30II Method and means involving a data processor are disclosed for retrieving data from the stored data base.

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Eriefly, the disclosed method retrieves, from a memory, data which is contained in a stored data base. The data base represents a sequence of events in which some events are the same and at least one event is different. The stored data base is represented by a plurality. of separately retrievable vector signals one for each different event.
Each retrievable vector signal represents at least one event-time value which represents the~or.der of occurrence of the corresponding'event. The method includes the steps og interrogating a selected vector signal to selectively form at least one event-time identification signal, and generating a unique event signal corresponding to a vector signal which represents an event-time value corresponding to the event-time identification signal. Hy selecting only those vector signals for interrogation which are of interest the necessity of interrogating all vector signals of the data base is avoided,.
Method and means involving the data processor are also disclosed fox retrieving from a memory, data which is contained in the multiple layered data base. Each layer represents an ordered sequence of enbries and events. One or more events represent each entry. . In each layer some events are the same and at least on.e is different, gome entries are the same and at least one is different. Each layer has a plurality of separately retrievable vector signals, one fox each different event for such layer. Each retrievable vector signal represents an event-time value for each occurrence of the corresponding event and the event-time values identify the order of occurrence of the corresponding events. The data base comprises at least first and second layers. At J
least some of the events in the second layer have a corresponding entry in the first layer. The method disclosed includes the steps of generating a first layer entry identification signal designating a first layer entry which corresponds to a second layer vector signal,.
The second layer vector signal represents at least one event-time value in a selected second layer entry. i~lso included is the step of generating a first layer event signal corresponding to the first layer vector signal loll which represents an event-time value in the designated first layer entry.
The mufti-layer system, preferably involves method and means for interrogating on each layer and generating signals from each layer. Briefly, the method involves the ~,$II step of interrogating a selected first layer vector signal to form at least one first layer entry identification signal which, in turn, designates at least one': second layer vector signal. The designated second layer vector signal is interrogated to form at least one second layer entry identification signal. The step of generating includes the generation of a first layer entry identification signal designating the first layer entry which corresponds to a second layer vector signal which represents at least one event-tune value in the designated second layer entry. A
~$i~ first layer event signal is,generated corresponding to the first layer vector signal which represents ari event-time value in the designated first layer entry.
Preferably the retrieval involves an initial step of forming a request comprising a series of coded event signals 30II representing the events of an entry. The step of interrogating -l~-'. ~ ' ) ,.--., ~3. ~'~~'~~.
I on the first layer includes the step of interrogating selected vector signals, which correspond to the events of the request, to locate an entry containing event-time values which represent events having a predetermined degree of match with the events represented by the event signals of the request. Preferably a signal is formed which identifies different allowable degrees of match between the events of the request and the events of an entry in the data base. The step of locating involves the step of . ~~i~ locating a data base entry which has the allowable degree of match. In this manner it is possible to locate a data base entry in the first layer which may not exactly match the events of the request.
Also disclosed is a concept generally referred to as 15~I piping. Briefly, a preferred method of piping is disclosed which involves the step of locating a data base entry which has at least a predetermined number of event-time values representing events positioned within a preselected number of event positions relative to events in the request.
2~~~ Preferably an alterable pipe cutoff signal represents such predetermined number of events. The pipe cutoff signal preferably represents the predetermined number of events as a fraction of the number'of events in an entry of the request and computations are made to determine the 25 actual number of events to be used in the step of interrogating based on the length of various parts of the request.
According to a still preferred embodiment the pre-selected number of event-time values is specified by a pipe width value which may be altered as desired.
30 In addition, the concept of brightness is disclosed. A

111 preferred method is disclosed wherein piping forms an intermediate entry identification signal. further interrogation is performed according to brightness in order to locate a data base entry which has at least a preselected degree of match as to order and presence of events, with an entry of the request.
In summary then it will now be seen that the piping feature locates entries which meet certain piping criteria and these entxies are then used by the brightness feature loll to locate data base entries which have the desired pre-selected degree of match as to order and presence of events with the entry of the request (i.e., brightness).
Preferably the preselected degree of match is specified by a brightness value cutoff signal which is alterable by the ,, user.
In a preferred method according to the invention, a length discrimination feature is provided in order to only locate those data base entries which have a preselected degree of match, as to number of events, as well as order 20I~ and presence of events.
Preferred methods are disclosed which utilize delimiters for locating entries during the interrogation and generation steps. ,Although the aforegoing description of the pipe and brightness features deals in large with interrogation 25 and generation on a single layer, it should be understood that the same features may be applied on one or more layers in a multiple layer system. Method and means are disclosed herein for interrogating on one layer to locate entries on the first layer which in turn identify events on the second layer. Tt will be recalled that each second layer event ~,r~~~'~~
lil will have a corresponding vector signal. By interrogating :;uch vector signals on the second layer, second layer entries are located by using pipe and/or brightness, and it is possible to locate portions of the data base which do not exactly match the request. For example, the request may be composed of~letter evens which in turn represent word entries which in turn represent a sentence entry. By interrogating the first layer using the pipe and/or brightness, it is possible to looate for each word of the request a word 10~~ in the data base which most closely matches the word of the request. These best words, represented by first layer entry signals, (second layer event signals), are then used to interrogate the second layer of the data base by using pipe and/or brightness. It is then possible to find a word in l~l, the data base which, although it does not exactly match the request word, is the best one represented in the data base.
The same is true of a sentence and the words which make up a sentence.
Although the foregoing description has been primarily 2011 directed to methods, it will be understood that data pr~cessing means are disclosed which include both hardware and programming for effecting the methods described.
Also disclosed are various ways of compacting data which will be described in more detail. One form is referred to herein as revolving. Briefly, an electronic data processor is disclosed for converting coded signals as follows. The combination of a given line value signal and a given line number signal is formed which together represent a given value. Additionally a number of lines value signal is formed.
30 'ignificantly, means is provided for converting such combina-tion of given line value signal and given line number signal -17~

i representing each different given value to any'combination of equivalent line value signal and line number signal in a unique set thereof which includes the given signals.
Each line value signal represents at least one digitally $ coded actual occurrence value out of a set of monotonically ordered possible occurrence values. Each line value signal is related to another in the same set by an exclusive OR
of the actual occurrence values thereof and the actual occurrence values thereof relatively shifted. Also provided is means for responding to each different value represented by the number of lines signal for causing the converting means to form a different predetermined one of the equivalent combination of line signal and line number signal within the set which corresponds to the combination of given line signal and given line number signal. Such an arrangement has particular application to systems such as the present one involving vector signals which may have an extremely large number of event-time values, as it permits the values to be compacted down to a small fraction of the 20II fully,expanded form. This is particularly applicable to vector signals which can be quite long. Significantly, as more values are added to a given line value the shortest equivalent line may actually becomelsmaller.
In ~ preferred embodiment of the foregoing processor, means is provided for causing those relatively shifted occurrence values which are not within the group of possible occurrence values to be eliminated from the equivalent line value signal, contributing to the compaction feature.
According to a further preferred embodiment the number.
of lines value signal is represented by one or more signals _le_ representing component powers of two thereby representing increments by which the given signal is moved through the equivalent signals.
According to a further preferred embodiment the SII operation of forming incremental number of lines value signals can be.done very fast and conveniently. Tn such an embodiment, means are provided for determining the larger of the difference between the values of the largest two actual occurrence value signals in the given line and of the difference between the values of the largest possible occurrence value and the largest actual occurrence value in the given line value. Preferably means is. also provided for forming one or more incremental number of lines value signals representative of the largest difference.
15 According to a still further preferred embodiment, a data processing compactor for coded signals is disclosed.
This is referred to herein generally as seed finding. In accordance with one such embodiment of the invention the forementioned data processing converting means is provided 20 with means for forming a plurality of incremental number of lines value signals causing the given line to be moved through successive equivalent signals. Means are provided for interrogating the formed equivalent line value signals for one of selected length, preferably the~shoxtest. A
25 signal indicative of the one of selected length is stored.
Preferably, both the equivalent line value signal and the equivalent line number signal are stored as the indicative signal.
Generally it is important to minimize required memory 3QI' space and accordingly length of data must be minimized.
_lg_ ii 1II Therefore, redundancies such as "o"s are preferably squeezed out of data to be stored by means such as an encoder. The compaction operation is preferably arranged to minimize the length of data as it exists after encoding and before storage in memory, According. to a preferred embodiment of the invention, data processing means is provided for outputting signals represented by the line value signal and the line number signal. This feature is generally referred to herein as output. In this connection the data processing converting means disclosed above is provided with means for forming a signal having a value representing the number of possible occurrence values in the set thereof, means for determining a value related to the difference between the number of possible occurrence value signals and the given line number signal. This value,is then used by the converting means to form the corresponding equivalent line signal which is the input/'output line.
Also disclosed is an electronic data processing coded 2~ signal changing means which is capable of changing signals represented by a line value signal and a line number signal.
Significantly the changes need not be made at the level of the given signals but can be made in the line value signal of one of the other equivalent signals in the corresponding ~5 set of equivalent signals. Briefly, to this end there is disclosed means for storing at least the combination of a given line value signal and a given line number signal which represent a given value. Means are provaded for forming a change signal representing at least one change occurrence value. Additions and deletions are indicated in the change signal. Additional means form a number of lines value signal. deans similar to that disclosed above converts the combination of given line value signal and given line number signal to one of the equivalent signals in the corresponding set. The equivalent signal is identified-by the number of lines signal. Means is provided for exclusive ORing the values represented by the equivalent line value signal and the change signal for forming a change line value signal. Preferably the number of lines . ~~I~ value signal represents the difference between the values represented by the given line number signal and the change line number signal. In this way the given line signal is rotated back to what is referred to as aa~ input line in the equivalent sets and then the input line is exclusive ~.5 ORed with the change signal.
Also disclosed is an electronic data processing method for checking for the presence of an actual occurrence value represented by.a given line value in the equivalent sets. This has been referred to generally as the DEL
20Ii function. Significantly, the presence of an actual occurrence value is to be checked not in the given line but in one of the other equivalent lines.. To this end a method is disclosed which utilizes the value iwpresented by the given line number signal for forming a signal representing 25 the number of lines of displacement between the given line and a desired line value of the equivalent set of line values.
A test signal is formed representing the desired possible occurrence value to be checked for presence in the desired line value. The values represented by the test signal and 30 the number of lines signal are combined to form a further a~z~~ r~
li) test signal identifying a further possible occurrence value for'test. The values represented by the test signal and the given line signal are compared for a predetermined relation. The values represented by the further test signal and the given line signal are also compared for a predeter-mined relation, Responding to the results of both comparing steps, a predetermined signal is formed indicating the presence of an actual occurrence value, in the desired line value, equal in value to that represented by the test signal. In addition to the method, means are provided for checking for presence.
In the compacting method and means, preferably the vector signals are encoded from a compact code to an expanded code before conversion to an equivalent signal.
15" Also preferably the equivalent line value is converted from an expanded code back to a compact code before length is checked using encoding techniques. A preferred encoder is disclosed for converting to hybrid form a received series of absolute coded words in decreasing value order which represent the vector signals. In such encoder, means is responsive to received previous and current absolute words for forming an output signal indicative of the difference.
Absolute or bit string form of hybrid output is indicated.
To this end,~means is provided for indicating a preselected minimum difference between successively received absolute words for absolute form of output, and means is provided for comparing the minimum difference indication arid the previous and current difference signal for indicating the value of the first being greater than, or less than or i equal to the latter. Absolute form outputs are provided.
i .,~, ZII ~'o this end, means is operative in response to the less than or equal to indication for outputting the stored current absolute word and an absolute flag. Bit string form outputs are also provided. To this end, there is means which is responsive to the greater than indication fox forming a set of ordered signals comprising a binary bit of one value (i.e., "1°°) separated by the number of binary bits of a second value (i.e., '.'~").,corresponding to the value of the previous and current difference signal.
Additionally, means selectively outputs the set of signals in association with a bit string flag and in a predetermined relation to an outputted absolute word. In this manner, absolute words are converted to a hybrid form of encoding.
A preferred form of the ~"lecoder converts hybrid coded 15 signals to absolute coded signals. In the system this decode operation is performed on hybrid coded vector signals coming from memory. The hybrid signals represent a series of occurrence values of decreasing value order.
The hybrid signals comprise a series of received binary 20 coded word signals including at least one absolute coded word and a bit string word. The bit string word represents an occurrence by the number of bits of displacement of a bit of predetermined value from an'absolute word in the series of hybrid words. The hybrid word also has a flag 25 indicating the type of word. The decoder includes an absolute word outputting arrangement that includes means responsive to an absolute word flag signal of a received hybrid word far owtputting the received word signal. Also provided is an absolute word outputting arrangement that 30~~ includes means responsive to an absolute word signal and each bit of predetermined value in a following bit string 7..~.~'~'~h'~~, word signal for foaming an absolute word signal for output indicative of the actual value of each said bit of pre-determined values In this manner retrieved vector signals are converted from hybrid form to absolute word form, each absolute word representing an actual occurrence value, In accordance with the invention as claimed in the present divisional application there is provided electronic data processing coded signal converting means comprising:
a) means for storing at least the combination of given line value signal and given line number signal which represent a given value;
b) means for forming a total number of lines value signal;
c) means for converting such combination of given line value signal and given line number signal representing each dif-fexent given value to any combination of equivalent line value signal and line number signal in a unique set thereof which in-eludes the given signals, each line value signal representing at least one digitally coded actual occurrence value out of a set of monotonically ordered possible occurrence values, each line value signal being related to another in the same set by an ex-elusive OR of the actual occurrence values thereof and the actual occurrence values thereof relatively shifted, comprising:
means. for responding to each. different value repre-sented by a provided number of lines signal fox causing the converting means to form a different predetermined one of the equivalent line signals within the set which. corresponds to the combination of. given value line signal and given line num-ber signalo ~y.

Brief Description of the Drawings Fig. 1 is a general block diagram of the data processing machine (DPM) ;
Figs. 2, 3 ..and 4 form a schematic and block diagram $ of the ENCODE MODULE;
Fig. S is a diagram showing the relationship of Figs. 2, 3 and 4;
Fig. 6 is a schematic and block diagram of the ALU
used in various modules in the DPM SYSTEM;

Figs. ~ and 8 form a flow diagram illustrating the sequence of operation of the ENCODE MODULE;

Figs. 9 and~.l0 form a schematic and block diagram of the DECODE MODULE;
I

Fig. 11 is a flow diagram illustrating the sequence of ~5 operationof the DECODE I MODULE;

Figs. 12, 13 and 14 foran a, schematic and block diagram of the CODE TI MODULE;
DE

Fig. 15 is a schematic and block diagram of the DELTA

MODULE;

Fig. 16 is a flow diagram illustrating the sequence of operationof the DELTA MODULE;

Fig. 1'7 is a schematic and block diagram.of the REVOLVE

MODULE;

Figs. 18A and 18B form a flow diagram illustrating the Z$ sequence of operation of the REVOLVE MODULE; , v Fig. 19 is a block diagram of an iso-entropicgram revolver employingthe REVOLVE MODULE;

Figs. .20 and 21 form a schematic and block diagram of the SEED MODULE; , Fig> 22 is a flow diagram illustrating the sequence of operationof the SEED MODULE;

1Ii Fig. 23 is a block diagram of a seed finder and employing the SEED MODULE;
Fig. 24 is a schematic and block diagram of the CHANGE MODULE;
SII Fig. 25 is a flow diagram illustrating the sequence of operation of the CHANGE MODULE;
Fig. 26 is a block diagram of a seed line changer employing the CHANGE MODULE;
Fig. 27 is a schematic and block diagram of a.generalized 101 clock control unit for use in designated modules;
Figs. 28,2,30 and 31 form a schematic and block diagram of the OUTPUT MODULE;
Figs. 32 and 33 form a flow diagram illustrating the sequence of operation of the OUTPUT MODULE;
15 Fig. 34 is a block diagram of the compaction and retrieval machine employing the OUTPUT MODULE; .
Figs. 35,36,37 and 38 form a flow diagram illustrating the sequence of operation of the PIPE MODULE;
Figs. 42A-D are graphs used to illustrate functions of 20 the BRIGHTNESS MODULE;
Figs. 43,44, 45 and 46 are schematic and block diagrams of the BRIGHTNESS MODULE;
Figs. 47,48,49 and 50 form a flow diagram illustrating the sequence of operation of the BRIGHTNESS MODULE;
25 Figs. 51,52 and 53 form a schematic and block diagram of the DPM TNTERFACE MODULE which includes the IPRF;
Fig. 54 shows the a/0 bus 1220 structure;
Figs. 55 and 56 form timing diagrams representing the sequence of operation of I/O bus output end input operations;
~0 Fig. 56A is a schematic and block diagram showing the control fox the BDONE flip flop in the DPM INTERFACE MODULE;

22'7'7'73 lIl Fig. 57 is a schematic and block diagram of the MEMORY
MODULE;
Fig. 58 is a write enable pulse diagram for the MEMORY MODULE;
Fig. 59 is a schematic and block diagram o~ the SWITCH MATRIx; ' Fig. 60 is a schematic and block diagram of the P/B MEMORY;
Fig. 61 is a block diagram of an alternate data 14 processing machine (DPM 2);
Fig. 61A, 61B and 61C form a schematic and block diagram of the ENCODE MODULE for, the.DPM 2 system;
Fig. 61D and 61E form a schematic and block diagram of the DECODE I MODULE for the DPM 2 system;
Fig. 61F, 61G and 61H foi:m a schematic and block diagram of the DECODE II MODULE for the DPM 2 system;
Fig. 62 is a schematic and block diagram of the DELTA 2 MODULE for use in the alternate machine of Fig. 61;
Fig. 63 is a flow diagram for the DELTA 2 MODULE;
Fig. 64 is a schematic diagram of the implies circuit of Fig. 62;
Figs. 65 and 66 form a schematic. and block diagram of the REVOLVE 2 MODULE; ' Fig. 67 is a flow diagram for the REVOLVE 2 MODULE;
-. 25 , Figs. 68 and 69 form a schematic and block diagram of the REVOLVE 3 MODULE;
Fig. 70 is a flow diagram for the REVOLVE ~ MODULE;
Figs. 71 and 72 form a schematic and block diagram of the SEED 2 MODULE; .
3Q Fig. 73 is a flow diagram for the SEED 2 MODULE;

n t r Figs. 74 and 75 form a schematic and block diagram of the OUTPUT 2 MODULE;
Figs. 76 and 77 form a flow diagram fox the OUTPUT 2 MODULE;

Fig. 77A is a schematic and block diagram of the MODULE;

Fig. 77H is a flow diagram for the CHANGE 2 MODULE;

Fig. 77C is an example of how information is moved between areas of the MEMORY

during operation of 1~ the CHANGE 2. MODULE;

Fig. 77D is a schematic and block diagram of the MODULE
;

Fig. 77E is a schematic and block diagram of the SWITCH MATRIX
2;

Fig. 77F is a schematic and block diagram of the AUXILIARY MEMORY 2;

Fig. 77G is a sketch showing the generalized diagram of the sof tware;

Fig. 78 is a generalized sketch showing the data 2p structure for each layer;

Fig. 79A is a sketch showing an example o the data structure for layer 0; v Fig. 79B is a sketch showing ah example of the data ' structure for layer 1;

25 Fig. 79C is a sketch showing the generalized design of the software;

Figs. 80 and 8l form a PARSER program flow diagram;

Figs. 82-84 form a PIPE program flow diagram;

Fig. 85 is a sketch illustrating the address linkage during PI2 2 et seq. of the PIPE program;

n ' Fig. 8~ is a sketch illustrating the address linkage during PI7 of the PIPE program;
Fig. 87 is a sketch illustrating the address linkage during PI11 of the. PIPE program;
Figs. 88-93 are sketches illustrating the .sequence of operation and primary storage areas during the operation of the PARSER, PIPE and BRIGHT programs;
Figs. 94-96 are BRIGHT program flow. diagrams;
Fig. 97 is an OUTPUT subroutine flow diagram;
Fig, 98 is a MEMDPM subroutine flow diagram;
Fig. 99 is a OpM, subroutine flow diagram;
Fig. 100 is a DECODE I subroutine flow diagram;
Fig. 101 is an INSERT subroutine flow diagram;
Fig. 102A is a pictorial flow diagram illustrating the 15 operation of the FORMATER program'during a layer 0 request;
Fig. 102B is a pictorial. flow diagram for the operation of the FORMATER grogram during a layer 1 request;
Fig. 102C is a FORMATER program flow diagram;
Fig. 103 is a COMMAND subroutine flow diagram;
2~ Fig. 104 is a GET INTEGER subroutine flow diagram;
Fig. lOS is a GET FLOATING POINT subroutine flow diagram; ..
Fig. 106 is a REQUEST subroutine flow diagram; i Fig. 107 is a PROCOUT (Process Output) subroutine flow 25II diagram;
Fig. 108 is a sketch gi~ring an example and illustrating ;i the correspondence between G2TBL table and the OUST list;
Fig. 109 is a SETUP subroutine flow diagram;
Figs. 110 and 111 form a GENERATE subroutine flow 3~ diagram; .
i -29_ / v Fig. 112 is a SORT subroutine flow diagram;
Fig. 113 is a PRINTR (Printer) subroutine flow diagram;
Fig. 114 is a conceptual view of the prior art data base system;
Fig. 115 is a conceptual view of a layered data base system according to the present invention;
Fig. 116 is a sketch illustrating layering data base structure of the data base;
Fig. 117 is a~sketch illustrating conversion tables CVRTBL and CVTBL2;
Fig: 118 is a sketch illustrating ESTAIi;
Figs. 119A-E are sketches illustrating available used space management for the seed lines;
Fig. 120 is a sketch illustrating an example of the l~ layered data structures after initialization;
Fig. 121 is a DATA BASE program flow diagram;
Fig. 122 is a layer INITI;ALI~ATION program flow diagram;
Fag. 123 is a LAYER BUILDING program flow diagram;
Fig. 124 is a PROCESS EN~'RY program flow diagram;
201 Fig. 125 is a PROCESS A LAYER 0 ENTRY subroutine flow diagram;
Fig, 126 is an ADD N EVENTS subroutine flow diagram;
Fig. 127 is a PUT NEW SEED IN'STORAGE program flow diagram;
25 Fig. 128 is a SEARCH FREE SPACE program flow diagram;
Fig. 129 is a RELEASE SPACE subroutine flow diagram;
Fig. 130 is a GARBAGE COLLECTION program flow diagram;
Fig. 131 is an ADJUST SEED HEADER subroutine flow diagram;
30~~ , C~

I N D E X
Contents , p_ac~e I. GENERAL 31 DESCRIPTION
OF DPM
SYSTEMS.....

A. Data Base Structure .............31 B. Iso-Entropicgram Techniques......36 C. Changes ........................a46 D. Verifying Presence of an Occurrence Value at Input Line .........,a.a....ao~ee.4~

E. Hybrid Coding ...................51 ZO F, Conventions and Components TJsed in the Figures .a.......a...55 I-A. GENERAL
ORGANIZATION
OF DPM
SYSTEM

VF FI GS . ~ ' ~ 4 . . . . o . , . . ~
. . , s . . a . s a . o o . . 1 .

II . ENCODE 6?
MODULE
o . o o . . o o s . o .
. a . s . a a a . a a a a Ao General Description a s r . s 6?
. o . s s . . .

~s Component8 0..mos.a.aa..s.am..rso?~

C~ Detailed Description ............?3 D. Example of Operation ............94 III. DECOD E I MOD~ILE ...a.sos.....o.ss.e..o.111 2~

A. General Description ......~......111 B. Components es...lss...eao..ss.s..s112 C. Detailed Description ....a....a..115 De Example of Operation ............126 Il -30a-n ~-~.~.~'~l'~'~1.
zNnEx Pale IV. DECODE II r~oDULE.... 137 ..................

V. DELTA MODULE ...,............. " ,...,.139 A. General Description..a............7.39 H. Components.....a...a...a....a.....140 C. Detailed Description.:.e....a.:a..142 1~ , D. Example o~ Operation..............149 VI. REVOLVE MODULE ............e..........152 A. General Description...,...........152 H. Components..aa............a........155 C. Detailed Description..............157 D. Example o~ Operation..............179 VIIe REVOLVER....e.........................190 VIII. SEED MODULE ......,...........e..a....194 A. General Description................194 He Components...ss.....s..,.e,..,as,.196 C s Detal.led DeeQ. ~ra.pt~(~n" w 19 . . , o . a a . o s . .

D. >~xample ~~ ~perat~.ono a . a a 217 . a . a , a . s o I~a pEED S INDER. a o a o a o a o . . 221 . o a s . a a a . a . a . a o a X. CHANGE MODULE ....o......e.....,.,....228 A. General Description.e.e...........228 H. Components'.s..oo..e~aoeo.eoao...e.o230 C, Detailed Description.......a....ee~231 D. Example of Operation.......e.....e239 XI. SEED LINE CHANGER..aa...........a..a..242 I
i XII. GENERALIZED CLOCK CONTROL.......... 243 " .

-30b-N D E X
(font°d.) pa~~' XIII. OUTPUT MODULE ...............e........ 246 A. General Description.........,..... 246 B. Components..........e............. 248 C. Detailed Description.............. 250 D. Example of Operationo.......e.....e 276 xlv. DATA coMPACTION Arab ~ETRTEVAL
MACHILyEa o o a a . . s a , s a s , a a s a a a o a . o s o 0 o s s 285 Xve ~IPEM~DULE o . a . , a , s , o a , a a a o a a a . . . . o s . 293 A. General Description............... 293 B. Components.....e..........:.e..... 306 C. Detailed Description.............. 308 XvI. BRIGHTNESS MODULE ...e.s.o....s...asse 365 A. General Descriptions........>..... 365 B. Components..os.o.ooa...e.e.....e.. 376 C. Detailed Descr~.ption........e....e 379 24 Xvz~. DPM ~NTE~ACE MoDULE......e...........449 ~~I~ MEM~R~ 475 e" MVDULE, s o o , a o s o s o a , s o a a .
a .
.
o .

X~~. SIV1T<.H 482 1'itlTRiX.
, o .
.
.
.
, o , a , o s .~s , a .
o s .

illis P~B ~MOR~.eo..soe..oae 49V

sseoe.se aeeseo.

XXI. GEIVEFiAL
ORGANIZATION
Op ALTERNATE

D.t'M~~~TEM 2 o a o . . . s o . s 493 25 . , s a a a o . a . a , s , o .

A. General Discussion...e.........e.493 8. Revised ENCODE MODULE.....e.....oe496 Ca Revised DECODE T MODULE..........e498 D., Revised DECODE ZI MODULE.e......e.499 E. PIPE and BRIGHTNESS MODULES..,..e..500 -30c-I
1~~ I r~ ~ ~ ~
(CC7nt ° Cl page XXII. DELTA 501 ...............,.....

~r A. General Description..............501 B: Components......>.. 504 .

.
.............

C. Detailed Description...............507 D, Example of Operation..............514 1~ XXIII. REVOLVE 521 2 MODULE.....................

A. General Description...............521 B s Components . . . . . . . . . . 523 . . . . . .

. . . . . . , .

C. Detailed Description...,.........525 D. Example of Operation.............544 15 ~IV REVOLVE 558 .....................

A. General Description, . . . . . 558 , . , . , . "

, B. Components..oo.....ss 560 .s.,.,ss...s.

C. Detailed Description..............561 D. Example of Operation.......,o.o..579 XXV. REE D 2 MODULE .......................596 ' A. General Description...............596 B. components....oaooo.o,a.e....,.....603 C. Detailed Description..............605 D. Example of Operation.. 617 ....,...,...

XXVI. OUr.~PUT 2 MODULE 6 2 3 . .
. a . s , s o o , . , r , , .
s a o A. General Description....,.....,....623 B. Components...................... 627 i C. Detailed Description......o....,.627 .

D. Example of Operation.........%.. 646 °30d-..: . ;: ,, . ;, , ,,,~. , , : , , l~l s r~ n E x (font°d. ) Pa a XXVII. CI~ANGE 2 MODULE ...................... 653 A. General Description............... 653 B. Components........................ 654 C. Detailed Description.............. 654 D. Example of Operation...,......,... 661 XXVIII.MEMORY 2 MODULE.............e.........663 XXIX. SWITCH MATRIX 2.......................664 XXX. AUXTLIARY MEMORY MODULE TI............ 666 XXXT. COMPUTER, DATA BASE ~ BOFTWARE

ORGANIZATION ........................ 671 A. MT6yI CO~UTER,e...oe.s.oo..oe...oe 671 ~5 H. General Description of Data Base Structure.................... 672 C. General Description of Software........s......s...o...... 673 1. Data Base Initialization .. 6T4 i 2. Layer Building ............ 675 2~ j XXXTT . ~N~U~RY ArrD RETRTEVAZ, HARDWARE/ .
~~~TWA~ ~RGA~TZATTO~ . . , . . . . . s o . . . , s a 68G
A. General Description of Tncguiry and Retrieval Softwaree.:.......... 682 B., SORI'lhTER pr~gra~.. o . . , a . . . o o . o . a . a 718 Co PARSER program.................... 721 25 p,~p ~. PTPE program. . . , . . o . . . , a s . s o s s s a s .,730 E. BRIGHT progra~e o s . . . o . . . . , a a . a . . , a 749 F. OUTPUT subroutine......,...... " ..765 G, MEMDPM subroutine..............e..769 H. DPMMEM subroutine..................772 30 .
T. ~~'.~CODE I subrVUtlne. . . . . .. . . .. .. .. 773 -30e-~ 12'7!'71 I N D E X
(Cont'rl. ) P_ ag a ~T. INSERT subroutine............ 775 .....

K. COMMAND subroutine................779 L. GET~INTEGER program...............789 M. GET FLOATING POINT program.....e..791 N. REQUEST subroutine...... 7-4 .

.
.. ss.se O. PROCOUT (Process output) e'u' ubrout 8 ~
ne v .
.
. s . o . , a . a a o 0 o a a s o o a a s a .

P s A7ETUP s L6iJroutlne o o a a 8 ~ 9 a . . a a a a o a a , a a s Q. GENERATE subroutine...e...........814 R. SORT subroutine...... 820 .e...e....e..

S. PRINTR (Printer) subroutine.e.....823 T. PRNTC (Print a Character) w~'lubroutj.n~. o . o o a a s 825 o a . o , a a a . . . a a .
a U. GETC (Get a Character) subroutine.eo..ee. 826 .

.
.eo..e.eeee...

~e~cxzi=aHARDWAREesoFTWARE
oRGANI~A~xoN
~oR

BUI LDTNG LAYERED DATA 1BASE ooseeessaes828 Ae LAYERED DATA BASE STRUCTURE.e.....828 a DATA ddASE program, LpvQ.l 1 84 , o a a a , o a C, LAYER zNITIALI~ATION program, Level 2 ~~1 ' a a a . o , a a . o a a a . .
o o e, s e . s a o s a a ~a LAYER BUILDING program, .

LeVe~ 2 o a o a o a a o 0 0 o ~ ~~
a a a o . a o 0 0 o a a o 0 25 E. PROCESS ENTRY program, , Level 3 859 e..eeee..ee........ee.e.e..

F. PROCESS A LAYER 0 ENTRY

subroutine.ee. 868 e..e..ee.....e..e...

G. ADD N Ei7ENTS subroutine, L eyel l.s o a o o a o 0 0 0 0 0 . a s o 0 0 0 0 0 0 . a 872 o a a i H. PUT NEW SEED IN STORAGE program, Level 2o...s..oae.ae.ae.e.ao.'...e.879 -30~-1 z N a ~ X
(Cony' d . ) Page z. SEARCH FREE SPACL program, Level 3 884 ...........e...............

~a. R~L~AS~ sPAC~ su~aROUTZN~ FLOW, LeVe 1 ~ . a s . . s m s a . o . . a . o 8 . . a . . s . . m s . 8 I~. GAR,SAGE C~LLECTI(7N program, L~~~.1 ~ . o s s . s s o . s m . a . . . 8 . . a o a . m . o , 0 8 , Lo ~~u~~ ~~~~ HliAD.f'rR

subroutx.neo.s....sm.s.. 890 eosso..e..s ~~ P~N~~~ A o . . s o a . . s . s a m . 8 s . . o a . . a . . m . s s m . s s . 9 Index ~ TaJJles.s..oas.a.a.o. 892 : j w.sm..o.m 1 1 ~a~lE:r~'. . a o 0 0 . . s s . . . o s .
o . s . s m m m m . s s . .. m 896 I

y : I

APPENDIX ~ sew ....s.eme...m.m.ss.s.es.e.....

Index o Program Li~t3aags...mm...m..m. 1002 PrdgrL~m LJ.rJlrlng$ommmo.amm.so..asm..mao 1'1/04 i 2~
3~!
_~Og_ ii I. GENER?aL DESCRIPTION OF DPM SYSTEMS
A. Data Base Structure Fig. 1 depicts a general diagram of an information storage and retrieval system and embodies the present invention. The system of Fig. 1 is referred to.herein as a data base management ~DPM) system. The DPM system is designed to perform certain general data base management functions, as follows. First is the.''enter'° function which is the ability 'to enter information into the data lOII base. Second is the '°update'° function which is the ability to change or delete information in the data base. Third is the "retrieval'° function which is the ability to retrieve information fxom the data base, and the fourth is the "discrimination" function which enables the user 15~I to discriminate upon the information in the data base.
The discrimination function is referred to herein as the '°piping and brightness" function.
In order to understand the above four functions, it is imperative that one first understands the structure of the data base and the technique of storage for the data base.
All incoming information to the DPM system is restructured by the MINI COMPUTER into a layered database in its main memory. Each layer is a lagical.entity or a group of entities called °°events°'. Each of these events is separated x5 by a delimiter from a set of delimiters for the layer. The group of events between two subsequent delimiters is referred to as an "entry°°. Layering is hierarchical in that the higher level layers encompass the lower level layers. For example, if one were to structure contextual data base, the following levels may exist: layer 3 consisting of sentences;
~31-1 layer 2 consisting of phrases; layer 1 consisting of words;
and layer 0 consisting of letters. Each layer has appro-priate and distinct delimiters. However for purposes of illustration only a two layer system is specifically disclosed. One layer is fox words and the second for sentences.
Table 1 is an example of the word layer 0. Each occurrence of an event is represented by a 1 whereas an 0 represents the lack of an event. As depicted, the layer 1p may be visualized as having two dimens:~.ons referred to as lines Ior rows) and columns. The number of lines is equal to the number of events in the layer. The number of columns is equal to the number of possible occurrence values for each event.
Entries are viewed as a series of events occurring in time. Each column is assigned an event-time, or possible occurrence value, from left to right in increasing monotonical value order. Table 1 depicts layer 4 for the sentence '°TI3IS
IS A TEST". Line 0 of layer 0 contains the delimiter ~
20 Irepresenting,a textual blank) which actually separates.the words of the sentence. Line 1 designates the T vents.
Line 2 designates the H events. Line.3 designates the I
events. Line 4 designates the s events. Line S designates the A events. Line 6 designates the E events.
25 Since the events can be considered as a series of chronologically occurring event-times, each event is represented in the layer by a binary 1 in.the appropriate line and column. Thus, if the event-times can be considered as being~represented by an occurrence clock, each time a 1 is entered in the layer corresponding to an event the occurrence clock is increased by 1. This is depicted in _g2_ II mz r~~~
1 Table 2A. Thus a delimiter a5 occurs at event-time 0, the letters T-H-T-S occur at event-times 1, 2, 3 and 4. A
second delimiter d5 occurs at event-time S. The letters T-S appear at event-times 6 and 7. Another delimiter ~
appears at event-time 8. The letter A appears at event-time 9. Another delimiter ~ appears at event-time 10 and the letters T-~-S-T appear at event-times 11,'12, 13 and 14. The ending delimiter ~5 appears at event-time 15.
All of the events in any one line are represented by an occurrence vector. The occurrence vector is represented by the occurrence values of an event shown at any particular line. Occurrence vectors are shown in Table 2B, fox each line of Table l, as a~series of decimal occurrence values.
Thus, for example, a "delimiter occurrence vector" for the delimiter ~6 event is depicted in the first line of Table 2. Similarly, the event occurrence vector for the letter T is depicted at the second row ~of Table 2, ete.
Table 3 depicts,a sentence layer 1 for the sentence '°THIS IS A TEST". The symbol "." is used as the delimiter 2~ symbol to delimit phrases. The first occurrence of "."
is implied, f~rming the initial leading delimiter for the word layer. A number of different types of delimiters may be aSSigned t0 each layer (e, g, ,. vv , n vv a n vv s ~ i i i etC>~
and can be selected as desired by the user. . The possible occurrence value at which each delimiter occurs in layer 0 is used as an implied line,pointer to layer 1: The line pointer is formed by assigning a value corresponding to the relative position of the events in line 0 of Table ~. and adding thereto a bias. The implied pointers of l, 2, 3, 4 ' and 5 are depicted at the bottom of Table 3. i . il ' 1II Consider now an example of the sequence of operation required in layering the phrase ~ THIS ~ IS ~ A ~ TEST 35 .
Considering the examples of Tables 1 and 3, in an actual example of the~system, the first delimiter ~n is implied and not physically present in the input stream. A line or event counter is used to keep track of~each .new event for each different layer. In addition, an event-time clock for each layer is provided for identifying event-times, or possible occurrence values.
gp Initially, the line and event-time clocks for each layer are initialized by setting them to 0. The lowest layer, layer 0, is tagged with event names, in this case the binary representation ofvthe character assigned to the line. This is not done with higher layers.
The implied delimiter h5 :is the first possible occurrence value encountered in the input phrase. Since this is not present in layer 0, the ~ is assigned to the next available line, line 0, by the, line counter. The first delimiter occurrence is marked by placing a binary 1 in column 0, line 0 corresponding to the state of the event-time clock and the line counter. The line counter and the event-time clock are then incremented by 1. The event-time clock now identifies event-time l, and the line Gaunter identifies line 1.
2~~~ For each event line, zeroes are used to fill in the positions in which a 1 is not entered.
The next event to be encountered is the T in the word "THIS". Accordingly, a 1 is entered at line l, column l, corresponding to the 1 states of both the event-time clock and the line counter. The event-time clock and the line n 1II counter are then incremented by 1. This operation continues until the "~ THIS'° has been entered in layer 0. The next event to be encountered is the end delimiter ~. The line counter is then reset to 0 and at this time the event-time S clock is at 5. Accordingly, a 1 is entered at line 0, column 5. The .complete word event dS THIS ~S has ~ now been entered on layer 0 and is to be processed on word layer 1.
The first occurrence of the "." phrase delimiter is implied and is therefore entered at line 0, column 0, corresponding 1~D to the event-time Block and line counter for layer 1. The event-time clock and line counter for layer 1 are incre-mented by 1 and a 1 is entered at column 1, line l, corresponding to the word THIS.
idext the series of input events °'IS ~°' are encountered.
first, letter layer 0 is checked to see if there is an event line in existence for each of the characters IS ~.
Since the events, T, 8, ~ have: previously occurred, but not in that order, only the event-time clock is incremented for each of these events and the line counter is appropriately positioned to identify the lines corresponding to each of these events.
A new event line is not added to layer 1 if the event has already occurred. Rather, only an occurrence mark is added at the appropriate column of the line corresponding I
to the event. A sequence o~ events between two delimiters is not added to the same event layer a second time if an implied pointer exists to a higher layer. Instead, the series of events between the two delimiters will be represented and entered in the layered system as an occurrence mark on the next higher layer, and nothing needs to be done on the lower layer.

1 To be explained in more detail hereinafter, the DPM
system of ~'ig. 1 implements the layering concept by representing data, not in lines and columns, but by occurrence vectors which represent event-time by actual occurrence values.
B. lso-entropicgram Techniques information is not stored in the DPM system directly in the event-time form shown on Tables land 3, but is translated into a special compacted form. The compaction is referred to herein as iso-entropic compaction. Specifically, an occurrence vector pr a word of information is~represented by a give:a line value and ~~'~ine number. Each given line value and line number has a set of equivalent line values and line number values which include the given line value and line number. Each equivalent repre~aentatian has the y same information content. Each line value represents at least one digitally coded actual occurrence value out of i a set of possible ones. Each line value is related to i 20 another in the same set by an exclusive OR of the values i thereof and the values thereof relatively shifted. The set of equivalent line values form an is~-entropicgram.
The representations in the set are of various lengths ' when leading 0°s are disregarded. The shortest one is i ~g referred to as the "seed". Mast retrieval operations i from the DPM system, along with the operations that change or modify the data base, are carried out directly on the seed and therefore are very efficient compared to conventional data base techniques.
30 Table 4-A gives an example of an iso-entropicgram using binary 1°s and 0°s. Each line represents one of the ~.~.~~~~.
1II representations of the complete set. The input line is depicted at the top of line 0. Referring to the input line, it will be seen that there are actual occurrence values 0, 1, 2, 4 and 6. Each line, moving down in the iso-entropicgram, is formed by shifting the binary bits of the preceding line in the iso-entropicgram by 1 bit position to the right and exclusive ORing the bits (or values) of the unshifted line with the shifted line. The .
"exclusive OR" is referred to herein as an XOR. An XOR
. 1Q operation on binary coded information is.a bit by bit half-add with a deletion or truncation of those resultant bits which, as a result of the shift, exceed the number of bits in the original unshifted line. In this case, the binary bits that are truncated are those to the right of the largest event-time or possible occurrence value 7.
Refer now to Table 5. and consider in detail the way in which line 1 is formed frozn line 0 of Table ~-A. The top two lines of Table 5 depict line 0 unshifted and line 0 shifted to the right by 1 binary bit. The vertical line indicates the point at which truncation occurs. The remaining bits of the shifted and unshifted line 0 are XOR'd resulting in line 1 of the iso-entropicgram. This process is repeated, using line 1 to form line 2, and using line 2 to form line 3, etc. It will be seen that after a number of lines equal in number to the number of bits in the input line have been generated, the next line~to be generated is the input line, also referred to ws the output line. Note for example that lines 0 through 7 of Table 4-A are each different, whereas.line 8 is the same as line 0, the input line, The iso-entropicgram is closed on~itself, lines 0 and 8 being identical. I

' 1 The process of going from one line to another in the same iso-entropicgram is referred to herein as °'revolving°°.
One limitation imposed on the iso-entropicgram is that the number of bit positions, i.e., the width, must be an integral power of 2 (e. g., 1,2,4,8,16, etc.). Tt will also be found that in an iso-entropicgram, one can look down-through the columns and pick any number of columns which are an integral power of 2 and the bits in these columns will repeat every integral power of 2 lines. By way of example, columns 0 and 1 repeat at line 2; columns 0, l, 2 and 3 repeat at line 4; columns 0, 1, 2, 3, 4, 5, 6, and 7 repeat at line 8; etc.
It will furbher be seen that as the lines of an iso-entropicgram are formed, past occurrence information appears to progressively sweep across the iso-entropicgram, influencing representation of later information. !;the sweeping in the iso-entropicgram of Table 4-A appears to sweep to the right.
F°or example, at line 7, the information in line 0, column 0, has interacted waith every column to the right and, in fact, all columns have interacted with columns to their right.
Table 6 illustrates this point by using, as the input line, the basic iso-entropicgram pattern created by a single binary coded bit of occurrence information. The basic pattern depicted in Table 6 has been named the "delta"
2511 Pattern, partly because of its rough similarity to delta modulation and partly because the physical shape outlined by the 1's appears like the delta symbol. The iso-entropicgram produced in Table 6 is actually a result. of the interacting ~0 ~

i~I patter~a produced by the delta's position at the input line.
Another example o': the delta interaction is depicted in Table 7 which shoos an iso-entropxcgrara with the 0's left out for clarity. Here it will be seen that the deltas are outlined; therefore their interference occurs at live 4.
The interference pattexn produced by the interaction of these deltas has similar properties as those of an optical hologram, Thus, in an optical hologram, each point is the combined result of a reflected beam whose intensity and path lQ distance is a function of the scene reflecting the bean.
The recorded intensity at each point is a result of the combined intensities of the two beams and the phase displacement between them caused by the reflected beam's path length.
Sim:islarly, the information at each point in the iso~entropicgram of Tables 6 and '~ is the result of two information intensities (binary 0 and binary 1~ and the phasing between them. At each point, past information is analogous to the optical hologram's reflected beam, and 20 the present information to its direct beam.
information stored in the iso-entropicgran~ is highly redundant. Thus each line of the iso-entropicgram forms one representation of a complete set of equivalent representations. All lines form the complete set.
2$ Each line represents a new encoding or transformation of the input line. Additionally, it has been found that large sections of the iso-entropicgram can be eliminated but the entire iso~entropicgram can be reconstructed from the remaining bits and pieces, using the interrelations of the lines and columns.
_39-l l ~ ) 1 ,As discussed above, lines 0 and 8 of the iso-entropiegram of Table 4 are identical in form. One can~generalize by saying that if line 0 is the input line, line 0 ~- 2N is the output line which is identical in form to the input line, where 0 -t- 2N
is equal to the, number of bits in the input line.
The purpose o~ utilising the iso-entropicgram techniques is to replace the input line with anather representation (line] which 3s equal to~but preferably shorter in length than the input line. The seed line is the one which can be.represented with the minimum number. of bits eliminating leading 0's9 Referring to Table 4-,A, i~t will be seen that the seed is line 2, where only four occurrence values, namely, 0 through 3, are needed to represent the information since the rest of the bits to the right are 0, The seed then represents a minimal encoding for vhe iso-entropicgram.
In the iso-entropicgram, the seed them is the one caith the least nuc~ber of possible occurrence value positions required to represent all occurrence values.
Tf all binary bit positions in a line are called the ~0 possible occurrence values and each 1 is called an actual occurrence Value, it can be said that the iso-entropicgram involves:
~1~ Grouping strings of actual occurrence values into lines and grouping the lines into a set, All lines in the set are equivalent and' interrelated, According to the preferred embodiment of the present invention, each line in the set is ' related to anather by shifting the occurrence values of the line one place and ~ORing the 30 shifted and unsh ifted lines, deleting those 111 shifted values vahich go beyond the width of the iso-entropicgram;
(2) X111 lines of the set are unique, that is, no line is repeated;
(3) The set of lines is closed upon itself in the sense that~by manipulating any one line, the entire set of lines can be repeated, and the set size (number of lines in the set) is predete.rmined~
The set size or number of lines for a given length~of lines can b~ specified as follows:
~J (number) ~ number of possible occurrence values per line and the number of lines per set. The log,2N is an integer.
General techniques are di~cclosed herein whereby any line of an iso-entropicgram set: can be generated from any other line by knowing the lane to be used as the reference and, i secondly, the number of lines betw~eer~ the line to be used a~ the input line.
Since the transmission of aa~y ~.ine of the iso-entropicgram set before eliminating leading 0's carries the same information and requires the same number of bits, the set is iso-entropic.
In terms c~f information theory each line has the same entropy.
Us~ang seed finding techniques disclosed herein, it is possibl~
to select a lane that will represent the input line with fewer occurrence values and hence the entropy is reduced, As a result, information representation may be stored or transmitted more efficiently.
The lines in an iso-entropicgram can ~be derived from any ~0~~ o ther'line without resort to a line by line revolve. Using Lox example, the line by line revolve, the seed lane is r revolved to the input line by revolving the seed through the number of lines of the iso-entropicgram which are necessary to generate the input line. For example, in Table 4-B, a revolve of 9 lines from the seed line 7 will generate the input line 16.
According~to one preferred embodiment of the invention, means is provided for generating the input line without generating each of the lines in between the seed line and the input line. According to the preferred embodiment of the present invention, this is done by detErmining the number of lines required to generate the input line and breaking this number down into its component powers of 2, , going from the largest possible to the smallest possible component power of 2. One XOR operation is then performed ~5 using each of the component powers of 2 to.move from the seed line to the input line. In each XOR operation a given line is shifted to the Height by the number of bit positions (possible occurrence positions) identified by the corresponding component power of 2. The shifted given ZOI line is then X0R'd with the unshifted given line.
The example of Table 4-B requires a revolve of nine lines to rotate the seed line to the input line. Breaking.
9 into its component powers of 2, going from the largest to the smallest, the component powers are 8 and 1. Table 25 4-0 top line shows the seed line unshifted. The next line of Table 4-~n shows the seed line shifted with respect to the first lane by 8 bits. The third line shows the XOR
of the first two lines. In this step, then, the seed line has been revolved from line 7 to line 15. (CF line 15 3011 of Table 4-D). The remaining component power of 2 is 1.

ii ~~~~~~s 3 accordingly, the ~:hird line of Talale 4-D, l:Lne 15 of the iso-entropicgram, is right shifted one bit position and :~OP,'d with itself to generate the input line 16.
Anoth~:r revolve technique is disclosed herein for generating any line of an iso-entropicgram directly from any other lix~ of the same iso-entropicgram without generating th a intervening lines, This may be done by a process of revolving which involves~a shift and FOR of the given line of an iso-entropicgram. The number of positions gp of shift is determined ~by one of the lines of the delta of Fig. 6. Basically the process involves;
1. Determining the number of lines in the corresponding iso-entropicgram by which the given line is to be revolved; .
1~ 2. ~nerating the line of the d~glt~ whose number is equal to that of the nuc~ber of lines to be revolved;
3. For each occurrence value in the selected delta forming at,lsast partially an individual representation of the given line and aligning gp the,representations of the given line with one end aligned with the corresponding occurrence value of the selected line of the delta;
,.
4. XORing the thus aligned occurrence value of the given lane eliminating those shifted occurrence values outside of the iso-entropicgram.
i Tables 46 and 4~ depict such an example. Referring to Table 479 assume that the given line is line 0. 3t will be seen that the sixth line in the iso-entropicgram from the l given line is line 6. Referring to Table 6, delta line 6 contains occurrence values 0, 2, 4 and 6. Taking the given 111 line depicted at line 0 of Table 47 forming a representation of that line for each of the occurrence values of the delta line 6 and aligning the left hand end with the corresponding occurrence values of the delta line 6 results in the pattern depicted at 0, 2, 4 and 6 in Table 46. XORing the aligned bits together results in line 6 of Table 47. In other words, there are occurrence values at 0, 2, 4, and 6 of delta line 6.
The given line is reproduced 4 times and separate ones of the reproduced lines are shifted 0, 2, 4 and 6 possible 1~ occurrence values. The resulting lines are XOR'd together to generate line 6 of the iso-entropicgram, eliminating any shifted accurrence values to the right of the edge of the iso-entropicgram.
Any line can be used as the given line of the iso-15!' entropicgram. The relative distance, i.e., number of lines a by which the revolve is to take place, .;is equal to the desired line number minus the given line r:umber. This difference determined the line o~ the delta to be used for i the praces's of shifting and XORing. I~ the desired line 20~i is lower in number than the.given line, for example a given line of 5 and a desired line of 3, the relative distance is negative. In that event,, the width o~ the isa-entrapicgram is added to the negative difference and the result designates the line of the delta to be used.
25 Far example, using a given lane of 5 and a desired line of 3, one wauld compute the delta line as follows:
3-5 = -2~ -2 + 8 6.
This general concept is implemented in the alternate DPM system of Fig. 61. However, to facilitate implementation, the process involves a shift and XOR of the delta line rather than the given line which is to be revolved. The process li ~ ~ ' ' b 111 implemented in the DELTA 2 MODIiLE and the DPM system of Fig. 51 is as follows:
1. Determining the number of lines in the corresponding iso-entropicgram by which the given line is to be revolved;
2. Generating the line of the delta whose number ~ is equal to that of the number of lines to be revolved, one such delta line at least partially being generated for each occurrence value of the given line, and aligning each generated delta line with one end of the delta line in alignment with the corresponding occurrence value of the given line;
3. XORing the thus aligned occurrence values y$ of the generated de:Lta line, eliminating those shifted occurrence values outside of the iso-entropicgram.
A more detagled~description of the DELTA 2 MODULE
. implementation is given in the sections on the DELTA 2 Zn MODULE and the REVOLVE 2 MODULE.
To be explained in more detail herein, any line of an iso-entropicgram is completely identified by a line number, a.line value and a width (or lengt~i) value. The line v number is the line number in the iso-entropicgram. The Z$ line value represents the actual occurrence values, excluding 0's to the right of the last 1. The width is the width of the corresponding i.so-entropicgram which in turn is the length of any line of the iso-entropicgram including 0's on the right.

II ' ' c' 1 Fur example, using this form of expression, the seed line of Table ~-A can be represented as line number of 2, line value of 1101 and t~idth of 8, To be explained in more detail, the actual embodiment of this invention operates an actual occurrence value expressed in binary coded~dec3.ma1 rather than lines and columns of 1's and 0's. Using this form of expression the above line value becomes.0, 1, 3.

c. Ch~n~e~
Changes to a data base consist of insertions, deletions and the addition of new information, Deletions remove actual occurrence values frost event occurrence vectors.
Z~ An insertion adds an actual occurrence value to one or more event, occurrence vectors and, if necess<:try, actual occurrence values are shifted to allow fog insertion. llew additions j.
to a data base add new actual .occurrence values to existing evemt occurrence vectors or add entire new event occurrence 20II vectors.
In accordance with a preferred embodiment of the present ' invention described hereinafter in connection with the I
C'HANGX MODULE, changes in the event occurrence vectors are made directly to the seed line. of an event occurrence vector.
25 In over words, it is not necessary to revolve an event occurrence vector back from has seed line to the input line of its iso-entropicgram. Tables 9-A and 9-E illustrate the sequence of operation for changing a hypothetical event X, j r Line a of Table 9-A depicts the occurrences of % in absa~lute decimal coded form. Lines b and c, respectively, depict n ._ i 1~~ deletions and insertions. Thus, occurrence values b and 12 are to be deleted and occurrence values 1, 3, 8, 9 and 11 are to be added to the event X depicted at line a, The change vector incorporating all the insertions and deletions is depicted at line d of Table 9-A. The change. vector includes all of'the occurrence values for the deletions and insertions sorted in an increasing incremental order from left to right. A change operation tatces place by XORing the change vector and the event occurrence vector to be changed. If lines 'a : and d of Table 7-A are XORed the result is as depicted at line e. Tt w i11 be seen that line a includes all of the actual occurrence values depicted ' at lines a and d with the common occurrence values 6 and 12 deleted, It will be recognised that the X~R dust described was described with both the event X and the change vector at their 0 or input line for their corresponding iso-entropicgramso Assume now that tlxe vector X is at its seed line as depicted at g in Table 9-Ao The seed of X is at line 6 , of 3.'t~ iso-entrop3cgram. According to the preferred embodiment of the present invention, the change vector is revolved through its iso-entropicgram until it is also at line 6 in its iso-k entropicgram. Line h of Table 9-A depicts the change vector at line 6 of its iso-entropicgram. According to the present invention the line values of X and the change vector depicted at g and h are then X~Red providing the result ', i indicated at line i~ Referring to i of Table,9-A, the XOR
results in the same lane number, namely, line 6, with a line !
value of 0,1. Table 9-R shows the iso-entropicgram for the ø
input line depicted at a of Table 9-Ao It will be seen that 30 ~'~1'~en the input line (line 0)~ of Table 9-L has been revolved to it, line G, its actual occurrence values are indeed 0 and 1 which is the same as that depicted at line i in Table 9-A.
Using the revolve techniques described hereinabove, the resultant value depicted at i, according to the present invention, is then revolved until its seed line is found.

With reference to Table 9-B, it will be seen that the seed is at line'5. Accordingly, line 6 depicted at i of Table 9-A and 6 of Table 9-B, is revolved forward 15 times until it arrives back at~line 5 of the same iso-entropicgram, as depicted at the bottom of Table 9-B. Line 6 plus 15 additional lines is line 21. Subtracting out of 16 (the total lines in the iso-entropicgram) leaves line 5 which is the seed line. Thus, the new seed line number 5 has a line value of 0. .

Significant to the present invention, ~t should be noted 1S that in the aforegoing example the changes involve five insertions~and only two deleta.ons. Even though the insertions and hence information content increased, it resulted in a net reduction in the seed. In other words, the seed event X

contains three occurrence values in its line value whereas the line value for the final seed contains only one occurrence value. This occurs because the seed is a representation i formed by information interference patterns which are not i controlled by the quantity or the number of occurrence values. The patterns are only influenced by the relationship ~5 between the occurrence values. As a result it is possible for a data base to shrink in sire with added information.

t I

n lIl D. Verifying Presence of Occurrence Value at Input Line As described above, Table 6 depicts a delta. The delta of Table 6 is the same width as the iso-entropicgram of Table 4-A. A delta is formed by placing a 1 at possible occurrence value 0 as the input line and revolving it until the original input line is formed using the desired iso-entropicgram width.
The delta can be used to verify the_presence of an occurrence value (i.e., a 1) at the input line of an iso-entropicgram without actually generating 'the input line.
The verification process may be accomplished using pencil and paper by physically inverting,~the delta from top to bottom and from side to side. Thus, the delta of Table 6 inverted becomes that depicted in Table 9-C. Plext, the lower ZS right-hand tip of the delta is positioned over the possible occurrence value calumn of interest at ~~he output line.
Next, the line of the inverted delta that coincides with the line of the iso-entropicgram which is going to be used for the test are ANDed together. The resultant line is then XORed.
20 gf the result of the XOR a.s a 1, an actual occurrence value is present at the input line in the possible occurrence value column of interest. If the result ~.s 0, an occurrence value is not present.
Although the foregoing method is accurate and useful 2~ using paper and pencil, the present invention embodies concepts similar to the foregoing in a more practical embodiment.
In the actual embodiment of the invention it is possible to have a seed expressed as a line number, a line value, and an ' i iso-entropicgram width to determine whether the input line b 1 of the corresponding iso-entrop~_c~ ram has any particular desired occurrence value and this ,can be done without revolving the seed ~baclc to the input line. 7lsually ' the line to be used for the checking process is the seed line, Therefore, the description of the embod imPnt of the invent ion will be described assumin; tf~ the line to be used as a basis for the test is the seed line.
Referring t~ the inverted delta, it will be seen that the numbers of positions between adjacent "1's" is an integral power 0~ Z for lines 0, 2, 4 and 6. For exempla, Line 2 has I's separated by two positions, whereas Line 4. has I's separated by four positions. ~ecawse of this characteristic of the delta, it is quite easy to generate occurrence values representing the~.occurrence values which are present in the lines of the delta which are component powers of 2. Ta this end, the seed line which is to be used as a basis for a test is first revolved in its iso-entropicgram until it is at the line whieh is an integral powex~ of ~ lines away from the input lime. Us ing Table ~-A by way' of example, seed line 2 ~°hen revolved two I3.nes, to line 4 is an integral poorer ~of 2 (namely, 4) away from the input line.
Referring to the inverted delta of Table 9 -C, it will be seen that line 4 contains occurrence values at 3 and 7.
Thus it should be, evident that the number of possible occurrence values separating the actual occurrence values in the delta (for those Iines which are integral powers of 2) is equal to the line number, Thus, applying the ,inverted delta of Table 9-C to the iso-entropicgram of Table 4-A, assume that it is desired to determine whether occurrence 50 value 6 ~s present in the input lane, Applying line 4 of the inverted delta of Table 9-C to line ~ of the iso-entropicgram of Table 4-A, occurrence value 6 is present in the inverted delta line of Table 9-C, whereas it is absent in the iso-entropic~,ram -JO_ (, j ',.1 ~~.~~~~r~~
i line of Table 4-A, whereas four places to the left of the occurrence value 6 (of interest), the inverted delta contains an occurrence value and so does the iso-entropicgram of Table 4-A. Tables 9-D and 9-E depict these operations.
The foregoing method for determining the presence of an occurrence value at the input line using one of~the non-input lines of the iso-entropicgram is referred to herein as the DEL function. The actual method whereby the embodiment of the present invention carries out the DEZ~function is 1011 described in more detail in connection with the section describing the OUTPUT MODULE.
E. Hybrid Coding The disclosed embodiment of the present invention involves 1$~~ a further compaction technique in which the occurrence vectors are represented in a hybrid encoded form. Information is stored in the MEMORY MODULE in hybrid encoded form. Thus, considering the iso-entropicgram technique used to represent a particular occurrence vector, the present invention involves 20~~ a technique which picks the line of the iso-entropicgram which in hybrid coded form is the shortest, not necessarily the one which is shortest in the unencoded form.
The reason for selecting the shortest hybrid coded iso-entropicgram representation for the seed is to enable 2$ the shortest or smallest memory space to be used for storage.
Referring now to Table 8, the possible occurrence values are depicted, and immediately below, the corresponding binary bits representing an occurrence vector are depicted at 1.
Up to this point, the occurrence vectors have been 3011 primarily described in what will be termed bit string form.

C l i ~.~~'~l"'l '~~.
lI~ In other words, a binary 1 or a binary 0 is used to represent the presence or absence of actual occurrence values. This form of representation is depicted at 1 in Table 8. 3 of Table 8 depicts the same information in a binary coded decimal 3 form called absolute code form. Thus, bit string form for the information of Table 8 requires 8 digits, each with 1 binary bit, for storage, whereas absolute code form requires five digits, each with 3 binary bits, for storage.
Each digit in bit string form requires only one binary bit for storage, whereas each of the digits in absolute form requires three binary coded bits. However, if the number of blanks or 0°s between two binary ones occurrences) becomes large, it will be seen that a point will be reached where it will be shorter and save memory space to represent the information in absolute form. Stating it differently, (, the distance between the binary 1°s in the bit string form determines whether bit string encoding or absolute encoding will give the best.compaction and hence the shortest length of information~to be stored.
~3Y way of example, in a very wide iso-entropicgram, the distance between two event-times ox occurrences may be great. For example, one occurrence value may be 5 and the next 2,673. In this case, absolute encoding should be used since it requires much fewer binary coded bits of information for storage. If the distance between event-times is short, and the number of occurrences is therefore frequent, bit string encoding will be better.
Accordingly, 'the present invention involves a technique where a hybrid encoding is used. A brief description of the hybrid encoding will now be given since ~it is an integral part of a preferred embcidiment of the seed determination process.

7..~~~i~, Table 9 depicts in hybrid code an example of the most significant six words of storage for an occurrence vector containing occurrences at event times 87, 88, 90, 93, 100, 114, 116, 119, 123 aril 125 . Each word contains a bit or "flag" at the left-hand end which identifies whether, it is a bit string word or an absolute word. A binary 1 indicates an absolute word whereas a binary 0 indicates a bit string word. Disregarding the bit string/absolute form bit at the left-hand of each ward, each. binary bit string word contains the largest occurrence i0 value ,at the right-hand end and the smallest at th.e left hand.
I
Word 1 is in absolute form and represents 125 with the most significant binary bit at th.e left and the least significant binary bit at th.e right (disregarding the bit string/absolute form bit at the left end of the word).
Word 2 is in bit string form and h.as seven binary bit positions representing possible occurrence values 118 through 124 but it only contains actual occurrence values depicted by binary l's for occurrence values 119 arid 123.
During the process of encoding to hybrid code, an occurrence vector in bit string form is scanned backward from the right-hand end as depicted in Table 4-A to the deft-hand end from the latest event time or largest occurrence value to th.e earliest event time or smallest occurrence value, assigning absolute and bit string form to the words for storage in memory. Memories are normally i organized so that information is stored in words. As the occurrence values are scanned from the largest to the smallest, absolute and binary form words are assigned so as to give the maximum compaction. Thus, word 1 is in absolute coded form and represents th.e occurrence value 125. Word 2 is in bat string form and has binary 1's at the second and sixth position in the teord, indicatin; occurrence values of 123 and 119. Vlord 3 is in bit string form faith binary 1 bits at the second and fourth positions, representinU
occurrence values of 1I6 and 1140 Encoding is changed from absolute to binary coded form when more than seven bits can be saved by switching from bit string form to absolute form. The occurrence value 100 is 14 possible occurrence values away from the occurrence value 119 In the encoding procedure, it is necessary to checlc the efficiency of changing 10~~ the forms of representation by calculaf ing the number of bits that are saved. Since there are three possible occurrence values to the left of occurrence value 114 in word 3, three bits are potentially wasted by switching to absolute ford, plus it eaill require a full word of seven binary coded bits 1~ to represent the information 3,n absolute form~ Thus a total of 10 (7+3) bits are requ~,red for changing to absolute coded form, producing a saving of four bitso There~ore, it is desirable to switch from binary form to absolute formm Thuss as depicted in Table Sy word G. is in absolute form 2011 $~ represents the occurrence value 100, Occurrence value 93 is seven possible occurrence values from the occurrence value 1000 Since seven bits are potentially saved knot more than 7) the form of encoding is not changed and the encoding for the next word 4 will remain in absolute 25'~ form.
Occurrence value 90 is only three bits away from occurrence value 93. ~ccordingly9 bit string encoding is more efficient and i~~ord 6 is in binary string forma Hybr3.d encoding is used to store all occurrence vectors 30~~ in the DPPi systemo Therefor~e9 although one particular line p 1 in an iso-entropicgram may produce the shortest length of occurrences in bit string form, it may be found that another lire of the same iso-cntropicgram c~aill actually produce the shortest length when converted to hybrid form.
Hybrid encoding is used to encode all of the occurrence vectors sent back to the auxiliary memory for storage and all occurrence vectors read from the au:ciliary memory for processing by the rest of the DPM SYSTEM, Decoding of the occurrence vectors read from the auxiliary memory and processed in the DPbi INTE~'ACE MODULE is accomplished by entering the hybrid coded string of words largest occurrence value first. Infoa~ion is processed in the DPM SYSTEM in absolute coded form. Accordingly, the DECODE I and DECODE II
MODUhES depicted in Fig. 1 translate all hybrid coded information transferred from the auxiliary memoxy into the MEMORY M~DULE into absolute coded form for processing by the DPM SYSTEM. Similarly, the ENCODE MODUL:translates all processed information in the DPM SYSTEM from absolute form back to hybrid coded foam for storage in the MEMORY
20 ~D~ and subsequent transfer back to the auxiliary memory.
The details for performing encoding and decoding in the ENCODE and DECODE MODULES will be described hereinafter with respect to each of these modules.
F'. Conventions and Com onents Used in the Fi ures 25 Each of the modules has control input/output lines {narrow lines) and information input/output lines (heavy lines). Ey way of example, the ENCODE MODULE shows these lines along the right hand side of Fig. 3. The narrow lines used to represent each con-trol input/output line represent a single conductor. Each heavy line represents 8 conductors for carrying_8 binary coded bits of infor;nation in parallel. Arrows to the. left indicate incoming sig-nals to the corresponding module whereas arrows to the right indi-cate outgoing signals, 1 Symbols are shown at the tail of each arrow representing each incoming control input/output line. Each of these syrnbol~ not only uniquely identi~i.es each line, but identifies the source or module ~xora which the signal for that line originates, , The convention employed is to use one or t~~ao letters followed by one or more numbers. The letters identify the originating module axrl the number gives a,unique identification to the line. For example, Fig. 3 of the ENCODE PIOD~ shocos the symbol Srs2 for the top line,. The signal for that line originates i~n the SEA riODtTLE. Table la gives a list of the letter symbols and' the correspondird; module. Some control input/output lines have identifying symbols which do not follota this convention and the originatinv module is identified. ~ i Outgoing control input/output lines (arrows to right) ;.
are also labeled. The symbols on the left (tail of arrow) are logic representing the logical equations fog gates used in generating the signal on the outgoing line. A symbol is used at the arroiahead to identify the line as it leaves and enters other modules. For eoampl~~ in the ENCODE I~ODUi~E, the logic P9 represents a gate used t~ generate a logic signal on tire line EVl.
Gating is shown in block diagram in some instances and in others, logical equations are used to represent the gating for simplificat~n , Standard symbols are used in the logical equations. Thuse a "~" represents an "O~i" condition; a "." represents an AND condition; and symbols representing the outputs from flip Elopes gates9 regis~ere counters, etc.
~4~I are used as the terms in the equations. By way of examples i ii 1 i, logical gating is depicted in the ENCODE P~ODUL.E, Fig. 4 to reset the flip flop ERFST to 0. The logic iso PS.G.ERFST.CLK. The gate represented by this logic is true when true signals are foamed at each of the outputs indicated in the equation, This, of course, illustrates an AND gate with each of tt~e indicated outputs as inputs to ar. AND gate. The logic PlO.G+P7.GE+Pll.Co for flip flop P2 represents three AND gating conditions combined v by two OR gating conditions.
Flip flops are extensively used throughout this patent appli-10~~ cation. One type of flip flop used extensively employs a type SN7474 positive edge triggered D~-type flip flop disclosed at page 121 ~f the book entitled The TTI~ Data l3oolc for Design Eneineers, published 197 by The Texas Tnstruments Co. Each.
of these flip flops is identified by a rectangular box with a ls~~ line in the upper left hand corner, such as that shown for flip flop Pl2 of Fig. ~. Each of these flip flops is character~.zed in that an input exists at the t~p side and one at the bottom side and ttao inputs exist at the le:Et hexed side. Also, each has a pair '-of complementary outputs at the right hand side, the upper one ~f!
20 which has the same symbol as the flip flop (i.e., P12) and the j.
lower one of which has a line over the top referred to as prime (i.e., '~I~). These flip flops operate as follows. A true signal ' app7.ia~ at . the top side (without clock sets the fli flo to a 1 p p , state, causing true aa~d false signals at the unprimed and primed outputs, respectively (i.e., P12 and °). A true signal applied at the bottom side sets the flip flop (without clock) to a 0 state t ~caus ing false and true signals at the unprimed and primed outputs, respectively (i.e., P12 and '), The.lower left side input of these flip flops is for cloelc, and the upper left side input is for control of the state into which the flip flop is set responsive to clock at I
I

'I
~1 1I~ th a locner left hand side input, A true signal at the upper left side input causes the corresponding flip flop to be set to a true utate responsive to a simultaneous~.y applied true clock pulse at the lower left side input, and a false signal at the upper left side input causes the corresponding flip flop to be set to a false state responsive to a simultaneously applied true clock pulse at the lower left side input.
~o simplify the drawings, the outputs on the right side of flip flops are not always shown as they are for flip flop P12. 1 i.
For example, see flip flop P1 of the ENCODE Z~20DULE~ However, the unprimed and primed outputs are always implied and will '' be used at various places in the system. ~'or example, tie P1 output of flip flop P1 is not shown on the right of flip flop 'P1, but it is shown in the logical equation gl'AGE for controlling the upper left side input to flip flop Pl.
Simi:~ to the control input/output ~.ines and the information input/output lines, heavy connecting lines ire used throughout to designate multiple signal conductors 2~~~ whexeas a thin line represents a single conductor.
Selection circuits are used throughout the system.
Ey way of eatample, the ENCODE ~~DULE has selection circuits EDSI-EDS7. The selection circuits each have two car snore I
labeled mufti-bit information input circuits, each input circuit for receiving multiple binary coded bits of information, and one mufti-b it output for receiving the same number of bits as an information input. the information input circuits are labeled directly on the outside of the box such as EDS1-EDS7 0;~ the ENCODE rzODULE. In some cases,

5~~~ the labels are implied such as for selection circuit DS1 n ~.. ., 1I~ of the DPri xNTTla1'~°ACE I~IODULI; where the label 3.s implied to be the same as the originating circuit of the information wignals.
Also, each seleci:,ion circuit has a control input corresponding to each of the information inputs which is correspondingly $ labeled inside of the boss. A true signal at the correspondingly j labeled control input causes the selection cixcuit to couple only those signals at the correspondingly labeled information input to the. output circuit. By u~ay of example, in the ENCODE IICJDUI~E, a true signal at the 1 side control 10~~ input of selection circuit EDS1 causes the output of register 104 to be coupled through EDS1 to the left input of the ALU.
Various modules also have an arithmetic logic unit ~IILU of the type SN74181 disclosed at page 381 of the above TTL boolc. An ALU is shown by way of erample in the ENCODE
D20DULE, Fig. 2, The arithmetic unit ALU is characterized in that 8 bit signals coded in the 1, 2, 4, 8 Binary coded number system applied at the inputs ~~1 arxd ~~2 enable ALU
to form 8 bit signals, coded in th ~ same number system, at an output OP. A true signal applied at the ADD input causes a signal at.the output OF representing the sum of the two coded signals applied at ,~~1 and ~~2. t~ereas, a control signal applied at the SUB input causes a signal at 0P, representing the c~fference between the signals at ~kl and ~~2 in 2 a s complement form.
The arithmetic unit ALU has additional outputs G, L
and E. A true signal is formed at tle G~ L and E outputs, respectively, when the number represented by the coded signal at .'1 is "greater than" ( ~ ), '°less than" ( ~ ), and "equal to" ( ~ ) than at ~~2.
The ALU design uho~~'n here is for a 4~ bit chip.

Y~~
'' \
1 However, it could be generalized into larger groupings.
In all likelihood, larger capacity ALU's (e.g., 24 or i 32 bits) would make use of type SN79182, look ahead carry generators, of the above TTL book. However, these are not i necessary for an 8 bit wide ALU.
It will be'obvious to those skilled in the art that minor circuitry peripheral to ~~.he SN74181 is required to receive the true signals_and provide the output signals shown and described with reference to the AZU and these circuits are depicted in the block diagram of Fig. 6.
Some modules have unprimed inputs (i.e., EOF3: of Fig. 17), whereas a primed form (i.e., EOFT) is used in the module. The primed form (i.e., EOFt) merely indicates the logical inverse of the unprimed form which is formed by conventional signal inverter circuits. Signal inverter circuits are not always shown hut are implied in some instances (as for example, EOFjC in Fig. l7).
Although specific hardware is disclosed for vari~us modules in the DPNd system, it should be noted that the 20 modules~might also be implemented using micro programmed mini computers with appropriate firmware programs.

II ~'~ ~.~.~~J~J
1~~ I-A. GENERAL ORGANIZATION OF DPM SYSTEM OF FIGS. 1-34 Reference should be made to Fig. 1 in the following discussion.
The DPM SYSTEM has a MINI COMPUTER and a DPM INTERFACE
MODULE. The MINI COMPUTER may be any one of a number of mini computers well known in the art, a micro-programmed computer or a specially designed computer. For purposes a 2. W o...~r~G, of illustration the PD P 11/45~with floating point arithmetic units is disclosed by way of example. Included therein is a MAIN MEMORY and an OPERATOR CONSOLE with typewriter and printer input and output. The MINI COMPUTER contains a user program which supervises and sequences the operations of the entire DPM SYSTEM. The DPM INTERFACE MODULE provides the interface between the MINI COMPUTER, an auxiliary memory for the MINA COMPUTER and the rest of the DPM SYSTEM.
The DPM contains an IPRF which .is a set of registers in which the MINI COMPUTER stores parameters to be used as input by the other modules in,the system as discussed more fully in connection with each module. The MINI COMPUTER through the DPM INTERFACE MODULE also stores information in the MEMORY MODULE for processing by the rest of the modules.
The information stored in the MEMORY MODULE is in the form of hybrid coded occurrence vectors: The DECODE I and II
MODULES decode all hybrid coded signals from the MEMORY
25~~ MODULE to absolute coded value signals and the ENCODE
MODULE encodes all signals being stored in the MEMORY MODULE
from absolute coded value signals to hybrid code. The exception is with respect to information signals transferred between the MINI COMPUTER or the DPM INTERFACE MODULE and the MEMORY MODULE.

The MINI COMPUTER causes an occurrence vector, in the form of a given line value of an iso-entropicgram, to be sent from the MAIN MEMORY to the MEMORY MODULE via the DPM ItJTERFACE MODULE. A REVOLVE MODULE reading from the MEMORY MODULE through the DECODE I and II MODULES writes into the MEMORY MODULE through the ENCODE bIODULE and causes the given line value and line number to be revolved through various lines in the corresponding uii 20 ~I
25' .,, lII iso-entropicgram. The seed is formed using the SEED MODULE.
Specifically, the REVOLVE MODULE revolves a given line, under control of the SEED MOD ULE, throuvh its iso-entropicgram.
The ENCODE MOD ULE determines the physical length of each encoded line of the iso-entropicgram as it is stored in the M~IORY MODULE. ~ The SEED MODULE lceeps track of the length of the shortest line and identifies the area in the PfE2~20RY MODULE that store's the shortest line.
The SEED MODULE during the seed finding process forms lU signals representing the number of Line revolves which must talce place to locate the seed line. This signal, called the total number of lines signal, is sent to the DELTA MODULE
which forms one or more signals representing the component powers of 2 of the total numb~:r of lines signal. The l~~i c~amponent powers of 2 signals are provided one by one to the P,EVOLVE MODULE which ire turn ~:e~rolves the given line by that number of lines. The input lip of an iso-entropicgram is retrieved from the seed line, or any other line, in a reverse sequence of operation. More specifically, the REVOLVE MODULE under control of the OUTPUT MODULE revolves the seed line until the input line is formed. In this case the ~UTfUT MODULE forms a signal representing the total number of lines required to revolve the seed to the input line.
The DELTA T~3DULE receives the total number of lines signal and forms one or more signals representing its component powers of 2. The REVOLVE MODULE again revolves the seed line by the amount specified by each component power of 2 signal until the input line is reached.
Data is entered in the existing data base by adding, 30~~ Changing or deleting. This is generally referred to as the ~1 ll~ update function. The update function is talcen care of by the CT1ANGE P~iODULl;, ~Jhen a seed is to be updated, the MINI COMPLiTER enters the changes, etc. into a word referred to as the "change vector", ~ ~~ T.he C1~11; ;r; P~20DULE first gets the occurrence vector in seed form from the data base. Using the DECODE I and II and ENCODE
MaDULES for communication with the MEMORY MODULE, the REVOLVE
MODULE revolves the change vector seed ba:cl: to the sa~rxe line of its iso-entropicgram as the sees. Tn~ change vector a.s 10~~ t'~en merged with the seed using the X0R operation discussed above, The OTJTPUT T~~DULE is provided primarily for the retrieval process of revolving a seed or other line to the kaput line of its iso-entropicgram. However, the OUTPUT MODULE also causes the DEL function to take place. The purpose of the 1~ DEL function, as discussed above, is to determine if a particular occurrence value e:Kists at t:he input line of an iso-entropicgr~m given the seed line. Significantly, the DEi. function allows this to be checked very rapidly without haring to revolve the seed-line back to the input line.
2011 The OUTPjJT MODULE has a special clapping function which allows the DPM SYSTEM to recall an occurrence vector from the data ba~e and retrieve dust a specified portion of the occurrence vector. For example, one might want to know how many. times the word "help" occurred between occurrence 23 event times 2,000 and 2,832. To be explained in more detail, the numbers 2,000 and 2,832 would be entered into the OUTPUT riODULE as loever and upper clipping bounds, allowing the event "help" to be retrieved only for those occurrences which lay between 2,000 wind 2,832.
The PIPE MODULE and BRIG23TNESS MODULE perform a 30 .
discrimination function in the DPM SYSTEM, This does not have anything to do with the data base managing functions.
SigniLicantly, the PIPE and BPIGEITNESS P~40DU~,ES allow near make up the user request. Each event is retrieved from the data base and compared against the others in the request.
The object is to find if the same sequence of events has occurred between any tcao delimiters in the layer in question.
The output of the PZl'E MODULE consists of two values for each logical entity in the layer as follocuss 1, A starting value, and B. A numerical value which gives the number of 1~ occurrences of evexits that appeared in the data base from the request. ' If the sign bat of the numer~.cal value 3s ~~ln (true), this indicates that the request bccurred e~aetly somewhere between the specified delimiters. The aforegoin~ is 20 Primarily the piping function.
The brightness function improves on the piping function.
~'or example, the piping function chooses the best candidate for brightness. The brightness function then chooses the best possible candidate.
Essentially, the brightness function talces the starting value caithin a logical entity which is received from the III miss retrievals. In other words, they allocn ine~:act retrieval of information from the data base.
Both the piping and brightness functions of the PIPE
and BRIGHTtZESS T40AULES caorl: on a sequence of events beteneen delimiters. These delimiters could be any level delimiters.
The PIPE tIODULE is presented caith a sequence of events which PTPE MODULE and then tapes each event from the input request and finds th a closest occurrence of the event to this starting value, if one e:~ists. The brightness function then finds this occurrence for each event in the request and the process is repeated for each logical entity which is to be checlced.

1 After all the events in the request have been processed, a calculation is made to find the brightness value for the request.
The brightness value can be described considering the following example. Picture the logical entity from the data base and immediately to its left the request.
The request is then shifted right, one event at a time, over the data base entries and a value is computed for each shift. The value indicates how close the request lines up with that of the data base. The best value is then passed as an output to the user at the OPERATOR
COi~SOLE. This value is computed for each logical entity which has been requested.
The exact way in which the piping and brightness functions work are best understood in connection with each module. Accordingly, reference should be made to the sections XV. PIPE and XVI. BR7:GHTNESS MODULE and the software sections XX~II for a imo~e complete description and understanding of these features.

30 fl ' - n II. ENCODE MODULE
A. General Description Section I GENERAL DESCRIPTION OF DPM SYSTEM describes hybrid. form of coding of the information, with respect to the example in Table 9. The ENCODE MODULE is provided in the DPM SYSTEM of Fig. 1 for the purpose of converting absolute coded occurrence vectors to hybrid coded form and controlling the writing of the hybrid ooded occurrence vectors into the MEMORY MODULE.
At the outset, it should be kept in mind that occurrence vectors represent a series of occurrence values out of a larger set of incrementally ordered possible occurrence values or event-tames. Occurrence vectors are stored, retrieved and processed such that the highest numbered occurrence value is first. The highest numbered occurrence value identifies the most recent occurr~enae in the event-time domain. The lowest numbered entry, and hence the entry farthest back in e~rent-time, is stored, retrieved and processed last. Examples of delimiter and event occurrence vectors (in absolute coded form) are shown at "d5'° and "T"
of Table 2. This form of information representation is quite important to an understanding of the ENCODE MODULE embodiment about to be described and with respect to each of the other module embodiments about to be described.
The MEMORY MODULE reads and writes information a word at a time. A word has ~ binary bits of information.
The ENCODE MODULE, in the encoding process, processes each occurrence vector as follows:
The ENCODE MODULE is called each time an absolute 30 occurrence is to be encoded by either the REVOLVE MODULE
or the OUTPUT MODULE. The module which calls the ENCODE

i 1 1~IODUL~ is hereinafter called the calling module.
The ~NCOD~ ~IODLTh); receives the absolute occurrence valuev of an absolute coded occurrence vector in decreasing value order. A currently received absolute word and a previously received word in the series are held~and compered. The difference between the current and previous absolute 'values represent the number of binary bits of displacement between them, If the difference is greater than some "specified number of bits" (in this case, 7 bits), then the previous absolute value is outputted in the hybrid word series as an "absolute" word (see word 0 of Table 9). If the difference is less than this "specif led number of bits", the present absolute value is entered as an occurrence into a bit string word (see word 2 of Table 9) 1~I of the hybrid series. The latter is accomplished by shifting the bit string word under formation the number of bit positions designated by the di:~'ference and entering a bit of predetermined values i.e., °'1", into the bit string word, and the ENC0D7~ r~ODUL~ is "exited" by terminating its 2~ operation. Z7hen a bit string rrJOrd under formation is complete, it is also outputted. 2t should be noted that binary bit at the most significant end of each word being outputted is reserved as a type or.flag bit to indicate the form of the hybrid word, A '°1" bit flag indicates 25 an absolute word whereas an "0" bit flag indicates a bit string word.
The hybrid form to which the absolute occurrence values are encoded is a series of absolute and bit string words starting with an absolute word, An absolute word in itself represents the value of one occurrence by a combination of _~g_ ~~z~~~~
1~~ binary coded signals. A bit string word represents an occurrencd value by the number of possible occurrence values of displace-meat of an occurrence of predetermined value, i.e., "1", from the previous absolute word or from the previous occurrence of i predetermined value in the hybrid word series. The ffirst word of each hybrid word series is always an absolute word v and therefore in itself, identifies the value of the first and largest accurrence. ~Iiowever, it should be understood that within the broader concepts of the invention, the invention may be employed in a system which is n~t bound by words, in which case the bit string portion of the hybrid form would not be confined to words.
Another purpose of the ENCODE MODtIr,E is to perform "clipping" and °'clipping" by ":Lnterval'°. Clipping is the operation of determining if ea<sh absolute word occurrence value lies between a top limit (TL) and a bottom limit (BL).
This operation is performed by comparing each absolute word with TL and BL. If the input entry is < TL and >_BL, the absolute word is within desired bounds, and encoding 2~ continues and, if not, a corresponding 'indication is formed.
If "clipping" by "interval" is to be performed, an "interval°' value (EI) is provided to the ENCODE 1~DULE.
If the absolute word is not.~.TL and ~ BL, then EI is subtracted from TL and BL, and the same absolute word is 25 again compared with the modified TL and BL values. This continues until gL goes below 0 at which time a corresponding signal is formed or the absolute word is found within the bounds of the modified TL and BL, according to the above criteria, at which time the absolute word is converted to hybrid form, as discussed above. The "clipping" by °°interval"

~1. ~~'~~'~~.
1 function is important un~~er certain conditions when it is needed to lcnoca if the input entry is within certain regular intervals, i.e., 45-40 or 25-20, 10-5. The values TL, liL and EI axe read by the ENCODE TiODULE from the corxespond-I ing registers of the IPRF.
E. Components The ENCODE MODULE includes registers..ET, EIR, EI, ER, E0, EHW, ETL, EBL and EOP. Each of these registers captains S bits of storage. With the exception of EOP and ER, each register is of type SN74100 disclosed at page 25~ of the above TTY. book and are character~.zed.:in that a true signal applied at the L input at the side thereof causes the binary coded signals applied at the upper side input to be applied to the lower output. 4~en the signal at the L input goes false, the information is ratafined in the register even though the information input signals ch;~nge thereafter.
The EIR register is shown with two specia9, autputs Ea and ~, True signals are formed at these outputs when the content of the EIR register is 0 and not 0, respectively, Tt w ill be understood that an appropriate circuit (pat shown]
is connected to the SN~4I00 register far ~arming these signals. Preferably, the circuit has the "1" output o~ each bit position connected t~
the input of a cowman "OR" gate. The output of the "0R"
2~
gate is the ~ output, whereas the output of the "0R" gate is connected through an inverter to the Eo output, The ER register i, a data latch o~ type SN74116 of the above TTL baolc and is similar to the SN74100, except that it has a "CLEAR°' line which provides a ape step clearing operztion.

C' II
Register IdOP consists of a flip flop HISB and a seven bit parallel-in/para11e1-out shift register 114 of type SN74199 as disclosed at page 4S6 of the above TTL book. Register 114 is a 7 bit register and is characterized in that parallel load ing is accomplished by applying the 7 bits of data at its upper side and malting the shift/load ~S/L) control input low or false when the CLOCK
input is not inhibited, i.e., receives a,true signal. A
true signal at S/L causes a shift to the right by register 114 30 responsive to the lead ing edge of a true pulse at the CLOCK
input. A false signal at S/L causes the ~ bits applied at its upper input to appear at the output of the register 114 and be stored therein responsive to the leading edge of a true pulse at the CLOCIZ input.
Considering register EOP in more detail, a false signal at P~3 causes register 114 to load the.i.nput s ignals applied at the upper side. Typically, a true signal is simultaneously formed at P9°BSW to the MSB fl~.p flop. When CT,K goes true, P9°BSW°CLK becomes true and, being applied to the 2011 CI~OCK input of the MSB flip flop and the register 114, causes the MSB flip flop to be set true and load 7 bits of information from register EO .
In addition, the ENCODE MODtTLE has counters MAR3, r~GN3, CTR and NOC. CTR has 8 states, NOC, r~lR3 and MLN3 2~~~ each have 256 states and are of type SN74161 disclosed at page 325 of the above TTL book.
CTR is a 3 bit up/down counter of type SN74191 disclosed at page 417 of the abave TTL boolc and is characterized in that a false signal at IJ/D causes the counter to count up when a true signal is applied to the CT

l~i input and a true signal at iJ/D causes the counter to count down when a true signal is applied to the CT input. The counter can be preset to a value corresponding to the signals applied at its input at the upper side while applying a true ~s3.gnal, to the L input. The block indicating CTR contains a circuit not shown, similar to that described for the ER register for forming true signals at the ~o and Co outputs when the Mate of CTR is 0 and not 0, respectively.
The ENCODE MODULE has counters ~A.R3, 1~N3, CTR and NOC.
CTR has 8 states, NOC, MARS, and MLN3 each have 256 states and are of type SN7~r161 disclosed at page 325 of the above TTL book, The counter CTR counts through its prefixed sequence of 8 states and automatically resets to ita initial or 0 state. Each of the MAR3, MLN3 and NOC counters are of type SNZ4161 of the above TTL boo~~ and are controlled to always count upwards. 'Not shown but ,~.ncl.uded within each box is a logical signal inverter to invert the signal at CLR before it reaches the SN74161. A true signal applied at the CLR (CLEAR) inputs of MAR3, MLN3 and NOC causes them to be cleared or reset to a "0°' state. A true signal a at the CT input causes the counters MAR3, MLN3 and NOC
to count up, Tha ENCODE MODULE..also has flip flops EFRST, ELAST, ' BSW, ECE, ~T/D and MSB. In addition, a control counter 113 has flip flops P1 to P12.
The ENCODE MODULE also has a source of recurring clock pulses 102. The source of clock pulses 102 forms a series of equally spaced (not essential) recurring true clock pulses at its output. The output of source 102 is connected to one input of an AND gate 112 which forms clock signals at CLK

W
,_,.
1~~ whenever the other input to gate 112 is true in coincidence with a clock pulse. A signal inverter 117 inverts the signal at CLK to form pulses at CLK.
The ENCODE MODULE also has an arithmetic logic unit ALU
at #1 and #2 in 2's complement form. Conventional OR gates 108 and 110 are'crnnected to G, L and E so that true signals are formed at a GE output of 108 and a LE output of 110, respectively, when the values of the signals at #1 are '°equal to or greater than" (Z) that at #2, and "equal to or less than" (C) that at #2.
The ENCODE MODULE also has selection circuits EDS1-EDS7 of the type disclosed above. The ENCODE MODULE also includes conventional logical OR gates 104-110, 118 and 119 and an AND gate 112.

C. Detailed Description The ENCODE MODULE can k~e most readily understood with reference to the description in connection with the block diagram, Figs. 2-~, and the corresponding flow diagram, 2011 F~gs° 7-8. As an aid, Table 11 contains symbols used to identify the counters, registers, flip flops, and one-shot multivibrators, together with the mnemonic meaning of the symbols used. Also as an aid, the, flow diagram contains P numbers adjacent to the various blocks, i.e., (P1), (P2), 25 etc. These P numbers correspond to~the outputs of the control counter 113 and thereby indicate the state of the control counter during which the indicated action shown in the flow diagram takes place. however, the same P number appears for more than one box. Therefore, for added ease in making 30 reference to the flow diagram, symbols EB1 through EB26 are used~to identify each box in the flow.

il 1 Table 11 shows the principal information inputs and outputs and the input control for the ENCODE riODULE . Top clipping limit, bottom clipping limit, interval and iso-entropicgram width are each 8 bits long and are loaded into registers of the ETdCODE T~iODULE by the modules indicated in Table 11.
Assume initially that clipping is not to be performed in which case OPSW, ETL,.EPL and EIR axe all initially 00 Also assume that the ENCODE T~iODULE is about to be called f or its encoding function for the first time. Preliminary to calling the module, the current absolute taord is received by the EDS 6 selection circuit either from the DS4 output of the REVOLVE P~10DULE or from the 0RT1 register of the OUTPUT PMODULE. The first current absolute word to be received is the first or largest absolute coded word (8 bits in length) of an occurrence vector. Afver the REVOLVE MODULE
supplies the current absolute word, tru~a signals are formed at Rt411 and RM6 by the REVOLVE MODULE. When the current absolute word is being supplied b y the OUTPUT MODULE, true signals are formed at 0M13 and 0M14 by the OUTPUT MODULEo A true signal at RMll,causes the EDSG selection circuit to couple the current absolute word at DS4 to the information input of register EI. The true signal at Ri~~6 enables the OR gate 109 to activate the load (L) input of E I and load the current absolute word into EI. Similarly,~a true signal at OT~tl3 causes EDS6 to route the information input from the 0RT1 output to the information input of EI and the true signal at 0M14 enables the OR gate 109 to activate the load (L) input of EI and load the current absolute word 30 into EI. It should be noted that all current absolute words ~1 lIl for one occurrence vector are supplied in sequence largest ' to smallest by the same calling module.
The iso-entropicgram width (IIV1) is stored in the input parameter resister file IPP,F. Loading of the iso-entropicgram ~~~idth into EI~ItJ is enabled by true signals at any one of the following outputs: 0P21 output of the OU~UT IaODUt~E; SM3 output of the SEED tiODULE; and the CI~Z3 outlet of the c~IANCE r~DULE.
OPSW is an output circuit of the O:PS47 flip flop in the ~~~ riODULE. P~S~J is the 1~gical inversion of OPSVI. Only the OUTPUT tiODULE determines if clipping is to tatce place and, if it is to talce place, the OPSiJ flip flop is in a 1 state, othexcaise it is in an 0 state. Since it is assumed for the following egcplanation that no clipping is to take 1~ place, a true signal appears at .
The EFRST f~.~.p flop is set to a 1 state whenever the present call on the ENCODE MClDULE is for converting the first absolute ~~aoxd in a particular occurrence vector.
EFRST is set by the calling module. Tn the case of the OL'~1E MODULE, a true signal is formed at the RM2 output, whereas, in the case of the OUTPUT Z~20DUI~E, a true signal is formed at the 02~. output, and enables the OR gate 105 to set the EFRST flip flop to a 1 state.
The EI~ST flip flop indicates if the current absolute word is the last one of an occurrence vector. A 1 state of E"~AST indicates the last one, whereas the 0 state indicates it is not the last one. ELAST is set by the calling module.
In the case of the REVOLVE MOD UhE, a true signal is formed at RM9 and in the case of the OUTPUT MODULE, a true signal is formed at OM1S, either of which causes the OR gate 106 to set ELAST to a 1 state.
_75_ Ilssume initially that E'DlIST is in an 0 state.
Tnitially the T~iTNI COT~~I'UTER forms a true signal at T,iINIT
which causes gates 113 and i17 to set all of control counters 113 and flip flop ECE to 0. To be explained hereafter, true signals at Ei~~2ID thereafter set these elements to 0. The ENCODE ~DLThE is called by the REGOLVE T~iODULE by forming a true signal at RM7 and by the OUTPdJT rTODULE by forming a true signal at ODilS. Either of these ticu~e signals enables the OR gate 107 to trigger thvENGO one~shot multi 1~I~ vibrator which, in turn, causes a true signal at the ENGO
output. The true signal at the ENOU output causes the ECE
flip flop to be set to a 1 state, The 1 state.of the ECE
flip flop causes a true signa2 at the ECE output which, in turn, causes the AND gate 112 to couple the CLK output of the clock 102 to the Block input of each of the eontxol oaunter x.13 flip flops Pl-P12. Clock signals now be3ang formed at the output of the AND gate 112 cause the ENCODE
hIODUJLE to commence its seeluence of operation by virtue of the control action of control counter 113. All flip flops P1-P11 being in an 0 state and a true signal being formed at cause flip flop P5 to be set to a 1 state, form ing a true signal at the P5 output.
One form of clipping is caused by the OPSW flip flop in a 1 state. An alternate form of clipping is automatically ~5~~ done by the ENCODE MODULEo Specifically, in the alternate clipping, the absolute words of an occurrence vector are received by the ENCODE PZODLTLE in decreasing order of magnitude.
The EN~DE P20DtJLE automatically clips or discards all of those absolute v.~ords which are larger than the 3so-entropicgram width ~OII and hence lie outside of the iso-~entropicgram. The alternate 1~~ form of clipping is very useful in connection with the REVOLVE AfOD ULE where the result of an exclusive OR is clipped tz~ keep only the loc.~er ordered values which are within the iso-entropicgram width. The ENCODE MODULE
Si~ will automatically perform this clipping, using flow chart blocks EB6 and EBB.
Considering the alternate clipping function in more detail, EFRST is set to 1 when the ENCODE MOD ULE
is called for the first time to encode an occurrence vectar~ This is done to insure that the alternate clipping function is performed. Thus at EB6, flip flop EFRST being in a 1 state, causes EB8 to be entered where the iso-entropiegram width in register EHLd is compared with the input current absalute word in register Ex. If the content 1511 of EFIZJ G EY, the operation of the ENCODE MODULE is exited by farming a true signa'1 at EMErR:a, thereby indicating tt~ the calling madule (i.e., REVOLVE) the t it has processed one absolute word. Actually, the absolute word is just discarded by the ENCODE MODULE. When the, ca'~.ing module again calls the ENCODE MOD ULE to cause another absolute word of the same accurrence vector to be processed, flip flop EFRST
will still be in a 1 state, causing EB8 to again be entered.
If the current absolute word is larger in value than the iso-entropicgram width, an exit is again taken. This is repeated until at EB8 the current absolute word is smaller than the iso.-entropicgram width (e.g. EI~IW> EI) at which time EB9 is entered to reset flip flop EFRST to 0. Thereafter when called, the ENCODE MODULE dog not perform clipping because the ENOODE MOD ULE gees from EB6 to EB7.
Consider now the operation during EB8 and Eli9 in details _77_ Assume EB1 and EB6 of the h1\CGDh t~IODULI; fha have been traversed, and assume EB3 is noon entered during which the iso~entropic~ram ~nidth in EHV is compared with the current absolute word in EI° If the current absolute word is larger than tl~e iso-entropicgram width, it is outside of the iso-entropicgrarn and therefore a ,'don't care" condition exists, To perform the comparison, the true signal at 'P5 causes EDS1 and EDS2 to couple the contents of EHG~d and EI to the arithmetic unit ALU. ALU, together.with the OR gates 108 and 110, in turn form true signals at outputs LE and G whenever the content of EHW is, respectively, ? than and ~ than the content of EI° If the ~ condition is sensed, true signals are now formed at the P5, LE anc~ EFP,ST outputs and the true signal at ~ causes the CLOCK S USfENS ION LOGIC
13 -122 (i°e°, P5°LE°~) to resE:t the ECE flip flop to an 0 state Which, in turn, removes the true signal at ECE and thereby causes the AND gate 7.712 to stop forming cloclc signals at the input of the control counter 113~ The same signal causes the one.~shot Er~ND to fixe and foam a true signal at EI~1~D ° This signal notifies the caller that the ENCODE function has been completed, It also resets control counter 113 through OR gate 112° This, then, in effect causes an EX7.T to be talven from the EN~DE tIODULE rahere no action is taleen until the next request is made to the ENCODE MODULE
2~~t from the REVOLVE or OUTPUT MODULE, If, on the other hand, the content of EI~W is ? than the content of EI (true signal at G), EI39 is entered, Assume during EI38 the content of E~IG7 is ~ than that of EI and a true signal is formed at G, causing E>i9 to be entered. The BSjv flip flop states of 0 and 1 indicate 'the previous absolu~tF
_~8_ n 1~' word has been entered in the hybrid called output in bit string form and absolute eaord form, respectively. Since the first hybrid caord is always in absolute caord form, ESrJ
is to be set to 0, indicating tI~ t .the corresponding output is in absolute word form and the Z~iAP,3 and riLN3 registers are cleared to.initial or 0 states, ready for the first hybrid word to be stored in the MEMORY ~~IODUiaE o During EB9, true signals are formed at the follocaing outputs: G, EFRST, and P.~. Hence, at the following pulse at ~-~s the counters and registers NOC, r9AR3 and Iil,N3 and flip flops EFP,ST and ELAST are a~.l reset to 0.
EB19 is then entered and the same signals cause ER
to be reset to 0 and the reset logic resets BS~1 and DiSB
of register E01' to 0, Followini; EBIg, EB20 is sintered during which the same true signals are also present which causes load logic to load the current abso Late word into E0. The current absolute word in EO note forms the previous absolute word for the next call on the ENCODE MODULE. The same logic 2~ also causes N0C to count up one state, indicating that one absolute word has now been provided t~ the ENCODE r~ODULEo At this point, a true signal is formed at the outputs P~, EfRST. Therefore, the next pulse at ChK, the ECE flap flop is reset to 0, thereby disabling the gate 112 from applying clock signals to the control,counter 113 as described above.
Subsequently, the calling module again calls the ENCODE DiODULE and provides the next current absolute word at which .time a true signal is applied at either the R~i7 or 30~~ 0M15 output ~of the hEVOLVE or OUTPUT Z.20DULES) causing _79_ 1~~ the OR gate 107 to trigger the one shot multi vibrator circuit ENGO, thereby setting the ECE flip flop back to a 1 state and enabling the AID gate 112 to apply clock signals to the control counter 113.
At this point, it is assumed that the next'current absolute word is not the last one in the occurrence vector and hence the ELAST flip flop is in an 0 state, forming a .
true signal at 'Si. This causes the next cloclc pulse from gate 112 to reset flip flop PS and set flip flop P6 10~~ to a 1 state, thereby enabling EB10 to be entered, During EBIO, a true signal is formed at the P6 output which cause: EDS1 axxl EDS2 to couple the previous absolute word contained in EO and the current absolute word contained in EX to the ALU eahich forms an output at OP corresponding ls~~ to the difference. This diffs~rence is referred to as the .!I previous 'and current difference signal. Additionally, the signal at EDS7 causes the selection circuit EDS7 to gate the previous and current difference signal to the information input of the ET into which the signal is loaded by the subsequent clock signal at ~"fL',. Thus, ET now contains the previous and current difference signal which is the number of bits of displacement (either in event time or in possible occurrence values) between the current absolute word in EI and the previous absolute word in E0. Additionally, the true signal at PS causes the U/D flip flop to be reset to a 1 state, asserting its true signal at the U/D output, thereby causing CTIt to be set so tl~ t it counts down. The P6 output of the PS flip flop is connected directly to the input of the P7 flip flop, thus the following clock coming 30 °ut of the gate 112 causes th a P7 flip flop to be set to a 1 state, thereby entering EB11.
-~80-,-1 During'EB11, the previous and current difference vignal contained in ET is subtracted from the remaining binary bit signal contained in ER, fhc remaining binary bit signals represent the remaining binary bits to be filled in the S4~ bit string word being formed in EOP. The subtraction results in a difference signal during EB11 which indicates one of two values and these will now be explained. If the content of EIt is larger than or equal t~ ET, the difference is > than 0, meaning that the difference represents the remaining available bits in the bit string sword (now under formation in EOP) after current absolute word is entered.
If the content of ER is ~ than ET, the difference is less than 0 (or m), meaning that the difference represents the number of bits needed in the next bit string word (to be l~~l formed) to enter the current absolute word. An example of these two conditions is now givens the bit string word has a maximum of 7 available bits (see register 114 in EOP
having 8 bits, less 1 flag bit ~ 7). Assume the remaining available binary bits signal in ER ~ S and the previous 20 and current difference signal in ET ~ 3, giving a positive difference of 2. The difference of +2 represents the remaining avail~le bits in the bit string word after the current absolute word. If the values are reversed (ER a 3 and ET ~ 5), then the difference is -2 and represents the number of bits needed in the next bit string word to enter the current absolute word, In other words, the current absolute word will require all remaining available bits HER) in the current bat string word under formation in EOP plus 2 add itional bits in the next bit string word to 30~~ be formed.

i ~ ~ ) When on a previous call to the EtICODE i~iODULE it was found (during EI318) tha t the current absoJ.ute word was to be outputted in absolute caord form, ER was reset to 0 at EBla and hence is 0 at the next entry to EB11. Under these conditions, a difference less than 0 is formed during EB11.
However, the di~ference is the negative of ET (0-ET ~ -ET).
Consider now the details of operation. Assume that the ENCODE MODULE is at EB11, and a true .control signal is being formed at the P7 outputs This ca uses EDS1 and EDS2 I to couple the content of ER and ET to ALU which, in turn, forms an output representing ER - ET. Assume the result is ~Ø A control signal is formed at the L output of ALU, indicating that there e,re insufficient bits in E0P for the current absolute word. EB12 is entered, During EB12, the control signal at P7 and L causes EDS7 and the load logic for ET to store the number of bits needed in the next bit string wore signal being formed at EOP into ET at the following pulse at '~L~, Additionally, the same true signals cause EOS3 and the load logic of CTR to store 20 the content of ER into the counter, setting it to a state corresponding to the content of ER. If ER contains 0, as occurs when this is only the second ca~l1 on the ENCODE MODULE
and hence is the second time through the flow, the true s3.gnals at P7 and L also cause the flip flop P3 to be set into a 1 state, thereby causing EB13 to be entererJ. Tf ER contains 0, CTS: is s et to 0, caus ing a true s ignal at the Co output.
The true signals at P3 and Co cause the P9 flip flop to be set to a 1 state and EB15 is entered, thereby skipping EB14.
To be explained in more detail, EBl4,causes the bit 30 str ing word be ing for. med in EOP to be filled out with lead a.ng 0's .

,°.
1 This operation, and hence EBllo, is slcipped cahen ER is 0 since n~ remaining bits need to be filled in the bit string woxd under fox mat ion.
Return now to EB11 and consider thsoperation when Eh is not 0 and ER-ET is G" 0 causing a true signal at. the T~ output of AhU: Note that ER is not 0 iahen a bit string word is being formed in EOP and available bits exist in EOP in the bit string word under formation. EB12 and 13 are exatered as discussed above and CTR is set to a state corresponding to the number of 1~~~ binar y bits remaining to be filled value contained in ER.
During EB14, a true signal exists at P8 and'~o (CTR is not 0) and each pulse at counts CTR dot~7n one and causes the EO P shift logic to shift the bit string word one bit position in the direction of the least significant bit thereof until ~,g~~ CTR reaches 0, at which time t:he true signal at '~ is removed and one is formed at: Co. Thin causes GTR and EOP to stop counting a~ shifting and EB15 is entered as discussed above.
Assucrie that during EB15 the BS~J flip flop is in an 0 state, having previously been set there during EBl9 thereby indicating i th at the ne~ct event in the hybrid output from the previous event is to be in the foray of an absolute word. With BS'J in an 0 state, EB16 is entered. lDuring EB16, the false signal at'P'g causes the load logic of register 114 to load the previous absolute word contained in EO into the register 114 of EOP and true s:tgnals at P9 and BSW cause the logic P9°ESW to set the MSB flip flop to a 1 state,lindicating that the word in EOP is an absolute word. Subsequently, EB17 is entered.
During EB17, the P9 output (see right hand of ENCODE
P~ODULE schematic) causes a Write Enable signal (EWI) to be w formed in the ME1~ORY MODULE, causing it to store the absolute word contained in EOP into the storage location designated by the eontent of r~AR3.
The true signals at P9 and the pulse at cause the content of rlARB and MI~13 to count up one state,' In thfis manner, the counter NU~19 always indicates the number of memory writes and hybrid coded words written in the MEMORY
MODULE. Thus, an absolute word is outputted by the formation of the true signal at the P9 output which, in turn,. causes la~~ the I~MORY MODULE to read the absolute word from EOPm Retura~ now to EE11 and consider the situation where a previous absolute word is contained in E~, a current absolute word is contained in EI, and ER is ~ ET. AI:U
foraas the difference between ER and ET (i.e., ER - ET) and ,ALU and gate lab form a true signal. Th~r difference signal at the output OP of AI~U represents the remaining available bits in the bit string word now under formation in E0P after entry of,the current absolute word in EI.
Under these conditions, the bit.,string word being formed ~pl~ in EOP is shifted by the number of bit p~sitions indicated by ET and they current absolute word is entered into EOP.
T'~ this end, E'R22 is entered from EE11. The truer signa.3s firmed at P7 and ~ cause the load logic of ER
to store the difference signal being formed at the OP
output of ALU into ER at the. orer~ce of the following pulse at ~e Thus, ER now contains the new number of bats remaining to be filled in the bit string word under formation which will exist after the current absolute word is entered.
Additionally, the same signals cause EDS3 and the load logic to store in CTR the previous and current d3.fference signal in ET. The true signals at P7 and GE cause the P11 flip flop ~p to be set to a 1 state at th a next c~:ock signal from gate 112 and thereby enter EB23.
During EB23, azrl the subsequent state EB24, CTR
is enabled to count through a sequence of states corres-ponding in number to the previous and current difference signal which Haas set into CTR from ET. To this end, the true signal at Pll and at CLIt, together with the true signal at UjD, cause CTR to count down 1 state r~spons ive to each true signal at CLK. Additionally, in the absence of an 0 state of CTR, a true s3.gna1 is formed at the Co output.
The true signals at P11, Co cause the register EOP to be shifted 1 bit position to the right in the direction of the least significant bit, This operation continues until the counter reaches 0 and a true signal is formed at the Co outputs 'rthen a true signal is former, at the Co output, counting,and shifting of CTR and EOP is complete and the ENCODE P-IODULE is ready to enter the value of tte current absolute word in EI into the sl~~.fted bit string word in EOP.
EB2S is entered.
Dur~g EBBS, a true signal is formed at the Co output and the subsequent true signal at C~ causes the flip flops IKSB of EOP and BSt~ to be set to a 1 state. To be explained, the, 1 bit stored in PiSB is subsequently shifted into register ~ 11~
~f E0P curing ~~z~s thereby causing a bit of predetermined 2~ value, i.e., a 1 bit, the bit string word being formed in EOP.
The number of bit positions existing between the currently formed 1 bit and the previously formed 1 bit or between the currently formed 1 bit and the previous absolute word in the series of hybrid word outputs indicates the value of the current absolute word. The 1 state of BSIJ ~.ndicates II c :~
n ~~.~~~~7~
l~l that a bit string caord 3.s nova being formed in IaOP.
The true signal at Pll and Co cause the flip flop P12 to be set to a 1 state at the follocriiy cloclc signal from gate 112 and EI326 is thereby entered.
During EB26, a true signal is formed at the P12 output and the subsequent pulse at Wit. causes the content of EOP, including the content of I~tSIi and register 11.4, to be shifted 1 bit position tocaard the right toward the least significant end, thereby placing the 1 bit into the register 111E portion lOII of EoP.
EB20 is now entered. During EB20, a control signal is now formed at the P12 output and the BS~l flip flop is in a 1 state. The subue~uent pulse at CZI:.causes load logic to store the c arrant absolute word contained in EI into EO , lSli thereby forming a new previous absolute: word and causes NOC to count up.one state, thereby indt;.cating that another absolute word hay been encoded into hybrid form. NOC counts, and thereby indicates, the number of 1 bits processed in any given seed. Additionally, the true siga~al at P12 20 causes the ECE flip flop to be set to an 0 state at the p alas at "C, disabling cloelc signals at the output of gate 1i2, causing the Eh~ND monostable to fire and thereby ~orm a true signal at the EMErID output. This causes counter 113 to be reset and the ENCODE 1~~ODULE operation to EXIT.
25~~ A very important operation in the ENCODE r20DULE is depicted at EB1~; This is the condition under which previous and current difference signal contained in ET is compared caith a predetermined threshold value. This is the heart of the decis 3.on cahich enables a change, in hybrid output, from bit strung word form to absolute caord form and the ii 1 operation is accomplished as follocns. During EB7.8, the P10 flip flop is in a 1 state, causing a true signal at the P10 output. This causes n7Sl and EDS2 to couple the s~n3tches 10~E and the output of ET to ALU. The FLU compares the applied signa~.s and adds the content of ET to the value 7 represented by 'tl~ switclae , 104 and forms a result at 0P.
It should be noted that when EB18 is entered, th a content of the ET is always a negative number, the,number being stored in 2°s complement form. The reason for this .
situation is that ET at this point in the operation always indicates the number of bits needed in the next bit string word to enter the current absolute word which is a situation where at EB11, ET was larger than ER resulting in a negative value. Thus, at EB18 cahen ALU combines the content of ET with the yr lue 7 from 104, a difference signal is formed, If the difference signal is ~ ~), i.e, the value ~
i~? the absolute value in ET, a control signal is formed at G and EB21 is entered. ~f the value ~ is < the absolute value in ET, the~d3fference signal will be ~- 0, causing 20 a Control signal at the LE output of OR gate 110, which in turn Causes EB19 to be entered. The result of the Comparison of the value 7 and the absolute value ix~ ET
is quite important in determining subsequent operations.
if the absolute value in ET is~ 7 (the value 7 is greater), a control signa3. is formed at G and the Criteria is not met 25 .
fox switching from bit string word to absolute sword ixa the hybrid output because 7 is greater than the absolute value in ET. Accordingly, EB21~~~26 are entered where the current absolute word in E1 is entered in the bit string word under formation in EOP. To this end, E0P is shifted right by the ~~., oT ~~.
number of bits indicated by the absolute value of the pxevious and current difference signal contained in ET and then a "1"
bit entry is made into the bit string word being formed in EOP.
If, on the other hand, the absolute value in ET is ~
than the threshold value 7, it ~~youlrl be a saving in memory space to switch ~ from bit string woxd form to absolute word form. EB19-20 is entered. During EB19_20, as discussed above, logic resets f3.ip_flop BSt~J to 0, indicating an absolute word form in the hybrid output for the current absolute tJOrd.
The operation during EB19 and EB26 has already been discussed hereinabove. Therefore consider EB21. During EB21, true signals are formed at the ~ollo:sing outputs:
P10, G and at the following pulse at , the U/D flip flop 1S is reset to an 0 state, causirng tine counter to be sat to count up and EB 2 , is entered, The least significant 4 bits of the 2'~ complement value in ET era set in CTR.
'l~aerefore as CTR is counted up 3t will xeturn to 0 after the number of counts represented by the absolute value of ET, During EB22, th~ content of ET is transferred to CTR
and subsequently during EB23 and 24, CTR is counted up until 3.t finally is recycled to an 0 state, causing a control signal at Co. ~°or each state ~~ GTR, the content of E0P is shifted right by one. Z~lhan CTR reaches 0, the control signal at Co causes the 2~B flip flop of EOP to be sat to l, thereb y providing another occurrence in the bit string word output and subsequently during EB26, the 1 bit is shifted into the register 114 of E~P, all as described above 30 Thus, it should nay be clearly understood that at EB13, determin ink; whethe-r the value in ET (the number of bits _88_ needed in the neat bit string word to enter the current absol--ute word) is j7, also determines whether the E2dCODE biOD'LTL,E
switches f.-..-om bit string word to absolute string form of output, 5~~ There is at least one occurrence held within the ENCODE.pIODULE that needs to be written out at the end of its operation. Therefore, after the calling module has finished using the ENCCDE Z~iODUi~E, the occurrence being held must be outputted, The calling modul~ outputs the remaining occurrence by setting flip flop ELAST. Flip flop ELAST
is set by the RE~3L'~ MODULE by forming a signal at ~Z9 and by the OUTPUT I~iODULE by forming a signal at Ot218s either of which causes the OR gate 106 to set ELAST to a 1 state. The 1 state of ELAST causes a true signal at the 15I~ ELAST output, thereby, indicating this is the last call on the ENCODE riODULE for the occurrence vector currently being converted to hybr3.d form. The control signal at the EI~ST output occurs when the ENCODE MODULE EXITS during the l state of P5. After the control signal at the ELAST
output is formed,.a control signal is foamed by the ltEVOL'VE or OUTPUT DiODULE at RP~Z? or OM15, thereby causing the OR gate 10? to trigger the ENGO shot mufti-vibrators thereby causing the ECE flip flop to be set to a 1 state and hence the AI~i gate 112 to start providing clock pulses where EB2? is entered.
During EB2?, the true control signals at~PS and ELAST
enable signals being formed at the output of svyitches 116, representing the 2°s complement of 8, to be gated through the EDS7 selection circuit and allow the following ,signal ~0 at CLIZ to load the 2's complement of $ ti. e. , a -a) into ET.
_89_ ~1 !1 112'7'!'71 1(( additionally, the true control signal at P5 enables the signal in ER, representing the number of binary bits rema3.ning to be filled (in the bit string ~nord under formation in EOPj, to be gated through L~ S3 to the input of CTR enabling the same pulse at CLIC to load this value into CTR. The true signals at outputs P5 and ELAST
cause the P3 flip flop to be set to a 1 state, the reby cans ing EB13 to be entered. During EB13 and 14, the bit string word in EOP is filled out with leading 0's and l0 l! right justified by shifting the bit string word in EOP
and counting CTR down until CTR ~ 0. Subsequently, EBlS
and 17 are entered where the resultant bit string word is outputted. Of course, should ER be 0 and hence the CTR
is set to 0, right shifting is skipped, and outputting is 1511 done immediately.
The foregoing description of the E'LVCODE,MODULE was made assuring t~ no clipping was to take place. Only the OUTPUT MODULE enables clipping to talce place. If clipping is tm take place, the OUTPUT MODULE initially forms true 20 signals which enable the bottom limit register EBL, the top limit register ETI,, and interval registers E IR t~ be loaded. To this end, the OUTPUT MODULE forms a true signal at.Orilb and then a true signal at 0M1. The input of selection circuits EDS4 and EDSS and register E ~ are connected to 25I~ the BL, TL and TR registers of 1PRF (~'ig.52). Thus, the true signals at 0Pi16 and OPiI cause the bottom limit, top limit and interval value (if an interval value exists) to be strobed from IPTth into EEL, ETL and EIR via the load logic contained in each of these registers. The interval ~0 value is only used and, hence, an interval value stored in --9p_ the interval register EIP, if the user ~oishes to ascertain if the output Zies in certain intervals. For example, if the user mere to eheclc the intervals bettaeen 35 and 25, and then a gain betc~aeen 15 and 5 0~ an occurrence vector, he specifies an interval value of 10. The clipping function in general forces the output to lie between certain values set by the user, Thin, the operation of the ENCODE t40DULE
is to compare the very first absolute word .of an occurrence vector, ~nhich of course is the highest one, with the content loll of ETL and EEL. If the interval value is 0, i.e., it is not des axed to check bet~~aeen different intervals, and if the current entry lies outside of either limit,. the ENCODE
2~i0D'ITLE operation EXIT'S since the value lies outside of the prescribed limits. If, on the other hand, t.ie interval 15 value contained in EIR is oth~:r than 0, th ~ means that it is desfired to check between different limits and the limits contained in ETL and EEL axe reduced to new limits by the interval value in EIR. .Then the comparison between EI and ETL and EEL is repeated using the new 20 reduced limits. It should be n~ted that in the enamp~.e of the ENCODE MODZTLE included herewith, it is only desired to check for increments in a downward direction. Therefore, if. the current ab3olute word contained in EI 3s above ETL, the ENCODE i~iODTJLE operation automatically EXITS eoithout 25~~ decrementing,.
Consider now tire actual clipping and interval function in the ENCODE PZODULE. The 0'ITrPUT r~t7DU'LE sets OPStv flip flop, contained therein, to a 1 state. GThen flip flops Pl-P11 of the control counter 113 are in an 0 state causing true 30 c°ntrol signals at the P~,P~ ... P~1' outputs and the OPSw output _91_ O
lI~ has a true signal, tLle neat clock causes the Pl flip flop to be set to a 1 utate. During EBS2, the control ~;x~l at the P3_ output causes the Zi~DSl and LDS2 selection circuits to couple the content o f ETL and EIP, to ~1LU. I:~ the top limit in ETL
5~i is < the currwnt absolute inord in EI, the current absolute ~JOrd is out of limit and a control signal is formed at the L output of ALU and at the following clock pulse at C , the ECE
flip flop is reset to 0, disabling the cloclc to the control counter 113, resetting counter 113 to 0, causing the I~ E~1CODE I~iODtJhE to E~TT and f icing one-shot EI~TE'i~ .
If the top limit in ETL is ~ the cuxrent absolute word in ET, a control signal is foamed at the GE output of the OIt gate 108. A true signal is also being formed at the P1 output and the combination of true signals at P1 and GE
15I~ causes the P2 flip flop to bs set to a ;ll state, thereby causing EB3 to be entered.
During EB3, the content of EBL is compared with the content of E1. To this and, the true signal at P2 causes EDS1 and EDS2 to couple the content of EBL and EAR to ALtl.
If the bottom limit in EBL is > the current absolute word in E~, a control signal is formed at the G output of ALU and EB4 is entered. 7Cf, on the other hand, the bottom limit in EBL is ~, the current absolute ~3ord in EI gate 110 forms a control signal at LE, causing EB6 to be entered. The operation 25~~ follo~aix~g EB6 is the same as that described above and need not be reconsidered here.
I~owever, assume that the bottom 'limit in EEL is greater than the current absolute word in EI and a control signal is farmed at the G output, causing EB4 to be entered. EB4 is only shown in the ENCODE P~IODULE flow in order to indicate that -92_ 1 a dec~.sion iJ made based on cnhether the interval value contained in ETf, is 0 or ~ Q. lf, at the time, true signals are formed at P2 and G, the content of 'E TI: i: not 0, a control signal is formed at the 'E-o output o~ EIT°,. The true signal at ~ in coincidence with the control signal at P2 and G.enables the P3 flip flop to be set to a 1 state at the follc~ing clock signal from gate 112, thereby enter ing EBS.
)During EBS, the top.limit in ETL.and.bottom limit in EBL
are decremented by the interval value contained in EIR. To loll this end, a true signal is now formed at the P3 output, causing EDS1 and F~S2 to couple the values contained in EBL
and EIR ~to the input of ALU, thereby causing ALU to form a decremented bottom limit correspanding to the difference (i (EBL - EIR). The true signal at P3 also causes EDS~ to couple the decremented bottom limit at OP to the input of EBL.
The subsequent signal at'c:auses the load logic of EBL to store the decremented bottom limit into EBL, Thus, EBL
now contains the previous bottom limit value decremented by the interval value contained in EIR. The true signal at the P3 output causes the PcE flip flop to be set to a 1 state at the follc~ing cloclt signal from gate 112, The control signal at P4 causes EDS1 and EDS2 to couple the content of'the top limit in ETL and the interval value in E~.t, to ALU, causing ALU to form a decremented top limit at OP
representing the difference (ETL - E1R). The, control signal at the P~. output causes EDSS to couple the decremented top limit from OP to ETL and the following signal at G~IC causes the decremented top limit to be stored in ETL. Thus, ETL
now contains the previous top limit value decremented by the interval value contained in E ~;, EB2 and EB3 are again ---, II
ll~ entered where the input value is again compared, this time with the decremented top and decxemented bottom limit values as described hereinabove.
n D.Example of Operation A better understanding of the operation of the ENCODE
bit7DULE c~J311 be had mith reference to the folloz~ing ENCODE
~20D~TiaE example. During this example, it is assumed that the ENCODE t~~ODULE is called six times to convert the following 101 input entries from one occurrence veetor and coded in absolute form to hybrid forms 125, 123, 119, 116, 114, 100.
To further aid in understandins of the invention, it is assumed that no clipping is to take place. Although the clipping fuxaction is an important feature in one aspect of the invention. !father than' giv~ a :~~omplete word description nf. the following operation, the operation is indieated in symbolie form. ' r. <,~ ~.
1 Input on the inztial call>
OPStd = 0 ; , ETL = EBL = EIR = ~S
EFRST = 1.; Era = 128 EI = 125 The sequence follorued is;

E EB6, EB8 - EB9, EB19 - EB20 B1, EB1 i ~~~~~~ ~- 0 s. control~o~s~J to EB

EB~ a E~R~~ ~ ~ .. controlgoe'~J to EB8 E : EI (125) ~ EHW (128,The input is less than the iso-es~tra-P~-c~Jram caidth. Therefore, control. goes to EB9;

EB9 : EE3.tST = ELEfST reset flip flops;
= 0 P~pO = 0 clear number of occurrences;

'~R3 = i~ILN3 = 0 clear output memory area address o register and length register;

EB19 s ER g 0 indicates there are no remaining bits left in output register E0P -I3ere used to force an absolute ones index form (AOI) output on the. next call;

BSW = 0 indicates coe are in absolute ones index form;

Z~
EB20 : E0(125) = EI(125) current input becomes previous input;
NOC(1) = NOG(0) + 1 up the number, of occurrences by one;
30~) ALT

l~l Output: EOP = 0 MLN3 = 0 NOC = 1 Memory area blank Second call: EI = 12~
E:ERST = 0 Other parameters remain as for first call;
Sequence of control: EB1, EB6-EB7, EB10-EB13, EB15-EB1S, - EB21-EB24, EB23y EB25-EB26, EB20 EBl OPSW = 0 .", control to EB6 EB6 EFRST = 0 .'. control to EB7 EB7 ELAST = 0 .'. control to EB10 EB10 ET(2) = EO(125) - ET(123) bit distance between previous and absolute word;
set. t1/D = 1 .'. CTR to count down ' EB11 ER(0') - ET(2) C 0 the current absolute word cannot be placed in the remaining number of bits in EOP :. control to EB12;
EB12 1ET = -2 kept in 2's,complement form; i.e., 1ET = x,1111110;
CTR (0) = ER (0) the amount the output register must be shifted; if in bit string form, to keep alignment; .
EB13 CTR = 0 .'. control to EB15 EB15 BSW = 0 .'. control to EB16 ~~~ E816 EOP(125) - ED(125) , set output equal to previous input -gs_ r /~v !
1 MSB (EOP) = 1 set sign bit to indicate absolute word form (AOI) ;
EB17 Memory write of EOP .
MAR3(1) = MAR3(~) + 1 pointer to next memory area address;
MLN3(1) = M1,N3(0) +.l current physical length of output;
EB18 ET(-2) ~- 7 > 0 0. control to EB21 gp EB21 Set counter to count-up since the number to be clocked TJ/D = ~ to CTR is < 0, must count up to reach 0;
EB22 ER(5) ~ ET(-2) + 7 number of remaining bits that can be used in EOP;
y5 CTR(6)~- ET(-2) the counter is loaded from the rightmost 3 bits of the 2°s complement of -2, i.e. 1111 10 EB23 CTR(7) = CTR(6) ~ 1 (~~):"control to EB2G
EB24 EOP = 0~0~ ~ shaft EOP xight;
20 EB23 CTR(0) ~ CTR(7) + 1 (=0) ,',control to EB25 since CTR is 3 bit register, adding a 1 to the.7 causes wraparound to occur;
EB25 EOP = 10000000 turn on sign bit;
~5 BSW = 1 ~ indicates bit string form;
EB26 EOP = O10'YX:~uC shift E0P right one since sign bit position is used to indicate types _97_ .~ v 1 EB20 E0(123) = EI(123) current absolute word becomes previous IVOC(2) = NOC(1) + 1 number of occurrences is bumped;
IiA LT
Memory Area Output EOP ~ OIOX.~X.~CX MLN3 = 1 NOC ~ 2 11111101 ~ = remaining bits to be used Third Call EI ~ 119 other parameters remain the same;
, Sequence control EBI, EBS-EB7, EB10-EB11, EB22-EB24, of i0 EB23-EB24, EB23-24, EB23, EB25-EB2~, , EB1 OPSW 0 .'. controlto EB6 =

EBV ESRST ~ o .o controlt~ EB/

EB7 EL~sT ~ o :, controlto EBIo 1S EB10 ET(~+)~ EO(123) - EI(119) ET ~ bit distanee to be cons ida~red;

EBll ER(S) - ET(~) > control to EB22 EB22 ER(1) ~ ER(S) -ET(4) ER
~ number of bits left in E4P after current absolute word process;

CTR(4)~ ET(4) number o positions EOP must be right shifted before the sign bit is set; , EB23 CTR(3)~--CTR(4) (~0) ~ control to EB24 -EBZ4 EoP 0olo~x xS EB23 CTR(2~-CTR(3) (~~) o~~ control to EB24 ~

EB24 EOP OOOIO.~R ' =

EB23 CTR(1)= CTR(2) (~0) ~A~a control to EB24 EB24 EOP OOOOIOX;~
=

EB23 CTR(0)= CTR(1) (=0) ,', control to EB25 _gg_ 1 EB25 EOP = 100010X.Y set on the most significant bit;
BSW = 1 indicate bit string;
EB26 EOP = 0100010X shift E0P right;
EB20 E0(119) = EZ(11~) current absolute word becomes previous N0C(3,~°NOC(2j + 1 bump the number of occurrences;
HALT ' Memory Area OUT E0P a 0100010X MLN3 = 1 N0C = 3 11111101 Fourth Call E1~ ~ 116 All other parameters remain the same;
Sequence of control EB1, EB6-EB7, EB10-EB14,_EB13, EB15, EB17-EB18, EB21-EB24, EB23 EB25-EB26, EB?.0;
EBI, EB6, EB7 same as be:~ore;
EB10 ET(3~j t- EO(119) - E1 (116) obtaatn bit distance;
E Bll ER(1) - ET(3) (< Oj there are not enough bits to eontrol to EB12 process this entry using . current information in EOP;
20 EB12 ET(-2)~-- ER(1) - ET(3) ET = 11111110 in 2ss complemen t form;
CTR(1)~-- ER(1) number of posit3.ons that EOP must be shifted to keep alignment;
EB13 CTR(1) ~ 0~ a o control to EB 14 25 EB14 CTR(0) = CTIt(~.) - 1 EOP ~ 00100010 right shift EOP;' EB13 CTR(Oj = 0 .'. control to EB15 EB15 BSW = 1 .". control to EB17 _99_ ,r-\ rw, EB17 write EOP to memory MAR3(2)f-~MAR3(1) 1 next memory address;
+

MLN3(2)~- MLN3(1) 1 physical length of memory area;
+

EB18 ET (-2) + 7 (~ controlto EB21 0),, EB21 set U/D = Vibe. up CTR to count EB22 ER(5) - ET(--2) 7 +

CTR(fi)~-~ ET(-2) CTR = rightmost 3 bits of 2's complement ET = 11111 10;

EB23 CTR(7) - CTR(_6) 1 (~0) ;, control to EB24 +

EB24 EOP = OOXXXXXX shift EOP X = remaining usable bits for EOP;

EB23 CTR(O) - CTR(,7~ 1.(=0) 3 bit register - therefore +

control to EB25 wraparound on the add;

EB25 EOP.= lOXXXXXX set sign bit in EOP;

BSW.= 1 indicate bit string form;

EB26 EOP = OlOXXXXX shift EOP since sign bit . indicates type;

EB20 EO(~116) - EI(116) previous unput is replaced by the current;
NOC ( 4 ) ~-- NOC (.3 ) + 1 HALT
Memory Area Output. EOP = OlOXXXXX MLN2 = 2 NOC = 4 11111101 oolooolo 1 Fifth Call ET = 114 remaining parameters remain the same;

seque nce of control EB1, EB6, EB7, EB10-EB11, EB22-EB24, EB23, EB25-EB25, EB20;

EBl, EB~6, EBB ' same as before;

EB10 ET(2)~-EO(llfi) - EI(114) bit distance;

set the counter t~ .down EB11 ER(5) - ET(2) 0 :, control to EB22 >

EB22 ER(3) = ER(5) ET(2) update the remaining;
-CTR(2)~- ET(2) number of bits;

EB23 CTR(1) ~ CTR(2) - 1 (~0) .p. control. to EB24 EB24 EOP $ OOlOXX3~ shift EOP right;

EB23 CTR(0)E CTR(1) - 1 (~0);,control to EB25 EB2S EOP a IOIO~XIL set s:lgn bit of EOP;

BS4J $ 1 ~ indic:~tte bit string form; .

EB26 EOP = 01010 shift EOP;

EB20 EO(114) ~ E1(114) N0C(5)~---N~C(4)+ 1 20. HALT

' Memory Area Output E0P ~ Ol0I0X~LX 2~IL~'N3 ~ 2' NOC ~ 5 11111101 C~ r 1 II ' Si:~th Call Ez = 100 all other parameters remain the same;
sequence o~ control EB1, EB6-EB7, EB10-EB14, EB13-EB14, EB13-EB14, EB1~, EB15, EB17-EB20;
EB1, EB6, EB7 same as before;
EBlo ET(~.~)~-EO(114) -_ Ez(xoo) set LJ/D ~ 1 ~ ~ CTR to count dorm EBl1 ER(3) - ET'(14) (<0) ,', control to EB12 EB12 ET(-11)t~ ER(~) ~ ET(14) ET in 2as complement form;
CTR(3) ~ ER(3) number of positions EOP must be shifted to keep alignment;
EB13 CT'R($) ~ 0 :. control to EB14 EB14 CTR(2) ~ CTR(3)~ - 1 E~~ ~ 0ololoxx EB1~ CTR(2) ~ ~ a. control to EB14 EBl4 CTR(1) ~ CTR(2) - 1 Eor ~ oooloio~
EB13 CT'R(1) ~ 0 :, control to EB14 EBl4 Cl°R(0) ~ CTR(i) - 1 E~1' ~ 00001014 EB13 CTR(0) ~ 0 0 . control to EB15 EB15 BSW ~ 1 ;e control to EB17 2~ EB17 write memory ~EOP
M,AR3 (3) ~ MAR3 (2) + 1 M~1V3 (3) = M~,N3 (3) ~- 1 ~.~ ~~! ~~~.
1 EB18 ET(~11) 'I- 7 < 0 0. control to EBl9 EB19 ER = 0 assure next call will carne;
0 current absolute word to be in absolute word form;
s EB2o Eo(loo) = Ez(loo) rroc(6)~z~oc(5) ~a- 1 I~IA LT
~,0 Memory area Output 0 MLN = NOC = 6 11111101 =

~ set ELAST
eventh = 1 all call other parameters remain ~,5 the same;

sequence ration EBI,.EB6-EB7, EB27, EBl3, of ope EB15-EB20;

EBl, EB6 same as before;

EB7 ELAST = ;,control to EB27 2~ EB27 cTT~~O' ER(O) in case we are in bit string;
=

ET ~ -8 assure proper balance at EB18;

EB13 CTlt(0) 0 0 , controlto EB15 =

EB15 BSt~I ~ ,", controlto EBl6 ~

25 EB16 EOP(100) ~ E0(100) prepare the output;

set sign bit of EOP indicates absolute wo~=~ types EB17 write EOP

M~1R3 (4 MAR3 (3 1 next addre s s ;
) ) 'I-MLN3(4) MLN3(4) 1 length;
+

-1.~D3-~..1.~''~''~ i ~B~.s ~T(-~) -f- ~ ~' 0 ~ ~ COntx01 to ~8~.~
BB19 BlZ = 0 these are meaningless BSaI = 0 steps on the last time EB20 BO(100) = EI(100) through - note that NaC
is not incremented this tine;
IAA LT
Memory area ~o~ = o M~N3 = ~ Noc = 6 lllxllol 000010x0 xxxooxoo xs i ~

ii In summary, w!iaL has been disci osed is an encoder for converting to hybrid iorr~ a received series of absolute chord signa7.s of decreasing value order, The hybrid form has a series of at least one absolute ~nord signal and bit string e~aord signals An absolute chord signal represents the value of one occurrence by tl~~ combination oL binary coded bit signals. A bit string word signal represents one occurrence by the number of bits of_d isplacement of ,a .bit of predetermined value therein from an absolute caord signal in the hybrid 10~~ 4'ord series. Means include the ALU, EDS2, X351 and control counter 113 operative during EB13 in response to received previous and current absolute word signals for forming an output signal and icative of the difference in value therebeteueen. The previous and current different signal is 15 ~~ formed at the OP output of AL'CP and is stored in ET.
Additionally, there is mer ns including 'ET and the control counter 113 for retaining the previous and current difference signal. This occurs at EB10..
The encoder also includes means for indicating 20 absolute or bit string word form of hybrid output and includes means, including the switches 104, for indicating a preselected minimum permitted difference (e;gp 7) between successively received word signals. Such means includes ALU, F~S1, EDS2 and the control counter 113 for 25 comparing the minimum difference indication and the retained previous and current difference signal and for indicating the f first beings than or ~. to the latter The encoder also has means an r providing absolute form outputs such means including the ~P load and shift logic, the BStd and its set and reset logic and the control counter 113 <>
a2 z r ~'7a 1 ~I operati_ve in respon se t:o the .~ indication for outputting the stored current absolute t~~ord and an absolute flag. This operation takes place durzng ES18-20, l_0-17.
The encoder also incl u~ae ~ r~eanu for providing bit S ~~ s trip ; form outputs and has means a.ncluding the EOP, CTP, and its load and control logic, EDS2, EP,, EOP siiift 'Logic, 2~iSB set logic and the control counter 113 tuhich are responsive to tae ~ indication for forming a set of ordered signals comprising a binary bit of one value ~e.g.~, 1) associated ~~ith the number of binary bits of a second value (e.g., 0) corresponding to the value of the retained previous and current difference signal. It w ill be seen that the operation is depicted by E1321-25. The means for providing bit string form outputs also includes means including the clocle and 1S the control counter 113 for selectively outputting the set of signa~a in association with. a bit string flag. The binary bit of one value in the bit string form output is in a predetermined relation to the outputted absolute word.
In this regard, the number pf bits of displacement between ZO a bit of the ono value arcl an absolute word indicates the value ~f the one bit.
A preferred embodiment of the enc~der has a current such as register EI for storing a currently received absolute cuord. Means including L'DSC~ control logic stores received absolute words into the current register EI. A previous register E0 is provided for storing a previously received absolute word. Means including the EO control logic and the control counter 113 tranufers the current absolute tnord from the current register to the previous register, forming 5011 therein the previous absolute wordo Th3.~, is accomplished at EB20.

112'7"d'79.
1~~ I1 further prererred embodiment o~ the encoder provides hybrid form output in a series of ~nords. The means for forming a set of ordered signa~.s includes counter means CTh.
CTr~ has output Ca :; or indicating completion of counting.
bit Jtring word for .Zing register EOP is provided and means including CTI: load and control logic and EDS2 is operative during EB21-2~E in response to the ,' indication for enabling the counter. means to count through a sequence o~ states corresponding in number t~ the retained current 10~~ and previous difference signal contained in ET, TIae indication at output Co from CTR indicates completion o~ the last-mentioned counting, Additionally included is means including EOP and its shift logic and control counter 113 operative during EI~21-25 for l shifting tine content of the bit string forming register one bit position in the direction o~ the most significant bit thereof for each of the last.-mentioned counter means states.
Additionally included is means including the r~SB flip flop and its set logic and the control counter 113 which is operative during EE25 in response to the last-mentioned completion indication at Co for inserting a binary bit signal of predetermined value (e, g., 1J at the least significant end o~ the content of the bit storing register E0, Ey this means, occurrence is entered in the hybrid form word output. The means for outputting add itionally comprises means including the P9 logic and the control counter 113 operative during EE17 for selectively outputting thecontent of the bit string raord forming re sister by forming a signal at the P9 output, indicating that the word'in EOP is now II ready :Cor output.

~3 -., 1~ An additional preferred embodiment of the encoder, according to the invention, is a bit string forming means which has means for entering a first occurrence in a neco bit string r~ord under .formation. Included in the last-mentioned means is means (EP,) for storing a signal representing the number of binary bits remaining to be filled in the bit string word forming register EOP, Also included is combining means including the ALU, EDS1, EDS2 and the control counter 113 operative during EB11 for forming a signal representing the difference between the values of the remaining number of binary bit to be filled signal and the previous and current difference signal. Add itionally included is means including the ALU, EDS1, EDS 2 and gates 108 a~ 110, and the control counter 1_13 operative during EB11 for comparing the values of the 15 Previous and current difference signal and the remaining binary bits to be filled signal for indicating that the value of the first signal is .'~ (GE) tfxan or < (L) than the latter signal. Additionally included is means including ET, EDS7 and the control counter 113 operative during EB12 in response to the ~ than indication at L for retaining the difference signal, in ET from the combining means as the number of bits needed in the next b it string word to enter a current absolute word.
Nfeans including the CTR load and control logic and EDS2 is operative during EB11, 22-2~E in response to the than indication at GE for enabling the counter means to count through a sequence of states corresponding in number to the retained number of bits needed in the next b it string word signal contained in ET. It should be noted that the 30 foregoing operation occurs when, during EB11, the retained s ~.2'~l ~"~''~.
1 number of bits needed in the next bit string caord contained in ER is ~ than the previous and current difference signal contained in ET. Also included is the 1;0P shift control logic, the control counter 113 for shifting the content of the bit string forming register EOP one bit position in the direction of themost significant bit contained therein for each of the last mentioned counter means states.
I~2eans including rzSB and its set logic and. the control counter 113 axe operative during EB2S responsive to the completion signal at Co for inserting bit signal of predetermined value (e.g., 1) at the least significant end of the content of the bit string register EOP.
A further preferred embodiment of the encoder has a bit string forming means which includes means f or filling out the bits of a bit string word being formed when no further occurrences can be entered therein. Included therein is means ER for storing a signal representing the number of binary bats remaining to be filled in the bit string word being formed. Combining means including ALtJ' 2~I EDS1, EDS2 and the control counter 113 is operative during EB11 for forming a signal representing the differences between the value of the remaining number of binar y bits to be filled signal, contained in ER, and the previous and current difference signal, contained in ET. Additionally, 25 there 3.s means including ALU, EDSI, EDS2, gates 108 and 110 and the control counter 113 operative during EB11 for comparing the value of the previous and current difference signal and the remaining binary bits to be filled signal-for indicating that the first is j than 4r ~, than the latter.

~a r~
1 rieans includ ing t~~c~ CTR load and control logic EDS aril EDS2 is operative during E1;12-14 'n response to the L. than indication for enabling the counter means CTi; to count through a sequence of states corresponding in number to that indicated by tte value of the stored remaining binary bits to be filled signal contained in ER, Also included is means including the EOP shift control. logic, the control counter 113 operative during EB13-14. for shifting the content of the bit string forming register EOP one bit position in the direction of the most significant bit thereof for each of the last mentioned counter means states.
According to a preferred embodiment of the encoder, clipping means is pro vided. included then ein is means including ETL and EBL for storing an upper limit value and 1~ a lower limit value. Means including A',LU, EDS1, EDS2 and gates 108 and 110 are operative during ~:~2-4 for comparing a current absolute coord with the upper and lower limit values and for indicating if i.t is out of the bounds defined by the limit values, According to a further preferred embodiment of the encoder, an interval adjusting means is provided along with the clipping means. Tncluded is means E IR fox storing an interval value, Means including the ALU, ~Sl, EDS 2, EDS5, gates 108 and 110,andcontrol counter 113 is operative during EB5 in response to the indication that,the current absolute taord is out of bounds for incrementally chatnging the stored upper and lower limit values in EBL and ETL
by the stored irt erval value in EIR. In the specific exempla shown, the incrementa'.l changing is a dec~ementing action.
AJ. so incl~.rded :l~ means for. anablin~; the comparxn~; means to rw repeat the comparing, using the incrementally changed upper and lower limit values and current absolute word.
III. DECODE I MODULE
A. General 'D'e's'cription Th.e DECODE I and II MODULES are internally similar.
The difference lies mainly in the input arAd output signals.
This section is devoted to th.e DECODE I MODULE. The next section will discuss th.e differences in the DECODE II MODULE.
The purpose of the DECODE I MODULE is to convert to absolute word form a series of received occurrences in a hybrid word. The occurrences are of decreasing value and are coded in hybrid form. Thus, th.e DECODE I MODULE converts information in th.e opposite direction from that of the ENCODE MODULE. Th.e hybrid coded form comprises a series of binary code words, including at least one absolute coded word followed by one or more bit string words and/or absolute words. Each absolute word represents an occurrence directly in coded form. Each. bit string word represents an occurrence by the number of bits of displacement of a bit of a predetermined value from either an absolute word or another one of such bits of predetermined value in the series of hybrid words.
Additionally , each hybrid word h.as a flag indicating whether it is an absolute or bit string type of word.
the DECODE I. MODULE operates in response to a call by a calling module. Th.e possible calling modules for the DECODE
I MODULE are: PIPE, SEED, REVOLVE, HRLGHTNESS, OUTPUT MODULES
and the DPM INTERFACE MODULE. In general terms, the DECODE I
MODULE decodes a hybrid word by reading it from the MEMORY MODULE
and if the flag bit indicates th.e word is an absolute word, L. l the DECODE I MODULE outputs the word, passing it directly to the calling module. The DECODE I MODULE saves the absolute word which has been outputted and then reads another hybrid word from the MEMORY MODULE. If the flag bit indicates that the new word is a bit string word, then the~bit string word is stored in a shift register and shifted until a "1"
bit (bit of predetermined value) is shifted out of the register.
With every shift, the previous absolute word value is counted down and each time a °'1'° bit is shifted out of the l~l~ shift register, the state of the counter is outputted as the absolute word.
B. Co_ mponents The DECODE I MODULE includes counters MARL, MLN1, DO1, and BCTR1. Counter MAR1 is a 256 state counter of type ~SN74161 in the above TTL book. Counter MLN1 is formed of an SN74191 type counter disclosed at page 417 of the above TTL
hook and counts up responsive to each true signal applied at the Ct input. The MLNl counter is also set to a state corresponding to the input signals applied at its upper side responsive to a true signal at the L or load input. Internal gating (not shown) forms a true signal at Mo when the MLNl counter is at state 0. Counter BCTR is an 8 state counter.
Counter DO1 is an 8 bit 128 state counter. Both counters BCTR and DOl are formed of an SN74191 type counter disclosed at page 427 of the above TTL book. These counters operate as follows: a true signal at the CLR input resets the counters to state 0, a true signal at the L input causes the counters to be set to a state represented by the information input 3~

\ l 1~~ signals applied at its upper input. Each true signal at the Ct input causes the counter to count up one state. Counter BCTP, has logic (not shown) for forming a true output signal at Bo and Bo when the counter is at state 0 and not at state 0, 5~~ respectively.
Also inc?.uded in the DECODE I MODULE is an INRI regis ter.
Contained therein is a shift register 202. The shift register 202 is a 7 binary bit storage register formed ofthe type SN7Z~199 disclosed at page 456 of the above T'fL book.
The DECODE I MODULE also includes flip flops P1 through P5, forming a control. counter 213, acrd flap flops D1FST, E0F1, D1SV1, D1END, MSB1, S1FF and DCE. Each of these flip flops is formed of type SN74.74 disclosed herein in section z.F, Conventions Used in the Figures, loll One-shot mufti-vibrators D1G0, DlD:IEND are also provided, Each of these one-shot mufti-vibrators is characterixed whereby a true signal applied at its input causes the indicated output to receive a true signal for a time period equal in length to the time period between the~beginning of~one clock pulse and the beginning of the next clock pulse at CL.K.
The DECODE I MODULE includes a source of equally spaced recurring clock pulses 240.
T'he DECODE I ~20DULE a3.so includes the necessary logic to control the various registers, flip flops and counters 2~ as indicated by logical equations using the notation indicated hereinabove with respect to the ENCODE biODULE. In addition, specific AND gates 216, 218, 220, 222 are shown and OF gates 224, 226, 228, 230, 23h and 235 are shown. The AND gates 218, 220, and 222 are actually indicated,schematically and 3011 comprise eight, individual AND gates (not shown) for gating o ~ 3. ~ ~'"l'~, eisht bits of information through to the corresponding outputs from the indicated source of information along the heavy line inputs. The second input to each of the eight lIND gates wiW in nrm ~ate~ 21.3, 220 and 222 is connected 5~~ to the indicated control. logic indicated by logical equations.
The output of the Ar7D gates within sash of the AND gates 218, 220 and 222 are 0F,'d together by the 0P, gate 22& and provided as an eight binary bit information input to the MLNI counter. - ..
1~~~ The rest of the AND and OR gates are also conventional gates well known in the computer art and need no further explanation other than that provided in the following detailed description.
The output of AND gate 216 is indicated by the symbol CLIr correspond ing to clock. The output of an inverter 232 is indicated by the symbol ~~"I~ corresponding to the logical 3n~erse of the clock signal. C'LK similaa to the ENCODE MODULE, The required input and output control lines to the DECODE I MODULE are indicated along the right hand side of 2~ Fig. 9; also indicated along the right hand side of Fig. 9 sacs the information input and output circuits using the system of notation described hereinabove.
Referr~.ng to the right hand side of the DECODE I MODULE
f ig ure , the informs Lion input s to the DECODE I MODULE are 25 shown in heavy lanes and are LN1 from IPRF, MLN3 from the ENCODE MODUi.E and ORT2 from the OUTPUT MODULE. The output from the DECODE T MODULE is from the D~1 counter (heavy line), the EOF1 output of the EOF1 flip flop, the D1MEND output of the one-shot mufti-vibrator DlriCND, and ~~ the output of a gate represented by the logical equation P2'DISId.

1~~ The information output from the Dol counter is the absolute words that have been decoded from hybrid form, Th a signal.
at DlstEf~D indicates the completion of each re: ui.tant absolute word in the Do 1 counter, thereby indicating to the $ calling module that it can read the absolute word ~crom D ol.
A txue_signal at the EOrl output indicates that the number c~f hybrid words, and hence the length of the memory area, indicated by the words stored in the t~Nl counter, have been.
converted and therefore th~ hybrid occurrence vector has been completely decoded.
C. Detailed Description Table 13 gives the symbols for the important counters, registers and flip flops in the DECODE I 1~TODULE of Figs. 9 15~~ and 10 and indicates the lengvth thereof:; and the primary output of the DECODE I T~IODULE. Table 11 shows the primary inputs. Fig. 11 is a flow chart indicating the sequence of operation of the DECODE I MODULE using similar notation to that described hereinabove with respact to the ENCODE r~ODUL~E, 20 Eeference to the DECODE I i20DULE flow diagram should be made in read ing the following description to a~Ld in a complete understanding of the present invention.
Similar to the ENCODE brD~JLE, the Oh gate 234 is responsive to an initial signal applied at MTNIT by the 25 MINI C02~~.'TJTER to apply a true signal to the resetting input of each of the flip flops Pl-P5, resetting them to 0. Also, OIt gate 235 responds to the MINIT signal for initially resetting the DCE flip flop to 0.
The DECODE I 2~10DULE, as mentioned above, is called 30 by any one of the following modules: PIPS, SEED, REVOLV.C, II
~ ~BRIGH'L~dE~S, OtTrPUT and INTERI'11C1;. The MINI COMPUTER' as later described throuh the DPI IrlTErr~'1CE IiODULE or one of the other modules stores into one area of Lhe hWiiOP,Y rA0DUL1; a hybrid coded occurrence vector. This hybrid coded.occurrence vector is SII to be converted to abso7.ute coded occurrence cuords usinb the DECODE I MODULE and/or DECODE II IMODULE) . A callin; module initializes the DECODE 7t i~iODULE by placing the number of words (length) of the hybrid form occurrence vector to be converted into the MLNI counter and by setting the D1FST flip lOII ~lop to a 1 state, indicating that the fixst call to the DECODE T MODULE is occurring.
The length o~ ttze occurrence vector is provided to the DECODE T Z~DDULE ~:~,om different sources according to the palling module as follows: P:CPE MODULE - LNl from IPRF;
15 II SEED MODULE - LI~1 . from IPRF; RE~i'OLVG PdODULE - MLN3 counter from ENCODE PIODULE; EIiI(~-ITNESS t-iODULE - LN1 from IPRF;
OUTPUT MODULh - LN1 from IPRF or ORT2 register in OUTPUT
I~T3I1LE; (~1ANC~E MC~ULE - 3311 frcan IPk~'; RE'ACE ~ - IN1 from IPRF.
loading MLNl is as follows; a true signal applied by the ouTPUT riODULE at Ob216 or OM17 causes AND gates 218 and 222 and OR gate 226 to couple the length value from LNl of IPP,F
and ORT2, respectively, to the inform-a.tion input of the MLN1 counter, The CHANGE fiiODtTLE loads the rILNl counter and the SEED MODULE calls the DECODE I PiODULEo To this end, Z$ the CHANGE fiiODUL.E applies a true signal at the CM4.output, causing the AND gate 218 and the OR gate 226 to couple the length value from LNl of IPP,F to the information input of the MLNI counter. The SEED MODULE applies a true signal at the Sri2 output which causes the A~ gate 218 and OR gate 226 to coup7.e the lenuth of occurrence value~from LNl of TPRF to n Lhe inFormation input o.f she ulLNl. counter. The hEVOLVE
2RODULE a;ap".! ies a true ,signal at r,:~J_4 to cause gates 220 and 226 to couple the 3.en~th of occurrence value from counter MLN3 of the ENCODE MODULE to 'the infor_raation input of counter I-iLNI, 3 0rie of the REVOLVE, SEED, OUTPUT, PIPE, BRIGHTNESS; and DPM
INTERFACE MODULES then sets the D1FST flip flop to a 1 state via OR gate 228 by applying a true signal, respectively, at the corres-ponding output P11, RM2, SM4, B3, OM21, and D1I which, as indicated above, indicates that the first call of the DECODE T MODULE is occurring.
Subsequently, the jailing module triggers the D1G0 one-shot r~ulti-vibrator, causing it to apply a control pulse at its D1G0 output. D1G0 is triggered by the gate 230 e~hich receives its control pulse from one of outputs P7.3, StZ6, I~ ~'Z~~ ~ D~ ~ and D1G0.
A true signal at output D1G0 sets ~;he DCE flip flop to a 1 state, causing a true signal at the DCE output which, in turn, enables AND gate 21~ to couple cloclc signals from the cloclc 240 to the CDI~ outputs Similar to the ENCODE MODULE, the inverter 232 forms the logical inverse of the cloclc fora:dd at CLI: at 3,ts output at CLK.
Since all of the flip flops of the control counter 213 are initially reset to zer~, true signals are noto formed at the outputs P~, P2, P3, P~ and ~5 and the cloclc pulse at CL1:
~3,I causes flip flap P1 to be set to a 1 state and D1131 of the DECODE floea is entered, During D1B1, the state of the D1FST flip flop is checlced, assuming that this is the first call an the DECODE Z 1~iODULE, The D1FST flip flop is in a 1 state, causing a true signal. at 30 the D1FST output. Add itional_ly, the Pl ~1ip flop is in a -~Z17-<~
fl 1 1 Mate. Accordi.n~,ly, D11;2 of tile D%:CODh I P~20DUL1; ~l.ow is entered ~~ahere i:he true signals at Pl, DIrST and CLI: cause the D 1SW flip flop to be reset to a 0 state. The clock pulse at CLI: in co:nl~ax~.ttd.on with the true signals at the P1 and 5II D1FST outputs causes each of the D IEND, D1FST and EOFl flip flops to be reset to an 0 state and cause the I~2~AR1 and BCTR1 counters to be reset to an 0 state. Additionally, the clocl: at CLK in coincidence with the true signal at output P1 causes flip flop P2 to be set to a 1 state and 10~~ flip flop P1 is reset to an 0 state.
The D1FST, EOFI, D1S4J and D9.END flip flops have been reset at this time for the follow ing reasons. The D1FST
flip flop is reset at this time to indicate that the resetting operat~n during D7.B2 has been completed. This is the only function of the D:LFST flip flop. EOF 1 is reset at this time to indicate that the hybrid words in the occurrence vector have not bean completely converted.
The DI.S~~1 flip fl~p is used to indicate within the DECODE I
MODULE that a DIC2~20I;Y MODULE read is neees sary. The 0 state of the D1SZ~3 flip flop indicates that a read from ME1~20RY MODULE
zo is necessary to obtain a hybr3.d ~~aord. This will subsequently talce place during D1BS. A 1 state of the DISt~J flip flop is used to indicate that a read is unnecessary and, as will be eg;plained subsequently, D1B5 is slsipped ~ohen DIStJ is in a 1 state. The DIED flip flop is an internal flip flop and, when set into a 1 state, indicates to the DECODE ~ MODULE
that after conversion of a hybrid coded occurrence vector the last absolute e~ord has been outputted or passed to the ca?.ling module. To be e~;plained in more detail, when the DIEND flip flop is set to a 1 state, any'subsequent call on the ao DECODE I tMODULE by the ca' link; rnodul.e ~.oi.ll force the DECODE I
-ms-( 1 /
PtODULE to form an end of file indica::ion by setting the EOI°1 flip flop to a 1 state.
~'ol7.ocoing D1B2, D1B3 is entered. During D1T33, the P2 flip flop is in a 1 state and the DJ_EITl7 flap flop is 5!I checked. If during D~_B3 the D1END flip flop is in a 1 state, which, as discussed above, occurs c~ahen the calling module provides the last r~~ord of a hybrid occurrence vector, D11319 of the DECODE I l~iODLILE flow is entered.
The action of the cloclc suspension Logic should nova be noted, The true signals at P2, D1E1'~D and CLK reset the DO1 counter to 0 and cause the clock suspension logic 222 to forts a true signal at the 0R gate 23S causing it to reset ~ the DCE flip flop to 0 and trigger the one-shot D12~~~ID.
Resetting o,f the DCE flip flop to an 0 state removes the 15 true signal at output DCE and causes the AND gate 2~.6 to remove the cloclc signals at: CLK, thereby causing .the DECODE I MODITt.~ operation to EXIT and await the next call on the DECODE I ?MODULE. The one~shot DIhZEND then Forms a true signal at output D1Z~~I~ which causes OR gate 23~~ to reset flip flops P~.~PS to 0~ The subsequent opexatLon caused by the D1END flip flop being in a 1 state will be further described hereinafter .
The above action of the cloclc suspension logic 222 is important aril should be kept in mind as a similar action is 25 enabled by th a clock suspension logic when any one of the other logic conditions indicated for bhe cloclc suspension logic 222 becomes true.
Assume that during D1B3 the last word of a hybrid occurrence vector has not been provided, and the D1E1VD flip flop 1I is in an 0 state, causing a true signal at the D .E ~ output.

C~ n 1 DID~f is entered tahere the state o:c the DlStJ flip flop is checl:ecl, It ~.ail1 be recalled that the D1SVJ flip fl op in a 1 state 3.ndicates that the 1~IE:IOP.Y r~IODUi..E read operation is to be skipped, vahereas i:C in an 0 state, causes a ~~ICUiOI;Y
P~iODLILE read. Assume that the DJ.St7 flip flop is. in an 0 stag, D1D5 is entered where the me~~ory read actually talces place.
An input to the DECODE 1 ~~iODULE is the SZ~I10 output of the SEED t~iODULE, To be s~:p'! ained in more, detail, the SEED
TiODULE uses the DECODE T DiODIJLE vahen computing the number of lines to be skipped in an iso-entropicgram. Hovaever, the SEED PiODULE when computing the lines to be skipped, does not require the length value ~.r~ counter MLN1 to be decremented.
Accordingly, the SEED MODULE normally forms a true signal at output SM10 but ~cemoves the true signal. when computing the number of lines to be slcipped, thereby inhibiting counter r~ILNI
from being decremented.
glowever, for the present description, assume that a true signal is formed at S1~~I10. True signals are also formed at P2 and . Therefore the 2~TLN1 counter receives a true signal at its Gt input, causing riLNl to be counted down one state reflecting the fact the one word of the hybrid occurrence vector is being read from the MEMORY MODt.II~. The logic p2''C"~f: being true causes a true signal at the Ct input of riAP,l, cau3ing P~iARl to be counted up one state, reflecting the fact that the next eaord of the hybrid occurrence vector is to be addressed in the r:~~ioTtY rlODDLE, The true signals at P2 and DTS~~I cause a true signal to be formed at the Dulll output of the DECODE I riODULE, thereby signalling the 2TEri0RY Z~iODULE, causing it to road out the content of the proper memory area specified by the ST~JITCII tiATRI~ at the memory location specified in the P-ZAR1 counter prior to its being counted up.

a W
The control sa.;~;nnal. at P2 enables the °~ bit caord read-out of the tltal~IOI;Y i~iODULE to be stored into the INhl reg islet.
The true visnaJ. at P7 causes the most sign:Ificant bit (v bit) of the caozd read _''rom the memory to b° stored in the i~B1 flip f:!op. The true si~,nal at P2 also goes to the S/L input circuit for the shift register 202 causing the remaining 7 bits of the r-~ord i~om the IMEt~ZOr,Y iiODtrLE to be loaded into the re sister 202 cahen the clock signal is applied from logic P2~DlStv1~CLI:. Accordingly, at the end of D1B5 of the DECODE
T P~ODtThE flow a hybrid cJOrd haS been read from the MEP:ORY
DZODULE from the appropriate memory. area and has bean stored in the I~~E;1 register and the T~NI counter has been decxeased by one so that the length of occurrence vector contained therein indicates the remaining words to be read 1~ ~I from the MEtTOP.Y rTODTJLE, Assume now that the word stored in the INRI register is an absolute hybrid word.. ~,t will be recalled that the first word of every hybrid occurrence vector string will always be an absolute word. Z~rhen the t~aord stored in INRl is 20 an absolute word, the flag bit, the most significant bit of the hybrid word, is stored in the 2i.SBl flip flop and causes the IyiSBl flip flop to be in a 1 state. With the r~SI31 flip flop in a 1 state, true signals are formed at the I~SB1 and P2 outputs: Accordingly, the P5 flip flop is set to a 1 state and DIBa is entered, 2~
A true signal is formed at the P5 output 'and the follocaing pulse at C~ causes a true signal at the v input of the D01 counter, causing the 7 bits in the shift register 202 of the TI~Ti:I register to be loaded into the DOl counter. The true s ignal at P5 in eoinc idence with the pul_s'e at ~K enabl es the G n cJ.oclc suspension logic -222 .:o reset the DCZ; flip flop to an 0 stale, therehy d~sabT.~.ng the cJ_oclc at CLh out of the gate 21G and resetting counter 213. An EXIT is t:alcen to a~nait the ne:a call. The ne:,t call is initiated by a control 5II signal, as described above at one o~ the inputs to OR gate 230.
xr, dur5ng the true signal at Z'2 the enord in the IT~I;7.
register read from nenory is a bit string word, the a-ZSBI
flip flop is in an 0 state and true siunals ~.re for:,ed at the i ~' ~ and D~ outputs and the P3 flip flop is set to a ~~ 1 utate, thereby cans ing D1B11 of the DECODE T iMODULE :~lora to be entered.
At the beginning of processing of each bit string word of a hybrid occurrence vector, the JaCTRl counter is in an 0 state having been set there at D1B2. Therefore, during ~,5~~ the first entry into D1B~.I of the DECODir I Z~~0D1TLE flora, the BCTRI counter is in an 0 state. Accordingly, a true signs?
is formed at the Bo output of tine BCTRI counter ,o indicating.
The true signal at 8o in comb3.nat;on with the true signal at P3 pauses the P~F flip flop to be set to a 1 slate and Dl$13 iS entered.
During Db.Bl3, the BCTRI counter iu ~.oaded with a ,ignal.
representing the ma.cimum number oL bits in a hybrid word to be processed. To this end, true signals are now formed at the P~;. and Bo outputv and the following pulse at CLIP causes 2~~~ the L input of the BCTP,l counter to be energized and the value 7, represented by the setting of the switches 23G, is loaded into the BCTP,1 counter, and DIBl~~ is entered.
Dur 3.ng D9.>;lr:. of the DECODE T g20DULaE flow a true s ignal is Lormed at t:he Pas output, l!ccording,ly, the shift register 30~~ 202 is repeatedly shifted one bit to the' right untwl a v:-~e -i22-bit indicating an occurrence is shifted out of register 202 into the S1FF flip flop. Each bit shifted out of the least significant end of the register 202 is stored in the sign flip flop S1FF. During D1B15 of the flow a true signal is formed at the P4 output and the pulse at CLK causes the Ct input of the BCTR1 counter to be energized and count the counter down one state. The same signals cause th.e CT input of the DOl counter to be energized and the counter DO1 to count down one state. For each. right bit shift of the register 202, the number of bits left to be processed in the :CNRl register identified by the state of the BCTR1 counter is counted down one and the absolute word value indicated by the DOl counter is counted down one state. This operat~.on continues until a 1 bit is shifted out of the shift register 202 into the sign flip flop S1FF thereby causing a true signal at th.e S'lFF.output. Th.e state of the DQl cr~unter at this time is an absolute word representing the actual value of the occurrence represented by the 1 b~.t shifted out of register 202 into the S1FF flip flop and acCOrdingly, the state of the DO1 counter is to be outputted to the calling module.
To this end, signals are formed at the P4 and S1FF
outputs and the following signal at CLK causes th.e~DCE
flip flop to be reset to an 0. state and fires the D1MEND
one-shot ,causing a true signal at the D1MEND output signalling the calling module that an absolute word is completed and contained in the DQl counter. The D1MEND signal resets the control countex 213 to 0. Th.e formation of the signal at D1MEND indicates completion of an absolute word and is referred to herein as outputting the absolute word.
Several important special conditions should be noted.

X

If, during the D1B15 and the 1 state of the P4 flip flop, the content of shift register 2Q2 is not 0, it means that there is a remaining 1 bit (representing an occurrence) yet to be converted to absolute form in a bit string word. Accordingly, a true signal is formed by register 202 at 10 causing the D1SW flip flop to be set to a 1 state at the following pulse at CLK. Th.e 1 state of the DlS~ni flip flop is used during th.e following entry into D1B4 of the flow to bypass the reading of another word from the MEMORY MODULE.
Th.e reason for this action is that with the D1SW flip flop in a 1 state, a new hybrid word will not be read from the MEMORY MODULE following D1B14, as there is still at least a portion of a bi.t string word remaining in the shift register 202 to be converted to absalute form.
Referring to D1B17 of th.e flow, whenever the bit string word contained in register 202 of the INR1. register goes to zero by virtue of the fact that all of the 1 bit (or occurrence) of the bit string word has been shifted out thereof, a control signal is formed at the L0 output of the shift register 202. When this occurs another hybrid word must be read from the MEMORY MODULE during D1B5. Awtrue signal is formed at the outputs P4 and IO causing the D1SW
flip flop .to be reset to a 1 state a~t the next pulse at CLK.
The 0 state of the D1S'Hl flip flop, during 'the following entry into D1B4, causes D1B5 of the flow to be next entered where a new hybrid word is read from MEMORY MODULE into the DECODE I
MODULE for~conversion. When the last word of a hybrid occurrence vector has been read from the MEMORY MODULE, the length. of occurrence vector value contained in the MLN1 counter will have been counted down to 0, and a control I
sa.~nal. is formed at the I~Io output of the IiLN1. counter, A true si.~nal_ at I:io and a true signal. at the P5, the P~f and TO outputs causes the D1END flip flop to be set to a 1 state at the neat pulse at ~I', thereby indicating that the last absolute ~nord has been outputted to the calling module, Glith the DlErT,D flip flop in a 1 state, the ioll_owing call on the DECODE I I-ZCDU'LE flow will cause the EOFI flip flop to be set to a 1 state responsive to true signals,at the P2 and DIEi~ outputs at the occurrence of the pulse at CLK.
une further special situation with respect to the DECODE T
MODULE should be noted. If, during the 1 state of the P3 flip flop, the BCTR1 counter is not in an 0 state, then D1$12 and D1I~11 of the flocn are utilized to insure that the proper aligxrnent is made from one b3"t string ~~ord to 2~II another. This is necessary :ahem the last 1 bit of a bit string word has been converted to absolute word form and outputted, and leading 0 bits remain in the bit string word under conversion in thg shift zveg~.ster 202. These leading 0 bits must be ~.leen into account in ~orning the next absolute 20~~ v'°rlt for output.
Rexerring to D1B11 and DlBl2 of the flocs and the corresponding action, a true signal at the P3 output in coincidence caith a true signal at the ho output causes the TiCTPI counter, as well as the DO1 counter, to be counted down 2s one state responsive to each pulse at GLI:, As a result, the absolute word be in; formed in DOl is ad,~usted downward by the number of leading 0's re~aain3.ng in shift register 202 which are indicated by the state of >3CTP,1. Finally, when the I3CTR1 counter reaches an 0 state, a control signal is formed 30 '~t the Bo output and the true si~;na,. is removed at the ~o output. terv~inat3ng 'the counting o:~ the BCTh1 and DO1. counters -i25-C:
~.~~~r~
y anc3 czusin~ D7.i;13 of ttae flo~o to be entered as e:;plained above, D, E;~ample oL Onerat:i.on Consider noco an e~cample of tine operation of the DECODE I
t~iODTlL);, Assume that your caords , matting up a hybrid occurrence vector, are contained in the rieuiory area 1 of the i~~I~IORY 2MOD'ULE
and ~e to be converted from hybrid to absolute word form.
E" t-?PLE
1~ Assume the follotaing is in the memory area 1of the ~-~2i0PY Z~ZODL1LE~
1 1 1 1 1 1 0 1 (125 ) 0 0 1 0 0 0 1 0 (139 llg) 0 0 0 0 1 0 1 0 (116, 11~) 1 1 1 0 0 1 0 0 X100) The phys ical length in vaords is ~~, Therefore it is the calling program's responsibility to load h~11~°-G. arid set the initialize flip flop D1FST to 1.
First call 2~ D1FST ~ 1 sequence of control o. D1B1 - D1B9 D1B1 D1FST ~ 1 .', control to D1B2 D1B2 D1FST = DIEND ~ EOFI ~ D1SS~I ~ 0 reset these flip flops;
t-:~1P.1 a 0, BCTI?1 ~ 0 initialize these rEgisters D1B3 DlEt~ ~ 0 v v control to D1B4 DIBt~ D1 St~J ~ 0 .', control to D1BS

1 D1A5 read memory l.IltO INR1 do the read;

:CNRI = 1!01 the result;
(125) MAR1 (1) TIARI (0) memory address to next = + 1 pOS3.~7.Un;

MLNI (3) MLNI(~E) - decrease the umber of words = ~. n D1B6 ~fiLN1(3) 0 :. control D1B7;
~ to D1B7 MSB( Ii~Rl) l:. control DIB AOI form = to D1B9 Do1 (125) INRl (125) ~inpiat becomes the output;
=

ZO D1SW = 0 assure a read on the BCTIt I = next call and set BCTRl 0 to Zero;

EXIT
output Dol = 125 EOF1 ~ 0 x5 ~
Second call initial condit:Lons: DlF~yT ~ 0 MLNI is not clocked sequence of contral D1B1, D1B3-D1B7, DlBtl, DiBl3-D1B1~, D1B14 ~ D1B17 20 D1B1 D1FST = 0 , ~ contr~~. to D1B3 D1B3 D1END ' ~ ' control to D1B4 a a D1B4 D1SW = 0 ao control to D1B5 D1B5 read memory do the read to INRI;
. INRI a 00100010 25 , ~~l(2) =t~AAR.I(1) + 1 increase address pointer;
ML1V1(2) =MhN1(3) - 1 decrease length register;

~l ....., 1 D1B6 MLN1 ~ 0 :, control D1B7 to D1B7 MSB(IrtR1) = 0 ,'.controlD1B11 to D1B11 BCTf1 - 0 .', control D1B13 to DiBl3 BCTItI = this counter monitors hocu much of the input register remain:, to be processed;

S1FF ~ 0 D1B15 BGTR1(6) BCTFt(7) - 'reduce the number of bits ~ 1 Dol(124) Do1(125) - to be processed & reduce = 1 D1SW m 1 the previous output - set D1SW to indicate no read is necessary on the next Call;

D1B16 S1FF ~ 0 ~, control D1B14 to DlBl~+ INlt.l = shift INI~.1;

S1FF ~ 1 S1FF ~ 1 because of the shift output from I1VR1 D1B15 BOTdtI(5) BCTRl(6) - decrement bits xemaining;
~ 1 D~1(123) Dol(124) - decrement previous output;
m 1 D1B16 S1FF ~ 1 ,', coaatrol D1B17 to DlBl7 I1 ~ 0 .' . I~hT

Output Dol ~ 123 EOF1 ~ 0 BXIT

U !
z~~;~r»
1 Thir~3 cazll. just assc,rt D1GU
sequence of control D1B1, D1133-D1B4, D1I314-D12316, D1B14-DlIilC~, D1B14-D1B1G, D1B14-DiBla ) same as before ) , D1B4 D1S47 = 1 , , control to D1B14 D1B14 zr1 = oooooloo Shift ir>Rl r~~ht;

S1FF = 0 S1FF = 0 since 'shift out"

. from INR1 ~ 0 DlBls I3CI'P,1(4) ~ BCTRI(s)1 -Dol(122) ~ Dol(123) I
-D1S'W~Z

D1B16 S1FF m 0 ,, control to D1B14 D1B14 zrm ~ ooooooia s1 FF = o 1s DlBls BCTRI(3) ~ BCTRl(4) 1 -Dol(121) ~ Dol(122) 1 -D1B16 S1FF ~ ~ ,, control t~ D1B14 D1B14 II~1R1 = o0~OOOOl SlFF=0 DlBls 'BCTRl ( 2) ~ I~CTRl 1 (3) -Dol(120) ~ Do1(121) 1 -D1B16 S~.FF ~ 0 control to D1B14 D1B14 Ir~~. ~ 00000000 sIFF ~ 1 DlBls BCTR1(1) ~ BCTR1(2) 1 -Dol(119) ~ Dol(120) ~. .
--ia9-,:
1 D1B16 S1FF = 1 ~~ control to D1B17 D1B17 INR1 = 0 ;, control to D1B18 D1B18 D1SW = 0 assure a read on the next call;
EXIT
output Dol = 119 EOF1 = 0 F.ouxth .ca.ll D1G0 to 1 sequence of control D1B1, D1B~3-D1B7, D1B11-D1B12, D1B11, D1B13.-D1B16, D1B14-D1B17 D1B1 ).

j same as above D1B3 ) D1B4 D1SW - 0 o COntr01 t0D1B5 D1B5 read memory read into INRIo INR1 = 00001010 MARL (3) ~-MAR1 (2) + bump the memory address;

MNLI (1) ~-- MLN1 (2) decrement the length D1B6 MLNI ~ 0 0, control toDlB7 D1B7 MSB (INR1) - 0 0, controltoD1B11 D1B11 BCTRl(:1) ~ 0 a control ~oDlBlz D1B12 BCTRl (.0) BCTRl (1) 1 - ~ the value in BCTRl - is a Dol (118) - Dol (119) 1 measure of the unshifted --bits from the previous read, Dol must be decremented by this unit;

D1B11 BCTR1(0) - 0 oecontrol toD1B13 °s;~' i''~_~..

1 D1B13 BCTP,1 = 7 bits to be processed in this word;
DlBl~a INR1 = 00000101 D1B1S BCTR{6) = BCTR{7) - 1 Do1{117) = Dol{118) - 1 D1SW = 1 no read necessary next time;

D1B16 S1FF = 0 ,', control to D1B14 D1B14 INR1 ~ 00000010 ~ ...

S1FF = ~.

D1B15 BCT,~1(s) ~ BCT~iI(6) - 1 Dol{116) = Dol{117) - 1 D1B16 S1.FF ~ 1 ,', control to D1B17 DlBl7 IN~i.I ~ 0 is ~xa~

output Dol ~ 116 BOF1 p 0 F~;fth call set D1G0 sequence of eontxol D1B1, D1B3-D1B4, D1B14-D1B16, same as above D1B3 ) D1B4 D1SW ~ 1 ,°° control to D1B14 . D1B14 IiVRI ~ 00000001 sift IPIRl r3.ght zs slFF~o 3011 ' ~~2"7'~'~.

1 D1B15 BcTrl(4) BcTr.1(~) - 1 =

Dol(11a) pol(116) - 1 =

D 1 S~~J
= 1 D1B16 S1FF = ' contxol to D1B14 0 ..

D1B14 IrlR1 = 00000 S1FF =

DiBlS BcTrl(3) BcTr~l(4) - 1 ~

Dol(114) Dol(115) - 1 =

D1B16 S1FF = ,', .control to D1B17 D1B1? IIV~31 ~', control t~ D1B18 - ~

. D1B1B D1S~J = read next time;

EDIT

output Dol = 114 EOF1 = 0 Sixth call set D~.GO
sequence of control D1B1, D1B3-DlB~fa, D1B10, D1B7-D1B9 D1B1 ~ .
same as ~efare D1B3 ) .
D1B4 DISt-d ~ 0 a , control to D1B~5 D1B15 Memory read INR1 ~ 11100100 .
1~~1(~a) ~ M~FtI(~) + 1 1(~) ~ 1(~) ~ 1 D1B1~ MiaNl ~ 0 ,°., control to D1B10 D1B10 D1END a 1 assures an EOFl on next cally J~

c~
1 D1B7 MSB(II~I~1) = 1 :.control to D1B~i reset the sa.gn bit9 D19 $CTR1 - 0 D1 StJ = 0 Do1 = loo (01100100) E~x~
output Dol = 100 EOF1 = 0 Seventh call set D1G0 sequence of control D1B1, D1B3, D1B19 D1B1 same as above D1B3 D1END = l .'. control to D1B19 D1B19 EOFI = 1 Do1 = 0 EDIT
output Dol ~ 0 E0F1 = 1 note the output retrieved was 125, 123, 119, 116, 114, 100 -the same as case encoded before -7:33-J
il ll~ In summary, it will be seen that what has been dis-closed is a decoder for converting hybrid coded signals to absolute coded word signals. The hybrid signals represent a series of occurrence values of decreasing value.
The hybrid signals have a series of received binary coded word signals including at least one absolute coded word and a bit string ward. The bit string word represents an occurrence by the number of bits of displacement of a bit of predetermined value (i.e., 1) from an absolute word in the series of hybrid words. A hybrid word also includes a flag signal indicating the type of word.
The decoder includes an absolute word outputting means including the D1MEND one-shot mufti-vibrator and its logic and the MSB1 flip flop and a contrdl counter 213 operative during D1B9 of the f~.ow in response to an absolute word flag signal of a received hybrid word signal for outputting the received word signal. In other words, the outputting means is responsive to the absolute word flag signal fox directly outputting the corresponding hybrid word since it is already in absolute word ~orm.
The decoder also includes absolute word signal forming and outputting means. The means includes the INRI register and its shift control logic, the S1F~' flip flop, the DO1 and BCTR1 counters and their load and count control logic and the control counter 213 which are operative during D1B14, 16, 7-9 in response to an absolute word signal and'each bit of predetermined value in a subseguently received bit string word for forming an absolute word signal indicative of the actual value of the bit of predetermined value. Also included is means such as the D1MEND one-shot mufti-vibrator and its control logic i __' ( ) II ~~.~~~~a.
operative during D1131G for outpur.t~.na each of the absolute ~nord signals foL:aed Lhereoy. The true signal at D7.i~ILrm outputs the absolute ,c~~ord signal represented by t(~;e state of the counter DO1.
In a preferred embodiment, the means for forming and outputting the absolute ~nord signal includes the shift register 202 in resister Irn;l for storing a received bit string r~aord signal. Also incl u~aed is , rneans inc7.uding the TTIR1 register and its shift ccmtxol logic and the control counter 213 operative during D1B1L: for repeatedly enab3_ing the shifting of the content of the shift register 202, 1 bit position in the direction of the least significant bit of the bit string ~~aord, Also included is means inc7.uding the S1FF flip flop and th a oowtrol counter 213 operative during D1B16 for providing an indication cthen a bit o:~
predetermined value arrives at the output of the shift register 202. Also included is the counter ?70? and means includinv the D01 load control logic and the control counter 213 operative during D1B7-9 responsive to an absolute word 24 flag signal of a hybrid word for setting the counter DO1 to a state, relative to the reference (0) state thereof, which corresponds to the value of the absolute word signet, Tieans including the DO1 count control logic and the central counter 213 is operative during D1B15 for enabling the counter to count one state towards its reference state for each shift of the shift register 202. r-ieans including the DIr~~ND one-shot mufti-vibrator and its control logic and the control counter 213 is operative durinv D1B16 in response to the bit of predetermined va~.ue in the S1FF flip flop for outputting the state of the counter by form inv a true a~~n~l at D11~.~'ND.

a ;
II
1 In a Lurther preferred embodiment there is means for adjusting the counter D01. Lor bits cahica are not of the predetermined value (e.g., 0) cahich remain in the shift register 202 alter decoding th a last bit of predetermined vat ue in a hybrid caord. Included is an additional counter means such as the I;CTR7_. Means includ ing the scaitches 236 indicate the marirnum number of bits in an absolute word for output, T~~eans including the BCTRI load control logic and control counter 213 is operative during D1B11~13 10~~ fox selectively setting the additional counter means BCTR1 to a state relative to a reference state (e. g., 0), which corresponds to the iaidication of the maximum number of bits in an absolute word signal. T~2eans including the BCTPa.
count control logic and control counter 213 axe operative during D1~15 for enaL~l3.ng the addit3on<~i counter means BCTR1 to count one state, relative to.t~he set state thereof towards the ~ reference state for each shift of the shift register means 202. The Bo output of the BCTP.1 counter indicates the occurrence of the reference state of BCTT;1.
2~~ T~oans including the count control logic of liCTR1 and control counter 213 is operative during D11312 in response to the flag signal of a bit string word signal. stored in T~1SB1 end the indication at Eo indicating the lacTt of a reference state of BCTR1 for further enabling the counting of the counter DOi.
25 and BCTR1, one count for each shift of the shift register means 202. 1By this arranbe:nent the high order ~l bits cahich are not of the predetermined value which are left in the shift register 202, after all bats of predetermined value are shifted out, are reflected into the absolute word signal 30 under formation in shift register 202, .

r 2v. DECODE xx ~soDULE
rigs. ? 2-14 forra a scher.~at~.c and b:i_ocl; diagram of the DECODE II t~IODUf,E. The DECODE II IiODULE is basicalJ_y conJtructed the same as the DECODE I .,IOD ULE except as ~~ descra.bed bed Owe Two decade rioelu7 es, DECODE I i~TODULE amd DECODE-II MOD ULE, are needed in the system in order to decode the occurrences of an occurrence vector from hybrid to absolute coded words and provide the resultant absolute coded ~~7ord s in two s tr eam; at d if ferent rates . DECOuE I
10~~ ZWD~E and DECODE II T~iODULE provide their respective streams of absolute coded words, one word (or occurrence) at a time rahen called;
The DECODE II xiODULE is virtually identica?. to the DECODE 7L T~IODULE as mentioned above. Tn keeping with the ~,5~~ virtual identical structure, the same symbols are used to denote the various parts of the DECODE II MODULE as are used for the DECODE I MODULE however, in some instances a 1 in a symbol for the DECODE I MODULE is changed to a 2 in the DECODE II t~IODULE to he~.p simplify the c~esoription or 20 distinguish between lines going batc~aeen modules. The components whose identity and s3~mbols have been changed in the DECODE II MODULE by changing a 1 to a 2 aye identified belowo ~~ ~~ ' J
ZII DECODE I DECODE II
BCTRl BCTR2 DOl D02 MLNl MLN2 EOFl - EOF2 A.data selector DDS1 similar to that described above replaces the gates 218-226 of the DECODE I MODULE for gating the occurrence vector length into counter MLN2. I~owever, a gating,; circuit similar to the DECODE I MODULE could be used.
The occurrence vector length is coupled from the information source indicated along the top of DDSl to the MLN2 counter responsive to true signals at the control lines indicated along the sides of the DDSI. Additionally, the gating conditions indicated for the load or L input of MLN2 20 differs from that of the DECODE I MODULE and should be noted.
The input control lines connected to gates 224°, 228°, 230' and 234', and the clock suspension legic 222°, differ in minor respects from that of gates 224, 228, 230 and 234 and suspension logic 222 of the DECODE I MODULE and the primes are affixed to these symbols to so indicate.
~4 p138--~.~, y"~. ~'0~~'~3.
V. DELTA MODULE
A. General Description The DELTA MODULE breaks the number of lines to be revolved (_in an iso-entropicgram) from a calling module and breaks the number into smaller increments. The implementation now to be described breaks the number of lines to be revolved into its largest possible component powers of 2 in decreasing value order which, in turn, corresponds to the number of lines to be revolved. This feature is described in the General Description with reference to Table 4-C and is of importance because the lines in the iso-entropicgram can be derived with a minimum of XOR
operations. Also, by revolving from one line to another in an iso-entropicgram where th.e second line is away from the first by a number of lines equal to a component power of 2,. the revolve to the second line is accomplished by a single shift and XOR operation.
The DELTA MODULE, in operation; receives a binary coded number in the 1, 2, 4,8 number code (from the calling module) representing the total number of lines to be revolved, and breaks the number into its largest possible component powers of 2. The largest component power of 2 is formed first, followed by the other largest powers of 2lin decreasing order of magnitude. Although the invention is not limited thereto, the DELTA MODULE about to be described operates on 8 bit words.
The DELTA 1KODULE converts a number by storing it into a first.register and then shifting the number towards the most significant bit .position, repeatedly, one bit position at a time. A second register with the same number of bits as the first register has a "1'° bit that is shifted towards the _. 139 -least significant bit position, one bit position each time the first register is shifted. Since the two registers are shifted in opposite directions by the same amount whenever a "1" bit arrives at the output of the first register, th.e "1" bit in the second register indicates directly the corresponding power of 2 of the 1 bit shifted out of the first register.
Table 14 is a DELTA MODULE example illustrating how th.e above operation takes place. The binary coded number to be converted represents the decimal number 13 and is stored in th.e first register in binary coded form, whereas the srecond register is. initially set to 0.
Eight shifts are depicted, one for each bit of the number to be converted. On th.e first shift, the first register is sh.i.fted 1 bit towards th.e most significant bit, whereas th.e second register has a 1 bit stored in the most significant end where it represents the binary coded number 128. SnTith each. subsequent shift of the first register towards the most significant bit, th.e second register is shifted towards the least significant bit. Following shift 5, a 1 bit for the first time is shifted out of the first register.
This indicates that th.e content of the second register, which now represents 8, can be read as it now contains th.e largest companent power of 2. Also, 1 bits are shifted out following shifts 6 and 8 and th.e second register at these times represents the numbers 4 and 1, respectively. Adding 8, 4 and 1 results in 13 which is the binary coded number originally stored in the first register.
B. ~ Components The DELTA MODULE, Fig. 15, contains inputs aril output control \_.i _ l lines indicated a~.ong the ril;ht hand sides The system Of notation described above in section I.F, Conventions Used in Figures, is used, Additionally, tlxere are information input and output lines. These input and output lines carr y multiple bits of inforr~ztion and are indicated by heavy lines.
Tao registers Dk;LI and DELO are provided. Resister DELI
includes an B flip flop shift register 302 and the register DELO includes an 3 flip flop shift register 304, Both of the registers DELI and DELO include a most signia scant bit flip flop, DELI containing MSBDELI and DELO
containing MSBDELO. ~~SBDELI has its input for setting it to a 1 state connected to the output BOUT of shift register 302. The output SOU'I of register 302 is the unprimed output from the most significant flip flop in register 302.
15 The 2~1SBDEI~ flip flop in DELO has its Z~LSEDEL~ (or unprimedj output connected to the "IN" input of register 304 which is the set to 1 input of the most significant flip.~flop in register 304, Logic (not shown] in register 302 applies true signaJls at Dx~o and ~b'fo when the register is 0 and not 0, 2~ respectively. The operating characteristics of shift registers 302 and 304 axe the same as shift register x.14 of the ENCODE MODU~LEo Register 304 also has a C'LIt input which is responsive to a true signal at CLR to reset register 304 to 0. Shift registers 302 and 304 are of 25 type SN74198 disclosed at page 456 of the above TTL boolc, A control. counter 313 has two flip flops.Pl and P2, Additionally, control flip flops DEL~'ST, DELE1~ and DELCE
are provided. The DELFST flip flop, when in a 1 state, indicates that the first call is occurring to the DELTA rIODULE.
The DELEND flip flop in a 1 state indicates tlat the word ~0 stored in DELI has been completely converted into its 1 ~~ component: poiners of 2. Thus, the 1 slate of DELE!'?D is an indication that the DELTA MODULE hay cor~pl_eted its operation.
The flip flop DELCE controls the for;~at3on oL clock pulses at CLIC. Each of the flip flops in the DELTI~. I~fODULE are of ~~ type SN7~E74 described in section z ~F Conventions Used in h'igurea.
One-shot molti-vibrators D~ ~ DELP~t~7 are contained in the DELTA P40DIlLE. One-shot.multi-virrator DEL~O
is set to a 1 state pursuant to each call on the DELTA TMODULE.
10~~ One-shot nulti vibrator DEL2~lEr;:~ indicates each eat from the DELTA MODULE operation by a true signal at the DELDTE21D output and resets the nodule. The one-shot DELfsO and DELt~ID have the same: chaxacteristics as the one-shot of the ENCODE hIODLILLE, A source of cloclc signals foamed by a clock 312 forms a 1511 series of regular xecurring true pulses; as depicted, The DELTA MODULE also in~:ludes OR gates 314, 315, 316, 317, 31B and 320, and an AND gate 322. These gates are conventional gating circuits taell lcnown in the computer art. The output of AND gate 322 is designated CLIP. The inverter 324 20 is a conventional logical inversion circuit o~hich forms the logical inverse of the signal at CLT~, and the inverted signal is designated , A selection circuit DELS is a conventional selection circuit of the same type disclosed in the section ~-Ii above.
25 Selector circuit DELS couples 3 bits of information from any one of the designated three 8 bit inputs to a. single 8 bit output cnha.ch is the information input into xegister 302.
C. Detailed Descrint~ion 30 The purpo se of the DELTA PIODULE is to xeceive a number representing; t:he nu~aber of lines to be revolved and convert l,l the number into its Iar;est poss~.ble component poc.~ers of 2 in dec::easin~ value order.
The DELT~. i-iODULE is called by either the P,EVOLVE i~:ODULE
or the OUTPUT MODULE. The DELTA I~20DULE is called by the REVOLVE and OUTPUT I~iODTJL,1;S by first setting the DELFST
flip flop to a'1 state. The OR gate 316 sets the DELFST
flip xlop to a 1 state and has inputs Rz~II and Oi~Z2 fro;n the P.EVOLVE and OUTPUT i,iODULEE, respective) y., , A control signal at either tl~ Rl~Zl output of the 1?EVOLVE I~iODULE or the 0112 1~ output of the OUTPUT MODULE enables OR gate 316 to trigger the DE;aFST flip flop to. a 1 state. Follo~~ia~g the signals at wither I~2~i1 or OM2, the REVOLVE and OUTPUT I~IODULES, respectively, provide signals at the RTM3 and 0ri3 outputs.
A control signal at either the F,I-Z3 or Oi~i3 output energizes the OR gate 320, causing a true s:Egnal to be applied to the one-.
shot DELGO, causing it to apply a true signal to the input of the DELCE flip flop, This causes the flip flop DELCE
to be set to a 1 state and causes the flip flops P1 and P2 to be reset to an 0 state, 2p The 1 state of flip flap of DELCE causes a true signal at the DEhCE output iohich, in turn, enables the AND gate 322 to couple the clocl: signals from clock 312 to the CLIZ output.
The resulting true signals at the'~'i and~P2 outputs of flip flops Pl and P2 cause flip flop P1 to be sat to a 1 state at the following pulse at CLIt. As a result, D1D1 of the DELTA
MODULE flow is entered.
Tha source of the number to be converted is determined by control signals at the 0M2, CM~+ and SM7 outputs of the OUTPUT, CHANGE and SEED MODULES, respectively, A true signal at OM2, 3~ Ctt4 or SM7, respectively, causes the DELS selection circuit -193~-i 1 to gate the ~3 bits of information from DS6 of the OUTPUT
MODULE from CL~IE of the CI-i~NGC 2~IODULE or from T1 of the SEED rtODULE, respewti.vely, to the information input of_ the shift regiater 307_ . The s ignal at P2 is noca false, cans ing register 302 to be in a load :~oue of operation and the .
true signal at.Si~i8 (SEED :~IODULE), 02~24 {OUTPUT DiODULI?), or 02~45 (CH.AN~';E IfODULE) enables the OR gate 31~f to cause register 302 to store the a bit information signal from DELS.
During the 1 state of flip flop P~., oontrol signals are formed at the P1 and DELFST outputs of flip flops Pl and DELFST, pausing the hiSBDELO flip flop to be set to a 1 state. To be explained in more detail, the 1 state of the MST'.DELO flip flop is used to enable a 1 bit to be shifted into the most significant bit position of the shift register 304 during the following shifts of register 302~
The true signals at Pl a;nd DELFST additionally cause the OR gate 31$ to reset the I)ELFST flip flop to an 0 state and reset the DELE23'D flip flop to an 0 state.
Register 302 no longer pontains all 09s' a number to be converted having been stored th,~_re~.n, therefore a true signal is formed at the DD Io output indicating that the register is not 0, This signal, in coincidence with the true signal at P9., causes the P2 flip flop to be set to a 1 state and DI33 is entered, The conversion is made by shifting register 302 containing the number to be converted towards the most - ..

1 sil;nificant bit and by shifting the register 304 towards the least significant bit. The first shift shifts a 1 bit into the most significant bit position of register 304 from flip flop MSBD>;LO. During DE7;3 of the flow, cuhenever the register 302 does not contain all 0's, a control signal is formed at the ~o output in coincidence with the true signals at P2 and IJBD; . Coincidence of these true signals cause the register 302 to be shifted one bit towards the most~significant bit position, causing the most significant bit in register 302 to be stored in the MSBDELI flip flop and causing the register 304 to be shifted 1 bit position towards the least significant bit position. During the first shift, the MSBDELO flip flop is in a 1 state, causing a 1 bit to be stored in the aaost significant bit position or flip flop of the register 304. It will be noted that the DELTA MODTJhE
flow indicates a"SHIFT DELO rt'° and "SHIFT DELO lft".
''SHIFT DELO rt" indicates a shift right towards the least significant bit position of register 304 whereas '°SHIFT
DELI lft" indicates a shift left towards the most significant bit position of the register 302.
Following DB4, DBS of the flow is entered where the MSBDELI flip flop is checked. If the MSBDELI flip f lop is not in a 1 state, i.e., a ~. bit having been ZS shifted there from register 302, DB4 of the flow is again entered where the above shift is repeated in the same manner as described above. The shifting proeess ~_.; ~1 II
1 continues until a 1 bit is stored into the P1SBD1:LI flip flop. ~Jhen this occurs, DBG of the flow is entered.
The 1 state of the MShDI;LI flip flop causes a true signal at the MSBDELI output. The true signals at P2, MSBDELI and CLK trigger the one-shot DI:LMhND to a 1 state, causing a true signal at the DELt~ND output from the DELTA MODULE and additionally resetting the DELCE
flip flop to a 0 state, thereby preventing the AND gate 322 from applying additional clock pu7.s~es~at CLK and ;p causing the shifting to terminate and operation of the DELTA MODULE flow to EDIT. The true signal at the DEL,2~ND output indicates to the calling module that it has finished processing~and that the word contained in register 304 of DELO may be read as it now contains one of the~component powers of 2 of the input number originally stored in reg~,stor 302. The true signs:!. at output DELMEND
also enables 0R gate 315 to reset control counter 313 to 0 (i.e. P1, P2 = 0) , The true signals at P2, MSBDELI
and CLK reset the MSBDELI flip flop to a 0 state.
20 The DELTA MODULE ~.s again Balled by either the REVOLVE MODULE or the OUTPUT MODULE by applying control signals at either the RM3 or 0M3 outputs. Either of these signals cause the OR gate 320 t~ again trigger the one~shot DET."CO which, in turn, sets the DELCh flip flop a5 to a 1 state, enabling the AI~TD gate 322 to form pulses at the CLIP output. Both the Pl and ~2 flip flops are n WJ
1 " in 0 states, accordingly, flip flop P1 is set to a 1 state at the 1:01104J7.11~ pulse at CLK. After the first call (signal at RIri3 or OrT3), the DELFST flip flop is in a 0 state, accordingly, DB3 of the flow is entered, 5II followed by DB4-6, as described above. During each entry into DB4.and DBS, the shift registers in DELI and DELO are shifted until another 1 bit is stored in MSBDELI, causi:~g another true signal at the output DELMEND, indicating to the calling module~that a new ~~ component power of 2 is now in register 30~ for output.
ii P~ally, when the last 1 bit of the input number contained in register 302 is shifted into the MBBDELI
flap flop, the content of register 302 is 0, causing a true signal at the DIo output. xf this occurs while gs'I the Pl~ flip flop is in a 1 state, the :'Eollc~~~~ing pulse at CLK sets the DELEI~D flip flop to a 1 state. If it occurs while the P2 flip flop is in a 1 state, the DELEND flip flop is set to a 1 state, irrespective of the cloclt.
The Z state of the DELEND flip flop and resulting control 2p (' signal at DELEND signals the calling nodule that the last and least significant power of 2 of the input number has been formed (e.g, entire number lass been converted .
A true signal at the DELEND output or,the DIo output in combination with true signals at Pl and C'~K cause 25 the DELN~ND one-shot to be set to a 1 state and the ~0 Il ~ 3~'"d'~'~~.
1 DI;LC1: fl:i.p flop to be reset to a 0 state, inhibi~:i_ng the gate from proviclin~ further pulses at CL1C.
D~LTiL:ND cloclc circuit becomes P1~DLLEI~TD~Z'I,Tt +
CLIC P2 viSBDLLI. These changes permit the DLLTA 140DULE
to convert the number set in DELI to its component pocaers of 2. After this has been done, Dzo will be' asserted. Then any further call on the DTaLTA MODUL1;
will cause DLL1;ND to be set during P1 and the module will terminate upon the -assertion of the, ChI~ signal lp during pulse Pl. Note that DELO is cleared.in this ease.
l~

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Claims (26)

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. Electronic data processing coded signal converting means comprising:
a) means for storing at least the combination of given line value signal and given line number signal which represent a given value;
b) means for forming a total number of lines value signal;
c) means for converting such combination of given line value signal and given line number signal representing each different given value to any combination of equivalent line value signal and line number signal in a unique set thereof which includes the given signals, each line value signal representing at least one digitally coded actual occurrence value out of a set of monotonically ordered possible occurrence values, each line value signal being related to another in the same set by an exclusive OR of the actual occurrence values thereof and the actual occurrence values thereof relatively shifted, comprising:
means for responding to each different value represented by a provided number of lines signal for causing the converting means to form a different predetermined one of the equivalent line signals within the set which corresponds to the combination of given value line signal and given line number signal.

2. Means as claimed in claim 1 in which said means for converting further includes means for forming the equivalent number value signal corresponding to the formed equivalent line signal; and the apparatus further includes means for converting the total number of lines value signal to one or more values representing incremental movements which may be made by said converting means and for providing a corresponding number of line value signal to the converting means.

3. Means according to claim 1 wherein said means for converting comprises means for causing those relatively shifted occurrence values which are not within the group of possible occurrence values to be eliminated from the equivalent line value signal which is formed.

4. Means according to claim 1 wherein said means for forming numbers of lines value signal comprises means for only forming signals representing a component power of two.

5. Means according to claim 1 wherein said means for forming a number of lines value signal comprises means for forming one or a series of numbers of lines signals identifying increments by which a combination of given line value signal and given line number signal is to be advanced through one or more equivalent combinations in the corresponding equivalent set thereof.

6. Means according to claim 5 comprising means for enabling the converting means to use an equivalent line value signal formed by said converting means for a number of lines signal in such series as the given line value signal for the next number of lines signal in such series.

7. Means according to claim 5 comprising:
a) means for receiving a signal identifying a total number of lines signal; and b) said means for forming one or a series of number of lines signals comprising means for converting said total number of lines signal into signals representing its component powers of two.

8. Means according to claim 7 wherein said means for converting said total number of lines signals comprises means for converting said total number of lines signal into signals representing its component powers of two in order from the largest value to the smallest value.

9. Means according to claim 1 wherein the converting means comprises:
a) means for forming a shifted line value signal containing actual occurrence values which represent the given line value signal shifted by the number of actual occurrence values represented by the number of lines value signal; and b) means for exclusive ORing the actual occurrence values represented by the given line value signal and the shifted line value signal to thereby form the equivalent line value signal.

10. Means according to claim 9 wherein said exclusive ORing means comprises means for ordering the actual occurrence values of the shifted and unshifted line value signals into monotonically ordered values and means for forming in said equivalent line value signal only those shifted and unshifted values which are not equal.

11. Means according to claim 10 wherein said means for ordering comprises:
a) means for comparing the shifted and unshifted values; and b) means for forming signals in the equivalent line value signal representing only those actual occurrence values which are not equal.

12. Means according to claim 9 comprising means for causing shifted actual occurrence values which are not among said possible occurrence values to be excluded from the resultant equivalent line value signal.

13. Means according to claim 9 wherein said means for forming a shifted line value signal comprises:
a) means for forming for individual actual occurrence values of the given line value signal an actual occurrence value signal; and b) means for combining the values represented by the number of line value signal and individual actual occurrence value signals to form shifted occurrence value signals making up such shifted line value signal.

14. Means according to claim 1 comprising means for utilizing the values represented by said number of lines value signal and said given line number signal to form the equivalent line number signal.

15. Means according to claim 14 wherein the utilizing means comprises means for combining the values represented by the number of lines value signal and the given line number signal.

16. Means as claimed in claim 1 or claim 3 or claim 4 further including:
a) at least one decoder means for converting the line number signal in the storage means from a first compact code to a second expanded code for use by the converting means;
b) encoder means for converting the equivalent line value signal formed by the converting means from an expanded code as provided by the converting means back to the first compact code; and c) means for storing the equivalent line value signal in such first code.

17. Means as claimed in claim 5 or claim 6 or claim 7, further including:
a) at least one decoder means for converting the line number signal in the storage means for a first compact code to a second expanded code for use by the converting means;
b) encoder means for converting the equivalent line value signal formed by the converting means from an expanded code as provided by the converting means back to the first compact code; and c) means for storing the equivalent line value signal in such first code.

18. Means as claimed in claim 8, further including:
a) at least one decoder means for converting the line number signal in the storage means from a first compact code to a second expanded code for use by the converting means;
b) encoder means for converting the equivalent line value signal formed by the converting means from an expanded code as provided by the converting means back to the first compact code; and c) means, for storing the equivalent line value signal in such first code.

19. Means as claimed in claim 1 or claim 4, or claim 5, including:
a) first decoder means for decoding the line value signal in the storage means from a first compact code to a second expanded code having an individual coded signal for any individual actual occurrence value represented in the given line value signal; and b) second decoder means for decoding the line value signal in the storage means from a first compact code to a second expanded code having an individual coded signal for any individual actual occurrence value represented in the given line value signal;
said means for converting further including 1) means for combining values represented by the actual occurrence values in the decoded line value signal and provided number of lines value signal for forming a shifted line value signal, 2) means for exclusive ORing the values represented by the actual occurrence values from the combining means and the first decoder means, and 3) means for forming an equivalent line value signal representing the results of the exclusive ORing which only represents actual occurrence values included in said possible set thereof; and the apparatus further comprising c) means for converting the total number of lines value signal into a value representing the component power of two thereof and providing corresponding number of lines value signals to the combining means;

d) encoder means for converting the equivalent line value signal from an expanded code back to the first compact code; and e) means for storing the converted equivalent line value signal in such first code.

20. Means as claimed in claim 5 further including:
a) means for forming such equivalent line number signal which corresponds to the formed equivalent line value signal; and b) means for enabling the converting means to utilize an equivalent line signal formed for one incremental number of lines value signal as the given line value signal for the next incremental number of lines value signal.

21. Means according to claim 20 for fast converting operations wherein the means for forming incremental number of lines value signals comprises:
a) means for determining the larger of the difference between the values of the largest two actual occurrence value signals in the given line and of the difference between the values of the largest possible occurrence value and the largest actual occurrence value in the given line value; and b) means for forming at least one of such incremental number of lines value signals representative of such largest difference.

22. Means according to claim 21 wherein said means for forming at least one such incremental number of lines value signal comprises means for forming a signal representing each of the component powers of two of the largest difference.

23. Means as claimed in any of claims 1, 3 or 4, in which said means for forming a total number of lines value signal comprises:
a) means for forming a signal having a value represent-ing the number of such possible occurrence values;
b) means for determining a value related to the values of said number of possible occurrence value signals and the given line number signal; and c) means. for forming and providing such number of lines value signal representing said determined value.

24. Means as claimed in claim 5, in which said means for forming a total number of lines. value signal comprises:
a) means for forming a signal having a value represent-ing the number of such possible occurrence values;
b) means. for determining a value related to the values of said number of possible occurrence value signals and the given line number signal; and c) means for forming and providing such number of lines value signal representating said determined value.

25. Means as claimed in any of claims 1, 3 or 4, in which said means for forming a total number of lines value signal comprises:
a) means for forming a signal having a value represent-ing the number of such possible occurrence values;
b) means for determining a value related to the values of said number of possible occurrence value signals and the given line number signal; and c) means for forming and providing such number of lines value signal representing said determined value and wherein the means for determining comprises means for determin-ing a value representing the difference in value represented by said number of possible occurrence values signal and said given line number signal.

26. Means according to claim 3 wherein said means for forming numbers of lines value signal comprises means for only forming signals representing a component power of two.