CA1127767A - Hybrid-absolute coded signal converter - Google Patents

Abstract

ABSTRACT OF THE INVENTION
Data processing information storage and retrieval system having a memory. A number of modules are interconnected with the memory. Encode and decode modules operate in conjunction with the memory for compacting and expanding data. In the compacting method and means, preferably the vector signals are encoded from a compact code to an expanded code before conversion to an equivalent signal. Also preferably the equivalent line value is converted from an expanded code back to a compact code before length is checked using encoding techniques. A preferred encoder is disclosed for converting to hybrid form a received series of absolute coded words in decreasing value order which represent the vector signals. A preferred form of the decoder converts hybrid coded signals to absolute coded signals. A revolve module in association with a delta module and a memory enable coded signals to be transferred into a number of unique but equivalent and related signals. A seed module enables the shortest of the equivalent signals to be located. A change module enables any one of the equivalent signals to be updated. An output module causes an equivalent signal to be converted back to the original signal representation. Pipe and brightness modules perform a discrimination function on stored information.

Description

DEMANDES OU BREVETS VOLUMINEUX

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CECI EST LE TOME ~ DE 4-NOTE: Pour les tomes additionels, veuillez contacter le Bureau canadien des brevets :
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THIS SECTION OF THE APPLICATION/PATENT CONTAINS MORE ~:
THAN ONE VOLUME

THIS IS VOLUME j~ OF 4 ~ . .~: `
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NOTE: For additional volumes please contact the Canadian Patent Office .
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INFORMATION STO~AGE AND RETRIl~yAL SYSTEM

BACKGROUND OF THE INVEiNTION ~
This invention relates to information storage and ¦
: . retrieval systems. ¦-Dlstinguishing the present invention from the prior art there are certain characteristics that are generally ti : applicable to prior art information storage and retrieval systems in existence today. These features are as follows: 1 1. As the size of a stored data base increases, the I .
average time required to retrieve data therefrom increases. ¦

2. Data compressed in a storage and retrieval iiystem ¦:
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1 must be expanded before it can be operated on.

3. If another element is added to a data base ~for example, a record i9 added to a file), the amount of space required to store the updated base alway~ increases.

4. Some inquirie~ will be rejected by a retrieval system because they are not stated or formated correctly.

5. As the 3ize of a random access data base increases, ----the efficiency of storage decreases (due to the requirements for indexing tables, pointers, etc.).
An embodiment of the present invention does not have any of the above features. ;
An embodiment of the present invention involves a method and apparatus of restructuring digital information ;~
to produce iso-entropicgrams and seeds. To be explained in more detail, a seed is an optimum way of representing a particular piece of information with minimum storage.
Stored infonmation is retrieved, not by searching the data base, but by a generation process. During the generation process a data request, along with stored iso-entropicgram 20 seeds, are fed as parameters to an output generator. ~ -In summary, some of the advantage~ gained from using `~
the technique~ according to the present invention may be achieved as o110ws: (1) les~ physical storage is required,~
~2) fa~t retrieval time, (3) ease of restruoturing and up-2 dating a data base, ~4) ease of specifying a new retrleval crit-eria, and ~5) ease of speciying and carrying out a process.
~: ;;~ ~- ' . '."'':.' The information storage and retrieval system described in the present patent application i~ a new class of machine, ~3~ based on an entirely new technology. Since it is based on : '.',.

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~ ;7 1 a new technology, a new word has been coined to describe this technology, the word belng "holotropic".
The holotropic inormation storage and retrieval system is not based upon a new component nor merely upon a S . ' /'~

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~ J'~7 1 rearran~ement o exi~tin~, components, bu~ inste~d i~ ba~ed upon new methods and apparatus for buildin~ ~ whole new cla~s o~ in~ormation proces~ing machines.
Some superficial simitarities will be found between S pre~ently available technique~ and the class of new machines disclosed herein. Ho~ever, the differences are muc~ more significant then the similarities, making it ~kward to ---describe the new technology in existing terms. For example, one aspect of the invention resembles holography in the sense 10 that information pertaining to an item is not stored in one -place. However, to ~ the word "holographic" to describe this new technoLogy would convey the totally incorrect impression that it is optical in nature and, at the same time, the term fails to refer to this technology's other character-istics. By way of further example, this aspect of the invention may behave in some respe~ts like an as~ociative memory. However, here again, the differences outweigh the similarities and the use of a descriptor like "associativet' genera~es more confusion that it does olarification. For this resson, the term holotropic is used to identify the technology involved.
One application of the holotropic method and apparatus is for information storage and retrieval. However, in des-cribing the functioning of a holotropic memory ~ystem, ¢are 2~ must be taken in u~lng the term~ used for pxevious techniques.
The mechanisms by which holotropic memosy ~ystems store and retrieve lnformation are totally different from the mechanisms associated with terms like "search", "scan", "match", "point", "link", or "thread". Thus, according to an embodiment of the present invention, instead of searching for the presence ~3C of stored data on the basis of matching an inquiry, the - ~
1~1.*7'767 1 holotropic memory sys~em uses ~he inquiry to lnvoke p~rameters which ~efine both the applicable pieces and any relations between these pieces and the rest o the information. Those parameters then produce the information requested in the inquiry, not by reading it out of storage, but by recomposing it.
In a holotropic memory system, the information itself is not found, it ~5 generated.
From the user's point of view, there are two character-istics of holotropic techniques which profoundly change conventional modes of dealing with an information storage and retrieval system. One characteristic concerns the absence of the need for descriptors, and another concerns file compression.
Attention will now be directed to descriptors and 13 exactness as it applie~ to an embodiment of ~he present invention. The data whlch is to be entered into the holotropic system for l~er retrieval need not be categorized, . indexed, described, or even formated for the ~rpose of retrieval. Should the user wish to set up a structure of categorie~ containing deQcriptors or indices because it makes it easier for him, he may of course do 80. An important distinction here i8 that a holotropic memory system -~
never impose~ ~uch structures upon the process. Eveh though the holotroplc memory ~ystem can accommodate ~uch ~tructure~, it doe~ not require them.
The same flexibilities characterize the making of inquiries of a holotropic memory system. The inquirer can simply a~k questions in whatever form, u~ing whatever words occur to him. Usually the person attempting to use an `30 information storage and retrieval system has no trouble '.' -~ , 77fi7 l s~ his inquiry in such a ~7~y that he understands it, an~l in such a way that other people understand it. The di1culty arises when he tries to translate his inquiry into nn equivalent question which meets the acceptance requirements imposed ~y conventional information storage and retrie~al systems.
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_ By prior information storage and retrieval systems, limits have to be set on the inquiry proces~. Since a holotropic ~:
memory system does not impose any requirements on the inquiry l process, necessary control i8 vested where it belong~, namely, with the user. The most important control the user -~
exercises concerns the degree of exactness of the match ~-between his inquiry and the contents of the data base.
The maximum setting on his "degree of exactness" control l would be that for an exact match. Should sn exact match not be found, the holotropic memory system en~ble~ it to tell the user that ~he situation exists and indicates that change must be made in the exactness settin8 80 that the inquiry will retrieve at least one relevant item.
The exactn-~s control sett~ng has no effect whatsoever on the search t~me of the holotropic memory system. However, slnce it indirectly controls the amount of data retrieved, it does efect the total response time in the sense that more retrieved data will tske longer to dlsplay in print.
2 Because o the diferences in the techniques of the inquiry process in trad~tional and in holotropic information storage and retrieval systems, the structure of the latter may be 1~ vastly different. In traditional retrieval information storage and retrieval systems, an inquiry can be re~ected ~3 becnu~e it contains an unallowable descriptor, or because some~ ing i8 misspelled, or because the~arts are ordered im~operly~ or because the lnquiry is not framed according to thc specifications. Thus, an inquiry can be re3ected

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1 regardless of whether the inormation it asked ~or is actually in the data base. In a holotropic data storage and retrleval sy~tem, no inquiry need ever be re~ected or such reasons.
The only sense in which an inquiry needs to be "re~ected"
S at all by a holotropic in~ormation storage and retrieval system is that it fails to retrieve, In other words, the data base does not conta~n anything which matches the inquiry at the specified level of exactness. If this happens, the user i8 told whether or not a change in exactness will retrieve an item, and if 80, the setting.
Another consideration for holotropic information storage and retrieval method and apparatus i9 file compression.
The nature of the holotropic system i9 such that the stored data is compressed into less space than would be lS used to store the data with presently available techniques.
This is true even if it were entered as a linear string, that i8, as a single record. The degree to which any particular data sample i8 compressed in a holotropic system is a function of two independent processes.
The first process is fairly easily described, and its effects are relatively predictable. The holotropic ~torage and retrieval system compresses input data by automatically taking advantage of any redundancy. In one te~t, a 10,000-word oample of ordinary English prose was comprosoed to approxi-matoly on~-half the space which would have boen requirod had the sample (without any index tablos, pointers, or other artifacts) be-n stored as a single record in a traditional information storage and retrieval sy~tem. The exploitation of these redundancies occurs at all levels. Once a ~30 ¦ character, a word, a sentence, a paragraph, or any other _7_ `
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1 arbi~r~rily specified input element hss been encountered, no subsequant occurrences of that same eLement need be Ytored in their original form. Instead, the holotropic system notes that a previously encountered element has occurred again, in a manner which permits reconstitution of any or every one of the multiple input elements in its orig~nal conte~t. -The second process contributing to data compression in a holotropic memory system ~s more difficult to predict.
It is more dificult to pred~ct as it is a function of the relatedness of elements which are part of a data base.
As each new input element is added to the data base, it i9 automatically correlated with every other appropriate element already stored Since thi~ process operates on the lS data base in its com~ressed form, it does not adversely affect storage time, One possible result of this correlation is that the content and structure of a new input element may reveal a relationship Setween itself and a number of already ~tored olements which permits all of the related elements to be treated as a single entity and stored together. Thu~, a number of elemsnts which at one time were stored separately, can be collapsed on the basis of their relationship with a su~sequent input element, with results that the updated file can require less totsl storage ~pace ehan it did prlor 2~ to the addltion of the new lnput element.
Another characteristic which is also very tlfferent in a holotropic system from tradltional information storage and retieval systems i~ that in a holotropic system ~oth the degree of compression and the relative speed of retrieval ~;
`30 may increase as the size of the data base increases. ----- ~ ~

~ 7~f~;7 1 A derivative eature of compression in a holotropie sy~tem i9 th~t certain processing or manipulation o~ the stored data is done in its compressed form, thus permitting higher processing speeds than 5 y8 tems which mu~t first expand the data.
Although the above discussion has been directed primarily to holotropic information storage and retrieval systems, specific holotropic method and apparatus techniques may be applied in other areas.
One area i~ in digital communications, where band width limitations place an upper bound on speed of transmission.
Here, a holotropic ~ystem can be used to encode the digitized data, and the speed o~ transmission of any message wil} be increased as a function of the d~gree of compres~ion as discussed with respect to information storage and retrieval spplication~. It is important to remember that the information thus compressed and transmitted can represent anything whatsoever, from a payroll file to a digitized pictorial image.
Significantly, other systems can be sed to efficiently compress and transmit data, However, one thing which makes the holotropic approach unique i8 tht, since holotropic compression i8 a function of the redundancy of the message, compression and orror corre~tion are one and the same mechanism.
S~gnificantly, holotropic techniques can be lmpl-mented 2S in software, but some or all are much more effici~nt when ~ -implemented in microcode, and are maximally efficlent when implemented d~rectly in hardware, Hcwever, even where holotropic techniques are implemented in sotware or microcode, holotropic memory systems can perform more `3 efficiently in terms of stor~ge, speed, e~c. than presently known techniques At the hardware level, holotropic `::
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~ '7~7 1 technology can take full advantage of the unique propertie~
of the latest components, such as, charge couple device~, magnetic-bubble logic, and memory, etc.
The technology de~cribed herein is applicable alike to large computers (for examplej information storage and retrieval systems), to subsystems (for example, intelligent --disk storage devices), or to very small stand-alone machines ~for example, battery-driven calculators)~
. :-SUMMARY OF THE INVEI~TION
One aspect of the present invention concerns novel method and means involving a digital data processor for creating or structuring a unique digital coded data base in a memory of the data processor. Briefly, a method is lS disclosed for forming, in a desired order of occurrence, and as input, a plurality of coded event ~ignals. At least ~ome of the event signals represent the same event and at least one ~ignal represents a different event. The event signals together represent plural entries. An event-time indication i~ formed for each event ~ignal representingthe order of occurrence thereof. In the memory, a stored data base is formed which comprises a separately retrievable event vector signal for each diffe~ent event and includes the step of forming in each retrievable event vector ~ignal a representation of those event-time indications which represent the order of occurrence of the corresponding event. Preferably, the event-time indications axe formed by counting the event signals as they are formed.
The vector ~ignals are referred to herein as being 3 retrievable because the vector signals need not be stored " -10- .

1'~7'767 l ~ se~ rate memory locations as separate signals but may ~ in a special form called a seed or may be combined with othcr seeds which may be retrieved to separate vector signals as required.
Also disclosed is a method and means utilizing a data processor having a memory for creating or structuring a multiple layered data base in the memory. The method involves the steps of ~orming, in a desired order of occurrence, and as input, a plurality of coded event signals;
at least some event signals represent the same event and at lea~t one even~ signal represents an event which is different from another one. The event signals, together, represent a ~equence of entries. Some of the entries are the same and at least one is different. A fir~t event-time indication lS i8 formed for each of the event signals. A second event-time indication is formed for each of the entries. The event-times represent the order of occurrence of the respective events an~ entries, representing the input.
The fir~t data base layer i~ entered in the memory and involves the steps of storing in the memory a retrievabIe f1rst layer vector ~ignal corresponding to each different valued event ~ignal and the step of forming in each of the .
first layer vector signa1s a representation of those first event-time lndications which repre~ent the order of occurrence o~ the corre~ponding valued event signals. The second data base layer 1g entered ln the memory and involves the step of storing in the memory a plurality of retrievable second - -layer vector s1gna1s. Those entries which are the same have a corresponding second layer vector signal and those entrie~
~3 which are different each have a different second layer vector ",:
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1 signal. Also includ~d in the step of forming the second layer is the step of forming in each second layer vector signal a representation of those second event-time indi-cations which represent the order of occurrence of the corresponding entries.
Preferably, redundancy is eliminated in the first data base layer. According to a preferred method, a test -is made to determine if a newly formed input ~ntry is already represented in the first data base layer. If the entry is not represented, the newly formed entry is added to the first data base layer, utilizin~ the step of storing.
If the entry is already represented, then it is not added to the first layer a second time. However, the entry is added on the second layer.
According to a further preferred embodiment of the invention, method and means are provided for storing -delimiter events in one or the other or both of the layers.
Briefly, a method is disclosed wherein the event signals of the input comprise at least one representing a delimiter.
20 At least one ~uch delimi~er event ~ignal is formed in each - -of the entries and in the order of occurrence of the entries so as to define the boundaries of the entries. The first event-time indications also identify the order of occurrence of each delimiter. A separately retrlevable vector slgnal i9 provided for the first event-time lndications which represent the order of occurrence of the delimiter event signals. A similar method is provided for forming a delimiter event signal in the second layer identifying the bounds of entries in the input.
3 Method and means involving a data processor are disclosed for retrieving data from the stored data base.

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1.~ 7 1 Briefly, the disclosed method retrieves, from a memory, data which is contained in a stored data base. The data base represents a se~uence of events in which some events are the same and at least one event is different. The stored data base is represented by a plurality of separately retrievable vector signals one for each different event.
Each retrievable vector signal represents at least one event-time value which represents the order of occurrence of the corresponding event. ~he method includes the steps of interrogatinq a selected vector signal to selectively form at least one event-time identification signal, and generating a unique event signal corresponding to a vector signal which represents an event-time value corresponding to the event-time identification signal. By selecting only those vector signals for interrogation which are of interest the necessity of interrogating all vector signals of the data base i~ avoided.
Method and means involving the data processor are also disclosed for retrieving from a memory, data which is contained in the multiple layered data base. Each layer represents an ordered sequence of entries and events. One or more events represent each entry. In each layer some events are the ~ame and at leAst one i8 difforent. Some ontrie~ are the ~ame and at least one is dif~erent. Each 2 layer ha~ a plurality of ~eparately retrievable ve¢tor signals, one for each different event for such layer. Each retrievable ` vector signal rèpresents an event-time value for each occurrence of the corresponding event and the event-time values identify the order of occurrence of the corresponding events. The data base comprises at least first and second layers. At ;;

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1 least some o~ the events in the secend l~yer have a corresponding entry in tlle first layer. The method disclosed includes the steps of generating a first layer entry identification signal designating a fir~t layer entry which corresponds to a second layer vector signal.
The second layer vector signal represents at least one event-time value in a selected second layer entry. Also included is the step of generating a first layer event signal corresponding to the first layer vector signal 0 which represents an event-time value in the designated first layer entry.
The multi-layer system, preferably involves method and means for interrogating on each layer and generating signals from each layer. Briefly, the method involves the step of interrogating a selected first layer vector signal to form at least one first layer entry identification signal which, in turn, designates at least one second layer vector signal. The de~ignated second layer vector signal is interrogated to form at least one second layer entry identification signal. The step of generating includes the generation of a first layer entry identification signal : de~ignating the first layer entry which corresponds to a second layer vector signal which represents at lea~t one event-time value in the deslgnated second layer entry. A
2 first layer event signal i~ generated corre~ponding to the first layer vector signal which represents an event-time value in the designated fir~t layer entry.
Preferably the retrieval involves an initial step of forming a request comprisinq a series of coded event signals ` repres-nting the events of an entry. The step of interrogating .,.
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1 on the ~irst layer inclu~es the step of interrogating selected vector signals, which correspond to the events of the request, to locate an entry containing event-time values which represent events having a predetermined degree of match with the events represented by the event signals of the request. Preferably a signal is formed which identifies different allowable degrees of match between the events of the request and the events of an entry in the data base. The step of locating involves the step of 0 locating a data base entry which has the allowable degree of match. In this manner it is possible to locate a data base entry in the first layer which may not exactly match the events of the request.
Also disclosed is a concept generally referred to as piping. ~riefly, a preferred method of piping is disclosed which involves the step of locating a data base entry which -~
has at least a predetermined number of event-time values representing events positioned within a preselected number of event positions relative to events in the request.
Preferably an alterable pipe cutoff signal represents such predetermined number of events. The pipe cutoff signal preferably repr-sents the predetermined number of events as a fraction of the number of events in an entry of the reguest and computations are made to determino the 2 actual number of events to be used in the step of interrogating based on the length of various parts of the request. -According to a still preferred embodiment the pre- ;
selected nu ber of evçnt-time values is specified by a pipe width value which may be altered as desired.
3 In addition, the concept of brightness is disclosed. A

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1 preferred method is disclosed whereln piping forms an intermediate entry identification signal. Further interrogation is performed according to brightness in order to locate a data base entry which has at least a preselected degree of match as to order and presence of events, with an entry of the reguest.
In summary then it will now be seen that the piping feature locates entries which meet certain piping criteria and these entries are then used by the brightness feature ,' , N to locate data base entries which have the desired pre-selected degree of match as to order and presence of , events with the entry of the request ~i.e., brightness). ~ , Preferably the preselected degree of match is specified by a brightness value cutoff signal which is alterable by the user.
In a preferred method according to the invention, a length discrimination feature is provided in order to only locate those data ba,se entries which h ve a preselected degree of mntch, as to number of events, as well as order and presence of events.
Preferred methods are disclosed which utilize delimiters for locating entries during the interrogation and generation steps. Although the aforegoing descrlption of the pipe and brightness features deals in large with interrogation 2S and generatlon on a ~lngle layer, it should ~e understood that the same features may be applied on one or more layers in a multiple layer system. Method and means are disclosed herein for interrogating on one layer to locate entries on the first layer which in turn identify events on the second layer. It will be recalled that each second layer event `: -16-- ,t ~
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wiLl have a corresponding vector signal. ~y interrogating such vector signals on the second layer, second layer entries ~re located by using pipe and/or brightness, and it is possible to locate portions of the data base which do not S exactly match the request. For example, the request may be composed of letter events which in turn represent word entries which in turn represent a sentence entry. By interrogating the first layer using the pipe and/or brightness, it i8 possible to locate for each word of the request a word in the data base which most closely matches the word of the request. The~e best words, represented by first layer entry signals, (second layer event signals), are then used to interrogate the second layer of the data base by using pipe and/or brightness. It i8 then possible to find a word in the data base which, although it does not exactly match the request word, i8 the best one represented in the data base. -The same i~ true of a sentence and the words which make up a sentence.
Although the foregoing description has been primarily directed to methods, it will be under~tood that data processing means are disclo-ed which include both hardware and programming for e$fecting the methods described.
Also disclosed are various ways of compacting data which will be described in more detail, One form i~ referred to 2 herein as revolving. ~riefly, an electronic data processor ls disclosed for converting coded signals as follows. The combination of a glven line value signal and a given line number signal i8 formed which together represent a given value. Additionally a number of lines value signal is formed.
~30 Significantly, means is provided for converting such combina-tion of given line value signal and given line number signal ~-~ ~
~Z7767 1 representing each different given value to any combination of equivalent line value signal and line number signal in a uniq~e set thereof which includes the given signals.
Each line value signal represents at least one digitally coded actual occurrence value out of a set of monotonically ordered possible occurrence values. Each line value signal is related to another in the same set by an exclusive OR ~ -of the actual occurrence values thereof and the actual occurrence values thereof relatively shifted. Also provided 0 is means for responding to each different value represented by the number of lines signal for causing the converting means to form a different predetermined one of the equivalent combination of line signal and line number signal within the set which corresponds to the combination of given line signal and given line number signal. Such an arrangement has particular application to systems such as the present one involving vector signal~ which may have an extremely large number of event-time values, as it permits the values to be compacted down to a small fraction of the fully expanded form. Thl~ is particularly zpplicable to vector signals which can be quite long. Signlficantly, as more values are added to a given line value the shorte3t eguivalent line may actually become smallar.
In a preferred embodiment o~ the ~oregolng proco8sor, 2 mean- is provlded ~or causing tho8e relatively shifted occurrence vaIues which are not within the group of possible occurrence values to be eliminated from the equivalent line value signal, contributing to the compaction feature.
According to a further preferred embodiment the number ~3 of lines value signal is represented by one or more signals '~ . ':
~ -18-~ 7f~7 1 representing componen~ powars of two thereby representing increments by which the given signal i9 moved through the equivalent signals.
According to a further preferred embodiment the operation of forming incremental number of lines value signals can be done very fast and conveniently. In such an embodiment, means are provided for determining the larger of the difference between the values of the largest two actual occurrence value signals in the given line and of the difference between the values of the largest possible occurrence value and the largest actual occurrence value in the given line value. Pre~erably means is also provided for forming one or more incremental number of lines value signals representative of the largest difference.
lS According to a still further preferred embodiment, -a data processing compactor for coded signals is disclosed.
This is referred to herein generally as seed finding. In 1 accordance with one such embodlment of the invention the forementioned data processing converting means is provided with means for forming a plurality of incremental number of lines value signals causing the given line to be moved through successive equivalent signals. Means are provided for interrogating the formed equivalent line value signals ~or one of selected length, preferably the shortest. A
signal indiaative o~` tho one of selected length i9 stored.
Preferably, both the equivalent llne value signal and the `-equivalent line number signal are stored as the indicative signal.
Generally it is important to minimize required memory 3~ space and a¢cordingly length of data must be minimized.
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~ ~ f-``) ~ 7~t;'7 1 Therefore, redundancies such as "o"s are preferably squeezed out of data to be stored by means such as an encoder. The compaction operation is preferably arranged to minimize the length of data as it exists after encoding and before storage in memory.
According to a preferred embodiment of the invention, data processing means is provided for outputting signals represented by the line value signal and the line number signal. This feature is generally referred to herein as 0 output. In this connection the data processing converting means disclosed above is provided with means for forming a signal having a value representing the number of possible occurrence values in the set thereof, means for determining a value related to the difference between the number of possible occurrence value signals and the given line number ~ignal. This value is then used by the converting mean~ to form the corresponding equivalent line signal which is the input/output line.
Also disclosed is an electronic data processing coded signal changing means which is capable of changing i~ignals represented by a line value signal and a line number signal.
Significantly the changes need no~ be made at the level of the given signals but can be made in the line value signal of one of the other equivalent signals in the corresponding set of equivalent slgnals. Briefly, to this end there is disclosed means for storing at least the combination of a given line value isignal and a given line number signal which represent a given value. Means are provided for forming a change signa1 representing at least one change occurrence value. Additions and,deletions are indicated in the change ^\
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1 signal. Additional means form a number of lines value signal. Means similar to that disclosed above converts the combination of given line value signal and glven line number signal to one of the equivalent signals in the corresponding set. The equivalent signal is identified by the number of lines signal. Means is provided for exclusive ORing the values represented by the equivalent line value signal and the change signal for forming a change line value signal. Preferably the number of lines value signal represents the difference between the values represented by the given line number signal and the change line number signal. In this way the given line signsl is rotated back to what is referred to as an input line in the equivalent ~ets and then the input line is exclusive 1 ORed with the change signai~
Also disclosed i8 an electronic data processing method for checking for the presence of an actual occurrence value represented by a given line value in the equivalent ~ets. This has been referred to generally as the DEL
2 function. Significantly, the presence of an actual occurrence value i8 to be checked not in the given line but in one of the other equivalent lines. To this end a method is disclosed which utilize~ the value repre~ented by the qiven line number signal for forming a signal representing 25 the number of lines of displacement between the glven line :~-and a desired line value of the equivalent set of line value~.
A test signal is formed repre~enting the desired possible occurrence value to be checked for presence in the desired line value. The values represented by the test signal and the number of lines signal are combined to form a further ''.`.,,~

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1 tes~ signal identi~ying a further possible occurrence value for test. The values represented by ~he test signal and the given line signal are compared for a predetermined relation. The values represented by the further test signal and the given line signal are also compared for a predeter-mined relation. Responding to the results of both comparing steps, a predetermined signal is formed indicating the presence of an actual occurrence value, in the desired line value, equal in value to that represented by the test 0 signal. In addition to the method, means are provided for checking for presence.
In the compacting method and means, preferably the vector signals are encoded from a compact code to an expanded code before conversion to an equivalent signal.
Also preferably the equivalent line value i~ converted from an expanded code back to a compact code before length is checked using encoding techniques. A preferred encoder i8 disclosed for converting to hybrid form a received series of absolute coded words in decreasing value order which represent the vector signals. In such encoder, means is responsive to received previous and current absolute words for forming an output signal indicative of the difference.
Abæolute or bit string form of hybrid output is indicated.
To this end, means is provided for indicating a preselected 2 minimum difference between successively received absolute words for absolute form of output, and mean~ is provided for comparing the minimum difference indication and the previous and current difference signal for indicating the -value of the first being greater than, or less than or 30 equal to the latter. Absolute form outputs are provided. -~

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~.. -- . -Y f : ' .' ~'.~,,,,,.' . ~ ''~ . '.'',:"~',''' ..'' ''' ''' ~-~, ~ ~
~ 7~i7 1 To this end, means is operative in response to the les~
than or equal to indication for outputting the stored current absolute word and an absolute flag. Bit string fonm outputs are also provided. To this end, there is means which is responsive to the greater than indication for forming a set of ordered signals comprising a binary bit of one value (i.e., "1") separated by the number of -binary bits of a second value (i.e., '!on) corresponding ~-to the value of the previous and current difference signal. - ~-0 Additionally, means selectively outputs the set of signals in association with a bit string flag and in a predetermined -relation to an outputted absolute word. In this manner, absolute words are converted to a hybrid form of encoding.
A preferred form of the decoder converts hybrid coded -signals to absolute coded signals. In the system this decode operation is performed on hybrid coded vector signa}s coming }rom memory. The hybrld signals represent a series of occurrençe values of decreasing value order.
$he hybrid signal~ comprise a serie~ of received binary 2 coded word signalQ including at least one ab~olute coded ;~
word and a bit string word. The bit string word represents an occurrence by the number of bits of displacement of a bit of predetermined value from an absolute word in the series of hybrld words. The hybrid word al80 has a flag indicating the type of word. The decoder includes an absolute word outputting arrangement that includes means ;
responsive to an absoIute word flag signal of a received ~-~ ~ , .
`~ hybrid word for outputting the received word signal. Also provided is an absolute word outputting arrangement that ~30 includes means responsive to an absolute word signal and each bit of predetermined value in a following bit string ':' -7~;7 word sigllal for forming an absolute word signal for output indicative of the actual value of each said bit of predetermined value. In this manner retrieved vector signals are converted from hybrid form to absolute word form, each absolute word representing an actual occurrence value.
In accordance wi.th t~e present invention as claimed in this divisional appli.cation there is provi,ded an encoder for convert- :
ing to hybrid form a received series of absolute words in a decreasing value order comprisi.ng:
a~ means responsi~e to rece.ived previous and current absolute words for forming an output signal indicative of the difference therebetwee,n;
b~ means for indicating absolute or bit string form of hy~rid output comprising .. .
lS 12 means for indicating a preselected minimum ~.
difference ~etween the values represented by successively received absolute ~ords for a~solute form of output, , 2~ means for comparing the minimum difference indication and the previ.ous and current difference signal and .' for indicating the value of the first being greater than, or less than or equal to the. latter;
C2 means for providing absolute form outputs camprising:
1~ meang operative in response to said less than or ,,' equal to indication for outputting the stored current absolute word and an absolute flag; and -,~
d2 means for pro~;.ding ~it string form ou~puts comprising:
1), means responsi.ve to said greater than indication ;~
for forming a set of ordered si.gnals comprising a binary bit of one value in association Wlt~. the number of binary bits of a .;

3Q second value corresponaing to the value of saia previous and ~. , 7~i7 current diff~rence signal, and 2) means ~or sel~ctively outputting sai~ set of signals in association wi.th a bit string flag and in a predetermined relation to an outputted absolute word.
Also in accordance wi.th the present invention as claimed in :
thïs applicatlon there is provid.ed an encoder for converting to -hybrid form a received series of absolute coded ~ords in decreasing value order COmpriSLng:
a~ a current regi.ster for storing a currently received --absolute word; .
b), means for storing a recei.ved absolute word in said current register; ~, c~ a previous register for storing a ~ord received prior ..
to the word in said current register; ' .:, d~ means for transferring a word from said current .
register to saia previous, register; ., e.l means responsive to the stored previous and current :' '-absolute wvrds for forming an output si.gnal indicative of the ,''' :
di.fferences in value therebetween; ':,-f~ means for retaining the previous and current difference :'.' si.gnal; .. -gl means for Lndicating absolute or bit string form of hybrid output comprIsing: ...
1~ means for indicating a preselected minimum difference in value fietween rece.~ved afisolute words for absolute form of output, ....
2~ means for comparing t~e minimum difference .'.
indication and the retained previous and current difference .:
signal and for indicating t~e value of the first fieing greater .'' than, or less than or equal to, the latter;
, - 24 ~

~2~7~7 h~ means for providing absolute form outputs campri~ing:
1) means responsibe to saii'. greater than indication for outputting a signal representing the stored current absolute word and an absolute flag; and i~ means for providing bi.t string form outputs comprisiny:
l) means responsive to said less than or equal to indicatïon for forming a set of ordered signals, comprising a binary bit of one value in association with bi.nary bits of a second value.the number of ~hich corresponds to the value of said retained previous and curre.nt difference signal, and .
2~ means for selectively outputting a signal representing said set of ordered signals in association with a bit string flag and in a pre.determined relation to an outputted absolute word.
Further in accordanc~ with the pre~ent invention as claimed in this applicat;on there is provided a decoder for converting hybrid coded signals to absolute coded word signals, the hybrid ~;
signals representing a serles of occurrence values of decreasing value, the hybrid signals comprising a series of received :
2Q binary coded word signals i.ncluding at least one absolute coded word and a bit string word, the bit string word representing an occurrence by the number of bits of displacement of a bit of predetermined value either from another bit of the same predetermined value or from the value represented by an absolute word in the series of hybrid words, a hybri.d word comprising a flag signal indicating the type of word comprising:
a~ absolute word outputting means comprising means responsive to an absolute word flag signal of a received hy~rid word signal for outputting the received word signal; and ' ', ~4 .

-76~

b~ absolute wo.rd signal formi.ng and outputting.means comprising:
11 means respons.ive to an absolute. word si.ynal and each said bit of prede.termined value in a subse.quent bit string word signal of a received hy~ri.d signal for forming an absolute word signal indicative of actual value of each said bit of predetermined value, and ::
2~ means for outputting each said formed ahsolute .:
word signal. - .
Further in accordance.wi.th the. present invention as claimed .:.
in this application th.ere. is provided a decoder for converting hybria coded signals to absolute coded word signals, the hybrid .- .
signals representing a serles of occurrence values of ~ -decreasing value, the ~ybrid signals comprising a series of ..
received binary coded wora signals including at least one ~.
ahsblute coded word and at l~ast one bit string word, the bit string wora representing an occurrence by the num~er of bits .
of aisplacement of a bit of pre.determined value from an absolute word in the series of hybrid words, a received word comprising a flag signal indicating the type of word, comprising: :
a) absolute word outputting means comprising means responsive to an absolute word flag signal of a received word signal for outputting the received word signal; and b) absolute word signal forming and outputting means comprising:
~; 1) shift register means for storing a received bit ...
~:~ string word signal, 2) means for repeatedly enabling the shifting of the -.
content of the shift register means one bit position in the .

.

'~:
'' .

direction of the least signifi.cant bit of the bit string word signal, 3) means for providing an indi.cation when a bit signal indicative of said predetermined value arrives at a preselected position with.respect to the shift register means, 4) counter means, 5) means responsive to a flag signal indicating a received absolute word signal for setting said counter means ..
to a state relative to a reference state corresponding to tbe :
1~ value of such absolute word signal, 6) means for enabling said counter means to count one state towards said reference state for each such shift of ..
said shift register means, and 7) means responsive to said indication of a bit for --outputting a signal corresponding to the state of said counter means. -. - 24 D -: ' ~.,f~7'~

1 ~rief Description of the Drawing~
Fig. 1 is a general block diagram of the data processing machine (DPM);
Figs. 2, 3 and 4 form a schematic and block diagram of the ENCODE MODULE;
Fig. 5 is a diagram ~howing the relationship of Figs. 2, 3 and 4;
Fig. 6 is a schematic and block diagram of the ALU used in various modules in the DPM SYSTEM;
Figs. 7 and 8 form a flow diagram illustrating the sequence of operation of the ENCODE MODULE;
Figs. 9 and l0 form a schematic and block diagram of the :--DECODE I MODU~E;
Fig. 11 is a flow diagram illustrating the sequence of -lS operation of the DECODE I MODULE;
Figs. 12, 13 and 14 form a schematic and block diagram of the DECODE II MODULE;
Fig. 15 is a schematic and block diagram of the DELTA
MODULE;
Fig. 16 is a flow diagram illustrating the sequence of operation of the DELTA MODULE;
Fig. 17 is a schematic and block diagram of the REVOLVE

Figs. 18A and 18B form a flow diagram illuQtrating the 2 sequence of operation of the REVOLVE MODU~E;
Fig. 19 i5 a block diagram of an iso-entropicgram revolver employing the REVOLVE MODULE;
Figs. 20 and 21 form a schematic and block diagram of the SEED MODULE;
3 Fig. 22 is a flow diagram illustrating the sequence of operation of the SEED MODULE;
- '."

--~
1.~.~7~7 1 Fig. 23 is a block diagram of a seed finder and employing the SEED MODULE;
Fig. 24 is a schematic and block diagram of the CHANGE MOD-lLE;
Fig. 25 is a flow diagram illustrating the sequence of operation of the CHANGE MODULE; -Fig. 26 is a block diagram of a seed line changer employing the CHANGE MODULE;
Fig. 27 is a schematic and block diagram of a generalized clock control unit for use in designated modules;
Figs. 28,29,30 and 31 form a schematic and block diagram of the OUTPUT MODULE;
Figs. 32 and 33 form a flow diagram illustrating the -sequence of operation of the OUTPUT MODULE; -Fig. 34 is a block diagram of the compaction and retrieval machine employing the OUTPUT MODULEt Figs. 35,36,37 and 38 form a-flow diagram illustrating the sequence of operation of the PIPE MODULE;
Figs. 42A-D are graphs used to illustrate functions of the BRIGHTNESS MODULE;
Figs. 43,44, 45 and 46 are schematic and block diagrams of the ~RIGHTNESS MODULEi;
Fig~. 47,48,49 and 50 form a flow diagram illustrating the sequence of opera~ion of the BRIGHTNESS MODULE~
2 Figs. 51,52 and 53 form a schematic and block diagram of the DPM IN~ERFACE MODULE which includes the IP~F;
Fig. 54 shows the I/O bus 1220 structure;
;~ Figs. 55 and 56 form timing diagrams representing the ~equence of operation of I/O bus output and input operations;
\3 l Fig. 56A is a schematic and block diagram showing the control for the BDONE flip flop in the DPM INTERFAC~ MODVLE;

L ~ ! :; ; i,.. : .; ., , ~,., .. '. , ,',, ' .
... ~ . .

~ f`) ~J.,~7~7 1 Fig. 57 is a schematic and block diagram of the MEMORY
MODULE;
Fig. 58 is a write enable pulse diagram for the MEMORY MODULE;
Fig. 59 is a schematic and block diagram of the SWITCH MATRIX;
Fig. 60 is a schematic and block diagram of the P/B MEMORY;
Fig. 61 is a block diagram of an alternate data processing machine (DPM 2);
Fig. 61A, 61B and 61C form a schematic and block diagram of the ENCODE MODVLE for the DPM 2 system;
Fig. 61D and 61E form a schematic and block diagram of the DECODE I MODULE for the DPM 2 system;
Fig. 61F, 61G and 61H form a schematic and block diagram of the DECODE II MODULE for the DPM 2 system:
Fig. 62 is a ~chematic and block diagram of the DELTA 2 MODULE for u8e in the alternate machine of Fig. 61;
Fig. 63 i8 a flow diagram for the DELTA 2 MODULE;
Fig. 64 i8 a schematic diagram of the implies circuit of Fig. 62 Figs. 65 and 66 form a schematic and block diagram of the REVOLVE 2 MODULE~
Fig. 67 i8 a flow dlagram for the REVOLVE 2 MODU~Et Figs. 68 and 69 form a schematic and block diagram of the REVOLVE 3 MODULE;
~;~ Fig. 70 is a flow diagram for the REVOLVE 3 MODULE;
Figs. 71 and 72 form a schematic and block diagram of the SEED 2 MODULE; , 3 Fig. 73 is a flow diagram for the S~ED 2 MODULE;

, ,, ~'7'~'G~

1 Figs. 74 and 75 form a schematic and block diagram of the OUTPUT 2 MODULE;
Figs. 76 and 77 form a flow diagram for the OUTPUT 2 MODULE;

Fig. 77A is a schematic and block diagram of the CHANGE 2 MODULE;
Fig. 77B is a flow diagram for the CHANGE 2 MODULE;
Fig. 77C is an example of how information is moved between areas of the MEMORY 2 MODULE during operation of the CHANGE 2 MODULE;
Fig. 77D is a schematic and block diagram of the Fig. 77E is a schematic and block diagram of the SWITCH MATRIX 2;
Fig. 77F is a schematic and block diagram of the AUXILIARY MEMORY 2;
Fig. 77G is a sketch showing the generalized diagram of the software;
Fig. 78 is a generalized sketch showing the data structure for each layer;
Fig. 79A i8 a sketch showing an example of the data structure for layer 0;
Fig. 79~ is a sketch showing an example of the data structure for layer 1;
2 Fig. 79C is a sketch showing the generalized design of the software;
Fig~. 80 and 81 form a PARSER program flow diagram;
- Figs. 82-84 form a PIPE program flow diagram;
Fig. 85 is a sketch illustrating the address linkage ~3 during PI 2 2 et seq. of the PIPE program;
' .

l -28-~77~7 1 Fig. 86 is a sketch illustrating the address linkage during PI7 of the PIPE program;
Fig. 87 is a sketch illustrating the address linkage during PIll of the PIPE program;
Figs. 88-93 are sketches illustrating the sequence of operation and primary storage areas during the operation of the PARSER, PIPE and ~RIGHT programs;
Figs. 94-96 are BRIGHT program flow diagrams; -Fig. 97 is an OUTPUT subroutine flow diagram;
Fig. 98 is a MEMDPM subroutine flow diagram;
Fig. 99 is a DP~ME~ subroutine flow diagram;
Fig. 100 is a DECODE I subroutine flow diagram;
Fig. 101 is an INSERT subroutine flow diagram;
Fig. 102A is a pictorial flow diagram illustrating the operation of the FORMATER program during a layer 0 request;
Fig. 102B $g a pictorial flow diagram for the operation of the FORMATER program during a layer 1 request;
Fig. 102C is a FORMATER program flow diagram;
Fig. 103 i~ a COMMAND subroutine flow diagram;
Fig. 104 i8 a GET INTEGER subroutlne flow diagram;
Fig. 105 i~ a GET FLOATING POINT subroutine flow diagramt Fig. 106 i~ a REQUEST ~ubroutine flow diagramt Fig. I07 1~ a PROCOUT ~Pro¢ess Output) subroutine flow 2 diagramt Fig. 108 is a sketch glving an example and illustrating the correspondence between G2$BL table and the OLIST list;
Fig. 109 i9 a SETUP subroutine flow diagram;
Figs. 110 and 111 form a GENERATE subroutine flow ~ ~30 diagram;
:~

,~ . I

--~ 7~7~7 1 Fig. 112 is a SORT subroutine flow diagr~m;
Fig. 113 i8 a PRINTR ~Printer) subroutine flow diagram5 Fig. 114 is a conceptual view of the prior art data base system Fig. 115 is a conceptual view of a layered data base system according to the present invention;
Fig. 116 is a sketch illustrating layerinq data base structure of the data base;
Fig. 117 is a sketch illustrating conversion tables CVRTBL and CVTBL2;
Fig. 118 is a sketch illustrating ESTAK;
Figs. ll9A-E are sketches illustrating available used space management for the seed lines;
Fig. 120 is a sketch illustrating an example of the 15 layered data structureæ after initialization: ~
Fig. 121 is a DATA BASE program flow diagram -Fig. 122 i8 a layer INITIALIZATION program flow diagrams Fig. 123 is a LAYER BUILDING program flow diagram;
Fig. 124 i~ a PROCESS ENTRY program flow diagram;
Fig. 125 i8 a PROCESS A LAYER 0 ENTRY subroutine flow diagram~
Fig. 126 is an ADD N EVENTS subroutine flow diagram;
Fig. 127 is a PUT NEW SEED IN STORAGE program flow diagramt 2 Fig. 128 1~ a SEARCH FREE SPACE program flow diagram;
Flg. 129 i8 a RELEASE SPACE subroutine flow diagram;
Fig. 130 ls a GARBAGE COLLECTION program flow diagram;
;~ Fig. 131 is an ADJUST SEED HEADER subroutine flow diagram;
3a . `

~ -30- ' L ~ ~

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~ 7767 I N D E X
1 . '~
Contents Page I. GENERAL DESCRIPTION OF DPM SYSTEMS...... 31 A. Data Base Structure ............... 31 B. Iso-Entropicgram Techniques........ 36 C. Changes ........................... 46 D. Verifying Presence of an Occurrence Value at Input Line ....................... 49 E. Hybrid Coding ..................... 51 F. Conventions and Component~
Used in the Figures ............... 55 I-A. GENERAL ORGANIZATION OF DPM SYSTEM
OF FIGS. 1-34 ........................... 61 II. ENCODE MODULE ............................ 67 lS A. General Description ................ 67 B. Components ......................... 70 C. Detailed Descriptlon ............... 73 D. Example of Operation ............... 94 ~ .

III. DECODE I MODULE ......................... 111 A. General Description ................ 111 B. Components ......................... 112 C. Detailed Description ............... 115 2 D. Exampl- of O eration ............... 126 :~
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~ 7~67 I I N D E X
¦ (Cont'd.) I Page 5 ¦ IV. DECODE II MODULE........................................ 137 ¦ V. DELTA MODULE ........................................... 139 ¦ A. General Description.................................. 139 ¦ B. Components........................................... 140 -~
¦ C. Detailed Description................................. 142 10 ¦ D. Example of Operation................................. 149 ¦ VI. REVOLVE MODULE ......................................... 152 A. General Description.................................. 152 ¦ B. Components..............~............................ 155 ¦ C. Detailed De~criptlon......... ........................ 157 15 ¦ D. Example of Operation......... ........................ 179 ~
¦ VII. RE W ~VER............................................................. 190 ;--¦ VIII. SEED MODULE ......................................................... 194 ¦ A. Gen-ral Descriptlon.................................. 194 ¦ B. Components........................................... 196 20 ¦ C. Detailed Descript~on................................. 198 ¦ D. Example of-Operation................................. 217 ¦ IX. SEED FINDER............................................. 221 ¦ X. CHANGE MODULE .............~............................ 228 l A. General De~cription........... .................... ,. 228 25 ¦ L. Components..............,.~... ,.................... , 230 ; ~ ¦ C. Detallèd Description.......... .... ................. , 231 ¦ D. Example of Operation.......... .... ................... 239 ¦ XI. SEED LINE CHAN OE R..~................................... 242 ¦ XII. GENERALIZED CLOCK CONTROL............................................. 243 30 I ' --30b- ~

; ~'... I :'''.
::; ~ ' ~l2~7~7 ~Cont'd.) Page 5 XIII. OUTPUT MODULE ....................................... 246 A. General Description............................ 246 B. Components..................................... 248 C. Detailed Description........................... 250 D. Example of Operation........................... 276 10 XIV. DATA COMPACTION AND RETRIEVAL
MACHINE........................................... 285 XV. PIPE MODULE .............................. 293 A. General Description.................... 293 B. Components............................. 306 C. Detailed Description................... 308 XVI. BRIG~TNESS MODULE .................................. 365 A. General Description............................ 365 B. Components..................................... 376 C. Detailed Description........................... 379 20 XVII. DPM INTERPACE MODULE................................. 449 XVIII. MEMORY MODULE..................................... 475 XIX. SWITCH MATRIX....................................... 482 XX. P/B MEMORY......................;............ 490 XXI. OE NERAL ORGANIZATION OF ALTERNATE
2 DPM SYSTEM 2............................ .. 493 A. General Discu~sion................... .. 493 B. Revised ENCODE MODULE................ .. 496 - C. Revised DECODE I MODULE.............. .. 498 ¦ D. Revised DECODE II MODULE....................... ~ 499 ¦ E. PIPE and BRIG~TNESS MODULES...................... 500 -30c-L

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l~Z~767 I N D E X
~Cont'd) Page 5 XXII. DELTA 2 MODULE ......................... ..501 A. General Description............... ..501 - B. Components......................... ..504 C. Detailed Description.............. ..507 D. Example of Operation.............. ..514 10 XXIII. ~EVOLVE 2 MODULE....................... ..521 ! A. General Description............... ..521 B. Components........................ ..523 C. Detailed Description.............. ..525 D. Example of Operation.............. ..544 15 XXIV. ~EVOLVE 3 MODULE ....................... ..558 A. General Description............... ..558 B. Components........................ ..560 . Detailed Description............. ..561 D. Example of Operatlon.............. ..579 20 XXV. SEED 2 MODULE ........................... ..S96 A. General De cription............... ..596 B. Components........................ ..603 C. Detailed Description..... ;........ ,. 605 D. Example of Operatlon..... ,........ ..617 25 XXVI. OUTPUT 2 MODULE .................. ...... ..623 A. General Description......... ...... ..623 B. Component~................. ...... ..627 C. Detailed Description....... ...... ..627 D. Example of Operation....... ...... ..646 -30d-Il ,~

:-' ~ Z77f~7 (Cont'd.) Page XXVII. CHANGE 2 MODULE ....................... . 653 A. General Description................... 653 B. Components........................... 654 C. Detailed Description................. 654 D. Example of Operation................. 661 0 XXVIII.MEMORY 2 MODULE......................... 663 XXIX. SWITCH MATRIX 2.......................... 664 XXX. AUXILIARY MEMORY MODULE II~ o~ 666 XXXI. COMPUTER, DATA BASE & SOFTWARE
ORGANIZATION ........................... 671 A. MINI COMPUTER........................ 671 B. General Description of Data ~ase Structure....................... 672 C. General Description of Software............................. 673 1. Data ~ase Initialization .. 674 2. Layer Building ................ 675 XXXII. INQUIRY AND RETRIEVAL HARDWARE/
80FTWARE ORGANIZATION ................... 682 A. General Description of Inquiry and Retrieval Software............... 682 D. FORMATER program...................... 718 C. PARSER program........................ 721 D. PIPE program......................... 730 I E. BRIGHT program....................... 749 F. OUTPUT subroutine.................... 765 G~ MEMDPM subroutine.................... 769 ~1 3 H. DPMMEM subroutine.................... 772 I. n~coDE I subroutine................. ~773 -30e-I ~`

~ 7'7~;7 l I N D E X
(Cont'd.) Page J. INSERT subroutine...................... 775 . COMMAND subroutine..... ,............... 779 L. GET INTEGER program.......... ,.................... .789 M. GET FLOATING POINT program......... ............... .791 N. REQUEST subxoutine........... ~.................... .794 O. PROCOUT (Process Output) 802 subroutine P. SETUP subroutine...................... .809 Q. GENERATE subroutine................... .814 R. SORT subroutine....................... .820 S. PRINTR (Printer) subroutine........... .823 T. PRNTC ~Print a Character) subroutine........................... .825 U. GETC ~Get a Character) ;~
subroutine........................... .826 XXXIII.HARDWARB/SOFTWARE ORGANIZATION FOR
BUILDING LAYERED DATA BASE .............. .828 A. LAYERED DATA BASE STRUCTURE....... ,... .828 -B. DATA BASE program, Level 1........... . .848 C. LAYER INITIALIZATION program, Level 2............................. . .851 D. LAYER BUILDING program, Level 2............................. . .856 E. PROCESS ENTRY program, Level 3.,...... ,.. ,,,,,.,,.,,.,,,, 859 F, PROCESS A LAYER 0 ENTRY
subroutine,,,,,.,.................... .868 G. ADD N EVENTS subroutine, -Level 1.......................... ~... .872 H. PUT NEW SEED IN STOR~GE program, -Level 2........ ,..................... , 879 ` -30f-~. ~

('''~

fi7 I I N D E X
(Cont'd.) Page I. SEARCH FREE SPACE program, Level 3............................ ..... 884 J. RELEASE SPACE SVBROUT.INE FLOW, Level 3............................ ..... 886 K. GARBAGE COLLECTION program, Level 3...... ;.......................... 888 L. ADJUST SEED HEADER
subroutine......................... ..... 890 ; AppENDIx A -.... -................................................ 892 1 Index of Tables.................................... 892 , Tables............................................. 896 ~i ' .
15 ¦ APPENDIX B .................................................... 1002 ¦ Index of Program Listings.......... 1002 ¦ Program Listings................... 1004 I
20 I ~:

I ,. :.',:' I . ' ' ''''.
2~

~ I

I' I . ,' I
:~ I -30g-':~ I . ,.
I 1.

!~ --) ~ ~ ~7767 1 I. GENERAL DESC~IPTION OF DPM SYSTEMS
A. Data ~ase Structure Fig. 1 depicts a general diagram of an information storage and retrieval system and embodies the present invention. The system of Fig. 1 is referred to herein as a data base management (DPM) system. The DPM system is `
designed to perform certain general data base management functions, as follows. First is the "enter" function which is the a~ility to enter information into the data base. Second is the "update" function which is the ability to change or delete information in the data base. Third is the ~retrieval" function which is the ability to retrieve information from the data base, and the fourth is the "discrimination" function which enables the user ~-to discriminate upon the information in the data base.
The discrimination function is referred to herein as the ~-"piping and brightness" function.
In order to understand the above four functions, it is imperative that one first understands the structure of the data base and the technique of storage for the data base.
All incoming information to the DPM system is re~tructured by the MINI COMPUTER into a layered data base in its main memory. Each layer i8 a logical ent~ty or a group of entities ~alled ~eventsn. Each of these avents i8 separated 2 by a delimiter from a set of delim~ters for the layer. The group of events between two subsequent delimiters is referred to as an "entry". Layering is hierarchical in that the higher level layers encompass the lower level layers. For example, if one were to structure contextual data base, the following levels may exist: layer 3 consisting of sentences; ;

,- '~
,, f~ r~

~ ~.Z7767 1 layer 2 consisting of phrases; layer 1 consisting of words;
and layer 0 consisting o letters. Each layer has appro-priate and distinct delimiters. However for purposes o~
illustration only a two layer system is specifically disclosed. One layer is for words and the second for sentences.
Table 1 is an example of the word layer 0. Each occurrence of an event is represented by a 1 whereas an 0 represents the lack of an event. As depicted, the layer may be visualized as having two dimensions referred to as lines (or rows) and columns. The number of lines is equal to the number of events in the layer. The number of columns is equal to the number of possible occurrence values for ~-each event.
Entries are viewed as a series of events occurring in time. Each column is assigned an event-time, or possible occurrence value, from left to right in increasing monotonical value order. Table 1 depicts layer 0 for the sentence "THIS
IS A TEST~. ~ine 0 of layer 0 contains the delimiter ~
~representing a textual blank) which actually separates the words of the sentence. Line 1 designates the T events.
Line 2 designates the H events. Line 3 des~gnates the I
events. Line 4 designates the S events. Line S designates the A evènt~. Line 6 designates the E event~.
2 Since the events can be considered as a series of chronologically occurring event-times, each event is ;
represented in the layer by a binary 1 in the appropriate ;~ line and column. Thus, if the event-times can be considered as being represented by an occurrence clock, each time a 1 . ..
~3 is entered in the layer corresponding to an event the occurrence clock in increased by 1. This is depicted in `
' . -~ -32-~ ; " ' ' ' ' ' . ' ' ' ! :' '` .. ,- ~, f~
~ 77f~

1 Table 2A. Thus a delimiter ~ occurs at event-time 0, the letters T-H-I-S occur at event-times 1, 2, 3 and 4. A
second delimiter ~ occurs at event-time 5. The letters I-S appear at event-times 6 and 7. Another delimiter ~
appears at event-time 8. The letter A appears at event-time 9. Another delimiter ~ appears at event-time 10 and the letters T-E-S-T appear at event-times 11, 12, 13 and -14. The ending delimiter ~ appears at event-time 15.
All of the events in any one line are represented by ~-10 an occurrence vector. The occurrence vector is represented -by the occurrence values of an event shown at any particular line. Occurrence vectors are shown in Table 2B, for each line of Table 1, as a series of decimal occurrence values. ~ -Thus, for example, a "delimiter occurrence vector" for lS the delimiter ~ event is depicted in the first line of Table 2. Similarly, the event occurrence vector for the letter T is depicted at the second row of Table 2, etc.
Table 3 depicts a sentence layer 1 for the sentence HTHIS IS A TEST". The symbol "." i8 used as the delimiter ~ -20 symbol to delimit phrases. The first occurrence of ".- -i8 implied, forming the initial leading delimiter for the word layer. A number of different types of delimiters may be assigned to each layer (e.g " ~ - n; H, n; ~; n; etc.) and can be selected as desired by the user. The possible occurrence value at which each delimiter oacurs in layor 0 is used as an implied llne pointer to laye~ 1. The line pointer is formed by assigning a value corresponding to the relative position of the events in line 0 of Table 1 and --adding thereto a bias. The implied pointers of 1, 2, 3, 4 ~-3 and 5 are depicted at the bottom of Table 3.
~ ~ ' ' ,':~.', -~ (' ~
~ 7 1 Consider now an example o the sequence of operation required in layering the phrase ~ THIS ~ IS ~ A ~ TEST ~ .
Considering the examples of Tables 1 and 3, in an actual example of the system, the first delimiter ~ is implied and not physically present in the input stream. A line or event counter is used to keep track of each new event for each different layer. In addition, an event-time clock for each layer is provided for identifying event-times, or possible occurrence values.
1 Initially, the line and event-time clocks for each layer are initialized by setting them to 0. The lowest layer, layer 0, is tagged with event names, in this case the binary representation of the character assigned to ~ -the line. This-is not done with higher layers.
1 The implied delimiter ~ is the first possible occurrence value encountered in the input phrase. Since this i9 not present in layer 0, the ~ is assigned to the next available line, line 0, by the line counter. The first delimiter occurrence is marked by placing a binary 1 in column 0, ~-2 llne O corresponding to the state of the event-time clock and the line counter. The line counter and the event-time clock are then lncremented by 1. The event-time clock now identifies event-time 1, and the line counter identifies ~ -lln~
2 For eaoh event line, zeroes are used to flll in the posit~ons in which a 1 i8 not entered.
The next event to be encountered is the T in the word -NTHIS". Accordingly, a 1 is entered at line 1, column 1, corresponding to the 1 states of both the event-time clock and the line counter. The event-time clock and the line _34_ ., . ~.

1 counter are then incremented by 1. This operation continues until the "~ THIS" has been entered in layer 0. The next event to be encountered is the end delimiter ~. The line counter is then reset to 0 and at this time the event-time clock i8 at 5. Accordingly, a 1 is entered at line 0, column 5. The complete word event ~ THIS ~ has now been entered on layer 0 and is to be processed on word layer 1.
The first occurrence of the ~, n phrase delimiter is implied and is therefore entered at line 0, column 0, corresponding to the event-time clock and line counter for layer 1. The --event-time clock and line counter for layer 1 are incre-mented by 1 and a 1 is entered at column 1, line 1, -corresponding to the word THIS.
Next the series of input events HIS ~1l are encountered.
First, letter layer 0 is checked to see if there is an -event line in existence for each of the characters IS ~.
Since the events, I, S, ~ have previously occurred, but not in that order, only the event-time clock ls incremented for each of these events and the line counter is appropriately positioned to identify the 11nes corresponding to each of these event-. ~
A new event line is not added to layer 1 if the event ;~-has already occurred. Rather, only an occurrence mark is -`~
added at the appropriate column of the line corre~ponding 2 ¦ to the event. A sequence of evantæ between two delimiters 18 not added to the same event layer a 8econd time if an implied pointer exi8ts to a higher lsyer. Instead, the series of events between the two delimiters will be represented and entered in the layered system aæ an occurrence mark on '--3 the next higher layer, and nothing needs to be done on the lower layer.
~.

.? --35--. .:''"

-~
~J.Z7767 1 To be explained in more detail hereinafter, the DPM
system of Fig. 1 implemen~s the layering concept by representing data, not in lines and columns, but by occurrence vectors which repreYent event-time by actual occurrence values.

B. Iso-entropicgram Techniques Information is not stored in the DPM system directly '--in the event-time form shown on Tables 1 and 3, but is --translated into a special compacted form. The compaction is referred to herein as iso-entropic compaction. Specifically, an occurrence vector or a word of information is represented by a givei line value and ~enne number. Each given line value and line number has a set of equivalent line values 15 and line number values which include the given line value --and line number. Each equivalent representation has the same information content. Each line value represents at least one digitally coded actual occurrence value out of a set of possible ones. Each line value is related to another in the same set by an exclusive OR of the values thereof and the value~ thereof relatively shifted. The set of equivalent line values form an iso-entropicgram.
The repr-sentations in the set are o} various lenqths ' - -when leading 0'8 are di~regarded. ~he shortest one i8 .
referred to as the ~seed". Most retrieval operations from the DPM ~ystem, along with the operations that change or modify the data base, ara carried out directly on the ~ .
seed and therefore are very eficient compared to conventional data base'techniques.
3 Table 4-A gives an example of an isQ-entropicgram using~ ' ~; binary l's and 0's. Each line represents one of the ~ I' ~ (-' ~
~77~i7 1 representations of the complete set. The input line is depicted at the top of line 0. Referring to the input line, it will be s~en that there are actual occurrence values 0, 1, 2, 4 and 6. Each line, moving down in the iso-entropicgram, is formed by shifting the binary bits of the preceding line in the iso-entropicgram by 1 bit position to the right and exclusive ORing the bits (or values) of the unshifted line with the shifted line. The Hexclusive OR" is referred to herein as an XOR. An XOR
10 operation on binary coded information is a bit by bit `` I
half-add with a deletion or truncation of those resultant bits which, ac a result of the shift, exceed the number of bits in the original unshifted line. In this case, -;
the binary bits that are truncated are those to the right ~"
of the largest event-time or po~sible occurrence value 7.
Refer now to Table 5 and consider in detail the way in which line 1 is formed from line O of Table 4-A. The `~
top two lines of Table S depict line O unshifted and line O shifted to the rlght by 1 binary bit. The vertical 20 line indicates the point at which truncation occurs. The ``
remaining bit~ of the shifted and unshifted line O are XOR'd resulting in line 1 of the iso-entropicgram. This process is repeated, using line 1 ~o form line 2, and using line 2 to form llno 3, etc. It will be seen that after a number o lines equal in number to the number o~ bits in the ; input line have been generated, the next line to be generated is the input line, also referred to as the output line. Note for example that lines O through 7 of Table 4-A are each dlfferent, whereas 11ne 8 i8 the same as line 0, the input 3 line. The iso-entropicgram is closed on itself, lines O
and 8 being identical.
.~-~. -37- 1 --~
~,~,,f~"^t'~;~ ' 1 The process of going from one line to another in the same iso-entropicgram is reerred to herein as "revolving".
One limitation imposed on the iso-entropicgram is that the number of bit positions, i.e., the width, must be an integral power of 2 te.g., 1,2,4,8,16, etc.). It will also be found that in an iso-entropicgram, one can look down through the columns and pick any number of columns which are an integral power of 2 and the bits in these columns will repeat every integral power of 2 lines. By way of example, columns O and 1 repeat at line 2; columns O, 1, 2 and 3 repeat at line 4; columns 0, 1, 2, 3, 4, 5, 6, and 7 repeat at line 8; etc.
It will further be seen that as the lines of an iso-entropicgram are formed, past occurrence information appears 15 ¦ to progressively sweep across the iso-entropicgram, influencing representatlon of later information. The sweeping in the iso-entropicgram of Table 4-A appears to sweep to the right.
For example, at line 7, the information in line 0, column 0, has interacted with every column to the right and, in fact, all columns have interacted with columns to their right.
Table 6 illustrates this point by using, as the input line, the baslc iso-entropicgram pattorn created by a single ¦ binary coded bit of occurrence information. The basic pattern depicted in Table 6 has been named the "delta"
pattern, partly because of its rough siDilar1ty to delta . modulation and partly because the physical shape outlined by the l's appears like the delta symbol. The iso-entropicgram produced ln Table 6 is actually a result of the interacting ~ ~ . , j.

.~ !~

~ ,7~;7 1 pattern~ produced by ~he delta~s position at the ~nput line, Another example o' ~he delta interaction i9 depicted in Table 7 wlich 3hows an iso-entropicgrarn w~th the 0~8 le~t out for clarity. Here it will be seen that the deltas are outlined; therefore their interference occurs at line 4.
The interference pattern produced by the interaction of ;
these deltas has similar properties as those of an optical hologram. Thus, in an optical hologram, each point is the combined re~ult of a reflected beam whose intens~ty and path ~-distance is a function of the scene reflecting t~ beam m e recorded intensity at each point i8 a result of the combined intensities of the two beam~ and the phase displacement be~1een them caused by the reflected beam's path length. :-lS Similarly, the information at each point in the iso-entropic~ram of Table~ 6 and 7 is the result of t~o information intensities (binary 0 and binary 1) and the phasing between them. At each point, past information i8 analogous to the optical hologram's reflected beam, and the presont information to its direct beam.
Inform~tion ~tored in the iso-entropicgram is highly redundant. Ths each llne of the iso-entropicgram forms one representation of a complete set of equivalent representa~ions, All llnes form the compl~te set.
2S Each line represents a new encoding or transormation of the input line. Addit~onally, it has been found that ;~ large sections of the iso-entropicgram can be eliminated but the entire iso-entrqpicgram can be reconstructed from the remaining bits and pieces, using the interrelations of the ` -~3 lines and columns.

-39- `
,,, i.

(~

~ 7~7 1 As discussed above, lines O ~nd 8 of the iso-entropicgram of Table 4 are iclentical in form. One can ~eneraLize by saying that if line O is the input line, line O ~ 2N is the output llne which is identical in form to the input line, where O ~ ZN
is equal to the number of bits in the input line The purpose of utilizing the iso-entropicgram techniques i8 to replace the input line with another representation (line) which is equal to but preferably shorter in length than the input line. The seed line is the one which can be represented with the minimum number of bits eliminating leading 019. Referring to Table 4-A, it will be seen that the seed is line 2, where only four occurrence values, namely, O through 3, are needed tO represent the information ~ince the rest of the bits to the right are 0. The seed lS then represents a minimal encoding for the iso-entropicgram.
In the iso-ontropicgrsm, tho se~d then i8 tho one wlth the least number of possible occurrence value positions required to represent all occurrence values.
If all binary bit positions in a line are called the possibl2 occurrence values and each 1 i8 called an actual occurrence value, it can be said that the iso-entropicgram involves:
(1~ Grouping strings o~ actual occurrence values into llnes snd grouping the lines into a set. All lines in the set are equivalent and interrelated.
According to the preferred embodiment of the present invention, each line in the set is related to another by shitlng the occurreDce values o the line one place and XORing the ¦~ 30 shifted and unstifted lines, deletin~ those ~-~ ~' ~

~ 77~7 1 shifted values ~lich ~o beyond the width o~ the iso-entropicgram;
(2) All lines o~ the 90t are unique, ~hat i~, no line is repeated;
(3) The set of lines is closed upon itself in the sense that by manipulating any one line, the entlre set of lines can be repeated, and the set size (number of line~ in the set) is predetermined ^-'"''',':':

Th~ set s~ze or number of lines for a given length of lines can be specified as follows: ;
N (number) - number of possible occurrence values per line and the number of lines per -set. The log 2N is tn integer.
General techniques are disclosed herein ~ereby any line of an iso-entropicgram se~ can be generat~d from any other line by knowing the line to Se used as the reerence and, secondly, the number of lines between the line to be used and the input line.
Since the transmissiDn of any line of the i~o-entropicgram set before eliminating leading 0'8 carries the same infonmation and requires the same number of bits, the set i8 iso-entropic.
In terms o inormation theory each liDe has tho same entropy. l;~
Using seed inding techniques disclosed hereln, it is possible 2 to select a l~ne that will represent the inpu~ line with fewer occurrence values and hence the entropy is reduced. j As a result, information representation may be stored or tran~mitted more efficiently. ! -The lines in an iso-entropicgram can be derived from any ~30 other line without resort to a line by line revolve. Using for e~cample, the line by line revolve, the seed line is -:

~ ~ -41-!~
\
~.~l.'~'7~7 1 revolved to the input line by revolving the seed through the number of lines of the iso-entropicgram which are necessary to generate the input line. For example, in Table 4-B, a revolve of 9 lines from the seed line 7 will generate the input line 16.
According to one prefexred embodiment of the invention, means is provided for generating the input line without generating each of the lines in between the seed line and the input line. According to the preferred embodiment of -the present invention, this is done by det~rmining the number of lines required to generate the input line and breaking this number down into its component powers of 2, going from the largest possible to the smallest possible component power of 2. One XOR operation is then performed ~5 using each of the component powers of 2 to move from the seed line to the input line. In each XOR operation a given line is shifted to the right by the number of bit positions ~possible occurrence positions) identified by the corresponding component power of 2. The shifted given line is then XOR'd with the unshifted given line.
The example of Table 4-B requires a revolve of nine lines to rotate the seed line to th- input line. Breaking 9 into its component powers of 2, going from the largest l~ -to the smallest, the ,component powers are 8 and 1. Table 2 4-D top line shows the seed llne un~hifted. The next llne of Table 4-D shows the seed line shifted with respect to the first llne by 8 bits. The third line shows the XOR
of the first two lines. In this step, then, the seed line has been revolved from line 7 to line 15. (CF line 15 ~-3 of Table 4-D). The remaining component power of 2 is 1. l -. :.

. .. , ~ . i, . .. ,.. .. . . 1 -:
,-~,; , ;"

~ 67 l Accordingly, the ~hird line of Tab~e 4-D, llne 15 o the iso-entropicgram, i8 right shited one bit posi~ion and ~oP~Id with itsel to generate the input line 16, Anoth~r revolve technique ~s disclosed herein for generating any line of an iso-entropicgram directly from any other lire of the same iso-entropic~ram without generating the intervening lines. This may be done by a process of revolving which involves a s~ift and XOR of the ~iven line of an iso-entropicgram. The number of positions of shift i8 determined by one of the lines of the delta of Fig. 6. Basically the process involves:
1. Determining the number of lines in the corresponding iso-entropicgram by which the given line is to be revolved;
2. Generating the line of the delta who~e number i8 equal to that of the number of llnes to be revolved; --3. For each occurrence value 1D the selected delta formiDg at least partially an individual representation of the given line and aligning the representation~ of the given line with one end aligned with the corresponding occurrence value of the selected llne of the delta;
4. XORing the thu~ aligned oc¢urrence valu~ of the given line eliminating those shifted occurrence 2 values outside of the iso-entropicgram.
Tables 46 and 47 depict such an example. Referring to Table 47, a~sume that the given line i8 line 0. It will ~e seen that the sixth line in the iso-entropicgram from the ~ given line is line 6. Referring to Table 6, delta line 6 : ~3a contains occurrence values O, 2, 4 and 6. Taking the given ~:

., (~

~ 776~

1 line depicted at line O of Table 47 forming a representation of that line for each of the occurrence values of the delta line 6 and aligning the left hand end with the corresponding occurrence values of the delta line 6 results in the pattern depicted at 0, 2, 4 and 6 in Table 46. XORing the aligned bits together results in line 6 of Table 47. In other words~
there are occurrence values at 0, 2, 4, and 6 of delta line 6.
The given line is reproduced 4 times and separate ones of the reproduced lines are shifted 0, 2, 4 and 6 pos6ible occur~ence values. The resulting lines are XOR'd together to generate line 6 of the iso-entropicgram, eliminating any shifted occurrence values to the right of the edge of the iso-entropicgram.
Any line can be used as the given line of the iso-entropicgram. The relative distance, i.e., number of lines by which the revolve is to take place, is equal to the desired line number minus the given line number. This difference determines the line of the delta to be used for the process of shifting and XORing. If the desired line i8 lower in number than the given line, for example a given line of 5 and a de3ired line of 3, the relative distance is negative. In that event, the width of the iso-entropicgram i- added to the negative differ-nce and the result dosignates the line of the delta to be used.
For example, using a glven line of 5 and a desired line of 3, one would compute the delta line as follows:
. 3-5 z -2; -2 + 8 - 6.
This general concept is implemented in the alternate DPM system of Fig. 61. However, to facilitate implementation, 3 the process involves a shift and XOR of the delta line rather than the yiven line which is to be revolved. The process l~

~2~'767 1 implemented in the DELT~ 2 MODULE and the DPM system of Fig. 61 is as follows:
1. Determining the number of lines in the corresponding iso-entropicgram by which the given line is to be revolved;
2. Generating the line of the delta whose number is equal to that of the number of lines to be ;-revolved, one such delta line at least partially being generated for each occurrence value of the N given line, and aligning each generated delta line with one end of the delta line in alignment -with the corresponding occurrence value of the given line;
3. XORing the thus aligned occurrence values of the generated delta line, eliminating tho~e shifted occurrence values outside of the iso-entropicgram. ~ -A more detailed description of the DELTA 2 MODULE
implementation i8 given in the sections on the DELTA 2 MODULE and the REVOLVE 2 MODULE.
To be explained in more detail herein, any line of an iso-entropicgram is completely identified by a line number, a line value and a width ~or length~ value. The line number is the llne number in the iso-entropicgram. The 2 line value represents the aotual occurrence values, excluding 0'8 to the right of the last 1. The width is the width of the corresponding iso-entropicgram which in turn is the length of any line of the iso-entropicgram including O's on the right.

(\~
~ ~a~7~7 1 For example, usin~ this ~orm of expression, the seed line of Table 4-A can be represented as line number o~ 2, line v~lue of 1101 and ~idth o 8.
To be explained in more detail, the actual embodiment of this invention operates an actual occurrence value expressed in binary coded decimal rather than lines and columns of l's and O's. Using this form of expression ~he above line value becomes 0, 1, 3.

. Chan~e~
Changes to a data base con~ist of insertions, deletions and the addition o~ new information. Deletions remove actual occurrence values ~rom event occurrence vectors.
An in~ertion adds an actual occurrence value to one or more event occurrence vectors and, if necessary, actual occurrence -~
values are shifted to allow for insertion. New additions -~
to a data base add new actual occurrence value~ to existing event occurrence vectors or add entire new event occurrence vectors.
In accordance with a preferred embodiment of the present invention described hereinafter in connection with the CHAN OE MODULE, change~ in the event occurrence vectors are made d~rectly to tho ~eed line of an event occurrence vector.
2 In other words, it i8 not neces~ary to revolve an event occurrence vector back from its seed line to the input line of its iso-entropicgram. Tables 9-A and 9-B illustrate the sequence of operation for changing a hypothetical event X.
Line a of Table 9-A depicts the occurrences of X in absolute decimal coded ~orm. Lines b and c, respectively, depict :' .
-46~

``\

1 deletions and insertions. Thus, occurrence values 6 and 12 are ~o be deleted and occurrence values l, 3, 8, 9 and ll are to be added ~o the cven~ X depicted at l~ne a. The change vector incorporating all the insertions and deletions is depicted at line ~ of Table 9-A. The change vector includes all of the occurrence values for the deletions ¦ and insertions sorted in an increasing incremental order ¦ from left to right A change operation talces place by ¦ XORing the change vector and the event occurrence vector 10¦ to be changed. If lines a and d of Table 7-A are XORed ¦ the result is as depicted at line e. It wiil be seen tha~ -¦ line e ~ncludes all of the actual occurrence values depicted ¦ at lines a and d with the common occurrence values 6 and 12 ¦ deleted. It will be recognized tha~ the XOR ~ust described 15 ¦ was described with both the event X and the change vector at ¦ their O or input line for their corresponding lso-entropicgrams.
¦ Assume now that the vector X i9 at its ~eed line as ¦ depicted at g in Table 9-A. The saed of X is at line 6 ¦ of ltg igo-entroplcgram. According to the preferred embodiment 20 ¦ of the present invention, the change vector i9 revolved through ¦ its iso-entropicgram until it i8 al80 at line 6 in its i90-¦ entropicgram. Line h o~ Table 9-A depicts the change vector ¦ at line 6 of its iso-entropicgram. Accordin~ to the present ¦ invention tho line values o~ X and the change vector 2S ¦ depicted at g and h are then XORed provlding the result ¦ indicated at line i. Referring to i of Table 9-A, the XOR
results in the same line number, namely, line 6, with a line value of 0,1. Table 9-B shows the iso-entropicgram for the input line depicted at e of Table 9-~. It will be seen that `30 ~hen the input line (line 0) o~ Table 9-B has been revolved to its line 6, its actual occurrence values are indeed O and 1 -~ i~

1 which is th~ same as that depicted at lin~ i in Tabl~ 9-~.
Using the revolve techniques described hereinabove, the resultant value depicted at i, according to the present invention, is then revolved until its seed line is found.
With reference to Table 9-B, it will be seen that the seed is at line 5. Accordingly, line 6 depicted at i of Table 9-A and 6 of Table 9-B, is revolved forward 15 times until it arrives back at line 5 of the same iso-entropicgram, as depicted at the bottom of Table 9-B. Line 6 plus 15 additional lines is line 21. Subtracting out of 16 (the total lines in the iso-entropicgram) leaves line 5 which `~
is the seed line. Thus, the new seed line number 5 has a line value of 0.
Significant to the present invention, ~t should be no~ed that in the aforegoing example the changes involve five insertions and only two deletions. Even though the insertions and hence information content increased, it resulted in a net l -reduction in the seed. In other words, the seed event X
GontainS three occurrence values in its line value whereas the line value for the final seed contains only one occurrence value. This occurs because the seed i9 a representation formed by information interference patterns which are not controlled by the guantity or the number of occurrence values. The pattern~ are only influenced by the relationship between the occurrence values. A~ a result it i9 possible for a data base to shrink in size with added information.
. ' ~

, .~:~

, , ,.:, ~ .. ~,;.. , , 1' ::

-~-' I
~ `Y767 ¦ D. V~rifyin~ Pre~enc~ of Occurr~nc~ Valuc at Input Line ¦ As described above, Table 6 depicts a delta. The delta ", ¦ of Table 6 is the same width as the iso-entropicgram of ¦ Table 4-A. A delta is formed by placing a 1 at possible 5 ¦ occurrence value 0 as the input line and revolving it until ¦ the original input line is formed using the desired iso-¦ entropicgram width. '-¦ The delta can be used to verify the presence of an ¦ occurrence value (i.e., a 1) at the input line of an iso-10 ¦ entropicgram without actually generating the input line.
¦ The verification process may be accomplished using ¦ pencil and paper by physically inverting the delta from top ¦ to bottom and from side to side. Thus, the delta of Table 6 ¦ inverted becomes that depicted in Table 9-C. Next, the lower 15 ¦ right-hand tip of the delta is positioned over the possible ¦ occurrence value column of interest at the output line.
¦ Next, the line of the inverted delta that coincides with the ¦ line of the iso-entropicgram which is going to be used for the ¦ t,est are ANDed together. The resultant line is then XORed.
20 ¦ If the result of the XOR is a 1, an actual occurrence value is ¦ present at the input line in the possible occurrence value column of interest. If the result is 0, an occurrence value is not pre8ent. ' `~
Although the foregoing method is accurate and useful using paper and pencil, the present invention embodies concepts similar to the foregoing in a more practical embodiment. ,' , In the actual embodiment of the invention it is possible to ~ have a seed expressed as a line number, a line value, and an 1~ iso-entropicgram width to determine whether the input line ' ~ -49-1. .......... ,.,,,.,,, 1.

~ ~2`7'7~;7 1 o~ tlle corre~pondLng i~o-entrop~cgram ha5 any par~icular desired occurrence value an~l ~his can be done ~itl~out revolvini tle seed back to the input llne. U~uaLly ~he line to be used for the checking process i9 the seed line.
Therefore, the description o~ the embodim~nt o the invention will be described assuming th~ the line to be used as a basis for the test is the seed Line.
Referring to the inverted delta, it will be seen that the -numbers of positions between ad~acent "l's" is an integral power of 2 for lines 0, 2, 4 and 6. For example, line 2 has l's separated by two positions, whereas line 4 has 1l8 separated by ~our positions. Bec~use of this characteristic of the delta, it i9 quite easy to generate occurrence values ~ -representing the occurrence values which are present in the lines of the delta which are component powers of 2. To this end, the seed line t~hich i8 to be used as a basis for a test is first revolved in its iso-entropi~gram until it is at the line which i8 an integral power of 2 lines away from the input line. Using Table 4-A by ~ay of example, seed line 2 ~en revolved two lines to line 4 is an integral power of 2 (namely, 4) away from the input line.
Referring to the inverted delta ~f Table 9-C, it will be seen that line 4 contains occurrence values at 3 and 7. ~-Thus it should be evident that the number o possible 2 occurrence values soparating the actual occurrence values in the delta (for those lin-s which are integral powers of 2) ;: i9 equal to the line number. Thus, applying the inverted delta o~ Table 9-C to the iso-entropicgram o Table 4-A, -~
assume that it is desired to determine whether occurrence 3 value 6 is present in tho input line. Applying line 4 o~ the inverted delta of Table 9-C to line 4 o the iso-entropicgra~
of Table 4-A, occurrence value 6 is present in the inverted delta line o~ Table 9-C, whereas it is ab~en~ in the iso-entropicgram ;

-` ~'X7767 1 line o Table 4-A, whereas four places to the l~ft of the occurrence value 6 ~of interest), the inverted delta contains an occurrence value and so does the iso-entropicgram of Table 4-A. Tables 9-D and 9-E depict these operations.
S The foregoing method for determining the presence of an occurrence value at the input line using one of the non-input lines of the iso-entropicgram is referred to herein as the DEL function. The actual method whereby the embodiment of the present invention carries out the DEL function is described in more detail in connection with the section describing the OUTPUT MODULE.

E. Hybrid Coding The disclosed embodiment of the present invention involves a further compaction technique in which the occurrence vectors are represented in a hybrid encoded form. Information is stored in the MEMORY MODULE in hyb~id encoded form. Thus, considering the iso-entropicgram technique used to represent a particular occurrence vector, the present invention involves a technique which pick~ the line of the iso-entropicgram which in hybrid coded form is the shortest, not necessarily the one which ls ~hortest in the unencoded form.
The reason for selecting the shortest hybrid coded iso-entropicgram representation for the seed is to enable 2 the shortest or smallest memory space to be used for storage~
Referring now to Table 8, the possible occurrance values are depicted, and immediately below, the corresponding binary bits representing an occurrence vector are depicted at l.
Up to this point, the occurrence vector~ have been 3 primarily described in what will be ter~ed bit striny form.
:: ~

.~ l~m67 1 Ill otll~r words, ~ binary 1 or a binary 0 is us~d to representthe presence or ~bsence o actual occurr~nce values. This form of representation is depicted at 1 in Table 8. 3 of Table 8 depicts the same information in a binary coded decimal form called absolute code form. Thus, bit string form for the information of Table 8 requires 8 digits, each with 1 binary bit, for storage, whereas absolute code form requires five digits, each with 3 binary bits, for storage.
Each digit in bit string form requires only one binary bit for storage, whereas each of the digits in absolute form requires three binary coded bits. ~owever, if the number of blanks or O's between two binary ones (occurrences) becomes large, it will be seen that a point will be reached where it will be shorter and save memory space to represent the information in absolute form. Stating it differently, the diqtance between the binary l's in the bit string form determines whether bit string encoding or absolute encoding -will give the best compaction and hence the shortest length -of information to be stored.
By way of example, in a very wide iso-entropicgram, the distance between two event-times or occurrences may be great. For example, one occurrence value may be 5 and the -next 2,673. In this case, absolute encoding should be used since it requlres much fewer binary coded bits of ~-2 information for storage. If the distance between event-times i8 short, and the number of occurrences i9 therefore frequent, bit string encoding will be better.
Accordingly, the present invention involves a technique ~-where a hybrld encoding is used. A brief description of the ; 3 hybrid encoding will now be given since it is an integral part ~ of a preferred embodiment of the seed determination process.
' ~'~

-52- -~

. ..

m67 T;l~)lc 9 ~lepic~s i~l hybri~ code an example of the rnost signiEicant ;i~ words o~ stor~ye Eor an occurrence vector containing occurrences at event times 87, ~8, 90, 93, 100, 114, 116, 119, 123 and 125 . Each word contains a bit or "flag" at the left-hand end which identifies whether it is a bit string word or an absolute word. A binary l indicates an absolute word whereas a binary O indicates a bit string word. Disregarding the bit string/absolute form bit at the left-hand of each word, each binary bit string word contains the largest occurrence value at the right-hand end and the smallest at the left hand.
Word 1 is in absolute form and represents 125 with the most significant binary bit at the left and the least significant binary bit at the right (disregarding t~e bit string/absolute form bit at the left end of the word).
lS Word 2 i8 in bit string form and has seven binary bit positions representing possible occurrence values 118 through 124 but it only contains actual occurrence values depicted by binary l's for occurrence values ll9 and 123.
During the process of encoding to hybrid code, an occurrence vector in bit string form is scanned backward from the right-hand end as depicted in Table 4-A to the left-hand end from the latest event time or largest occurrence value to the earliest event time or smallest occurrence value, assigning absolute and bit string form to the words for storage in memory. ~qemories are normally organized so that information is stored in words. As the occurrence values are scanned from the largest to the smallest, ~,: : . .
~-~ absolute and binary form words are assigned so as to give : - . . . .
~ ~ the maximum compaction. Thus, word l is in absolute coded -~ 30 form and represents the occurrence value 125. Word 2 is in bit string form and has binary l's at the second and sixth -~; 53 ~;' ~ ''' :
(''' ! ~
. , .
~ ~7 7 67 1 position in the wo~d, indic~tin~ occurrence values o~
123 ancl 119. Word 3 i9 in bit strin~ ~orm with blnary 1 bi~s at tlle ~econd ~nd fourth positions, rep~esenting occurrence values o 116 and 114. Encoding is changed from absolute to binary coded form when more than seven bits can be saved by switching ~rom bit string form to absolute form. The occurrence va~ue 100 is 14 possibl~ occurrence values away from the occurrence value 114. In the encoding procedure, it is necessary to check the efficiency o changing the forms of representation by calculaeing the number of bits ¦ that are saved. Since there are ~hree pos~ible occurrence `~
values to the left of occurrence value 114 ~n word 3, three bits are potentially wa~ted by s~itching to absolute form, plus, it will require a full word of seven binary coded bit~
to represent the information in ab~olute form. Thus a total of 10 (7~3) bits are requ~red for changing to absolute coded form, producing a saving of four bits. Therefore, it is desirable to switch from binary form to absolute form.
m u~, as depicted in Table 8, word 4 is in absolute form and represents ehe occurrence value 100.
Occurrence value 93 18 seven possible occurrence values from the o¢currence value 100. Since seven bits are potentially saved (not more than 7) the form of encoding 18 not changed and the encoding for the next word 4 will remain in absolute 2S form.
Occurrence value 90 i8 only three bits away from ~-occurrence value 93. AccordinglyJ bit string encoding i8 more efficient and ~ord 6 is in binary string form, ;~ Hybrid encodin~ i9 used to store all occurrence vectors 3a in the ~P~I system. Therefore, althou~h one particular l~ne ..'`' ~' ':'.''.' ~
....
. ~ , ", `~ ~ ~
l~Z7q~7 1 in an iso-entropicgram may produce the shortest length of occurrences in bit string orm, it may be fo~nd that another line o~ the same iso-entropicgram will actually produce the shorteqt len~th when converted to hybrid orm.
Hybr~d encoding is used to encode all of the occurrence vectors sent baclc to the auxiliary memory for storage and all occurrence vectors read from the au~iliary memory for processing by the rest of the DPM SYSTEM.
Decoding of the occurrence vectors read from the aux~liary memory and processed ~n the DP~ INTERFACE MODULE is accomplished by enter~ng the hybrid coded string of words largest occurrence value first. Info~tion i8 processed in the DPM SYSTEM ln abaolute coded form. Accordingly, the DECoDE I and DEOODE II
M~DULES depicted in Fig. 1 translate all hybrid coded information transferred from the auxiliary memory into the MEMORY MODULE into absolute coded form ~r proces9ing by the DPM SYSTEM. Similarly, the ENOODE MDDULE translates all processed information in the DPM SYSTEM from absolute form back to hybrid coded form for storage in the MEMORY
2 MODULE and subsequent transfer back to the auxiliary momory.
The details for performing encoding and decoding in the E~CODE and DECODE M~DULES will be described hereinafter with respect to each of these modules.
F. Conventions and ComPonents Used in the Fi~ures Each o~ the ~odules has control input/output llnes ~narrow lines) and information lnput/output lines (heavy lines). By way of example, the ENOODE MODULE shows these lines along the right hand side of Fig. 3. The narrow lines used to represent each con-trol input/output line represent a sin~le conductor. Each heavy 3 line represents 8 conductors or carrying 8 binary coded bits of inormation in parallel. Arrows to the le~t indicate incoming sig-nals to the correspondin~ module whereas arrows ~o the ri~lt indi-; ~ cate out~oin~ signals.

- ~ ~ ~
i ~Z~ 7 1 Symbols are sho~n at the tail o~ each arrow representin~
each incomlng control input/output line. Each o the3e s~,lbols no~ only uniquely identiies each line, bu~
~dentifies the source or module from whicIl the si~nal for that line originates.
The convention employed is to use one or ~o letters followed by one or more numbers. The letters identify the originating module a~d the number gives a unique identification to the line. For e~ample, Fig. 3 o~ the ENCCDE ~IODU~E shows the symbol ~2 for the top line. The 9 ignal for that line originates in the SEED ~DULE. Table 10 gives a list of the letter symbols and the correspondir,~ module, Some ~ -control inpu~/output lines have identifying symbols which do not follow this convention and the originating module i8 identified.
Outgoing control input/output line~ ~arrows to xight) are also labeled. The sy~bols on the left (tail of arr~) are logic representing the logical equations for gates used in generatin~ the signal on the outgoing line. A symbol is used at the arrowhead to identify the line as it leaves and enters other modules. For example, in the ENCODE MODULE, the logic P9 represents a gate used to generate a logic I;~
signal on ~e line ~l.
G~ting i8 shown in block diagram in some instances and 2 in others, logical quatioDs are used to represent the gating for simplifi~ion ~ Standard symbols are used in the logical equations~ Thus, a "~" represents an "OR" condition; a "." represents an ~ND condition; and symbol~ representing the ou~puts from flip flops, gates, regis~ter, counters, etc, are used as the terms in the equations. By way of example, 1:-`

7Gr7 1 lo~ical gatin~ is depicted in the ENCODE ~IOD~.E, Fi~. 4 to rese~
the ~Lip ~lop ERFST to 0. Tlle logic is: P5.G.ERFST.~. The gate represented by this logic i9 true when true signals are formed at each of the outputs indicated in the equation, This, S of course, illustrates an AND gate w~th each o~ ~e indicated outputs as inputs to ar. AND gate. The logic PlO.G~P7. OE +Pll.~
for flip flop P2 represents three A~D gating conditions combined by two OR gating conditions.
Flip flops are e~tensively used throughout this patent appli-l ;
~0 cation. One type of flip flop used extensively employs a type SN7474 positive edge triggered D~type flip flop disclosed at L
page 121 of the book entitled The TTL Data Book for Desi~n En~lneers, published 1973 by The Texas Instruments Co. Each.
of these flip flops iQ identified by a rectangular box with a line in the upper left hand corner, such as that shown for $1ip flop P12 of Fig. 4. Each of these flip flops iB characterized in that an input exists at the top side and one at the bottom side and two inputs exist at the left hand side. Also, each has a pair of complementary outputs at the right hand side, the upper one of`
which has the same symbol as the flip flop (i.e., P12) and the lower one of which has a line over the top referred to as prime (i.e., ~q~). These flip flops operate as follows. A true signal appli~ at the top side (without clock) sets the flip flop to a 1 ~tate, càusing true and fal~e signal~ at the unprimed and primed 2S outputs, re~pectively (i.e., P12 and ~q~). A true signal applied I
at the bottom slde sets the flip flop (without clock) to a O state causing false and true signals at the unprimed and primed outputs~
respectively (i.e., P12 and ~q O . The lower left side input of j-these flip flops is for clock~ and the upper left side input ~30 is or control o the state into which the flip 10p is set responsive to clock at ~ '767 ~

l the lower ~e~t hand side input, A true si~nal at the upper le~t side input causes the correspondinz ~lip 10p to be set to a true state responsive to a simul~aneo~sly applied true cloclc pulse at the lower left side input, and S a false signal at the upper left side input causes the corresponding flip flop to be set to a false state responsive to a simultaneously applied true clock pulse at the lower left side ~nput.
To simplify the drawings, the outputs on the right slde f 10 of flip flops are not alway~ sh~on as they are for flip flop P12, For example, see flip flop Pl of the ENOODE ~IODUL~. However, the unprimed and primed outputs are always implied and will be used at various places in the system. For example, the Pl output o 1ip flop Pl i8 not shown on the right of flip 15 flop Pl, but it is shown in the logical equation Pl GE for controlling the upper left side input to flip flop Pl.
Simikr to the control input/output lines and the -~
information input/output lines, heavy connecting lines are used throughout to designate multiple si~nal conductors 20 whereas a thin llne represents a single conductor. l -S-lection circuits are used throughout tho system.
By way of example, the ENCODE ~aDULE has selection circuits r EDSl-EDS7. The selection circuits each have two or more labeled multi-bit inormation input circuits, each input 25 circuit for receiving multiple binary coded bit~ o inormation, and one multi-bit output for receiv~ng ~he ;
same number of bits as an information input. The information input circuits are labeled directly on the outside of ~he --box such as EDSl-EDS7 o~ the ENOODE ~Dl~-. In som2 cases, 1 -~
3 the labels are implied such as for selection circuit DSl -s8- `
. ~.

~ ~ i7~7 . I, 1 of the DPM INT~RFAC~ MODULE where the la~el i9 lmplied to be the sa~c as the originating circuit o~ the inonma~ion Di~nals.
Also, each seloc~ion circuit has a con~rol input correspondin~
to each o~ the in~ormation inputs ~hich i~ corres~ondingly labeled inside of the bo:c. A true si~nal at the correspondingly' labeled control input causes the selection circuit to couple only those signals at the correspondingly labeled information input to the.output circuit. By way of example, in the ENCODE l~loDULE, a true signal at the 1 side control input of selection circuit EDSl cau3es the output of register 104 to be coupled through EDSl to the left input of the ALU.
Various modules also have an arithmetic logic unit ~LU of the type SN74181 disclosed at page 381 of the above TTL book. An ALU i5 sh~n by way o example in the ENCODE
lS MODULE, Fig. 2. The arlthmetic unit ALU is characterized ' in that 8 bit signals coded in the 1, 2, 4, 8 ~inary coded -~
number sys~em ~pplied at the input~ #1 and #2 enable ALU "~
to ~orm 8 bit signals, coded in the same number system, :
at an output OP. ~ true signal applied at the ADD input causes a signal at the output OP representing the sum of the two coded slgnals applied at ~1 and #2. Whereas, a .' control signal applied at the SUB input cau~es a signal at OP, representing the d~ference bet~een the signal~
at $1 and #2 in 2'8 complement ~orm.
2S The arithmetic unit ~LU has additional outputs G, L
. and E. A true signal is formed at t~ G~ L and E outputs, respcctively, when the number represented by the coded signal at ~1 is "greater than" ( ~r ), "less than" ( C ), and "equal to" ( ~ ) than at ~2.
The ALU design sh~n here is ~or a 4 bit chip.
. , :~'.

``.~ -59- 1 ~: ~: .,.,, ., ~",; ',, `;` ` ;-; ~, --c~ ~
~ Jr~7 1 However, it could be generalized into larger grouping~.
In all likelihood, larger capacity ALU's ~e.g., 24 or 32 bits) would make use of type SN74182, look ahead carry generators, of the above TTL book. However, these are not necessary for an 8 bit wide ALU.
It will be obvious to those skilled in the art that minor circuitry peripheral to the SN74181 is required to receive the true signals and provide the output signals l -shown and described with reference to the ALU and these ¦--1 circuits are depicted in the block diagram of Fig. 6.
Some modules have unprimed inputs (i.e., EOFl of Fig. 17), whereas a primed form (i.e., EOFI) is used in `
the module. The primed form ~i.e., EOFI) merely indicates ~`~
the logical inverse of the unprimed form which i5 formed 1 by conventional signal inverter circuits. Signal inverter ^~-circuits are not always shown but are implied in some instances (as for example, ~F~ in Fig. 17).
Although specific hardware i~ di~closed for various modules in the DPM ~ystem; it ~hould be noted that the -2 modules might al~o be Lmplemented using micro programmed :
¦ mL~1 c t-r- w1~h appropriaee fLrmw-re progr ~

2 ;
' . ' -`~
~ . ~'''' :~ ~ .

. -60 . ~,.

1 I-A. GENERAL ORG~NIZ~TION OF DPM SYSTEM OF FIGS. 1-34 _ , Reference should be made to Fig. 1 in the following discussion.
The DPM SYSTEM has a MINI COMPUTER and a DPM INTERFACE
MODULE. The MINI COMPUTER may be any one of a number of mini computers well known in the art, a micro-programmed computer or a specially designed computer. For purposes ~ k~
of illustration the PDP 11/45lwith floating point arithmetic units is disclosed by way of example. Included therein is a MAIN MEMORY and an OPER~TOR CONSOLE with typewriter and printer input and output. The MINI COMPUTER contains -a user program which supervises and sequences the operations of the entire DPM SYSTEM. The DPM INTERFACE MODULE provides -~
the interface between the MINI COMPUTER, an auxiliary memory for the MIN~ COMPUTER and the re4t of the DPM SYSTEM.
The DPM contains an IPRF which ls a set of registers in which the MINI COMPUTER stores parameters to be used as input by the other modules in the system as discussed more fully in connection with each module. The MINI COMPUTER through the DPM INTERFACE MODULE also stores information in the MEMORY MODULE for processing by the rest o the modules.
The information stored in the MEMORY MODULE i8 in the form of hybrid coded occurrence vectors; The DECODE I and II
MODULES decode all hybrid coded signals from the MEMORY
MODVLE to absolute coded value signals and the ENCODE
MODVLE enco~es all signals being stored in the MEMORY MODULE
from abso1ute coded value signals to hybrid code. The exception i~ with respect to information signals transferred between the MINI COMPUTER or the DPM INTERFACE MODULE and 3a the MEMORY MODULE.

~- -61-~ 7767 1 The MINI COMPUTEI~ cau~e~ an occurrence vector, in the form of a given line value of an iso-entropicgram, to be sent f rom the MAIN MEMORY to the MEMORY MODULE via the DPM INTERFACE MODULE. A REVOLVE MODULE reading ~rom the MEMORY MODULE through the DECODE I and II MODULES writes into the MEMORY MODULE through the ENCODE MODULE and causes the given line value and line number to be . ~
revolved through various lines in the corresponding : -. . , ~, , , ~ `!, , ~ ` , , ' . ~ ~ ~' ~ ' ' ' c' ~Z7'7G7 1 iso-en~ropicgram. The seed is formed using the SEED MODULE, Specifically, the REVOLVE M~DULE revolves a given line, under con~rol of the SEED ~DULE, through it~ iso-entropicgram.
The ENCODE MODULE determines the physical len~th of each encoded line of the iso-entropicgram as it ic stored in the MEMORY MODULE. The SEED MODULE keeps track of the length of the shortest line and identifies the area in the -ME~RY ~DDUIE that stores the shortest line.
The SEED ~DULE during the seed finding procesQ forms signals representing the number of line revolves which must take place to locate the seed line. Thi~ signal, called the total number of lines signal, i9 æent to the DELTA MODULE
which forms one or more signal~ representing the component powers of 2 of the total number of lines sigDal. The component powers of 2 signals are provided one by one to the RE W LVE MODULE which in turn revolves the given line by that number of lines. The input line of an iso-entropicgram i8 retrieved from the seed line, or any other line, in a reverse sequence of operation More specifically, the REVOLVE MODULE under control of the OUIPUT MODULE revolves the seed line unt~l the input llne is formed. In this case the OUTPUT MnDULE forms a signal representing the total number of lines required to revolve the seed to the input line.
The DELTA MODULE recoives the total number o lines signal 2S and forms one or more signals repr~senting its component powers of 2. The REVOLVE MODULE again revolves the seed ; line by the amount specified by each camponent power of 2 signal until the input line is reached.
Data i~ entered in the existing d~ta base by adding, ~3a chang~ng or deleting. Thi~ is generally referred to as ehe ~ 67 1 update function. The upda~e unc~ion i9 taken care oE by the CHANGE ~DULE.
~ hen a seed i9 to be updated, the MINI COMPUTER enters the changes, etc into a word referred to as the "change vector"
Ihe Cl~l'G~ ~DULE ~ir9t gets the occurrence vector in seed form from the data base. Using the DECODE I and II and ENCODE
MODULES for communication with the ~IORY ~DULE, the REVOLVE
MCDULE revolves the change vector 3eed b&ck to .he same line of its iso-~ntropicgram as the seea. Tne change vector is t;~en merged with the seed UBing the XOR operation discussed above The OUTPUT I~DULE is provided prim rily for the retrieval process of revolving a seed or other line to the`~put line of its iso-entropicgram. However, the OUTPUT ~IODULE ~lso causes the DEL function to take place. The purpose of the DEL function, as discussed above, is to determine i a particular occurrence value exists at the input line of an iso-entropicgram given the seed line. Signi~icantly, the DEL function allows this to be chec~ed very rapidly without having to revolve the seed line back to the input line.
The OUTPUT ~DU~E has a special clipping function which ~ `
allo~s the DPM SYSTEM to recall an occurrence vector from the data base and retrieve 3ust a specified por~ion of the occurrence vector. For example, one might want to Icnow how many ti~es the word "help" occurred between occurrence 2 event times 2~000 and 2,832. To be explained in more detail, the numbers 2,000 and 2,832 would be entered into the OUTPUT ~DDULE as lower and upper clipping bounds, allowing the event "help" to be r2trieved only for those `
occurrences which lay between 2,000 and 2,832.

3a The PIPE MODULE and BRIGHTNESS MODULE perform a discrimination function in the DPM SYSTEM. This does not have anythin~ to do Wittl the data base managing functions.
Signi~icantly, the PIPE and BRIGIIq~NESS M~DULES allow near ...... . .. ,,.". . .. ., . . . , .. ... .. . . ,. . ~ . ~. . . ~. .

C~ Q
~fx7qG7 1 miss rctrieval~. In other words, tlley allow ine~:act retriev~l of ino~mation ~rom the d~ta ba~e.
Both ~he piping and brig~ltness functions o~ the PIPE
snd BRI~I~SS ~DULES work on a sequence of events bet~een delimiters, These deli~iters could be any level dellmiters, The PIPE I~IODULE is presented with a sequence of events which malce up the user request. Each event is retrieved from the data base and compared against the others in the request~
The object is to find if the same sequence of events has occurred be~een any two delimiters in the layer in question, The output of the PIPE ~ICDULE consist~ of two value~ for e~ch logical entity in the layer as follows:
1, A starting value, and 2, A numerical value ~hich gives the number of occurrences of events that appeared in the data base from the request, If the sign bit of the numerical value i8 ~ (true), this indicates that the request occurred e~actly somewhere between the spec~fied delimiters, The aforegoing is primarily the piping function, The brightness function improves on the piping function, For example, the piping function chooseQ the best candidate for brightness. The brightness unction then chooses tho best posslble ~andidate, 2S Essentially, the brightness function talces the starting value within a logical entity ~hich is received ~rom the `
PIPE ~ODULE and then takes each event from the input request and finds the closest occurrence o~ the event to this starting value, if one exists. The ~ri~htness function then ~nd~
3a thls occurrence for each event in the request and the process ~-is repeated for each lo~ical entity ~lich i9 to be checlced.

.... , . ,. .. ..... , .. ,.,.. ,.. ... , ~ ... ., ..... - . . .

(~ z7~6~ ~

1 After all the events in the request have been processed, a calculation is made to find the brightness valu~ or the request.
The brightness value can be described considering the following example. Picture the logical entity from the data base and immediately to its left the request.
The request is then shifted right, one event at a time, over the data base entries and a value is computed for each shift. The value indicates how close the request 0 lineæ up with that of the data base. The best value is then passed as an output to the user at the OPERATOR
CONSOLE. This value is computed for each logical entity which has been re~uested.
The exact way in which the piping and brightness functions work are best understood in connection with each module. Accordingly, reference should be made to the sections XV. PIPE and XVI. BRIGHTNESS MODULE and the ~-80ftware sections XXXII for a more complete description and understanding of these features.
`

:: ~

I -6~-., .;.. -.. ; ~ .~;, . ~ - , ~ , ;, ,; ,~-~7'767 1 II. ENCODE MODULE
_ _ A. General Description Section ~ GENERAL DESCRIPTION OF DPM SYSTEM degcribe9 hybrid form of coding of the information, with respect to the example in Table 9. The ENCODE MODULE is provided in the DPM SYSTEM of Fig. 1 for the purpose of con~erting absolute coded occurrence vectors to hybrid coded form and controlling the writing of the hybrid oaded occurrence vectors into the MEMORY MODULE.

0 At the outset, it should be kept in mind that occurrence vectors represent a series of occurrence values out of a - -larger set of incrementally ordered possible occurrence values or event-times. Occurrence vectors are stored, retrieved and processed such that the highest numbered 1 occurrence value is first. The highest numbered occurrence va}ue identifies the most recent occurrence in the event-t~me domain. The lowest numbered entry, and hence the entry farthest back in event-time, is stored, retrieved and -processed last. Examples of delimiter and event occurrence vectors (in absolute coded form) are ~hown at -~" and ~T"
of Table 2. This form of information representation ls quite important to an understanding of the ENCODE NODULE embodiment about to be de-cribed and with respect to each of the other module embodiments about to be described.

2 ¦ The MæMORY NODULE reads and writes information a word at a time. A word ha~ 8 binary blts of information.
The ENCODE MODULE, in the encoding proces~, processes ~ each occurrence vector as foilows:
;~ The ENCODE MODULE is called each time an absolute 3 occu~rence ~s to~be encoded by either the RE~OLVE MODVLE
or the OUTPUT MODULE. The module which calls the ENCODE

", ~

-~ ( ~ r ~
~ 7767 1 ~IODUL~ is hereinaft:er called the calLing module.
The ENCODE ~IODULE receives l:he absolute occurrence values of sn ~bsolute coded occurrence vector in decreasing value order. A currently received absolute word and a 5 previously received word in the series are held and compared The d ifference between the current and previous absolute ~alues represent the number of binary bits of displacemeDt between thern. If the difference is greater than some "specified number of bits" (in this case, 7 bits), 1 thien the previous absolute value i9 outputted in the hybrid word series as an "absolute" word (see word O
of Table 9). If the difference is less than this "specified number of bits", the pxesent absolute value is entered as an occurrence into a bit string ~i~ord (see word 2 of TaSle 9) 15 of the hybr~d series. The latter is accomplished by shifting the bit string word under formation the number of bit positions designated by the difference and entering a bit of predetermined value, i.e., "1", into the bit string word, and the ENCODE MODULE is "exited" by terminating its 20 operation. ~hen a blt stsin~ word under formation i~
complete, it i8 also outputted. It should be noted that binary bit at the most significant end of each word being outputted i8 reserved as a type or flag bit to indicate th~ form of the hybrid word. A "1" bit flaEc indicate~
2 an absolute word whereas an "O" blt slag indicate8 a bit ~tring word.
~ he hgbrid form to which the absolute occurrence values are encoded i~ a series of absolute and bit ~tring words starting with an absolute word. An absolute word in itself `3~ represents the value of one occurrence by a combination of ~.

(' ( ) ~i~."767 1 bi~ary coded signals. ~ bit s~rin~ word represent~ an occurrence value by the number of possible occurrence values o~ displace-ment of an occurrence of predetermined value, i.e., "1", ~rom the previous absolute word or from the previous occurrence of predetermined value in the hybrid word series. The first word of each hybrid word series is always an absolute word and therefore in itself, identifies the value of the first and largest occurrence. However, it shoud be understood that within the broader concepts of the invention, the invention may be employed in a system which i9 not bound by words, in which case the bit string portion of the hybrid form would not be confined to words.
Another purpose of the ENCODE MDDULE i9 to perform "cliQping" and "clipping" by "interval". Clipping is the operation of deter~ining if each absoiute word occurrence value lies between a top limit ~L) and a bottom limit (BL).
This operation is performed by comparing each absolute word with TL and BL. If the input entry is C TL and ' BL, the absoluee word is within desired bounds, and encoding continues and, if not, a corresponding indication is formed.
If "clipping" by "interval" is to be performed, an "interval" value CEI) i8 provided to the ENOODE MoDULE.
If the absoluto word is not ~ TL and ~ BL, then EI i~
subtracted from TL an~ BL, and the ~sme absolute word is again compared with the mndiied TL and BL va~ues. This continues until BL goes below 0 at which time a corresponding ~ignal is formed or the ab~olute word is found within the bounds of the modified TL and BL, according to the above criteria, at which time the absolute word ~s converted to ~3C hybrid form, as discussed above. The "clipping" by "interval"

-69- ~`

" . ,,~ t~ ~, ", ~, ~", . ,,, ""~ ,",,,;, ~

~ x7767 1 function is important un~er certa~n conditions when it i9 needed ~o Icno~J i~ the input entry i8 within certain re~ular intervals, i.e., 45-40 or 25-20, 10-5. The values TL, BL and EI are read by the ENCODE ~IODULE ~rom the correspond-ing registers of the IPRF.

B. ComPonents The ENCODE MDDULE includes registers ET, EIR, EI, ER, --~
EO, EHW, ETL, EBL and EOP. Each of these registers contains

8 bits of storage. With the exception o EOP and ER, each register ~ of type SN74100 disclosed at page 259 of the above TTL book and are characterized~in that a true signal applied at the L input at the side thereof causes the binary coded signals applied at the upper side input to be applied to the lower output. When the signal at the L input goes false, the information i~ retained in the register even though the information input signals change thereafter.
The EIR register is shown with two special outputs Eo and ~. True signals are formed at these outputs when the content of the EIR register 19 O and not 0, respectively.
It will be understood that an appropriate circuit (not shown) i8 connected to the SN74100 regi3ter for forming these signals. Preerably, the circuit has the "1" output of each bit position connected to the input of a common "OR" gate. The output o the "OR"
gate i8 the E~ output, whereas the output o the "OR" gate i~ connected through an inverter to the Eo output. -The ER re~is~er i5 a data latch of type SN74116 of the above TTL book and i9 similar to the S~74100, except that it has a "CLE~R" line which provides a one ` 30 step clearing operation.

--~.Z'7767 1 Re~ister EOP consists o a ~lip flop MSB and a seven bit parallel-in/parallel-out shift regi3ter 114 of ~ype SN741~ as disclosed at pa~e ~56 of tl-e abov~
TTL boolc. Register 114 is a 7 bit register and is characterized in that parallel loading is accomplished by applying the 7 bits of data at its upper side and making the shift/load (S/L) control input low or false when the CLOCK -input i~ not inhibited, i.e., receives a true signal. A
true signal at S/L causes a shift to the right by register 114 responsive to the leading edge of a true pulse at the CLOCK
input. A falso signal at S/L causes the 7 bits applied at its upper input to appear at the output of the register 114 and be stored therein responsive to the leading edge of a ~-true pulse at the CLOCK input.
1~ Considering register EOP in more detail, a false signal at ~ causes register 114 to load theinput signals applied at the upper side. Typically, a true signal i9 simultaneously formed at P9'~3-W to the MSB fl~p flop. When CLK goes true, P9 BSW-~-K becomes true and, being applied to the CLOCK input of the MSB flip flop and the register 114, causes the MS8 flip flop to be set true and load 7 bits of ~;
information from register EO .
In addition, the ENCODE MODULE has counters M~R3, MLN3, CTR and NOC. CTR has 8 states, NQC, ~R3 and MLN3 ~-each have 256 states and are of type SN74161 disclosed at page 325 of the above TTL book.
~:~ CTR is a 3 bit up/down counter of type SN74191 disclosed at page 417 of the above TTL book and is characterized in that a false signal at U/D causes the 3 counter to count up when a true signal is appl~ed to the CT

. - .

r ~Z'77~7 1 input and a true signal at U/D causes the counter to count down when 8 true signal is applied to the CT input. The counter can be preset to a value corre~ponding to the signals applied at its input at the upper side while 5 applying a true signal to the L input. The block indicating CTR contain~ a circuit not shown, similar to that described for the ER register for forming true signals at the ~ and Co outputs when the ~tate of CTR i~ O and not 0, respectively.
The ENCODE M~)DllLE has counters MAR3, MLN3, CTR and NOC.
10 CTR has 8 states, NOC, ~R3, and ~N3 each have 256 state~
and are of type SN74161 disclosed at page 325 of the above TTL book. The counter CTR counts through its prefixed sequence of 8 states and automatically resets to its initial or 0 state. Each of the MAR3, MLN3 and NOC counters 15 are of type SN74161 of the above TTL book and are controlled to always count upwards. Not shown but included within each box is a logical signal inverter to invert the signal at CLR before it reaches the SN74161. A true signal applied at the CLR (CLEAR) inputs of MAR3, MLNi and NOC causes 20 them to be cleared or reset to a "O" state. A true s1gnal at the CT input causes the counters MAR3, MLN3 and WOC
to count up. ;`
Th~ ENC'ODE M!ODULE also has fl1p flops EFRST, ELAST, BSW, ECE, U/D and-MSB. In addition, a control counter 113 2 has flip flops Pl to P12.
The ENCODE M~DUI.E also has a source of recurring clock pulses 102. The source of clock pulses 102 forms a series of equally spaced (not essential) recurring true clock pulses at its output. The output of source 102 is connected to one -3C input of an A~D gate 112 which forms clock signals at CLK

ilZ7767 1 whenever the other input to gate 112 i9 true in coincidence with a clock pulse. A signal inverter 117 inverts the signal at CLK to form pulses at CLK.
The ENCODE MODULE also has an arithmetic logic unit ALU
at #1 and #2 in 2's complement form. Conventional OR gates 108 and 110 are ccnnected to G, L and E so that true signals are formed at a GE output of 108 and a LE output of 110, respectively, when the values of the signals at #l are "equal to or greater than" t2) that at #2, and "equal to or less than" (<) that at #2.
The ENCODE MODULE also has selection circuits EDSl-EDS7 of the type disclosed above. The ENCODE MODU~E also includes conventional logical OR gates 104-110, 118 and 119 and an AND gate 112.

C. Detailed Description The ENCODE MODULE can be most readily understood with reference to the description in connection with the block ~-diagram, Figs. 2-4, and the corresponding flow diagram, Figs. 7-8. As an aid, Table 11 contains symbols used to identify the counters, registers, flip flops, and one-shot --multivibrators, together with the mnemonic meaning of the symbols used. Also as an aid, the flow diagram contains P numbers ad~acent to the various blocks, i.e., ~Pl), tP2), etc. These P number~ correspond to~the outputs of the control counter 113 and thereby indicate the state of the control counter during which the indicated action shown in the flow diagram takes place. However, the same P number appears for more than one box. Therefore, for added ease in making reference to the flow diagram, symbols EBl through EB26 are used to identify each box in the flow.
,.j ~' ~
~Z~767 1 Table 11 shows ~he principal inorm~tion inputs and outputs ~nd the input con~rol or tIIe ENCOD~ ~IOD ~ . Top clipping limit, bottom clippin~ limi~, interval and i90-entropic~ram width are each 8 bits long and are loaded into registers o~ the ENCODE ~`IODULE by the modules indicated in Table 11.
Assume initialLy that clipping is not to be performed in which case OPSW, ETL, EBL and EIR are all initially 0.
Also assume that the E~CODE 2~IODULE is about to be called for its encoding function for the first time. Preliminary to calling the module, the current absolute word i8 received by the EDS6 selection circuit either from the DS4 output of the REVOLVE ~DULE or ~rom the ORTl register of the OUIPUT ~ODULE. The first current absolute word to be received 18 the first or largest absolute coded word (8 bits in length) of an occurrence vector. After the ~EVOLVE ~DULE
suppl~es the current absolute word, true signals aré formed at RMll and RM6 by the REVOLVE ~DULE. When the current absolute word i9 being supplied by the OUTPUT M~DULE, true signals are formed at C~I13 and OM14 by the OUIPUT ~IODULE.
A true signal at R~ll causes the EDS6 selection circuit to couple the current absolute word at DS4 to the information input of register EI. The true signal at ~I6 enables the OR gate 109 to acdvate the load (L) input of EI and load 2 the current absolute word into EI, Similarly, a true signal at ~I13 causes EDS6 to route the information input : from the ORTl output to the information input of EI and ~: the true signal at O~I14 enables the OR gate 109 to activatethe load (L) input of EI and load the current absolute word -:
~3 into EI. It should be noted that all current absolute words -74- `

~ f~
-`~ ~27767 1 for one occurrence vector are suppli~d in sequence lar~est to smallest by the same cnlling module The i30-entropicgram width (HW) is stored in the input parame~er register ile IPP~F. Loading of the iso-entropicgram width into El~ is enabled by true si~nals at any one of the following outputs: OMl output of the OUTPUT I;~ODULE; SM3 output o~ the SEED I~DULE; and the CM3 outlet of the ~LANGE ~DULE.
OPSW i9 an output circuit of the OPSW flip flop in the OUTPUT ~DULE. OPSW is the lo~ical inversion of OPSW. Only the OUTPUT ~IODULE determines if clipping is to take place and, if it 18 to take place, the OPSW flip flop is in a 1 state, othexwise it is in an 0 state. Since it is sssumed for the following explanation that no clipping is to take place, a txue signal appears at ~n~R.
The EFRST flip flop is set to a 1 state whenever the present call on the ENCO~E MoDULE i8 for convertin~ the first absolute word in a particular occurrence vector.
EFRST is set by the calling module. In the case of the REVO~VE ~I~DULE, a true signal is formed at the RM2 output, whereas, in the case of the OUTPUT MODULE, a true signal is formed at the OMl output, and enable~ the OR gate 105 to `
set the E$RST flip flop to a 1 state.
The EL~ST flip flop indicate~ if the current absolute word is the last one of an occurrence vector. A 1 state of 2S EIAST indlcates the last one, whereas the 0 state ind~cates it is not the last one. ELAST i8 set by the calling module.
In the case of the REVOLVE M~ULE, a true signal is formed at RM9 and in the case o~ the OUTPUT ~SODULE, a true signal ~: .

3a is forn~d at O~118, either of which causes the OR gate 106 to!~ set ELPST to a 1 state, .., ~ -75- -- ~ S~ ~ _ ~' ~
~ 767 1 ~ssume initi~lly that ELAST i5 in an O ~tate InitiaLly the MINI CO~IPUlER ~orms a true signal at MINIT
whicll causes gates 118 and 117 to set all of control counters 113 and flip flop ECE to 0. To be explained hereafter, true signals at E~ thereafter set tl~ese elements to 0. The E~CODE MODULE is called by the RE~DLVE ~DULE by forming a true signal at RM7 and by the OUTPUT ~IODULE by forming a true signal at OM15. Either of these true signals enables the OR gate 107 to trigger theENGO one-shot multi vibrator which, in turn, causes a true signal at the ENGO
output. The true signal at the ENGO output causes the E OE
flip flop to be set to a 1 state. The 1 state of the E OE
flip flop causes a true signal at the E OE output which, in turn, causes the A~D gate 112 to couple the CLK output lS of the clock 102 to the clock input of each of the control counter 113 flip flops Pl-P12. Clock ~ignals now being formed at the output of the AND gate 112 cause the E~CCDE -MCDULE to commence its sequence of operation by virtue of the control action of control counter 113. All ~lip flop3 Pl-Pll being in an 0 state and a true signal being formed at ~FgR cause flip flop P5 to be set to a 1 state, fon~ing a true signal at the P5 output.
One orm of clipping i9 caused by the OPSW flip flop ln a 1 state. An alternate form o clipping ls automatically done by the ENOODE MO~ULE, Specifically, in the alternate clipping, the absolute words of an occurrence vector are received by the ENCODE MDDULE in decreasing order of magnitude.
The ENCODE ~DULE automatically clip8 or discards all of those absolute ~ord~ wbich are larger than the iso-entropicgram width 3a and hence lie ouL~ide of the iso-entropicgra~. The alternate ~ -76-L

~ c ~iz~

1 form o cl~ppin~ i9 very useful ln connection with ~he REVOLVE ~`IODUL~ where the result of an exclusive OR is clipped ~ keep only the lower ordered values which are within the iso-entropicgram width The ENCODE MODULE
will automatically perform this clipping, using flow chart blocks EB6 and EB8.
Considering the alternate clipping function in ~-more detail, EFRST is set to 1 when the ENCODE MODULE
i~ called for the first time to encode an occurrence vector. This is done to insure that the alternate clipping function is performed. Thus at EB6, flip flop EFRST being in a 1 state, causes EB8 to be entered where the iso-entropicgram width ~n register E~ is compared with the input current absolute word in register EI. If the content 15 of E~ ~ EI, the operation of the ENCODE ~DULE is ~ ;
exited by formin~ a true signal at E~lEND, thereby indicating to the calling module (l.e., REVOLVE) that it has processed one absolute word. Actually, the absolute word is 3ust discarded by the ENCODE MCDULE. When the c~ing module again calls the E~CODE M~DULE to cause another absolute word of the same occurrence vector to be processed, flip flop EFRST
will still be in a 1 state, causing EB8 to again be entered.
If the current absolute word is larger in value than the iso-entropicgram width, an exit i8 agaln taken. This is 25 repeated until at EB8 the current absolute word i9 smaller -`
than the iso-entropicgram width (e,g. EHW~ EI~ at which time EB9 is entered to reset flip 10p EFRST to 0. Thereafter when called, the ENCODE MODULE do~ not perform clipping because the ENOODE MCDULE goes from EB6 to EB7.
3 Consider now the operation durin~ E~8 and EB9 in detail. --~'Z~ 76~

1 ~ssume EBl ~nd EB6 of the ENCOD~ ~`IODULE ~low have been travers~d, and assume EB~ is no~ entered during which the iso-entropicgram widtll in E~ i9 compared with the current absolute ~ord in EI. If the current absolute word i9 larger than tlle iso-entropicgram width, it is outside of the iso-entropicgram and therefore a "don't care" condition exists.
To perform the comparison, the true signal at P5 causes EDSl and EDS2 to couple the contents of EH~I and EI to the arithmetic unit ALU. ALU, together with the OR ~ates 108 and 110, in turn form true signals at outputs LE and G whenever the content of EHW is, respectively, ? than and c than the content of EI. If the C condition i~ sensed, true signals are now formed at the P5, LE an~ EFRST outputs and the true signal at ~ causes the CLOCK SUSPENSION LOGIC

-122 (i.e., P5-LE'CLK) to reset the ECE flip flop to an O
state which, in turn, removes the true s~gnal at E OE and thereby causes the AND gate lt~ to stop forming cloclc signals at the lnput of the control counter 113. The same --signal causes the one-shot EMEND to fire and form a true signal at EI~1END. This signal notifies the caller that the ENCODE function has been completed. It also resets control counter 113 through OR gate 112. This, then, in effect causes an EXlT ~o be taken from the ENOODE ~IODULE where no action is talcen until the next request is made to the ENCODE MODULE
from the RE~DLVE or OUTPUT ~ODULE, If, on the other hand, the content of E~ is ~ than the content of EI (true signal at G), EB9 is entered. Assume during EB8 the content o~ EHW is ~ than that o EI and a true si~nal is formed at G, causing EB9 to be entered. The-~3 BS~ flip flop states of O and 1 indicate the previous absolute ~-~ ~ ~
~2~7G7 1 word has been entcred in the hybrid coded output in bit string form and a~solute word Eorm, respectively. Since the ils~ hybrid word i9 al~ays in absolute word form, ESW
is to be set to 0, indicating tl~ t the correspondin~ output S is in absolute word form and the ~R3 and ~ ~ 3 registers :
are cleared to initia~ or O states, ready for the first hybrid word to be stored in the MEMORY ~IODULE.
During EB~, true signals are formed at the following ~-outputs: G, EFRST, and P5. Hence, at the follot~ing pulse at ~ , the counters and re~isters NOC, MAR3 and ~N3 and flip flops EFRST and EL~ST are all reset to 0.
EBl9 iB then entered and the same signals cause ER
to be reset to O and the reset logic resets BSW and ~B :
of rezister EOP to 0.
lS Followlng EBl9, EB20 i9 entered during ~hic'.l the sane :.
true signal~ are also present ~hich causes load logic to . load the current absolute word into EO. The current absolute word in EO now forms the previous absolute word for the next call on the E~CODE ~IODULE. The same logic 20 also causes NOC to count up one state, indicating that one -~
absolute word has now been provided to the ENCODE MoDULE.
At this point, a true signal i8 formed at the outputs P5, EFRST. Thereore, the next pulse at ~3g, the E OE flip -:;`
flop is reset to 0, thereby disabling the gate 112 ~rom applying clock signals to the control counter 113 as described above.
Subsequently, the calling module again calls the ENCODE ~DULE and provides the next current absolute word at which time a true signal i9 applied at either the R~I7 or 3 OMl5 output (of the ~EVOLVE or OUIPUT ~IO~ULES) causing `

.'. ' :~ -79-~27767 1 the OR gate 107 to trigger the one shot multi vibrator circuit ENGO, thereby setting the ECE flip flop baclc to a 1 state and enabling the AND gate 112 to apply clock signal~ to the control counter 113.
~t this point, it is assumed that the next current absolute word is not the last one in the occurrence vector and hence the ELAST flip flop is in an 0 state, forming a true signal at ELAST. This cause~ the next clock pulse ~rom gate 112 to reset flip flop P5 and set flip flop P6 to a 1 state, thereby enabling EB10 to be entered.
During EB10, a true signal i~ formed at the P6 output which causes EDSl and EDS2 to couple the previous absolute word contained in EO and the current absolute word contained in EI to the ALU which forms an output at OP corresponding to the difference This difference i8 reerred to as the previous and current difference signal. Additionally, the --signal at EDS7 causes the selection circuit EDS7 to gate the previous and current diference signal to the information input of the ET into which the signal is loaded by the subsequent clock signal at ~ . Thus, ET now contains the prevlous and current difference signal which i8 the number of bltq of displacement (either in event time or in possible occurrence values) between the current absolute word in EI and the previous absolute word in EO. Additionally~
the truo signal at P5 causes the U/D 1ip flop to be reset to a 1 state, asserting its true signal at the U/D output, thereby causing CTR to be set so th~t it counts down. The P6 output of the P6 flip flop is connected directly to the input o~ the P7 flip ~lop, thus the ~ollowing clock coming `30 out o~ the gate 112 causes the P7 flip flop to be set to a 1 state, thereby entering EBll~

' - ~
~z~767 1 Durin~ EBLl, the previou~ ~nd current di~erenoe signal contained in ET is subtracted from the remainin~ binary bit signal contained in ER, ~he remaining binary bit signals represent the remaining binary bits to be filled in the bit string word being formed in EOP, The subtraction results in a difference signal during EBll which indicates ~
one of two values and these will now be explained. If the ~- -content of ER is larger than or equal to ET, the difference is ~ than 0, meaning that the d~fference represents the remaining available bits in the bit string word (now under formation in EOP) after current absolute word is entered. - -If the content of ER is ~ than ET, the difference is le98 ;
than O (or -), meaning that the difference represents the -~
number of bits needed in the next bit string word ~to be formed) to enter the current absolute word. An example of thesQ two conditions is now given: the bit string word has a maximum of 7 available bits (see register 114 in EOP ;:
having 8 bits, less 1 fla~ bit - 7). Assume the remaining available binary bits signal in ER - 5 and the previous and current difference signal in ET ~ 3, givin~ a positive difference of 2. The difference of +2 represents the remaining avai~ble bit~ in the bit string word after the current absolute word. If the values are reversed CER ~ 3 and ET - 5), tben the diference is -2 and representa the number of bits needed in the next bit string word to enter the current absolute word. In other words, tbe current absolute word will require all remaining available bits ~R) in the current bit string word under formation in EOP plu9 2 additional bits in the next bit s~ring word to ~3 be formed. ;

~ ~ ~ r -~ f~ ~
~X`'~767 1 ~en on a previous cnll to the E~lCODE ~IOD~.E it W~9 ~ound (during E~13) tha~ the current absolute word was to be outputted i~ ~bsolute word orm, ER wa~ reset to O at EBl~
and hence is O at the next entry to E~ll. Under these condi~ions, a difference less than O is formed durin~ EBll.
Howeve~, the difference iq the negative o~ ET (O-ET D -ET).
Consider now the detail~ of operation. Assume that ~-the ENCODE MODULE is at EBll, and a true control signal is being formed at the P7 output. This causes EDSl and EDS2 to couple the content of ER and ET to ~LU which, in turn, forms an output representing ER - ET. Assume the result i8 ~- O. A control signal is fonmed at the L output of ALU, -indicating that there are insufficient bits in EOP for the current absolute word. EB12 is entered.
During EB12, the control signal at P7 snd L cause3 EDS7 and the load logic for ET to store the number of bits needed in the next bit 3tr~ng word signal being formed at EOP into ET at the ~ollowing pulse at m. Additionally, the same true signals cause EDS3 and the load logic of CTR to store the content of ER into the counter, setting it to a state corresponding to the content of ER. I~ ER contains 0, as occurs when this is only the second call on the ENCODE MODULE
and hence is the ~econd time through the flow, the true signals at P7 and L also cause the ~lip ~lop P8 to be set into a 1 state~ thereby causing EB13 to be entered. If ER contains O, CTr~ is set to 0, causing a true signal at the Co output.
The true signals at P8 and Co cause the P9 flip flop to be set to a 1 state and EB15 i8 entered, thereby skipping EB14, To be explained in more detail, EBl4 causes the bi~
3a string word being formed in EOP to be ~illed out with leading O's.
. , '. ~, "; ~

~ 77~7 l This opera~ion, ~nd hence E~14, is slcipped ~hen ER i~ O
since no remaining bits need to be illed in ~he bit string word under formation.
Return now to EBll and consider t,~,operation when E~ is not O and ER-ET is C~ O causing a true signal at the J. output of ALU; Note that ER is not O when a bit string word is being formed in EOP and available bits exist in EOP in the bit string word under formation. EB12 and 13 are entered as discussed above - -~and CTR is set to a state corre~ponding to the number o binary bits remaiuing to be filled value contained in ER.
During EBl4, a true signal exists ~t P8 and ~ (CTR is not O)`
and each pulse at ~ counts CTR do~?n one and causes the ~ -EOP shift logic to shift the bit string word one bit position t in the direction of the least signi~icant bit thereof until CTR reaches 0, at which time the true Yignal at ~ is removed and one is formed at Co. Thi~ causes CTR and EOP to stop counting and shifting and EB15 i~ entered as discus~ed above. l~-Assume that during E815 the BSW flip flop i8 in an 0 state,having previously been set there during EBl9 thereby indicating 2 that the next event in the hybrid output from the previous ¦ event i8 to be in the fonm o~ an absolute word. With BSW in ¦ an 0 state, EB16 i9 entered. During EB16, the fal~e signal ¦ at ~Y causes the load logic of register 114 to load the ¦ previoua absolute word contained in EO lnto the re8ister 114 2S ¦ of EOP and true 8i8nal9 at P9 and ~ c~use the logic ¦ P9-~R to set the ~$B fllp flop to a 1 state~ indicating ¦ that the word in EOP i9 an absolute word. Subsequently, ¦ EBl7 is entered.
¦ During EB17, the P9 output ~ee right hand of ENCODE
30 ¦ t~ULE schematic) cause~ a ~rite Enable ~ignal ~WI) to be !-1~
. -~
.
1.

-~` ~
I l~Z~.~7~7 1 ¦ formed in the MEMORY M~DULE, cau~ing it to store the absolut-¦ word contained in EOP into the storage location de~ignated by ¦ the content of ~fAR3 ¦ The true signals at P9 and the pulse at ~;R cause the S ¦ content of MAR3 and MLN3 to count up one state In th~s ¦ manner, the counter ~N3 always lndicates the number of ¦ memory writes and hybrid coded words written in the MEMDRY
¦ MODULE. Thus, an absolute word is outputted by the formation ¦ of the true signal at the P9 output which, in turn, causes --10 ¦ the MEMDRY ~ULE to read the absolute word from EOP.
Return now to I~Bll and consider the situation where ¦ a previous absolute word i9 contained in EO, a current ¦ absolute word i8 contained in EI, and ER is ~ ET. ALU
I forms the difference between ER and ET (i.e., ER - ET) lS I and ALU and gate 108 form a true signal. The difference ¦ ~ignal at the output OP of ALU represents the remaiDing ¦ avallable bits in th- bit string word now under formation ¦ in EOP after entry of the current absolute word iD EI.
¦ Under these coDditions, the bit strlng word being formed 20 iD EOP is shifted by the number of bit positions ~ndicated ¦ by ET and the current absolute word ~8 entered into EOP.
To this end, hB22 is entered from EBll. The tru-~igna'~ fo~d at P7 and GE cauoe the load logic of ER
¦ to store the differen~- Jignal being formed at the OP
2S ¦ output of AI~U lnto ER at thej c~uer~ of tA- followiDg ¦ pulse at ~g. Thus, ER ~ow containJ the new number of bits ¦ ~eemalning to be fill-d ln the bit strlng word under formation which will exist after the curreDt absolute word is entered.
Addltlonall~r, th- same sigDals cause EDS3 and the load logic ~0 to store in CTR the pr~vious and current difference signal iD ET. The true ~ignals at P7 and OE cause the Pll flip flop --~ ~ 7~7 1 to be set to a 1 3tate at the next cloclc signa~ from gate 112 and thereby enter E823.
Dur~ng EB23, a~ the subsequent state E~24, CTR
i5 enabled to count tllrough a sequence o states corres-ponding in number to the previous and current difference signal which was set into CTR fxom ET. To thi~ end, the ~ -true signal at Pll and at C~, together with the true signal at U/D, cause CTR to count down 1 state responsive to each true signal at CLK. Additionally, in the absence of an O
state of CT~, a true signal i9 formed at the æ output.
The true signal~ at Pll, Z~ cause the reglster EOP to be shifted 1 bit position to the right in the direction of the least ~ignificant bit. This operation continues until the counter reaches O and a true 9ignal i8 formed at the Co output. When a true signal i8 formed at the Co output, counting and shifting of CTR and EOP i9 complete and the --ENCODE ~DDULE i8 ready to enter the value of the current absolute word in EI into the shifted bit string word in EOP.
EB25 is entered.
During E825, a true signal is formed at the Co output and the subsequent true signal at ~g causes the fllp flops MSB of EOP and BSW to be set to a 1 state. To be explained, the 1 bit stored in MSB i9 subsequently shi~ted into register 114 of EOP durin~ EB26, thereby causing a bit of predetermined 2S value, i.e., a 1 bit~ the bit string word being formed in EOP.
The number of bit positions existin~ between ~he currently formed 1 bit and the previousl~ formed 1 bit or bet~een the currently formed 1 bit and the previous absolute word in the series of hybrid word outputs indicates the value 3a of the current absolute word. The 1 state o 8S~ indicates ~7767 1 that ~ b~t s~rin~ word is now bein~ form~d in EOP
The true signsl at Pll and Co cause the ~lip flop P12 to be set to a 1 state at the ~ollowiu~ clock si~nal from gate 112 and EB26 i8 thereby entered.
During EB26, a true signal i~ formed at the P12 output and ~he subsequent pulse at ~ causes the content of EOP, including the content of ~ISB and register 114, to be shifted 1 bit position t~ard the ri~ht toward the least significant end, thereby placin, the 1 bit into the register 114 portion of EOP, EB20 is now entered. During EB20, a control signal is now formed at the P12 output and the BSW flip flop is in a 1 state. The subsequent pulse at C~ causes load logic to store the current absolute word contained in EI into EO
thereby formin~ a new previous absolute word and causes ~OC to count up one state, thereby indicatin~ that another absolute word ha~ been encoded into hybrid form. NOC countY, and thereby indicates, the number of 1 bits proce~sed in any given seed. Addltionally, the true signal at P12 causes the EOE flip flop to be set to an 0 state at the pul~e at ~g, di~abling clock signals at the output o gate 112, causing the E~D monostable to ~ire and thereby form a true slgnal at the EME~ output. This causes counter 113 to be reset and the ENCODE ~DULE operation to EXIT, 2 A very important operation in the ENCODE ~DDULE i8 depicted at EB18; This is the condition under which previous ~` and current diference signal contained in ET is compared with a predetermined threshold value. This is the heart o the deciiion which enables a change, in hybrid output, 3 from bi~ strin~ word orm to absolute word form and the ..

i -86- -~'.

~-~ (' ~ ~
~Z'7767 1 operation ~s accomplished ~9 follows. During EBl~, the P10 ~lip ~lop is in a 1 9 ~ate, cau~n~ a true si~n~l at th~ P10 outpu~. This causes EDSl and EDS2 to coupl~ the ~witches 104 and the output o~ ET to ~LU The ~LU compare9 the applied si~nal3 and adds the con~ent of ET to the val~e 7 represented by theswitches 104 and orms a resul~ at oP.
It should be noted that when EBl~ is entered, the content o~ the ET i5 always a negative number, the number being stored in 2's complement form. The reason for this 10 situation i~ that ET at this point in the operation always - -indicates the number of bits needed in the next bit string word to enter the current absolute word which i8 a ~ituation where at EBll, ET was larger than ER re~ulting in a negative valu~. Thus, at EB18 ~hen ALU combines the content of ET with the value 7 from 104, a difference ~ignal is formed. ~f the difference signal i8~ O, i.e, the value 7 i~ the absolute value in ET~ a control signal is formed at G and EB21 is entered. If the value 7 i9 ~ the absolute value in ET, the d~Fference signal will be C 0, causing a control si~nal at the LE outpu~ o~ OR gate 110, which in turn causes EBl9 to be entered. The result of the compari~on of the value 7 and the absolute value in ET
is quite important in determining subsequent operations.
If the absolute value in ET i9~ 7 (the value 7 is grea~es), a contxol si3nal 18 formed at G and tho criteria is not met or switching from bit string word to absolute word in the hybrid output because 7 is greater than the absolute value ~ in ET, Accordingly, EB21-26 are entered where the current ; absolute word in EI i8 entered in the bit string word underformation in EOP, To this end, EOP i8 shifted right by the ~ ~3a l~Z~767 1 number o blts indicnted by the nbsolute val~e o~ the prev~ous and current di~ference si~nal contained in ET and ~hen a "1"
bit entry i9 made into the bit strinz ~ord bein~ formed in EOP, I~, on the oth~r hand, the absolute value in ET is ~
tllan the threshold value 7~ it would be a saving in memory space to s~7itch ~rom bit string word ~orm to absolute word form. EBl9-20 is entered During EBl9-20, as discussed above, logic resets flip flop BSW to 0, indicat~ng an absolute word form in the hybrid output for the current absolute s~ord.
The operation during EBl9 and EB26 has already been discùssed hereinabove. Therefore consider EB21. During EB21, true signals are for~ed at the following outputs:
P10, G and at thc ollowing pulse at ~g, the U/D flip flop is reset to an O state, causing the counter to be set to count up and EB2 is entered. The least significant 4 bits of the 2's complement value in ET are set in CTR.
'~herefore as CTR is counted up it ~ill return to O after -~ -the number of counts represented by the absolute value of ET. -During EB22, the content of ET 18 transferred to CTR
and subsequently during EB23 and 24, CTR is counted up until it finally is recycled to an 0 state, causing a control sigDal at Co. For each state of CTR, the content of EOP 18 shifted right by one. When CTR reaches O, the 2S control signal at Co causes the MSB 1ip flop of EOP to b~
set to 1, ther-by pxoviding another occurrencc in the bit ~tring word output and subsequently during EB26~ the 1 bit i~ shifted into the reglster 114 of EOP, all as described above.
3a Thus, it should now be clearly understood tbat at EB18, determining whether the value in ET (the number of bits ~ : '. ' o f~
i~z~67 ~ .
1 needed in the ne~ct bit str~ng word to enter t~ current absol-ute ~Jord) is ~7, ~lso determines whether the ENCODE ~DULE
switches ~--om bit string word to absolute string form of output.
There is at least one occurrence held within the ENCODE ~DULE that needs to be written out at the end of its operation~ Therefore, after the calling module has finished using the ENCCDE ~XDULE, the occurrence being held must be outputted. The calling module-outputs the remaining occurrence by setting flip 10p ELAST. Flip flop ELAST
is set by the RE~DLUE K DULE by forming a signal at R~I9 and by the OUIPUT ~ICDULE by ~orming a signal at 0M18, either of which cau~es the OR gate 106 to set ELAST to a 1 state. The 1 ~tate of ~LAST causes a true signal at the lS ELAST output, thereby ind~cating this is the last call on the ENCODE ~ODULE for the occurrence vector currently béing converted to hybrid form. The control signal at the ELAST output occurs when the ENCODE MODULE EXITS during -the 1 st~te o~ P5, After the control signal at the ELAST
output is formed, a control signal is formed by the REV~LVE or OUTPUT ~DULE at F~I7 or OM15, thereby causing the OR ~ste 107 to trigger the ENGO shot multi-vibrator, thereby causing the ECE flip flop to be set to a 1 state and hence the AND gate 112 to start providing clock pulses ~here EB27 i8 entered.
During EB27, the true control signals at P5 and ELAST
enable signals being formed at the output of ~witches 116, representing th- 218 complemient of 8, to be gated through the EDS7 selection circuit and allow the following signal 3 at CIl~ to load the 219 comolement of 8 ti.e.~ a -8) into ET.
~ .
' ~.

`!~

~ ~ 7767 1 ~dditionally, the ~rue controL 9 ignal at PS en3bles the si~nal in ER, representin~ the number o~ binary bits remalnin~ to be illed (in the bit ntring ~70rd under formation in EOP), to be ~ated through EDS3 to the input o~ CTR enabling the ~ame pulse at CLI~ to load thi3 value ~nto CTR, The ~rue signa~ at outputs P5 and ELAST
cause the P8 flip flop to be set to a 1 state, thereby causing EB13 to be entered. During EB13 and 14, the b~t string ~ord in EOP is filled out with leading 019 and ri~ht justiied by shifting the bit string word in EOP
and counting CTR d~n until CTR ~ O. Subsequently, EB15 and 17 are entered where the resultant bit string word is outputted. Of course, should ER be O and hence the CTR
i8 set to 0, right shifting is skipped, and outputting i~
done im~ediately.
The fore~oing description of the E~CODE ~D~ULE was made assuming t~ no clipping was to ta~ce place. Only the OUTPUT ~ODULE enables cllpping to take place If clipping is to take piace, the OuLrUT ~DDULE initially form~ true signals which enable the bottom limit register EBL, the top limit register ETL, and interval registers EIR to be loaded. To this end, the OUTPUT MODI~ forms a true signal at OM16 and then a true signal at OMl. The input o~ selection circuits EDS4 and EDS5 and register EIR are connected to 2S the BL, TL and IR registers of IPRF OE ig.52)~ Thus, the true signaLs at 0~16 and o~ll cau3e the bottom limit, top limit and interval value (if an interval value exist~) to be strobed from IPRF into EBL, ETL and EIR via the load logic contained in each of these registers. The interval ~3 value i9 only used and, hence, an interval value stored in -90- ~.
.; ~ '`

c) ~`~
~ l~Z7767 1 the interval re~ister EIP~ i the user ~ es ~o ascertain i~
the ou~put l~e~ in certain intervals. For ex~mple~ i~ the user were to check the intervals between 35 and 25, and then agaln between 15 and 5 o~ an occurrence vector, he speci~ies an interval value of 10. The clipping ~unction in general forces the output to lie bet~Jeen certain values set by the user. Thus, the opexat~on of tlte ENCCDE MODULE
i~ to compare the very ~irst absolute word of an occurrence vector, which of course i9 the highest one, with the content lO of ETL and EBL. I4 the interval value ls 0, i.e., it is -not desired to check between different intervals, and if the current entry lies ou~3ide of either limit, the ENCODE
~XDULE operation EXITS since the value lies out~ide of the pre~cribed limits. If, on the other hand, ~e interval - lS value contained in EIR is other thsn 0, this means that it i8 desired to check bet~een different limits and the limits contained in ETL and EBL are reduced to new limits by the interval value in EIR. Then the comparison between EI and ETL and EBL is repeated using the new reduced limits. It should be notod that in the example of the ENCODE M~DULE included herewith, it is only desired to check for increments in a downward direction. Therefore, if the current ab301ute ~ord contained in EI iq above ETL, the ENC~DE IIODULE operation Automatically EXITS without 2S decrementin~.
Conside~ no~ the actual clippin~ and interval function in the ENCODE ~IODULE. The OUTPUT ~DULE sets oPS~r flip flop, contained therein, to a i state. ~hen flip flops Pl-Pll of the control counter 113 are in an O state causing true 3C control signals at the ~ 11 out~uts and the oPsw output . ..
-91- :

-~ o liZ'^~67 l has a ~rue signal, ~lle ne~;~ clocl; causes the Pl ~lip 10p to be set to a 1 ~tate Dur~n~ E~S2, the control~n~l at the Pl ou~put c~uses ~he ~DSl ~nd ~DS2 ~election circuits to couple the content o~ ETL and EIn to ~LU I~ the top limit in ETL
is ' the curr~nt absolute word in EI, the current absolute word i3 out of limit and a control signal is ~ormed at the L output of ALU and at the following cloclc pulse at CLK, the EOE
flip ~lop is reset to O, disabling the clock to the control counter 113, resetting counter 113 to 0, causing the ENCODE ~DDULE to E~IT and firing one-shot E~ND.
If the top limit in ETL is C the current absolu~e word in EI, a control signal i9 formed at the GE output of the OR gate 108. A true signal i9 also being formed at the Pl outpu~ and the combination of true signals at Pl and GE
causes the P2 ~lip flop to be set to a 1 state, thereby causing EB3 to be entered.
During EB3, the content of EBL is compared with the content of El. To thi3 end, the true signal a~ P2 causes EDSl and EDS2 to couple the content of EBL and EIR to ALU.
I~ the bottom limit in EBL i~ the current ab~olute word in EI, a control signal is formed at the G output of ALU and EB4 i3 entered. If, on the oth~ hand, the botto~ limit in EB~ is ~, the current absolute word in EI gate 110 forms a control signal at LE, causing EB6 to be entered~ The operatlon followlng ~B6 i8 the same as that described above and need not be reconsidered here.
However, assume that the bottom limit in EBL is greater than the current absolute word in EI and a control si~nal i9 fDrmed at the G output~ causing EB4 to be entered. EB4 i9 `3 only shown in the ENCODE ~IODULE flow in order to indicate that -'.

,..

~' . , ,, " : ~!, ~. ~ ` , . . ,. . .

~ c~
~ 1~7767 1 ~ decision is made based on ~hether the interv~l value contalned in EIR is 0 or ~ 0. I~, at the time, t~ue ~i~nals are ~onmed at P2 and G, the content o~ EI~ i3 not 0, a control signal i9 ormed at the E~ output o~ E m, The true signaL at ~ ~n coincidence with tlle control signal at P2 and G enables the P3 flip flop to be set to a 1 state at the foll~ing clock signal from gate 112, thereby entering EB5 During EB5, the top limit in ETL and bottom limit in EBL
are decremented by the interval value contained in EIR. To this end, a true signal is now formed at the P3 output, causing EDSl and EDS2 to couple the values contained in EBL
and EIR to the input of ALU~ thereby causing ALU to form a decremented bottom limit corresponding to the di~ference ~EBL - EIR). The true signal at P3 also causes EDS4 to couple the decremented bottom limit at OP to the input of EBL.
The sub~equent signal at ~R causes the load logic of EBL to store the decremented bottom limit into EBL. Thus, EBL
now contains the previou3 bottom limit value decremented by the interval value contained in EIR. The true signal at the P3 output csuses the P4 flip flop to be set to a 1 state at the folloing clock signal from gate 112. The control signal at P~ causes EDSl and EDS2 to couple the content o~ the top limit in ETL and the interval value in EIR to ALU, causing A~U to form a decremented top limit at OP
2S repxesenting the difference (ETL - EIR)~ The control signal at the P4 output causes EDS5 to couple the decremented top limit from OP to ETL and the follo~ing signal at CL~ causes the decremented top limit to be stored in ETL. Thus, ETL -~:~ now contains the previous top limit value decremented by the ~: ~ interval value contained in EIR. EB2 and EB3 are again .' : -93--~ 1~'~7767 1 entered ~here the input val~e is a~ain compared, ~his time wi~h the decrement~d top and decremented bottom limit values as de3cribed hereinabove .Example of O~eration A better understanding of the operatlon of the ENOODE
~DULE will be had with reference to the following ENCODE
~ULE example. During th~ example, it i~ assumed that the ENCODE ~DULE ~s called six times to convert the ollowing input entries from one occurrence vector and coded in absolute form to hybrid form: 125, 123, 119, 116, 114, 100.
To further aid in undexstanding of the invent~on, it is assumed that no clipping i9 to take place. Although the clipping funclion i8 an important feature in one aspect of the invention. Rather than give a complete word description of the following opration, the opera~ion i8 indicated in symbolic form.

2~
: . ' '"' ~ ',,',.' -, ~ 30 I
: .

..
.;,, "~ o ~

Input on the in~tia~ call:
OPSI~ - O , ETL ~ EBL - EIR
EFRST 8 1; E~ ~ 128 EI ~ 125 ..
The sequPnce ~ollowed is:
EBl, EB6, EB~ - EB9, EBl9 - EB20 EBl : OP~J = O .-. control goes to EB6 EB6 : EFRST - l:. control goes to EB8 EB8 : EI (125) ~ E~ (128) The input is less than the iso-entrp-picgram width. Therefore, control goes to EB9;
EB9 : EFRST ~ ELAST - O reset flip flops;
NOC - O clear number of occurrences;
MAR3 ~ MLN3 - O clear output memory area address . register and length register;
: EBl9 : ER ~ O indicates there are no remaining bits ~ft in output register EOP
Here used to force an absolute .
ones index form (AOI) output on the next call;
BSW ~ O indicates we are in absolute ones index fonm;

EB20 : EO(125? - EI~125) current input becomes previous input;
~ NOC(l) o NOC(O) ~ 1 up the number of occurrences :~ by one;
: ~3 HALT
~ . .
~ -95- ~ .

~ o ~
1~27'~67 1 Output: EOP ~ 0 MLN3 = 0 NOC ~ 1 Memory area blank second call: EI = 123 EFRS~ - 0 Other parameters remain as for first call;
Sequence of control: EB], EB6-EB7, EB10-EB13, EB15-EB18, EB21-EB24, EB23; EB25-EB26, EB20 EBl OPSW = 0 .~. control to EB6 EB6 EFRST = 0 .'. control to EB7 EB7 ELAST s 0 .-. control to EB10 EB10 ET(2) - EO(125) - EI(123) bit distance be ween previous and absolute word; -.-~
set. U/j ~ 1 .'. CTR to count down lS EBll ER(0) - ET(2) ~ O the current absolute word cannot . be placed in the remaining number of bits in EOP :. control to EB12; .
EB12 ET - -2 kept in 2's complement form; i.e., ET = 11111110~ .-CTR (0~ z ER (0) the amount the output register must be shifted,if in bit string ~:
form, to keep alignment;
EB13 CTR - 0 .. control to EB15 : .
EB15 BSW - 0 .. control to EB16 .. -EB16 EOPtl25) - EDtl25)set output equal to previous input.:

~- .' '.''.
: -'' '`

~ 30 : . ;`,~' ~ o 1~27767 l MSB ~EOP) ~ 1 set si8n bit to indicate absolute word form (AOI);

5 EBl7 Memory write of EOP
MhR3(1) - MAR3(0) ~ 1 pointer to next memory area address;
MIN3(1) ~ MLN3(0) ~ 1 current physic~l length of output;
EB18 ET(-2) + 7 ~ O :. control to EB21 EB21 Set counter to count-up since the number to be clocked U/D ~ O to CTR i8 ~ O, must count up to reach O;
EB22 ER(5) ~ ET(-2) ~ 7 number of remaining bits that can ~.-;
be used in EOP;
CTR(6)~ ET(-2) the counter is loaded from the .-rightmost 3 bits of the 2'8 ~
complement of ^2, i.e. 1111 ~ : :-EB23 CTR(7) - CTR(6) ~ ) .control to EB24 EB24 EOP - OXXXXXXX shift EOP`right;
EB23 CTR(O) - CTR~7) ~ O).'.control to E825 since CTR is 3 bit register, adding a 1 to the 7 causes wraparound to occur;
EB25 EOP - 10000000 turn on sign bit;
2 BSW - 1 indicates bit strin~ form;
EB26 EOP ~ OlOX~ 9hift EOP right one since sign bit position is used to indicate type;
~ ~ . . .
: ~ ~ -' . ' ,'~':
:-: -97- :.

( ) ~lZ7767 1 E~20 EO(123) - EI(123) ~urren~ absoluto word become~ previous NOC(2) ~ NoC(l) ~ 1 number o~ occurrences is bumped;
I~LT ~emory ~rea Output EOP - OlO~YXXX MLN3 ~ 1 NOC ~ 2 llllllOl X ~ remaining bits to be used Third Call EI ~ 119 . other paramaters remain the same;
Sequence of control EBl, EB6-EB7, EB10-EBll, EB22-EB24, -EB23-EB24, EB23-24, EB23, EB25-EB26, :

EBl OPSW ~ O :. control to EB6 -~
EB6 EFRST - O :, control to EB7 EB7 ELAST ~ O :. control to EB10 :--EB10 ET(4) - EO(123) - EI(119) ET - bit distance to be considered;
EBll ER(5) - ET(4) ~ O control to EB22 EB22 ER(l) ~ ER(5) - ET(4) ER - number of bitg left in EOP after current absolute word process; - -CTR(4) ~ ET(4) nwmber of positions EOP must be ri8ht shifted before the sign bit ~:
. i8 set;
: EB23 CTR(3)~-CTR(4) ~ 0). control ~o EB24 ::
EB24 EOP - OOlOXXXX `
2 EB23 CTR(2~t-CTR~3) - 1 (fo) ,~ control to EB24 : ;
EB24 EOP - OOOlOXXX ;-EB23 CTR(l) - CTR(2) - 1 (~0) ,',control to EB24 ;~
EB24 EOP ~ OOOOlOXX
EB23 CTR(O) ~ CTR(l) - 1 (-O) .'. control to EB25 - .
. ," .
~3 . ...
: -98- ;~`

~ ~ .

~,~Z7 1 EB2S EOP ~ 100010X,Y se~ on tho mos~ significant blt;
BSW - 1 indicate bit string,;
EB26 EOP 8 0100010X shift EOP righ~;
EB20 EO(ll9) ~ EI(llg) current absolute word become~ prevlous NOC(3)~NOC(~) + 1 bump the number of occurrences;
}~9LT
Memory Area OUT EOP - 0100010X ~LN3 - 1 N0C - 3 11111101 .

. .
Fourth Call EI - 116 All other parameters remain the same; ~-Sequence of control EBl, EB6-EB7, EB10-EB14, EB13, EB15, EB17-EB18, EB21-EB24, EB23 EB25-EB26, EB~.0;
EBl, EB6, EB7 same as before;
EB10 ET(3)~-- EO(ll9) - EI(116) obtain bit distance;
EBll ER(l) - ET(3) (< 0) there are not enough bits to control to EB12 process this entry using current information in EOP;
EB12 ET(-2)~ER(l) - ET(3) ET - 11111110 in 2's complement form;
CTR(l) ER(l) number of positions that EOP must be shifted to keep alignment; :
EB13 CTR(l) ~ 0 :. control to EB 14 2 EB14 CTR(0) - CTR(l) - 1 EOP ~ 00100010 ri8ht shi~'c EOP;
EB13 CTR(0) - 0 .: ~ontrol to EB15 ~ .
EB15 BSW ~ . control to EB17 . ~, :: _99_ z7767 EB17 write EOP to memory MAR3(2)~--MAR.~(l) + 1 next memory address;
MLN3(2)~-- MLN3(1) ~ 1 physical length of MemOry area;
EB18 ET(-2) ~ 7 (~ 0),', control to EB21 5 EB21 set U/D = 0:. CTR to count up EB22 ER(5) = ET(-2) + 7 CTR(6)~ --ET(.-2~ CTR = rightmost 3 bits of 2's complement ET = 11111 ~ ;
EB23 CTR(7) = CTR(.6~ + 1 ~0~ , control to EB24 EB24 EOP = OOXXXXXX shift EOP X = remaining usable bits for EOP;
EB23 CTR(O) = CTR(7~ + 1 (=0~ 3 bit register - therefore control to EB25 wraparound on the add;
EB25 EOP = 10XXXXXX set sign bit in EOP;
BSW = 1 indicate bit string form; :
EB26 EOP = 010XXXXX shift EOP since sign bit -~
indicates type; ~.
.

EB20 EOC116) = EI(116~ previous unput is replaced by :
the current; :~.
NOC(4~ NOC(3~ + 1 HALT :
Memory Area :
Ou~put EOP = 010XXXXX MLN2 = 2 NOC = 4 11111101 ':
,.

~

, ~127767 1 Fifth Call El z 114 remaining parameters remain -the same;
sequence o control EBl, EB6, EB7, EB10-EBll, EB22-EB24, EB23, EB25-EB26, EB20;
EBl, EB6, ~B7 ' same as before;
EB10 ET(2)t EO(116) - EI(114) bit distance; -set the counter to.down EBll ER(5) - ET(2) ~ 0 . control to EB22 EB22 ER(3) - ER(5) - ET(2) update the remaining;
CTR(2)~ ET(2) number of bits;
EB23 CTR(l) - CTR~2) - 1 (~0).: control to EB24 EB24 EOP - 0010XXXX shift EOP right;
EB23 CTR(0)~- CTR(l) - 1 (-O):.control to EB25 -EB25 EOP ~ 1010XXXX set sign bit of EOP;
BSW - 1 indicate bit string form;
EB26 EOP ~ 01010XXX shift EOP;
EB20 EO(114j ~ EI(114) NOC(5)~NoC(4) + 1 HALT
Memory Area ;;
Output EOP - 01010XXX MLN3 ~ 2 NOC - 511111101 .' . ..
: .
~ ~3 ~, -101-~:

~1: ' ` , . ' ' .,'' ' : ;1 .', ~ .

o (~

1~2~767 Six~ll Call El - 100 all other p~rameters remaln the same;
sequence of control EBl, EB6-EB7, EB10-EB14, S EB13-EB14, EB13-EB14, EB13, EB15, EB17-EB20; :
EBl, EB6, EB7 same as before;
EB10 ET(14)~--EO(114) - EI(100) . - ~
set U/D = 1 :. CTR to count down : -! 10 EBll ER(3) - ET(14) (<O) :, control to EB12 EB12 ET(-ll)~--ER(3) - ET(14) ET in 2's complement form;
CTR(3) - ER(3) number of positions EOP mu~t ; ~.
be 8hifted to keep alignment;
EB13 CTR~8) ~ O :. control to EB14 :-.
EB14 CTR(2) ~ CTR(3) ~
EOP ~ OOlOlOXX ~- .
EB13 CTR(2) ~ O :.control to EB14 ~-EB}4 CTR(l) ~ CTR(2) - 1 .
EOP - OOOlOlOX
20 ¦ EB13 CTR~l) f O .: control to EB14 EB14 CTR(O) - CTR(l) - 1 -EOP - 00001010 ~ :
EB13 CTR(O) ~ O :.control to EB15 EB15 BSW - 1 ., control to EB17 ~S EB17 write memory EOP -MAR3(3) ~ MAR3(2) + 1 NlN3(3) - MI.N3(3) ~ 1 ~
. .. .

~3 ,.

o ~z7~6~

1 EBlS ET(~ 7 < O :.control t~ E~19 EB19 ER = O assure next call will wrlte;
BS1~1 - O current ab~olute word to be in absolute word form;
EB20 EO(100) = EI(100) NOC(6)~ 0C(5) + 1 HALT
. . ..

Memory area Output EOP = O MLN = 3 NOC ~ 6 11111101 Seventh call set ELAST 3 1 all other parameters remain ,.--the same;
sequence of operation EBl, . EB6-EB7, EB27, EB13, EB15 -EB20;
. EBl, EB6 same as before;
EB7 ELAST = 1 . control to EB27 20 EB27 CTR(0) = ER(0) in case we are in bit string;
ET ~ -8 . assure proper balance at EB18;
. EBl3 CTR(O) - O .control to EBl5 EBl5 BSI~ - O , control to EB16 : -2S EB16 EOP~100) ' EO~100) prepare the output;
set sign bit o~ EOP indicates absolute woxd type;
EB17 write EOP
MAR3(4) MAR3(3) -~ 1 next address;
MLN3(4) MLN3(4) ~ 1 length;

:

... ~ 1127767 1 ¦ 13Bl~ ET~ 7 < O ,-, control ~o EB19 ¦ EB19 El~ z O these are meanin~less ¦ BSI~ ~ O ste~s on the last time ¦ EB20 EO(100) - El(100) throu~h - notc that NOC
5 ¦ is not incremented this time;
¦ HALT
¦ Memory area ::
¦ EOP z O MLN3 = 4 NOC = 6 11111101 I 00100010 . -.
10 I 00001010 ,.'' ;'', I 11100100 .. ':.`'' . .

~3 :: '.: ' -lOq-.. ."

~ 67 1 In su~nary, ~7!1~ h~ been disclosad i9 ~n encoder Eor convertin~ ~o hybrid Eorm a received series OL absolute ~qord signal3 of decreasin~ value order. The hybrid ~orm ha~ a series o at least one absolute ~rd si~nal and bit string ~Jord signal. An absolute word signal represent$ t~ value of one occurrence by tl~ combination OL binary coded bit signals. A bit string word signal represents one occurrence by the nu~ber of bits of displacemen~ o a bit of predetermined value therein from an absolute ~ord signal in the hybr~d 10 word series. Means include the ALU, EDS2, EDSl and control ~;
counter 113 operative durin~ EBl~ in response to received previous and current absolute word signals for forming an output signal indicative of the difference in value therebet~een. The previous and current diferent signal is formed at the OP output of A W and i8 stored in ~T.
Additionally, there is me:ns including ET and the control counter 113 for reta~ning the previous and current difference signal. This occurs at EB10.
The encoder al~o ~ncludes means for indicating ab~olute or bit string word form of hybrid output and includes means, lncluding the switches tO4, for indicating a preselected minimum permitted d~fferenre (e.g. 7) between ~ucces~ively received word signals. Such means includes ALU, EDSl, EDS2 and the control counter 113 for comparing the mlnimum difference indication and the retained previous and current difference signal and or indicating the first being~ than or f- to the la~ter.
The encoder also has means ~ r providin~ absolute form ~~
outputs such means including the EOP load and shift logic, the `3 BSW and its set and reset logic and the control counter 113 `~
:.

.i-105- `:

~Z7767 1 oper3~1ve in rcsponse t:o the ' indicQ~lon ~or ol~tp~ lnr, tlle stored curren~ absolute ~ord and an ab~olute ~la~. This operation t~lce3 place durin~ EBlS-20, 10-17.
The encodex ~150 include~ means i~or providin~ bi~
s~rin~ form outpu~s and ha3 means includin~ e EOP, CT
and i~cs load and control logic, EDS2, EP~, EOP sliift log~c, ~ISB set lo~ic and the control counter 113 which are responsive to the ~ indication for forming a set of ordered si~nals comprising a binary bit o~ one value (e.~., 1) associated ~ith the number of binary bits of a second value (e.~., 0) corresponding to the value of the retained previous and current difference signal. It will be seen that the operation i8 depicted by EB21-25. The means ~or providing bit string ~orm outputs also includes means includin~ tke clock and the control counter 113 for selectively outputting the se~
of ~ignals in association with a bit strin~ fla~. The binary bit of one value in the bit string form otput i8 in a predetermined relation to the outputted absolute word.
In this re~ard, the number of bits of displacement between a bit of the one value and an absolute word indicates the value of the one bit.
A pre~-rred embodiment of the encoder has a current such as regist-r EI for storing a currently received absolute ~ord. Means including EDS6 control logic ~tores received 2S absolute words into the current register EI. A previou~
re~ister E0 is provided for storing a previously received absolute word. Means including the E0 control lo~ic and the control counter 113 tran~fers ~he current absolute word ~rom the current re~ister to the previous re~ister, ormins 3 therein the previous absolute word. This is accomplished at EB20.
. :~.
~."--106- ~
1:

1~27767 1 A ~u~ er pre:~er~ed ~mbodiment oE the encoder provide~
llybrid form outpu~ in a series of ~10rds. The means ~or formin~ a set o~ ordered si~nal~ includes coun~er me~n~ CTr~.
CTR h~9 output Co :~or indicating compLetion of coun~ing.
A ~it strin~ word ~orr.lin~ register EOP is provided and means including CTr~ load and control logic and EDS2 is operative durin~ EB21-24 in response to the ~ indication for enabling the counter means to count through a sequence of states corresponding in number to the retained current and previous difference signal contained in ET.
The indicatlon at output Co from CTR indicates completion o the last-mentioned counting Additionally included is means including EOP and i~s shift logic and control counter I13 operative during EB21-25 for shifting tb content of the bit string forming register one bit ~osition in the direction of the mo~t significant bit thereof for each of the last-mentioned counter means states.
Additionally included i8 means including the ~SB flip flop and its set logic and the control counter 113 which i9 operative during EB25 in resPonse to the last-mentioned completion indication at Co for inserting a binary bit signal of predetermined value ~e.g., 1) at the least signiicant nd of the content of the bit storing register EO.
By this me~ans, occuxrence i8 entered in the hybrid form word 2S output. The means or outputting additionally comprises ¦ mean~ including the P9 logic and the control countar 113 operative during EB17 for selectively outputtin$ th content of the bit stxing word fonming register by forming a signal at the P9 output, indicating that the word-in EOP is now 3a ready for output.

:~ `'''':':

~127767 1 ~n ad~ition~l ~re~rred embod~men~ o~ ~he encoder, accordin~ ~o the invention, is a bit strin~ forlnin~ mean~
whlch has means ~or enterin~ a ~irst occurrence ln a new bit string ~ord under forma~ion. Included in the last-mentioned means is means ~R) for storin~ a signal representin&
the number of binary bits remaining to be filled in the bit string word ~orming register EOP. ~lso included is combining means including the ALU, EDSl, EDS2 and the control counter 113 operative during EBll for forming a signal representing the dif~erence between the values of the remainin~ number of b~Erybit to be filled signal and the previous and current difference signal. Additionally included is means including the ALU, EDSl, EDS2 and gates 108 a~ 110, and the control counter 113 operative during EBll for comparing the values of the - 15 previous and current difference signal and the remaining binary bits to be filled signal for indicating that the value of the first signal is ~ (OE) than or ~ ~L) than the latter signal. Additionally included is means including ET, EDS7 and the control counter 113 operative during EB12 in response to the ~ thsn indication at L for retaining the diference signal in ET from the combining means as the number of bits needed in the next bit string word to enter a current absolute word.
Means including the CTR load and control logic and EDS2 is operative during EBll, 22-24 in response to the than indication at GE or enabling the counter means to `
count through a sequence of 8tate8 corresponding in number to the retained number of bits needed in the next bit ~trin~
word signal contained in ET. It should be noted that the 3 foregoing operation occurs when, during EBll, the retained ~ 7767 1 numl~er o~ bits need~(l in ~he ne~t ~lt strin~ word contained in E~ is ~ than the previous and current di~crence sl~nal contained in ET. ~lso inclu~ed i9 the EOP shift control 1ogic, the control counter 113 for shiftin~ the content o the bit string orming re~ister EOP one bit position in the direction o~ tk most sign~icant bit contained therein for each of the last mentioned counter means states.
t~eans including ~B and its set logic and the control counter 113 are operative during EB25 responsive to the completion signal at Co for inserting bit signal of predetermined value (e.g., 1) at the least significant end of the content of the bit string register EOP.
A further preferred embodiment of the encoder has a bit string forming means which includes means for filling out the bits of a bit string word being formed when no further occurrences can be entered therein. Included therein is means ER for storing a signal representing the number of binary bits remaining to be filled in the bit string word being formed. Combining means including ALU, EDSl, EDS2 and the control counter 113 i5 operative during EBIl for forming a signal representing the differences between the value o the remaining number of binary bit~
to be filled signal, contained in ER, and the previous and current difference signal, contained in ET. Additionally, there i9 means including ALU, EDSl, EDS2, gates 108 and 110 and the control counter 113 operative during EBll for comparing the value of the previous and current difference signal and the remaining binary bits to be fitled signal ; for indicating that the first is ~ than ~r ~ than the ~ ~3 la~ter ., ~ ~ ' " ~

-~Z~67 Means including the CTR load and control logic EDS ~nd EDS2 is operative during EB12-14 in response to the < than indication for enabling the counter means CTR to count through a sequence of states corresponding in number to that indicated by the value of the stored remaining binary bits to be filled signal contained in ER. Also included is means including the EOP shift control logic, the control counter 113 operative during EB13-14 for shifting the content of the bit string forming register EOP one bit position in the direction of the most significant bit thereof for each of the last mentioned counter means states.
According to a preferred embodiment of the encoder, clipping means is provided. Included therein is means including ETL and EBL for storing an upper limit value and a lower limit value. Means including ALU, EDSl, EDS2 and gates 108 and 110 are operative during EB2-4 for comparing a current absolute word with the upper and lower limit values and for indicating if it is out of the bounds defined by the limit values.
According to a further preferred embodiment of the encoder, an interval adjusting means is provided along with the clipping means. Included is means EIR for storing an interval value. Means including the ALU, EDSl, EDS2, EDS5, gates 108 and 110, and control counter 113 is operative during EB5 in response to the indication that the current absolute word is out of bounds for incrementally changing the stored upper and lower limit values in EBL and ETL
by the stored interval value in EIR. In the specific example shown, the incremental changing is a decrementing action.
Also included is means for enabling the comparing means to ~27767 repeat the comparing, uaing the incrementally changed upper and lower limit values and current absolute word.

III. DECODE I MODULE
S A, General Description The DECODE I and II MODULES are internally similar.
The difference lies mainly in the input and output signals.
This section is devoted to the DECODE I MODULE. The next section will discuss the differences in the DECODE II MODULE.
The purpose of the DECODE I MODULE is to convert to absolute word form a series of received occurrences in a hy~rid word. The occurrences are of decreasing value and are coded in hybrid form. Thus, the DECODE I MODULE con~erts information in the opposite direction from that of the ENCODE MODULE. The hybrid coded form comprises a series of binary code words, including at least one absolute coded -word followed by one or more bit string words and/or absolute words. Each absolute word represents an occurrence directly in coded form. Each bit string word represents an occurrence by the number of bits of displacement of a bit of a predetermined value from either an absolute word or another one of such bits bf predetermined ~alue in th~ series of hybrid words.
Additionally , each hybrid word has a flag indicating whether it is an absolute or bit string type of ~ord.
~he DECODE I MODULE operates in response to a call b~
a calling module. The possible calling modules for the DECODE
I MODULE are: PIPE, SEED, REVOLVE, ~RIGHTNE5S~ OUTPU~ MODULE5 and the DPM INTERFACE MODULE. In general terms, the DECODE I
MODULE decodes a hybrid word by reading it from the MEMORY MODULE
and if the flag bit indicates the word is an absolute word, ;,'.
- 111 - .

,, .

~' () ~ z7~67 1 the DECODF. I MO~UL~ outputs the word, passîng it directly to the calling module. The DECODE I MODULE saves the absolute word which has been outputted and then reads another hybrid word from the MEMORY MODULE. If the flag bit indicates that the new word is a bit string word, then the bit string word is stored in a shift register and shifted until a "1"
bit ~bit of predetermined value) is shifted out of the register. -With every shift, the previous absolute word value is counted down and each time a "1" bit is shifted out of the N shift register, the state of the counter is outputted as the absolute word.
. . ,:' .
B. Components The DECODE I MODULE includes counters MARl, MLNl, DOl, and BCTRl. Counter MARl is a 256 state counter of type SN74161 in the above TTL book. Counter MLNl is formed of an SN74191 type counter disclosed at page 417 of the above TTL
book and counts up responsive to each true signal applied at the Ct input. The MLNl counter i~ also set to a state corre~ponding to the input signals applied at its upper ~ide responsive to a true signal at the ~ or load input. Internal gating (not shown) forms a true signal at Mo *hen the MLNl counter i5 at state 0. Counter BCTR is an 8 state counter.
Counter DOl is an 8 bit 128 state counter. Both counters BCTR and DOl are formed of an SN74191 type cou,nter disclosed at page 427 of the above TTL book. These counters operate as follows: a true signal at the CLR input resets the counters to state 0, a true signal at the ~ input causes the counters to be set to a stato represented by the information input 30 .
'~

, -112-i~Z7767 1 signals appli~d ~t ~ts upper input. Each true slgnal at the Ct input causes the counter to count up one state. Counter BCTR has logic (not shown) ~or ~ormin~ a true outpu~ si~nal at ~ and Bo when the counter is at state 0 and not at state 0, respectively, ~ lso included in the DE00DE I M0DULE is an INRl register.
Contained therein is a shift register 20?. The shift register 202 is a 7 binary bit storage register for~ed ofthe type SN74199 disclosed at page 456 o~ the above T~L boo~, -The DECODE I MODULE also includes flip flops Pl through P5, forming a control counter 213, and flip flops DlFST, EOFl, DlSW, DlFND, MSBl, SlFF and D OE . Each of these flip flops is formed of type SN7474 disclosed herein in section I.F, Conventions Used in the Figures.
One-shot multi-vibrator~ DlG0, Dl~ND are also provided. -Each o~ these one-shot multi-vibrators i9 characterized whereby a true signal applied at its input causes the indicated output to receive a true signal for a time period equal in length to the time period between the beginning o~one clock pulse and the beginning of the next clock pulse at CLK.
The DECODE I ~DULE includes a source o~ equally spaced recurring clock pulses 240.
m e DECODE I ~DULE also includes the necessary logic to control the various regis~ers, flip flops and counters 2 as indicated by logical equations using th notation indicated hereinabove with respect to the ENC0DE ~DDUL$, In addition, specific AND gates 216, 218, 220, 222 are shown and OR gate~
224, 226, 228, 230, 234 and 235 are shown. The AND gates 218, 220, and 222 are actually indicated,schematically and 3 comprise eight individual ~ND gates (not shown) ~or gating ;-:, -113- ;
. ..

~;Z77~;7 1 eigll~ bi~s o inorm~10n tll~o~zh ~o ~he correspondin~
ou~put9 from ~he indicated source o~ in~orm~tion 210ng the heavy line inputs. The second input to each of tlle ei~ht AND ~ates wi~lin AND ~a~es 2J8, 220 and 222 i9 connected to the indicated con~rol logic indicated by lo~ical equations.
The output of the AND gates within each of the AND gates 2l8, 220 and 222 are OR'd togetIler by the 0~ gate 226 and provided as an eight binary bit information input to the MLNl counter.
Ths res~ of the AND and OR gates are also conventional gates well known in the computer art and need no urther explanation other than that provided in the following detailed description.
The output of AND gate 216 is indicated by the symbol CL~ corresponding to clock. The output of an inverter 232 i~ indicated by the symbol ~R corresponding to the logical inverse of the clock signal CLK simila~ to the ENCO~E M~DULE.
The required input and output control llnes to the DECODE I MODULE are indicated along the right hand side of Fig. 9; also indicated along the right hand side of Fig. 9 are the in~orma~ion input and output circuits using the syste~ of notat~on described hereinabove.
Referring to the right hand side of the DECODE I M~DULE
figure, the information inputs to the DEOODE I MDDULE are 2S shown in h-avy lines and are LNl from IPRF, MLN3 from the ENCODE MODULE and ORT2 from the OUTPUT MODULE. The output from the DECODE I MODULE i~ from the Dol counter ~eavy line), the EOFl output of the EOFl flip flop, the I ~ DlM~ND output of the one-shot multi-vibrator Dl~ND, and .: :.
~ ` 30 I the output of a gate represented by the logical equation P2-DlSW.
. . ,'.

~Z7767 1 The inEormation ou~put ~rom ~he Dol counter i9 the absolute words that have been decoded ~roln hybrid ~orm. The si~na~
~t DlMEND indicates ~he completion oE each resultant absolute word in the DOl coun~er, ~hereby indicatin~ ~o the calling module that it can read the ~bsolute word from Dol.
A true signal at the EOEl output indica~es that the number of hybrid words, and hence the length o~ the memory area, indicated by the words stored in the ~LNl counter, have been converted and therefore the hybrid occurrence vector has been completely decoded.

C. Detailed Descri~tion Table 13 gives the symbols for the important counters, registers and ~lip flops in the DEOODE I ~DDULE o Figs. 9 and 10 and $ndicates the length thereo and the primary output of the DECODE I ~DULE. Table 11 shows the primary inputs. Fig. 11 i8 a flow chart indicating the sequence of operation of the DECODE I MODUIE using similar notation to that described hereinabove with respect to the ENCODE ~DULE.
Reference to the DECODE I 2~ULE flow diagram should be made in reading the following description to aid in a complete understanding of the present invention.
Similar to the ENCODE ~DULE, the OR gate 234 is responsive to an initial signal applied at MINIT by the 2S M~NI COMPUTER to apply a true signal to the resetting input of each o~ the flip 10ps Pl-P5, resettlng them to 0. Also, OR gate 235 responds to the MINIT signal or initially resetting the DCE ~lip 1op to 0.
The DECO~E I ~DULE, a8 mentioned above, is called 3 by any one o~ the following modules: PIPE, SEED, r~EVoLvE, ~ -:

-115- ~

~127767 1 ~r~GHrNE:SS, ourwr ar~l INIl~'l~CE:. The MINI COMPUTER, as later de~cribed thro~gll tlle DPM INT~r~FACE MODULE or one of ttle o~:her ~odules stores in~o one area of ~he ME~ORY MO~ULE a llybrf.d coded occurrence vec~or. This hybrid coded occurrence vector i5 to be conver~ed ~o absolute coded occurrence words usin~ the DECODE I MODULE (and/or DECODE II l~lODULE). A calling module initializes the DEOODE I MODULE by placing the number of words (length) of the hyb.id form occurrence vector to be converted into the MLNl counter and by setting the DlFST flip flop to a 1 state, indicating that the first call to the DECODE I M~DULE is occurring.
The length o~ the occurrence vector i5 provided to the DEOODE I MODULE rom different sources according to the calling ~odule a~ follows: PIPE ~ICDULE - LNl from IPRF;
SEED ~ODULE - LNl . from,IPRF; REVOLVE ~DULE - MIN3 counter ~rom ENCODE ~DDULE; BRI~ITNESS MDDULE - LNl from IPRF; : -OUTPUT ~IODULE - LNI from IPRF or ORT2 re~ister in OUTPVT
MoX~E; o~xæ MoDULE - INl from r~; rNn~EP~S M~X~E - LNl from r~F. ~', loadhg MLNl is as follows: a true signal applied by the ,.
OUTPUT ~DULE at 0Ma6 or OM17 causes AND ~ates 218 and 222 and OR gate 226 to couple the length value from LNl of IPRF ' and ORT2, re~pectively, to the in~ormation input o the MLNl counter. The CHANGE ~DULE load~ the MLNl counter and ',-the SEED'M~DULE calls the DECODE I ~DULE. To thi~ end, the CHAN OE MCDULE applies a true sienal at the C~14.output, causing the AND gate 218 and the OR'gate 226 to couple the ~:~ length value from LNl of IPRF to the lnformation input of ,, the ~ ~ 1 counter. The SE$D ~DVLE applies a true signal at the SM2 output which causes the AND gate 218 and OR ~ate 226 3 to couple the length o~ occurrence value rom LNl of IPRF to '-':' .
~ -116-, . .

~1;~767 tl~ information input of the MLNl counter. The REVOLVE
MODULE appli~s a true signal at RM14 to cause gate~ 220 and 226 to couple the length of occurrence value from counter MLN3 of the E~CODE MODULE to the information input of counter MLNl.
One of the REVOLVE, SEED, OUTPUT, PIPE, BRIGEITNESS, and DPM INTERFACE MODULES then sets the DlFST flip flop to a 1 state via OR gate 228 by applying a true signal, respectively, at the corresponding output Pll, RM2, SM4, B3, OM21, and DlI which, as indicated above, indicates that the first call of the DECODE
I MODULE is occurring.
Subsequently, the calling module triggers the DlGO
one-shot multi-vibrator, causing it to apply a control pulse at its DlGO output. DlGO is triggered by the gate 230 which receives its control pulse from one of outputs P13, SM6, RM4, B5, and DlGO. -A true signal at output DlGO sets the DCE flip flop to a 1 state, causing a true signal at the DCE output which, in turn, enables AND gate 216 to couple clock signals from the clock 240 to the CLK output. Similar to the ENCODE MODULE, the inverter 232 forms the logical inverse of the clock formed at CLK at its output at CLK.
Since all of the flip flops of the control counter 213 --are initially reset to zero, true signals are now formed at the outputs ~1, P2, ~, P~ and P5 and the clock pulse at CLK
causes flip flop Pl to be set to a 1 state and DlBl of the DECODE flow is entered.
I During DlBl, the state of the DlFST flip flop is checked, assuming that this is the first call on the DECODE I MODULE.
The DlFST flip flop is in a 1 state, causing a true signal at the DlFST output. Additionally, the Pl flip flop is in a ~ -, ~:, `' '.
. ,~
..

~ . , ".. ,! ., .

1 s~e. ~cco~tlin~,ly~ Dl~2 o~ e D~COD~ I ~IOD~ R ~0~1 is entered ~hare t:he true si~nal3 n~ Pl, DlFST ~nd ~C cause the DlSI~ 1ip ~lop ~o be reset to a 0 state. Tlle cloclc pulse at C~ in co~h~n~on wi~h the true signals a~ the Pl and DlFST outputs causes each of ~he DlEND, DlFST and EOFl fLip lops to be reset to an O state and cause the ~ARl and BCTRl counters to be reset ~o an O state. Additionally, the clocl; at CLK in coincidence witl the true si~nal at output Pl causes flip flop P2 to be set to a L state and flip flop Pl is reset to an O state.
The DlFST, EOFl, DlSW and DlEND 1ip flops have been reset at this time or the ~ollowing reasons. The DlFST
flip flop is reset at this time to indicate that the resetting operatbn during DlB2 has been completed. This is the only function of the DlFST flip flop. EOFl is reset at this time to indicate that the hybrid ~rds in tl~
occurrence vector have not been co~pletelg conver~ed.
The DlS~J flip ~lop is used to indicate within the DECODE I
MDDULE that a ME~RY ~IODULE read i~ necessary. The 0 state of the DSW flip flop indicates that a read from ME~ORY ~IODULE
i8 necessary to obtain a hybrid word. This ~ill subsequently take place during DlB5. ~ l state of the DlSW flip lop i8 used to indicate that a read is unnecessary and, as will be explained subsequentlg, DlB5 is skipped when DlSW is in a l state. The DlEND flip lop i9 an internal flip flop and, when set into a l state, indicates to the DECODE I MO~ULE
that after conversion o a hybrid coded occurrence vector the last abso1ute word has been ou~putted or passed to the calling module. To be e~:plained in more detail, when the DlEND ~lip f10p is set to a 1 state, any subsequent call on the DECODE I ~ ULE by the callin~, module will ~orce the DECO~E I

J.~27767 1 ~DU~E ~o orm an end oE ~ile indica~ion ~y se~tin~ ~hc EOFl ~lip flop to a 1 st~e.
Follot~inz DlB2~ DlB3 i9 entered, Durin~ DL~3, tlle P2 1ip Elop i5 in a 1 sta~e and the Dl~ lip ~lop i~
S checked. If durin~ DlB3 the DlEND flip flop i5 in a 1 state, whicL~, as discussed above, occurs when tle callin~ module provides the last word of a hybrid occurrence vector, DlBl9 of the DECODE I ~IODUL~ flow is entered. - ~ -The action of the clock suspension logic should now be noted. The true signals at P2, DlEMD and ~-K reset the D~l counter to O and cause the clock suspension logic 222 to for~ a true signal at the OR gate 235 causing it to reset the DCE flip flop to O and trig~er the one-shot D~;~MD.
Resetting of the D OE flip ~lop to an O state removes the true si~nal at output DCE and causes the A~D gate 216 to remove the cloclc signals at CLK, thereby causing the DECODE I ~DULE operation to EXIT and await the next call -~
on the DECODE I ~DULE. The one-sl~ot Dl~END then orms a true signal at output Dl~ND which causes 0~ gate 234 to reset flip flops Pl-P5 to 0. The subsequent operation caused by the DlEND flip flop being in a 1 state will be ~further described hereinafter.
The above action o the clock suspension logic 222 i9 important and should be kept in mind as a similar action is 2 enabled by th- clook suspension lo~ic when any one o the `~
other logic conditions indicated ~or the cloclc su~pension logic 222 beco~e3 true.
Assume that during DlB3 the last word of a hybrid ;~
occurrence vector has not been provided, and the DlEND 1ip 10p -. `
3 is in an 0 state, causin~ a true si~nal at the DlEWD output.
: ` . . .~

o ~
~ 767 1 Dl~ is entered ~ ere ~he stal.e o~ tlle DlS~ flip ~lop in clleclced. It ~Jill be rec~led tLlat the DlS~J ~lip ~lop in a 1 state lnclicates th~t ~lle ~ ORY ~DULE re~d operation is ~o be ~kipped, whereas i in an O state~ causes a ~rIO~Y
~ODULE read. Assume ~hat the DlS~l ~lip ~lop i~ in an O state.
DlB5 is entered where the me~nory read actually talces place An input to the DECODE I ~DULE i5 ~he SM10 output o~
the SEED ~ULE. To be e:~.plained in more detail, the SEED
~IODULE uses the DEOODE I ~DULE when computing the number o~ -lines to be skipped in an iso-entropicgram. However, the SEED ~DULE when computing the lines to be skipped, does not require the length value in counter ~nLNl to be decremented ~ccordingly, the SEED ~IODULE normally orms a true signal at output SM10 but removes the true signal when computing the nu~ber of lines to be skipped, thereby inhibiting counter from being decremented~
However, for the present description, as~ume that a true signal i3 formed at s~no. True signals are also formed at P2 and bls~. Therefore the ~DLNl counter receives a true ~ignal at i~s Ct input, causing ~ ~ 1 to be counted down one state reflecting the fact th~t one word of ~he hybrid occuxrence vector is being read from the ME~RY MODUIE. The logic P2-~51~-~ being true causes a true signal at the Ct input of ~P~l, causing ~ARl to be coun~ced up one ~tate, reflecting 2 the ac~ tha1: the next word o~ the hybrid occurrence vector i3 to be addressed in the ~ lO~Y ~DDU~E. The true signals at P2 and ~ cause a true~ si~nal to be formed at the D~ll output ~ -of the DECODE I ~DULE~ thereby ~ignalling the ID~20RY ~i~DULE, caus~n~ it to read out the content o~ the proper memory area 3 speci~ied by the SWITCU ~ TRIX at the memory location speciied in ~:he ~ r~l counter prior to its being counl:ed up.
: -120-~lZ7767 q~ control signal at P2 enablcs the 8 bit word read-out of thc M13MORY MODUIJ~ to be stored into the INRl register.
The tru~ signal at P2 causes the most significant bit (8 bit) o the word read from the memory to be stored in the MSBl 1ip flop. The true signal at P2 also goes to the S/L input circuit for the shift register 202 causing the remaining 7 bits of the word from the MEMORY MODULE to be loaded into the register 202 when the clock signal is applied from logic P2-DlSW-CLK. Accordingly, at the end of DlB5 of the DECODE
I MODULE flow a hybrid word has been read from the MEMORY
MODULE from the appropriate memory area and has been stored in the INRl register and the MLNl counter has been decreased by one so that the length of occurrence vector contained therein indicates the remaining words to be read from the MEMORY MODULE.
Assume now that the word stored in the INRl register is an absolute hybrid word. It will be recalled that the first word of every hybrid occurrence vector string will always be an absolute word. When the word stored in INRl is an absolute word, the flag bit, the most significant bit -~
of the hybrid word, is stored in the MSBl flip flop and causes the MSBl flip flop to be in a 1 state. With the MSBl flip flop in a 1 state, true signals are formed at the MSBl and P2 outputs. Accordingly, the P5 flip flop is set to a 1 state and DlB8 is entered.
A true signal is formed at the P5 output and the following pul e at CLK causes a true signal at the L input of the DOl counter, causing the 7 bits in the shift register 202 of the -INRl register to be loaded 1nto the DOl counter. The true signal at P5 in coincidence with the pulse at CLK enables the - . . .
; - 121 -,; ~ ' ', ~Z7767 c]ock suspension logic -222 to reset the DCE flip flop to an 0 state, thereby disabling the clock at CLK out of the gate 216 and resetting counter 213. An EXIT is taken to await the next call. The next call is initiated by a control signal, as described above at one of the inputs to OR gate 230.
If, during the true signal at P2 the word in the INRl register read from memory is a bit string word, the MSBl flip flop is in an 0 state and true signals are formed at the MSBl and DlSW outputs and the P3 flip flop is set to a l state, thereby causing DlBll of the DECODE I MODULE flow to be entered.
At the beginning of processing of each bit string word of a hybrid occurrence vector, the BCTRl counter is in an 0 state having been set there at DlB2. Therefore, during the first entry into DlBll of the DECODE I MODULE flow, the BCTRl counter is in an 0 state. Accordingly, a true signal is formed at the Bo output of the BCTRl counter so indicating.
The true signal at Bo in combination with the true signal at P3 causes the P4 flip flop to be set to a l state and DlB13 is entered.
During DlB13, the BCTRl counter is loaded with a signal representing the maximum number of bits in a hybrid word to be processed, To this end, true signals are now formed at the P4 and Bo outputs and the following pulse at CLIC causes the L input of the BCTRl counter to be energized and the value 7, represented by the setting of the switches 236, is loaded into the BCTRl counter, and DlB14 is entered.
-~ During DlB14 of the DECODE I MODULE flow a true signal is formed at the P4 output. Accordingly, the shift register 202 is repeatedly shifted one bit to the right until a one : .

~ 1127767 ~it ln~licatincl an occurrence is shited out oE r~gister 20~
into the slrl~F ~lip Elop. Each bit shifted out of the least significant end of the register 202 is stored in the sign flip flop SlFF. During DlB15 of the flow a true signal is formed at the P4 output and the pulse at CLK causes the Ct input of the BCTRl counter to be energized and count the counter down one state. The same signals cause the CT input of the D01 counter to be energized and the counter D01 to count down one state. For each right hit shift of the register 202, the num~er of hits left to be processed in the INRl register identified by the state of the BCTRl counter is counted down one and the absolute word value indicated by the D01 counter is counted down one state. This operation continues until a 1 bit is shifted out of the shift register 2Q2 into the sign flip flop SlFF thereby causing a true signal at -the SlFF output. The state of the DQl counter at this time is an absolute word representing the actual value of the occurrence represented by the 1 bit shifted out of register 202 into the SlFF flip flop and accordingly, the state of the 20 D01 counter is to be outputted to the calling module.
To this end, signals are formed at the P4 and SlFF
outputs and the following signal at CLK causes the DCE
flip flop to be reset to an 0 state and fires the DlMEND
one-shot causing a true signal at the DlMEND output signalling 25 the calling module that an absolute word is completed and contained in the Dal counter. The Dl~END signal resets the ¦ control counter 213 to a. The ormation of the signal at DlMEND indicates completion of an absolute word and is referred to herein as outputting the absolu`te word.
, . .
Several important special conditions should be noted.
. '`

. I ~ "'"''.

`~ ~lZ7767 Ii., durin~ the DlB15 and the 1 stat~ of the P4 flip flop, the content of shift register 2Q2 is not 0, it means that there is a remaining 1 bit (representing an occurrence) yet to be converted to absolute form in a bit string word. Accordingly, a true signal is formed by register 202 at ~ causing the DlSW flip flop to be set to a 1 state at the following pulse at CLK. Th.e 1 state of the DlSW flip flop is used during the following entry into DlB4 of the flow to bypass the reading of another word from the MEMORY MODULE.
The reason for this action is that with the DlSW flip flop in a 1 state, a new hybrid word will not be read from .
the MEMORY MODULE following D1~14, as there is still at least a portion of a bit string word remaining in the shift register 202 to be converted to absolute form. -~
Referring to DlB17 of the flow, whenever the bit string word contained in register 2Q2 of the INRl register goes to zero by virtue of the fact that all of the 1 bit (or occurrence~ of the bit string word has been shifted out ~ ~
thereof, a control signal is formed at the I0 output of :
the shift register 202. When this occurs another hybrid word must be read from the MEMORY MODULE during DlB5. A true signal is formed at the outputs P4 and I0 causing the DlSW
flip flop to be reset to a 1 state at the next pulse at CLK.
The 0 state of the DlSW flip flop, during the following entry into D1~4, causes DlB5 of the flow to be next entered where .
a new hy~rid word is read from MEMORY MODULE into the DECODE I
MODULE for conversion. When the last word of a hybrid :. :
occurrence vector has been read from the MEMORY MODULE, the length of occurrence vector value contained in the MLNl counter will have been counted down to 0, and a control ..

.--: - 124 - -.

. .

' `'` l~Z7~7 si~nal is formed at the Mo output of the MLN1 counter.
A true signal at Mo and a true signal at the P5, the P4 and IO outputs causes the DlEND flip flop to be set to a 1 state at the next pulse at CLK thereby indicating that the last absolute word has been outputted to the calling module.
With the DlEND flip flop in a 1 state, the following call on the DECODE I MODULE flow will cause the EOFl flip flop to be set to a 1 state responsive to true signals at the P2 and -DlEND outputs at the occurrence of the pulse at CLK.

10One further special situation with respect to the DECODE I
MODULE should be noted. If, during the 1 state of the P3 flip flop, the BCTRl counter is not in an 0 state, then DlB12 and DlBll of the flow are utilized to insure that the proper alignment is made from one bit string word to another. This is necessary when the last 1 bit of a bit string word has been converted to absolute word form and outputted, and leading 0 bits remain in the bit string word under conversion in the shift register 202. These leading 0 bits must be taken into account in forming the next absolute -~

work for output.
Referring to DlB11 and DlB12 of the flow and the `
corresponding action, a true signal at the P3 output in coincidence with a true signal at the Bo output causes the BCTRl counter, as well as the DOl counter, to be counted down one state responsive to each pulse at CLX. As a result, the absolute word being formed in DOl is adjusted downward by the number of leading 0's remaining in shift register 202 which are indicated by the state of BCTRl. Finally, when the BCTRl counter reaches an 0 state, a control signal is formed at the Bo output and the true signal is removed at the Bo output terminating the counting of the BCTRl and DOl counters ~r;.`' ' ~Z7767 and caus.in~ DlB13 of the :Elow to be entered as explained above, D. Example of Operation Consider now an example of the operation of the DECODE I
MODULE. Assume that four words, making up a hybrid occurrence vector, are contained in the memory area 1 of the MEMORY MODULE
and are to be converted from hybrid to absolute word form.

EXAMPLE
Assume the following is in the memory ~rea l of the MEMORY MODULE: -. 1 1 1 1 1 1 0 1 (125) 0 0 1 0 0 0 1 0 (123, 119) 0 0 0 0 1 0 1 0 (116, 114) :
1 1 1 0 0 1 0 0 (100) The physical length in words is 4.
Therefore it is the calling program's responsibility to load MLNl~- 4 and set the initialize fl~p flop DlFST to 1.

First call MLNl = 4 DlFST
sequence of control DlBl - DlB9 DlBl DlFST = 1 . control to DlB2 DlB2 DlFST = DIEND = EOFl = DlSW = 0 reset these flip ~ flops;
MARl = O, BCTRl = O initialize these registers DlB3 DlEND = 0 - control to DlB4 DlB4 DlSW = 0,', control to DlB5 .

",..-, I
. I l~Z7767 1 ¦ Dlns rea~ m~mory i.ll~o ~NRl do ~h~ rea~l;
¦ INRl ~ 5) ~he r~sult;
l MAUl (1) 3 ~IARl (0) ~ 1 memory acldre3s to next ¦ posi~ion;
5 ¦ MLNl (3) ~ MLNl(~ 1 decrease the number o~ words ¦ DlB6 MLNl (3) 7~ 0 . control to DlB7;
¦ DlB7 MSB(INRl) - 1:. control to DIB8 AOI form : :

I DlB9 Dol (125) = INRl (125) input becomes the output;
10¦ DlSW ~ O assure a read on the ¦ BCTRl ~ O next call and set BCTRl to zero;
EXIT
¦ output Dol - 125 EOFl - O .
151 -: -I second c811 initial conditions: DLFST ~ O
l ... v- ~_~ , . -i8 not clocked sequence of control DlBl, DlB3-DlB7, DlB U, DlB13 l DlB16, DlB14 - DlB17 201 DlBl DlFST ~ 0 .-. control to DlB3 DlB3 DlEND - O . control to DlB4 ¦~`
I DlB4 DlSW - O . control to DlBS .`
¦ DlB5 read memory do ~he read to INRl; . -~ ~:
I INRl ~ 00100010 :~
25 ¦ MARl(2) ~M~R~ 1 increase address pointer; 1:
l MLN1~2) ~MLN~3) - 1 decreasq length re8ister;

30 I .
` I . ','.

~- . ': .
' :' ~7767 1 Dl~G MLNl ~ O ,'. con~rol ~o D1~7 DlB7 MSB~INR~) ~ O,.con~rol to Dlnll DlBll BCTr~l - O ., control to DLB13 DlB13 BCTl~l - 7 this count~r monitors how ~uch of the input register remain:; to be processed;
DlB14 INRl 00010001 SlFF ~ O -DlB15 BCTR1(6) - BCTRt7) - 1 reduce the number of bits Dol(124) - Dol(125) - 1 to be processed & reduce DlSW ~ 1 the previous output - set DlSW to indicate no resd . i8 necessary on the next call;
DlB16 SlFF - O :. control to DlB14 DlB14 INRl - 00001000 shift INRl;
::~ SlFF - 1 SlFF - 1 because of the shift output from INRl . , . ' '''-, ' DlB15 BCTR1(5) - BCTR1(6) - 1 decrement bits remaining;
Dol~(123) - Dol(124) - 1 decrement previous output; ~-~
DlB16 SlFF - 1 .'. control to DlB17 DlB17 INRl ~ 0 ..... HALT :
: Output Ddl - 123: EO~l ~ 0 : 25 EXIT

30 ~ : :
.
~ -128-., : '."

~lZ7767 (~

1 ~I~Lrd cnl.l ~usl: as~.~r~ l)lG() sequ~ncc o~ control DlBl, 1)133-l)lB4, DlB14-D1~16, DlB14-DlB16, DlB14-DlB16, DlB14-DlBl~

same as before DlB3 DlB4 DlSI~J - 1 ,, control to DlBl~
DlB14 INRl c 00000100 sh~ ft INRl right;
SlFF ~ O SlFF ~ O since "shift out"
from TNRl a O

10 DlB15 ~CTR1~4) - BCTR1(5) - 1 -Dol(122) - Dol(123) - 1 DlSW - 1 DlB16 SLFF ~ 0 ,-, control to DlB14 ~.
DlB14 INRl ~ 00000010 --SlFF ~ 0 . -DlB15 BCTRl(3) - BCTRl(4) Dol(121) ~ Dol(122) ~
DlB16 SlFF - 0 ,-, control to DlB14 :
DlB14 INRl ~ 00000001 DlB15 BCTR1(2) ~ BCTR1(3) - 1 . .
. Dol(120~ - Dol(121) - 1 : DlB16 ~ FF o O control to DlB14 DlB14 INRl ~ 00000000 SlFF - 1 25 DlB15 BCTRl(l? ~ BCTR1(2) - 1 .
: Dol(ll9) - Dol(120) - 1 '.-.
. ' ...
~: 30 ~ ~ "

: : ' 1 DlL~16 slFr~control to DlB:L7 DlB17 INRl -- 0,', control to DlB18 Dlal8 DlSW = 0 assure a read on the next call;
EXIT
output Dol = 119 EOFl = 0 Fourth call DlGO to 1 sequence of control DlBl, DlB3-DlB7, DlBll-DlB12, DlBll, :
DlB13-DlB16, DlB14-DlB17 DlBl I same as above DlB3 DlB4 DlSW = a.: control to DlB5 DlB5 read memory read into INRl;
INRl = aooololo MARl(31 ~- MARlc2l + 1 bump the memory add~s;
MNLl~ MLN1~21 - 1 decrement the length DlB6 MLNl ~ 0 ,: control to DlB7 DlB7 MSB(:INR1~ = 0 :,control to DlBll 2Q DlBll BCTRl(ll ~ 0 :.control to DlB12 DlB12 BCTR1 (a~ = BCTRl(l) - 1 the value in BCTRl is a Dol(118) = Dol(ll9~ - 1 measure of the unshift~d bits from the previous read, Dol must be decremented by this unit;
DlBll BCTRl(a) ~ 0 .control to DlB13 ~ .

C` llZ7~7 ~
. .

1 ~lB13 BCTRl ~ 7 bit~ ~o be processed ~n this word;
DlB14 IMRl = 00000101 Sl~F = O
DlB15 BCTR(6) - BCTR(7) - 1 Dol(117) 3 Dol(118) - 1 DlSW z 1 no read necessary next t~me;
DlB16 SlFF ~ 0 .-. control to DlB14 -:
DlB14 INRl a 00000010 ~ ~;
SlFF ~
DlB15 BCTR1(5) - BCTR1(6) - 1 ;. -Dol(116) - Dol(lli) DlB16 SLFF - 1 ,'. control to DlB17 -~
DlB17 INRl f O
15 EXIT - . .--output Dol - 116 EOFl - O

F~fth call ~et DlGO. :
sequence of control DlBl, DlB3-DlB4, D1~14-DlB16, DlBI4-DlB18 DlBl ) ~ same a8 above .
DlB3 ~ -: DlB4 DlSW - 1 ,control to DlB14 . DlB14 INRl - 000000019hift INRl ri~bt;
2S SlFF a O
. ,',.
. ~ ;.`'.

, ~ ~ . .
~`: 3 ~, ~ ` -131- ~
.~. "; .
'~
~ ~ !.~

o ( ) ~iZ7767 1 ~1l315 BCTRl(4) ~ ~C~1(5) - 1 Dol(115) - ~ol(116) ~ 1 DlS~J = 1 DlB16 SlFF G O .', con~rol to DlB14 DlB14 I~ 00000000 SlFF = 1 DlB15 BCTRl(3) - BCTR1(4) - 1 Dol(114) ~ Dol(115) - 1 DlB16 SlFF - 1 ,'. .control to DlB17 10 DlB17 INRl - O ,. control to DlB18 -DlB18 DlS~ ~ O read next time;
EXIT
output Dol 8 114 EOFl ~ O
. "' 15 Sixth call set DlGO -., sequence of control DlBl, DlB3-DlB6, DlB10, DlB7-DlB9 DlBl ) ~ same as before DlB3 ) DlB4 DlSW - O , control to DlBL5 20 DlB15 Memory read INRl - 11100100 MARl(4~ - MARl(3) + 1 ~Nl(O) ' ~LNl(O) - 1 ,.
. DlB16 MlNl - O ,'., control to DlB10 Z5 DlB10 DlEND - 1 assures arl EOFl on ¦ next call;

~ ;: . ' ~'' ', 3 ' :

,:- , .:

llZ7767 1 DlB7 MSB(INRl) ~ 1 :.con~rol to DlB8 re~et ~he ~ign b~;
Dl9 BCTRl ~ O
DlS~ - O
Dol - 100 (01100100) EXIT
output Dol = 100 EOFl = O
. ,'. :', Seventh call set DlGO ;-:-seqùence of control DlBl, DlB3, DlBl9 DlBl same as above DlB3 DlEND ~ 1 .'. control to DlBl9 . DlB19 EOFl ~ 1 -;
Dol ~ O
EXIT
output Dol - O EOFl ~ 1 .
'' .-. .:
note the otput retrieved was 125, 123, 119, 116, 114, 100 -the same as was encoded before 20~
. ~', ~: ~ ... "", ~ ` . ' .,.
~: -133-.~-,. , ~ .

~27~7 1 In summary, it will be seen that what has been dis-closed is a decoder or converting hybrld coded signals to absolute coded word signals. The hybrid signals represent a series of occurrence values of decreasing value.
The hybrid signals have a series of received binary coded word si~nals including at least one absolute coded word and a bit string word. The bit string word represents an occurrence by the number of bits of displacement of a bit of predetermined value ~i.e., 1) from an absolute word 0 in the series of hybrid words. A hybrLd word also includes a flag signal indicating the type of word.
The decoder includes an absolute word outputting means including the DlMEND one-shot multi-vibrator and its logic and the MSBl flip flop and a contrdl counter 213 operative during DlB9 of the flow in response to an absolute word flag signal of a received hybrid word signal for outpùtting the received word signal. In other words, the outputting means is responsive to the absolute word flag signal for directly outputting the corresponding hybrid word since it is already in absolute word form.
The decoder also includes absolute word signal forming and outputting means. The means includes the INRl register and its shift control logic, the SlFF flip flop, the D01 and BCTRl counters and their load and count control logic and -the control counter 213 which are opèrative during DlB14, 16, 7-9 ln response to an absolute word signal and`each bit of ; predetermined va}ue in a subsequently received bit string word ;~ for forming an absolute word signal indicative of the actual value of the bit of predetermined value. Also included is means such as the DlMEND one-shot multi-vibrator and its co~trol logic :~
1~ -134-~ ' . ' '':

11'~7767 operativ~ during D1~16 for outputting e~ch of the absolute word signals formed thereby. The true signal at DlMEND
outputs the absolute word signal represented by the state of the counter DOl.
In a preferred embodiment, the means for forming and outputting the absolute word signal includes the shift register 202 in register INRl for storing a received bit string word signal. Also included is means including the I~Rl register and its shift control logic and the control counter 213 operative during DlB14 for repeatedly enabling the shifting of the content of the shift register 202, 1 bit position in the direction of the least significant bit of the bit string word. Also included is means including the SlFF flip flop and the control counter 213 operative during DlB16 for providing an indication when a bit of predetermined value arrives at the output of the shift register 202. Also included is the counter DOl and means including the DOl load control logic and the control counter 213 operative during DlB7-9 responsive to an absolute word flag signal of a hybrid word for setting the counter DOl to a state, relative to the reference (0) state thereof, which corresponds to the value of the absolute word signal. -Means including the DOl count control logic and the control counter 213 is operative during DlB15 for enabling the counter to count one 9tate towards its reference state for each shift of the shift register 202. Means including the DlMEND one-shot multi-vibrator and its control logic and the control counter 213 is operative d~ring DlB16 in response to the bit of predetermined value in the SlFF flip flop for outputting the state of the counter by forming a true signal at DlMEND.

~ 11;:7767 1 In fl Eurtllcr preferred em~odi.ment tllcre li~i meansi or adjusting ~lle coun~er D01 ~or bits wllich are not o~ the predetermined value (e,g , 0) wllicl~ remain in the shit re~ister 202 after decoding the last bit of predeterm~ned value in a hybrid word Includ~d is an additional counter means such as the BCTRl. ~Ieans including the switches 236 indicate the maY.imum number of bits in an absolute word for output. Means including the BCT~l load control lo~ic and control counter 213 is operative during DlB11-13 or selectively setting the additional counter means BCTRl to a stste relative to a reference state (e.g " 0), ~hich corresponds to the indication of the maximum number of bits in an abisolute word signal. Means including the BCTRl count control logic and control coun~er 213 are operative ; :
during DlBL5 for enablin~ the additional counter means BCTRl to count one state, relative to the set state thereof towards the p reference ~tate for each shift of the shift register mean~ 202. The ~ output of the BCTRl counter : indicates the occurrence of the reference state of BCTRl.
Means includin~ tbe:count control logic of BCTRl and control counter 213 i3 operative during DlB12 ~n response to the flag -signal of a bit string word 9ignal stored in ~Bl and the indication at ~ indicating the lack of a reference state of BCTRl or further enabling the countin~ o~ the counter D01 and BCTRl, one count for each shift o the shift register meansi 202. By thi6i arrangement the hi~h order 0 bits ~hich are not o the predetenmined value which are let in : the shift register 202, ater all bits o~ predetermined value . are shi~ted out, are re1ected into the absolute word si~nal 3 under ~ormation in shi~t re~ister 202, '.':

~ (-`' ~) ' l~Z~67 1 IV. D~COD~ II MODULE
Eigs. 12-14 form a schematic and bloclc din~lram o~ tlle DEOOD~ Il MODUI.E. The DECODE II IIODULE i5 ba:~ic~lly co~s~ucted tlle same as the DECODE I MODULE except as S described beLow. Two clecode moclules, DECODE I MODULE and DECODE II MODULE, are needed in the system in order to decode the occurrences o~ an occurrence vec~or from hybrid to absolu~e coded words and provide the resultant absolute coded words in two stL^eams at diferent rates. DECODE I
10 MDDULE and DECODE II MODULE provide their respective ~ .
streams of absolute coded words, one word (or occurrence) at a time when called.
The DECODE II ~ULE is virtually identic~l to the DECODE I MODULE as mentioned above. In keeping with the virtual identical structure, the same symbols are used to denote the various parts o~ the DECODE II ~DULE as are used ~-for the DECoDE I ~DULE. However, in some ins~ances a 1 in a symbol ~or the DECODE I ~lODULE is changed to a 2 in the DEOODE II ~DDULE to he~p simplify the description or distinguish bet~een lines going between ~odules. The components t~hose identity and symbol~ have been changed in the DECODE II MDDULE by changing a 1 to a 2 are identiied below.
. ,.

1 DE~ODE I DECODE II
BCTRl BCTR2 DOl ~ D02 INRl INR2 MARl MAR2 MLNl MLN2 DlFST D2FST
EOFl EOF2 ~ -DlGO D2GO
0 DlMEND D2MEND
A data selector DDSl similar to that described above replaces the,gates 218-226 of the DEC~DE I MODULE for gating the occurrence vector length into counter MLN2. However, a '~ ' gating, circuit similar to the DECODE I MODULE could be used. - ;
The occurrence vector length is coupled from the information ~ource indicated along the top of DDSl to the MLN2 counter responsive to true signals at the control lines indicated along the sides of the DDSl. Additionally, the gating ~,~
conditions indicated for the load or L input of MLN2 ~-20 differs from that of the DECODE I MODULE and should be noted. , ' , The input control lines connected to gates 224', 228', 230' and 234', and the cloc~ suspension logic 222', differ in minor respects from that of gates 224, 228, 230 and 234 and ''''' su~pension logic 222 of the DECODE I MODULE and the ,, primes are a~fixed to the~e ~ymbol9 to ~o indicate.
: ~ ' ' ~ 3 , ~, ~ ~ . .. '-' ~ :` -138-~:
. .

V. VELTl~ MODUL,E
A. General Description -The DELTA MODULE breaks the number of lines to be revolved (in an iso-entropicgram) from a calling module and breaks the number into smaller increments. The implementation now to be described breaks the number of lines to be revolved into its largest possible component powers of 2 in decreasing value order which, in turn, corresponds to -the number of lines to be revolved. This feature is described in the General Description with reference to Table 4-C and is of importance because the lines in the -iso-entropicgram can be derived with a minimum of XOR
operations. Also, by revolving from one line to another in an iso-entropicgram where the second line is away from the first by a number of lines equal to a component power of 2, the revolve to the second line is accomplished by a single shift and XOR operation. -The DELTA MODULE, in operation, receives a binary coded -number in the 1, 2, 4,8 number code (from the calling module) representing the total number of lines to be revolved, and breaks the number into its largest possible component powers of 2. The largest component power of 2 is formed first, followed by the other largest powers of 2 in decreasing orderof magnitude. Although the invention is not limited thereto, the DELTA MODULE about to be described operates on 8 bit words.
The DELTA MODULE converts a number by storing it into a first register and then shifting the number towards the most significant bit position, repeatedly, one bit position at a time. A second register with the same number of bits as the first register has a "1" bit that is shifted towards the ~ 13~ -- -. . .

lZ7767 least signi.Eica~t bit position, one bit position each time the first register is shifted. Since the two registers are shlfted in opposite directions by the same amount whenever a lll" bit arrives at the output of the first register, the "1" bit in the second register indicates direct~y the corresponding power of 2 of the 1 bit shifted out of the first register. .-Table 14 is a DELTA MODULE example illustrating how the above operation takes place. The binary coded number to be converted represents the decimal number 13 and is stored in th.e first register in binary coded form, whereas the second register is. initially set to 0.
Eight s~ifts are depicted, one for each bit of the number. ~:
to be converted. On th.e first sh.ift, the first register is shifted 1 bit towards the most significant bit, whereas. .
the second regIster has a 1 bit stored in thè most significant .
end wh.ere it represents the binary coded number 128. With .
each.subsequent shit of the first register towards the most significant bit, th.e second register is shifted towards 2a th.e least significant bit. Following shift 5, a 1 bit for the first time is shifted out of the first register.
This indicates that the content of the second register, : which now represents 8, can ~e read as it now contains the largest component power of 2. Also, 1 bits are shifted out following shifts 6 and 8 and th.e second register at these times represents the numbers 4 and 1, respectively. Adding 8, 4 and 1 results in 13 which is the ~: ~ binary coded number originally stored in the first register. .-: .
: ., . - , ~:
.... .... . , ':
8. Components The DELTA MODULE, Fig. lS, contains inputs and output control - o ~r) . 1127767 1 lines indicatccl ~lon~ e riEr,ht h~nd n~de, Tlle sy3te~n o~
nota~ion described ~bove in section I.F, Conven~ion~ Used in Fi~ures, is used. Add~tion~lly, tl~ere are inormation input and output lines These input and output lincs carry multiple bits of in~orn~tion and are indicated by heavy lines.
~ 70 re~isters DELI and DEL0 are provided. Register DELI
inciudes an ~ flip flop shift re~ister 302 and the re~ister DEL0 includes an 8 flip flop shi~t register 304. Both o the registers DELI and DELO include a most s~gni~icant bit flip flop, DELI containing M~BDELI and DEL0 conta~ning MSBDELO. M~BDELI has its input for ~etting it to a 1 state connected to the output SOUT of shift re~ister 302. The output SOUT of regi3ter 302 is the unpr~med output from the most significant flip flop in register 302.
The ~DEL0 flip flop in DEL0 has its ~BDE~0 (or unprimed) output connected to the "IM" input of register 304 which is the set to 1 input of the most signi~icant 1ip flop in register 304. Logic (not ghown) in register 302 applies true signals at DIo and ~ when the register is 0 and not 0, ~0 respectively. The operating charactexistics of ~hift registers 302 and 304 are the same as shift register 114 of the ENCODE MODULE, Register 304 also has a CLR input which is responsive to a true signal at CLR to reset register 304 to 0. Shift re~isters 302 and 304 are o~
type SN74L98 disclosed at page 456 of the above TTL book, A control counter 313 has two 1ip ~lops Pl and P2.
~dditionally, control fllp ~lops DELFST, DELE~D and ~LLCE
are provided. The DELFST flip flop, when in a 1 state, indicates that the ~irst call is occuxring to the DELT~ ~DULE, ~--3a The DELEND 1ip ~lop in a 1 state indicates tl~t the word stored in DELI has been completely converted ~nto its o ~
l~Z77~;7 1 component ~owers of 2. T~lus, tlle ~. sl:~te o~ l~ELE:MD is an indica~ion that the DELTA MODULE llas complcted its operation, Tlle ~lip ~lop DELC:E controls tlle for;nAtion o~ clock pulses at CLK,. Each of the flip ~lops in tlle DELTA N~DULl: are of 5 type SN7~74 de~cribed in section I.F Convention~ Used in Figure~.
One-shot multi-vibrators DE~ and DELMEN~ are contained in the DELTA ~IODULE. One-shot multi-vibra~or DELGO
i~ set to a 1 state pursuant to each call on the DELTA MODULE.
One-shot multi-vibrator DELME~D indicateg each exit from the DELTA M~DULE operation by a true signal at the DEI~ output and resets the module. The one-shot DELÇO a~d DEL~ have the sa~e characteristics as the one-~lot of the ENCODE ~IODULE.
A source of clock signals formed by a clock 312 forms series of regular recurring true pulses as depicted.
The DELTA M~DULE also includes OR gates 314, 315, 316, 317, 31~ and 320, and an AND gate 322. These gates are conventional gating circuit~ ~ell kno~m in the computer art. The output of A~D gate 322 i8 designated CLI~. The Inverter 324 i8 a conventional logical inversion circuit which ~orm~
. the logical inverse of the signal at CLK, and the ~nverted signal i~ designated ~rR.
A selection circuit DELS is a conventional selection cixcuit of the ~a~e type disclosed in the section $-B above.
Selector circuit DELS couples 8 bits o~ in~ormation rom any one o the designated three 8 bit inputs to a s~ngle 8 bit output which i8 the information input into register 302.
'.:
C. DetailQd Descrip~ion . . .
\ 3 The purpose o the DELTl~ ~ODULE is ~o rcceive a number : :
repre~entin~ ~he number o~ lines to be revo~ved and convert . ~ -142-. . .

~127767 1 the nu~ber into i~s l~rgest possiblo component power~ o~ 2 in decreasing value order.
Tlle DELT.~. IEODULE ~ c~lled by eitl~cr the P~EVOLVE ~;ODU~,E
or tlle OUTPUT ~IODUIE. The DELT~ )DULE i9 c~Lled by khe ~EVOLVE and OUIPUT ~IODU~ES by irst set:ting the DELFST
1ip flop to a 1 state. The OR gate 316 sets the DELFST
~lip flop ~o a 1 state and has inputs RMl and OtI2 from the REVOLVE and OUTPUT L~IODULE~, respectively A control signal at either the RMl output of the REVO~VE I~ULE or tlte 0~2 output of the OUTPUT MODULE enables OR ~ate 316 to trig8er the DELFST flip flop ~o a 1 state. Follo~ing the signal3 at either RUIl or OM2, ~he REVOLVE and OUTPUT ~DULES, respectively, provide signals at the RM3 and O~I3 outputs.
A control si~nal at either the P~I3 or OM3 output ene~gizes the OR ~ate 320, causing a true signal to be applied to the one-shot DELGO, causing i~ to apply a true si~nal to the in~ut o ~he DELCE flip ~lop. This cau~es the flip flop DELCE
to be set to a 1 state and causes the flip flops Pl and P2 to be reset to an 0 state.
The 1 state of flip flQp of DELOE causes a true signal at the DELCE output t~hich, in turn, enables the AND gate 322 to couple the clock ~ignal~ from clock 312 to the CLK output.
The resulting true ~ignals at the ~1 and ~ outputs of flip --flops Pl and P2 cause flip flop Pl to be set to a 1 state at the following pulse at CLK. As a result, Dl~l of the DELTA
MODULE 10w is entered.
The ~ource of the number to be converted i9 determined by control signals at the OM2, C~4 and SM7 outputs of the OUTPUT, CHANGE and SEED ~DULES, respectively. A true signal at OM2, 3 ¦ C~4 or SM7, respectively~ causes the DELS selection circuit ;; . , ~ -143-~Z7767 1 to ~ate ~h~ ~ bits o~ ln~orm~tion ~ro~ DS6 o~ the OUTPUT
MODULE ro~ CLIN~ o~ tlle CII~NGE IIODULE or rom Tl of the SEED ~IODUL~, resp~tively, to the in~ormation input of the shift re~ister 302 The si~nal at P2 is now false, causing re~ister 302 to be in a load mode of operation and the true si~nal at S~I8 (SEED ~I~IODULE), O~I4 (OUTPUT ~IODULE), or CM5 (CHANGE I~ODULE) enables the OR gate 314 to cause re~ister 302 to store the 8 bit information ~ignal from DELS.
During the 1 state of flip flop pl, control 3ignals are formed at the Pl and DELFST outputs of fl~p flops Pl and DELFST, causing the ~3BDELO flip flop to be set to a 1 state. To be explained in more detail, the 1 state of the ~ DELO fl ip flop is used to enable a 1 bit to be shifted into the most significant bit position of the shift register 15 304 during the following shifts of register 302. ~ -The true signals at Pl and DELFST additionally cause the OR g2te 318 to reset the DELFST flip flop to an O state and reset the DELEND flip flop to an 0 state.
Register 302 no longer contains all 0'~, a number to be converted having been stored th:rein, therefore a true signal is formed at the ~ output indicating that the regi~ter is not 0. This signal, in coincidence with the true signal at `
Pl, causes the P2 flip flop to be set to a 1 state and DB3 is entered. ! `--The conversion is made by shifting register 302 contalning the number to be converted towards tbe mo~t ~

~ ~~~ ` ' ~;
_~~~~~~ ~~ - '':, , ~ 3 ~ ` , .
~i -144- - --'. ' ~Z7767 1 si~n~~c:~n~ bit and by ~hiftin~ ~l1Q LC~5tCr 304 ~owards the least si~nifi~ant bit. The first sllit shi~s a 1 bit in~o the most significant bit position of register 304 from flip flop MSBDELO. Durinz DEB3 o~ the flow, whenever the reg~ster 302 does not contain all O's, a control signal is fonmed at the ~ output in coincidence with the true si~nals at P2 and ~ISBD~L~. Coincidence of these true signals cause the register 302 to be shifted one bit towards the most significant bit position, causing the most significant bit in register 302 to be stored in the MSBDELI flip flop and causing the register 304 to be shifted 1 bit position towaxds the least significant bit position. Durlng the first shift, the MSBDELO flip flop is in a 1 state, causing a 1 bit to be stored in the most significant bit position or flip flop of the register 304. It will be noted that the DELTA MODUIE
flow indicates a"SHIFT DELO rt" and "SHIFT DELO lft".
"SHIFT DELO rt" indicates a shift right towards the least significant bit positlon of register 304 whereas "SHIFT
DELI lft" indicates a shift left ~owards the most significant bit position of the register 302.
Following DB4, DB5 of the flow i8 entered where the MSBDELI flip flop i9 checked. If the MSBDELI flip flop i9 not in a 1 9tate, i.e., a;l bit having been 2S shifted there from regi8ter 302, DB4 of the flow 18 a8ain enteret where the above shift is repeated in the same manner as described above. The shifting process ~:

~ 3 ~
. ''.

, .-.

~ ~-.Y ~

(.! llZ7'767 ( ~

con~inu~si un~ L bl~ i~. stored in~o tlle ~Sr~ LI ~llp ~lop. I~hen this occurs, DB6 of the Elo~ is en~red.
The l state of the MS~DELI 1ip flop causcs a true sign~l at the MSEDELI output. The true s~als a~
S P2, MSBDELI and C~ trigger the one-shot DELMEND to a 1 state, causing a true signal at the DE~ND output ~rom the DELTA MODULE and additionally resetting the DELCE
flip flop to a O state, thereby preventing the AND gate 322 from applying addi~ional clock pulses at CLR and csusing the shi~ting to terminate and operation of the DELTA MODULE flow to EXIT. The true signal at the DELMEND output indicates to the calling module that it ha~ finished processing and that the word conta~ned in register 304 of DELO may be read as it now contains one lS of the component powers of 2 of the input number originally stored in regist~r 302. The true signal at output DELME~
also enables OR gate 315 to reset control counter 313 to O (i.e. Pl, P2 - O). The true signals at P2, MSBDELI
and CLK reset the MSBDELI flip flop to a 0 state.
The DELTA MODULE is again called by either the REVOLVE MODULE or the OUTPUT MODVLE by applying control signal8 at either the KM3 or OM3 ou~puts. Either of these signals cause the OR gate 320 to again trigger the one-shot DELGO which, in turn, sets the DELCE flip flop 25 to a l ~tate, enablin~ the AND gate 322 to form pulses ;-~
¦¦ ~t the utput. Both the P1 nd P2 11p 10p8 ar~ ;

::
~, ~ -146- `

` ~1L~ ~ 7 1 in O ~t~S, ~ccortlin~ly~ Pllp ~lop Pl is s~t ~o a l st~e at the ollowin~ pulse at CLK. After the firs~
c~ nal at RM3 or 0~13), tlle DELFST flip lop is in a 0 s~atc, accordingly, DB3 of the flow is entered, S followed by D~4-6, as de~cribed above. During each entry into DB4 and DB5, the shift registers in DELI and DEL0 are shi~ted until another l bit is stored in MSBDELI, causing another true signal at the output DELMEND, indicating to the calling module that a new component power of 2 is now in register 304 for output.
Finally, when the last l bit of the input number contained in register 302 i8 shifted into the MSBDELI
flip flop, the content of register 302 is 0, causing a true signal at the DIo output. I~ this occurs while lS the Pl ~lip flop is in a l state, the follo~in~ pulse at CLK sets the DELEND flip flop to a l state. If it occurs while the P2 flip flop is in a l state, the DELEND flip flop i8 set to a l state, irrespective o~ the clock.
The l state of the DELEND flip flop and resulting control signal at DELEND signals the call~ng module that the last and least significant power of 2 of the input number has been formed (e.g. entire number has been converted).
A true signal at the DELEND output or the DIo output in combinat10n with true signals at Pl and ~g cause the DELMEND one-shot to be ~et to a l state and the ... ,~

~ ' ' 11;~7767 1 ~I;LCI'. 1.il- 10p ~t~ ~ r~se~ ~ a O n~c, inllibl~inu tlle ~ut~ from provl~in~ urthcr pulses a~ CLI~.
DE~ ~ND clock circuit becomes Pl~ELEI~
C~IC P2 ~1SBDELI. These changes permit the D~LT~ ~ODULE
S to convert the number set in DELI to its component powers of 2. After this has been done, Dlo will be asserted. Then any further call on the DELTA MODULE
will cause DELEND to be set during Pl and the module -will terminate upon the assertion of the ~R signal during pulse Pl. Note that DELO is cleared in this case.

'I \,~

. `~ '-," '.

:- -148-~ \'''"'';

D. Example of Operation With the foregoing detailed organization in mind, consider an actual example of the operation of the DELTA MODULE. For the example, assume initially that the number 13, which in ~inary coded form is 00011010, is to be converted and the DELTA MODULE is called by control signals at RMl and RM3 or OM2 and OM3 from the REVOLVE
and OUTPUT MODULES, respectively, as described abo~e.
The binary coded num~er 00011010 is loaded into the register 302 as described above, The sequence of operation thereafter is as follows.

sequence of control DBl-DB5, DB4-DB5, DB4-DB5, DB.4-DB5, DB4-DB6;
DBl DELFST = 1 ,; control to DB2 DB2 DELFST = DELEND = 0 reset these flip flops;
set MSBDELO of DELO (100000000);
2Q DB3 DELI (13) ~ 0:.oontrol to DB4 ~
DB4 DELI = 00011010 shift DELI left; .
DELO = 10000000 shift DELO right;
DB5 MSB (DELI~ = Q :.oDntrol to DB4 --DB4 DELI = Q011Qla0 DELO = 01aa000Q
DB5 MSBCDELI~ ~ Q:.control to DB4 DB4 DELI = all0100a DELO = QOlOQ000 DB5 MSB CDELI~ ~ 0:.control to DB4 ~: - 14~ -~ .
:~ :

~ ;7 1 ¦ Dl34 D13LI ~ 11010000 ¦ DELO o 00010000 ¦ DB5 MSBI)'~LI - O .'. control to DB4 ¦ DB4 DL~LI - 10100000 ¦ DELO - 00001000 ¦ DB5 MSBDELI e 1 ,: control to DB6 ¦ DB6 MSBDELI - 0 DELI - lO100000 ¦ HALT
OUTPUT DELO - 8 (highest component power of 2 in 13) 10 ¦ DELEND ~ O

¦Second- call DELI is unaltered ~ -i --¦ DELFST ~ O
¦ sequence of control DBl, DB3-DB6 15 ¦ DBl DELEST - O .~ control to DB3 ¦ DB3 DELI ~ O ... ~. control to DB4 . ` .--¦ DB4 DELI - 01000000 - .
DELO - 00000100 ~;
DB5 MSBDELI - 1 .'. control to DB6 DELO - 4 - next component power of 2 :
DB6 MSBDELI ~ O DELI ~ 0100~000 HALT
OUTPUT DELO - 4 DELEND - O ;
. ~, Third call all par~meters are unaltered on input .
sequence of control DBl, D93-DB5, D84-DB6 DBl) ) as explained above D83) ,'~ . .
: 30 . ''"',,.
. -150- .:

I . ' ( ' ~ ~
llZ7767 1 l)B4 ~LI ~ 10000000 DELO ~ 00000010 DB5 MSB(DELI) - O ............... con~rol to DB4 DELO - OOOOOOOl DB5 MSB(D~LI) = 1 ,control to DBG
DB6 MSB~DELI) - ODELI - OOOOOOOO;
HALT
OUTPUT DELO - 1 DELEND = O
. ~' ., Fourth call sequence of control DBl, DB3, DB7;
DBl as before DB3 DELI ~ O :. control to DB7 -:

OUTPUT DELO e 0 DELEND - 1 . ,-,~.
' , '~' ' '' '' ~: 30 . ~
,:., -. -151-, ~- 11;i~7767 1 VI. R~VOLV~ MODULE
A. General Description As disclosed and described herein above with respect to Table 5, a line in an iso-entropicgram,represented by l's and O's can be generated simply by shifting the preceding line 1 bit position to the right and XORing the unshifted and .~' shifted preceding line together, truncating above the most .''~
significant bit to the right. Also, lines of an iso~
entropicgram can be skipped to generate a second line 10 in an iso-entropicgram from a first line. This is done by ,.' breaking the number of lines, between the fir~t l~ne and . '~,.-the second line, into its component powers of 2, going '' ., from largest to smallest power of 2. If the component powers ..
of 2 are used to determine the increment in which revolve 15 takes place from the first to the second 11ne, each increment ';,, is.a simple shift and XOR operation. This has been described above in connection w1th Table 4-C. ~ :' However, each occurrence ma~lng up a line of an iso- ',, entropicgram is represented in absolute coded form rather ,.
than by binary l's and O's, to facilitate implementation.
As a result, the shift and XOR operation are accomplished .,' according to the embodiment of the invention using absolute .' coded occurrence values rather than.i's and 0'9. Table 4-E '.
illustrates this process for the revolve operation disclosed ' ,', 2 and described in connection with Table ~-D. Thus, the l's only need be represented and are represented by absolute '' decimal numbers. Line 7 i5 shifted by 8 places to the right simply by addlng 8 to the absolute decimal value of line 7. XORing takes place simply by sorting the unshifted ..
3a and shifted values in order of magnitude, deleting . ~-: , . -152~
~ . ..

~27767 1 ~hose absolute occurrence values which are the ~me and those values which go beyond the end of the iso-entropicgram.
In this manner the result of the first XOR results in Line 15 of the iso-entropicgram of Table 4-B which is a simple sort of the unshifted and shifted values. Note, however, that the shift of line 15 by 1 results in a value 16. Since 16 exceeds the width of the iso-entropicgram, it is d~scarded.
Also during the subsequent XOR the values 3, 7, 8, 11 and 15 --are discarded. The sort of the remaining numbers results 0 in a sequence of decimal values representing Line 16.
Turning now to the REVOLVE MODVLE, the revolve operation is performed principally under control of the REVOLVE MODULE -with a8sistance of the MEMORY, ENCODE, DECODE I and II, and DELTA ~.uDULES.
Fig. 18 shows a flow chart which illustrates the sequence of operation of the REVOLVE MODULE. `The symbol RB
followed by a number identifies each box in the flow and the ~ymbol P followed by a number identifies the flip flop(s) -of the control counter 413 which is (are) in a 1 state for the corresponding flow blocks.
The REVOLVE MODULE serves the following two functions:
1. It revolves a llne of an iso-entropicgram down the number of lines which the calling module has set into the DE~I register of the DELTA MODULE.
2. It merge~ two 11nes ~i.e., XOR'~ two lines) of an iso-entrop~cgram together without any revolve. This function is accomplished by the calling module 1 8 placing an ~ in the DELI
register of the DELTA MODVLE.

`3 ~. ' ' ' -153- ~

1~2~767 1 The purpose of ~he first Eunction is to find the "seed"
line or the output line of the lso-entropicgram. The second function is used in connection with the CHANGE
MODULE where the CHANGE MODULE uses the REVOLVE MODULE to revolve the changes down to the seed line and then uses the REVOLVE MODULE to merge these changes with the seed line.
Thereafter, the REVOLVE MODULE performs its first function `
of revolving the merged line to the seed line.
The REVOLVE MODULE receives as input actual absolute -N coded occurrence values provided by the DECODE I and II
MODULES. DECODE I and II MODULES act independently in the sense that they select in order all occurrence values of a common input line from the MEMORY MODULE at different rates.
The rate at which DECODE I and II MODULES select the occurrence values from a common input line is determined by the REVOLVE MODULE which calls or requ~sts occurrences as require~.
The REVOLVE MODULE also receives absolute coded values representing the component powers of 2 formed by the DELTA
MODULE. These values each represent a number of lines in the iso-entropicgram to be revolved. Each component power of 2 signal i8 combined with each occurrence value provided by the DECODE I MODULE to form the shifted occurrence values. ;
The actual received (unshifted) occurrence values provided 2 by the DECODE I MODULE and the shifted values are then XOR'd and the result is the new line in the iso-entropicgram.
The most important function of the REVOLVE MODULE is the XOR (exclusive OR) function. To this end, the REVOLVE MODULE
compares all of the shifted values with the unshifted values and 3 sorts these two series of values in decreasing order of magnitude.

1 Si~niicantly, when a shitcd value and an unshi~ted occurrence value are ~ound to be equ~l, the two values are deleted As a result, the excl~slve ORing (XOR) function is provided. The result.~nt series o~ values are provided from the P~S4 selection circuit a~ output of the P~EVOLVE
MODULE to the El register of the ENCODE MODULE The ENCODE -~DVLE in turn, by use of one of its two clipping functions (described for ENCODE MODULE), clips off those high order occurrence values from the resultant series which are larger than the width o~ the iso-entropicgram, i.e., lar~er than the width of the original input line.
The resultant series of occurrence values provided by the REVDLVE ~DULE to the ENCODE ~VLE are in absolute coded form ant the ENCCDE I~DU~E converts these occurrence values to hybrid form for storage in-the ~RY MODULE as described above.

B. ComPonents The REVOLVE MODULE of Fig. 17 includes 8 bit or 8 flip 20 flop register~ CRl, CR2 and DN. Each of these registers ~ -i8 formed of register type SN74100 disclosed at page 259 in the above TTL boo~. Each has load circuitry which, responsive to a control signal at the L input along the side of the registers, causes the 8 bit information signals 2S applied at the upper side to be stored into the correspond-in~ re~ister.
Selection circuits RDSl-RDS4 are provided. The selection circuits are o the same type disclosed above which, responsive to a control signal at the numbered inpu~ts along the side of ~3 the selec~ion circuits, couple the 8 bit inputs indicated ~lon~ the upper side o e~ch seLection circuit throu~h ~o an .
,'.

- o llZ7767 1 ~ hit output circuit.
In ad~Iition, an ~rithmetic ALU i~ provided o tIle same type disclosed above Additionally, lo~ical signal inverters 402 and 403 are provided for ormin~ the lo~,ical inversion of the signal at E and CLK, respectively, and for providin~ corresponding outputs at E and ~
A clock 412 is a source of regular occurring, equalLy spaced clock pulses. Flip flops RCE, RS and Pl through P9 are provided, flip flops PL-P9 forming the control counter 10 413. One-shot multi-vibrato~ REVG0 and REVEND are provided. -One-shot multi-vibrators P~VGO and REVE~D normally form a false signal at outputs REVGO and REVEND but re~pond to a control signal applied to their input9 for setting to a 1 state wherein true signals are formed at outputs REVGO

and ~EVEND for a time interval equal to that between the beginnings of ~o successive clock pulses from the clock 412.
REVEND when formin~ a true signal at output REVEND signals the calling module that the revolve operation is co~plete.
Switches 404 and 406 are provided, each providing at -;
its output a continuous 8 bit binary coded signal, repre-senting the 2'~ complement of l, thereby representing -1.
AND gate 416 and OR gates 418 and 420 are conven~ional ~ND and OR gates well Icnown in the computer art and need no `-further explanatlon. Boolean logical equations are used to indicate varlous loglcal ~ates in the system as dlscussed above. Cloclc suspension logic 422 suspends operation of the REVOLVE MDDULE by terminating the CLK and ~g pulse while one of the other module~ co~npletes its operation.
Along the right side of the REVOLVE r~DULE schematic 3a are shown the input and output control lines for the llZ776~

1 REVOLVE ~lODUL~, ~nd the in~orm~tion in~u~ and O~ltpU~ lines usin~ ~he sal~e sys~em o nota~on descr1l~d hereLnabove.

C. Detailed Description The REVOLVE ~DU~E during its revolve function cooperate~
with the ~;~ORY, ENCODE, DECODE I and II, and DELTA ~ODULES.
Normally the DELT~. ~DULE provides the component powers of 2 of the number of lines to be revolved and the DECODE I and II
MODULES each read and decode the same event occurrence vector from the ~IORY MODULE. The DECODE I and II MODULES provide the absolute coded occurrence values, making up the event occurrence vector, one at a time as requested by the REVOLVE
MODULE. Both the DECODE I and II ~DULES prov~de the absolute coded occurrence values in the same order but one decode module may be requested to provide several occurrence values before the other decode module provides an occurrence value. To be explained in more detail, this operation i9 required in carrying out the exclusive Y,ORing operation.
m e resuLt ~ormed by the REVOLVE ~DULE is a ~equence of abso~ute coded occurrence values which are encoded by the ENCODE ~DVLE back to hybrid fonm and written into the ME~DRY M!ODULE.
To be explained in more detail, a simple merge of the occurrence values may be effected by the REVOLVE ~DULE
without XORing simply by providin~ a value o~ O to the DELTA ~ULE a~ the nu~ber of lines to b~ revolved.
To obtain a better overa}l vi~ o~ the REVOLVE ~DULE, refer n~ to ~he REVOLVE ~IODVLE flow, Fig. 18 and the REVOLVE~ODULEschematic and blockdiagram, Fig. 17, and consider in general the sequence of operation. ~s indicated 1~27767 1 in Table lL, th~ REVOLVE t~D~E cloes not h~ve ~ ~or~l~L set o~ input and o~put values. Ilowever, ~lle in~uts and output3 indicated for tlle ENCODE, DECODE I a~d II and DELT~ ISODVLES
are present. The result o~ the revolve function i9 a line o an iso-entropicgram which is stored in the ~EI~Y ~IODULE, During RBl and RB2 of the REVOLVE rIODULE flow, the DELTA
MODULE is called by the REV~LVE MODULE, causing the DELTA
~ODULE to provide its first component power of 2 malcing up the n~mb~r of lines to be revolve~. The first aad subsequent component powers of 2 are stored in the re~i~ter DN in the REVOLVE I~DULE.
During RB2, the DEC~DE I and DEC~DE II ~DULES and tle ENCODE
~DULE (the latter not indicated on flow) are initialized by setting the appropriate initial conditions therein prece~ing the first call on these modules.
During RB4, flip flop DELEND is checked and if in an O
state, the value of the number of lines to be revolved contained in DELI of the DELT~ MODULE has not been completely broken into all of its component po~ers of 2 and, re~ardless --of the state of flip flop RS, control goes to RB5 for further processing. If, during RB4 and RB5, flip flops DELEND and RS are in 1 and 0 states, respectively, the flip flop DELEND ind~cates that the value of the number of lineg to be revolved contained in DELI has no~ been conple~ely brolcen down into its component power~ of 2, and the flip flop RS indicates that a no~n zero value i8 ~tored in DELI and RB5 is also entered for further processin~, However~ ij during RB4 and RB6, flip 10ps DELEND and RS
are both in a 1 state, flip flop RS indicates a simple merge operation and that an n va~ue has been stored in 3 DELI by the calling module. DELEND indicates that the 11~7767 1 t:wo s~ries o occurrence~ rom tllc DECOl)~ I and II MODUL~S
hav~ ~lready been merged. Accordin~ly, ~:he REVOLVE MoDuLE
operation is EXITED.
DuL ing RB5 the DECODE I ~ODU~E i9 called by the REVOLVE
~ODULE by set~ing the DlGo multi-vibrator to a 1 state and, the fir~t time in P~B5, the irst and hl~hest numbered occurrence from the input line to be revolved is provided by the DECODE I ~DULE and stored in the CRl register of the REVOLVE ~IODULE. Typically~ the ne~t operation is in ; -RB8 through RB9, combin~ng the highest component power of 2 of the number of lines to be revolved contained in the DN register with the occurrence value contained in the CRl register and the result i8 stored back into the CRl register.
Since the occurrence value provided by the DECODE I MDDULE ~
15 is in absolute binary coded form, the sum results in a ~ -value simulating the right shift of '~N" places of the occurrence value provided by DEOODE I.
Over10w i~ checket during RB10. If overflow has occurred, this meaDs that the resultant shifted value in CRl is larger than the DPM c a n h a n d 1 e.
Thus, the content of CRl i9 larger t~an the current i80-entropicgram width. Thls is so since the width i~
constrained to lle within the bounds of the machine.
Therefose, when over1~ occurs, control returns to RBs 2 and the DECODE I MODULE is again called, 80 th~t it reads the next s~aller occurrence value which ls then combined with the contene o~ DN and stored into CRl. Therefore, the result previously formed during RB9 and stored in CRl ¦ is ignored. On the other hand, i~ overfl~ did no~ occur ~30 ¦ or if flip 10p EOFl(end o Eile for DECODE I MoDuLE) is true, ~;

-159- ~
~ ' L ' '' 1 1~27767 1 ¦ conl:roL ~oe~ t:o ~r,L2.
¦ Durin~ r~Bl2-Ls~ e D~CODE II ~DUI~E i~ called by ¦ set~ing ~lle D2GO mul~i-vibrator into a 1 state. Ini~ially, ¦ ~he D~OODE II M~DUL~ p~ovides the lar~est occurrence value S ¦ and this value is stored in re~ster CR2. I there ~9 ¦ nothing to read (i.e., end of file has ~een reached Eor ¦ DECODE II 2~DUL~), flip flop EOF2 i9 true and RB15 i5 ~ .
¦ entered where C~2 i8 loaded with a value of -1 ;
l D~ring RBl6~ outputs EoFl and EOF2 are checked to see 10 ¦ i~ both are true and if so, th~ indicates the end of file ~-¦ for both DECODE I and DECODE II ~DDULES. If end of file ¦ has been reached, control goes to RBl7-RBl9 because ¦ this portion of the revolve or merge is complete.
¦ Accordingly, flip flop ELAST is set and the ENCODE ~ODVL~
15 ¦ is in~tructed to write out its final value. MLN3 in the ¦ E~ICODE ~DULE contains the physical length of the line ~hich ¦ ~as ~ust generatet. This value is clocked into MLNl and ¦ MLN2 of the DECODE I and II MODULES. This i~ done in ¦ case another revolve i8 needed.
20 ¦ I either or both of the flip lops EOFl or EOF2 are in a 1 state, the end of one or both o the files being ¦ read by DECODE I and II ~DULES has been reached and RB20 ¦ i8 entered ~ollowing RB16. During RB20, the shifted occurrence value in register CRl i8 compared with the un~hlfted oocurrence value in CR2. If the shited value contained in cnl i9 larger, then it is necessary to ~rite out this value and accordin~ly, RB23-24 are entered where the ENCO~E ~DDULE i9 called by setting the ENGO mul~i-vibrator to 1, causin~ the content of register CRl to be sent to the EI
register o~ the ENOODE ~DULE where it is subgequen~ly encoded and .. -160-~, ..

'~ llZ7767 written out in a pre~elc,te.d area o the MEMORY MODUL~. Duriny R~25-RB28, the D~COD~ I MODUI,E i8 aqain called by ~etting DlGO
to 1; the next lower occurrence value is read from the same lnput line; the next lower occurrence value is combined with the 6 same component power of 2 value contained in the DN register;
and the result ('shifted occurrence value) is stored in the CRl register. Subsequently, RB20 of the REVOLVE MODULE flow is again entered where the content of registers CRl and CR2 is again com-pared. This operation occurs-and is repeated as long as the shifted value stored in register CRl is larger than the unshifted value in register CR2.
If, during RB2~ of the ENCODE MODULE flow, it is found that the unshifted occurrence value contained in CR2 is larger than the shifted occurrence value in CRl, RB21-RB23 are entered where the ENCODE MODULE is called and the unshifted occurrencevalue contained in the CR2 register is sent via the RD~S4 selection circuit to the EI register of the ENCODE MODULE for encoding and writing out in the same preselected area of the MEMORY MODULE. RBl~ is re-entered where the DECODE II MODULE is again called, causing the next lower '`~
2~ occurrence value to ~e read out by the DECODE II MODULE and stored -`
in register CR2. This operation also occurs and is repeated until an unshifted occurrence value is stored in CR2 that is larger than the shifted occurrence value in the CRl register.
If during RB2~ of the REVOLVE MODULE flow it is found that the shifted occurrence value oontained in CRl is equal to the '`
unshifted ocaurrence value contained in CR2, then RB5-RBl9 of the REVOLVE MODULE flow are again entered where the action of the ENCODE MODULE of storing a value in the iSo-entropicgram is skipped, and two new occurrence values are read from the same input -''~
line by the DECODE I and DECODE II MODULES.

` ::`

I
; " ` `

l~Z7767 1 When ~he end o file o bo~h the DECO~E I ~nd II
MODULES are reached (i.e., no further occurrence values remain to be read by either the DECODE I or the DECODE II
MODULE), RB17-19 are entered where the ENCODE MODULE ig signaled to write out the last occurrence value being formed ln the preselected area of the MEMORY MODULE.
It should be noted that during a revolve operation the MARl register of the DECODE I MODULE and the MAR2 register of the DECODE II MODULE form pointers for the respective modules which indicate which occurrence value of the common input line is next to be read by the co responding decode module. In this manner, the DECODE I and DECODE II MODULES
can provide a string of occurrence values from the same input line at different rates, the occurrence values being provided one by one by the respeetive decode modules, as called by the REVOLVE MODULE. During a CHANGE operation the MARl register and the MAR2 register form pointers for the respective modul 8s which indicate occurrence values from different memory areas that are to be read by the corresponding decode module.
Refer now in more detail to the organization of the REVOLVE MODULE, referring to the schematic diagram of Fig. 17 and the flow dlagram of Fig. 18. Initially, the MINI
COMPUTER forms a true signal at the output MINIT causing 2S the circuits to which it i9 connected, including control counter 413, flip flops Pl-P9, to be reset to 0. The REVOLVE
MODULE is called by any one of the following modules: SEED, : CHANGE and OU~PUT, by forming a true signal at the respective outputs SM9, CM6 and OM5, any one of which causes the 3 O~ gate 418 to trigger the one-shot multi-vibrator ~--~. ` . ' . .

~ ` 1127767 RF.VGO to a 1 ~tate, causing a true signal at the REVGO
output. The true signal at REVGO causes the RCE flip flop to be set to a 1 state. The 1 state o~ the RCE flip flop enables the AND gate 416 to start coupling the clock pulses from the clock 413 to the output CLK and through the inverter 403 to CLK.
The one-shot multi-vibrator REVGO returns to a 0 state.
Since flip flops Pl... P9 are all 0, the following pulse at -CLK causes the flip flop Pl to be set to a 1 state, thereby ;~
10 causing RBl of the REVOLVE MODULE flow to be entered. The -1 state of the Pl flip flop causes a control signal at the output Pl of the Pl flip flop. The control signal at `
output Pl in turn resets flip flop RS to 0; causes a true signal at the RMl output of the input and output 15 control lines from the REVOLVE MODULE causing the DELFST -flip flop in the DELTA MODULE to be set to a 1 state; and also causes a true signal at the RM3 output from the REVOLVE MODULE, setting the DELGO multi-vibrator in the -DELTA MODULE to a 1 state, thereby calling the operation of 20 the DELTA MODULE as described hereinabove. -The DELTA MODULE then converts a number representing ~-the number of lines in the iso-entropicgram to be revolved to its component powers of 2 starting with the largest power of 2, all as described in connection with the DELTA MODULE.
25 At this point in time, the DELMEND one-shot multi-vibrator in the DELTA MODULE is in an 0 state forming a false signal at the DELMEND output whiIe a true signal is concurrently being formed at the R~3 output from the REVOLVE MODULE.
Accordingly, logic RM3.DELMEND of the clock suspension 30 logic 422 become false, causing a false signal at the input ;
.~ , ~: :
~' ,,.

to the ~D ~ate ~16, disabling urther clock signals from bein~ applied at the CLK and CLK outputs, thereby disabling further operation in the REVOLVE MODULE. The DELTA MODULE
independently completes the formation of the component power of 2 of the number Te~resenting the lines to be revolved and then sets the DELMEND one-shot multi-vibrator to a 1 state, applying a true signal at the DELMEND output. The term RM3.DELMEND then goes true, causing the clock suspension logic 422 to again apply a true signal to the AND gate 416, again causing clock pulses to be formed at ~-the CLK and CLK output. The true signal at output Pl at the following pulse at CLK sets the P2 flip flop to a 1 state, causing a true signal at the P2 output thereof and resets flip flop Pl to 0. The true signal at the P2 output causes a true signal at the L input to the DN
register, which in turn causes the DN register to store the largest power of 2 signal formed in the DELO register of the DELTA MODULE, and RB3 of the REVOLVE MODULE flow is entered. The true signal at the P2 output of the P2 flip flop causes the DECODE I and DECODE II MODULES and the ENCODE MODULE to be initialized. Initialization is a process whereby a true signal at the P2 output of control counter 413 causes a true signal at the RM2 output of the REVOLVE MODULE, which in turn causes the DlFST flip flop in DECODE I MODULE, the D2FST flip flop in the DECODE II MODULE, and the EFRST flip flop in the ENCODE MODULE, all to be set to a 1 state. RB4 of the REVOLVE MODULE flow is now entered where the state of the DELEND monostable of the DELTA
MODULE is checked and if in a 1 state, control goes to RB5.
If, however, the DELEND is in a 1 state, then control goes llZ7767 to ~B~ re the RS Elip flop of the REVOLVE MOD~LE is checked.
If in a 1 sta~e, flip flop RS signals a merge operation. The logic P2.DELEND is true, resetting flip flop RCE and monostable REVEND to 0, causing the clock signals from gate 416 to be disabled and the operation to EXIT.
The REVEND monostable applies a true signal to OR gate 420 causing it to reset counter 413 to zero. At the same time, the true REVEND signal is applied back to the calling module indicating that the REVOLVE MODULE has completed its function.
Assume now that during RB4 the DELEND monostable in the DELTA MODULE is in a 1 state forming a true signal at the DELEND output, this signal, in coincidence with true signals at RS, the P2 output of control counter 413, and --the pulse at CLK, causes a true signal at the RM8 output which goes to the SWITCH M~TRIX, causing the SWITCH MATRIX
to be activated to perform its reading and writing operation -in the prescribed MEMORY MODULE area in the manner to be -;`
described hereinafter. The true signals at the P2 and CLK outputs in the REVOLVE MODULE additionally cause a true signal at the RM4 output of the REVOLVE MODULE which -~
in turn sets the DlGO monostable of the DECODE MODULE to a 1 state, thereby calling and causing the DECODE I MODULE
to provide the next smaller occurrence in the input line from the MEMORY MODULE and provide it as an absolute binary coded occurrence value at the DOl output of the DECODE I
MODULE. ~he true signal at the RM4 output of the REVOLVE
MODULE in coincidence with a true signal at the DlMEND
output from the DECODE I MODULE causes the clock suspension logic 422 to again form a false signal and disable the gate 416, preventing further clock signals from being ormed at the CLIC and CLK outputs, thereby disabling the operation of the REVOLVE MODULE. When the DECODE I MODULE completes its operation, the true signal is removed at the DlMEND output, thereby causing the clock disable logic 422 to again enable the gate 416 and clock pulses to be formed at the CLK and CLK
outputs. The true signal at the P2 output of control counter 413 in coincidence with the pulse at CLK causes the P3 flip flop to be set to a 1 state, thereby forming a true signal at the P3 output and the P2 flip flop is reset to 0. The true signal at the P3 output of the control counter 413 and at the EOFl output of the ENCODE MODULE (indicating that the end of file has not yet been reached), causes the logic P3.EOFl to be true and the value of the input line provided by the DECODE I MODULE -is coupled through the RDSl selection circuit to the information input of the CRl register. The true signals at P3 and the signal at CLK cause the load circuitry in CRl to store the occurrence value from the DOl output of the DECODE I MODULE
into the CRl register.

During RB7, if the end of file had been reached and the - -DECODE I MODULE was forming a true signal at the EOFl output, RDSl would not have coupled the output DOl from the DECODE I
MODULE to register CRl but, instead, would have coupled the signal representing the 2's complement of 1 ~-1) formed by the switches 404 to the information input of CRl causing the corresponding value to be stored in re~ister CRl. This occurs during RBll of the flow after the end of file is reached by the DECODE I MODULE where no further occurrences are to be provided by DECODE I MODULE and a -1 insures that further occurrences will not be obtained from DECODE I MODULE nor : ~~

" .", , , ~ . , , , ' . , ! ` ~ ` " `

outputted ~rom register CRl. All ~urther occurrences, if any, are taken ~rom CR2.
The true signals at the P3 output of control counter 413 and the RS, and CLK outputs also cause a true signal at the RM12 output of the REVOLVE MODULE, which in turn sets the special flip flop SP in the SWITCH MATRIX. To be explained in more detail, the SEED MODULE forms a true signal at SM5, causing the SP flip flop to be set to a 1 state only if a current output is considered to be the best seed. This will be discussed in more detail in connection with the SEED MODULE. ~
The tru~ signal at the P3 output also causes the P4 flip :-flop to be set to a 1 state and flip flop P3 is reset to an 0 -state at the following pulse at CLX, and RB9, RB10, RB12 of ~
the REVOLVE MODULE is entered. The true signal at the P4 output of the P4 flip flop causes the RS flip flop to be set to a 1 state. As explained before, this is done so that after the first pass the REVOLVE MODULE will EXIT when DELEND (DELTA
MODULE) is in a 1 state.
The true signal at the P4 output causes the RDS3 selection circuit to couple the power of 2 signal in the DN register to the ALU and causes the ALU to add the content of the registers CRl and DN and form an output signal at OP corresponding to the sum. This signal represents the occurrence value shifted -towards the most significant position by the number of 2S possible occurrence values indicated by the power of 2 value in regisLer DN. This signal is called the shifted occurrence value.
The ALU forms a true signal at the OVL output, causing the RDSl selection circuit to couple the shifted occurrence value from the OP output back to the information input of the CRl register. Additionally, the true signal at P4 and .. - ~ .
".

- ~ ~
llZ~767 1 ~FI in ~oincidcnce wi~ he pul~a a~ CJ.I~ ca-lse3 tlle loacl circul~ o~ tlle CRl rc~ ter to store the vaLue bacl in~o ~he cr~l resister.
I~ over~lo~ occurred ~rom tlle 9Um 0~ the Cr~l and DM
registers, the result i3 lar~er than the width of the iso-entropic~r~m and there is ormed a true si~nal at the OVL output which in con~unction with the CLK puLse causes the output P~M~
to be true. In addition, the true si~nals at the P4 output from counter 413 and the OVL output from the ~LU cause the input to flip flop P3 in counter 413 to be 9et to a 1 state.
In the flcw dia~ram this is equivalent to going from RB10 to RB5. The reason for this flow is thst if overflow occurs in the addition of Cl'l and DN, this indicates that the simulated right slift has generated an iso-entropicgra~
~5 column value which cannot be represented by the DP~I, If this is the case, we know the number i9 larger than the current iso-entropicgram width (which obviously is represented in the machine) and thus the above value would have been clipped by the ENCODE MODULE. Going from RB10 to 20 RBS eliminates the call to the ENCODE MODULE and nothing is written in the MEMORY MOD~LE.
RM4 ~ets the DloO monostable in the DECODE I MDDULE.
As a result the next lower occurrence value is provided by the DECODE I MCDULE. In addition, the logic RM4.Di~DEND is true, 25 causin~ the clock suspenslon lo~ic 422 to suspend the cloctc until the DECODE I ~DULE is fin~shed. When f~nisbed, the ne~t lower occurrence value in DOl o~ the DECODE I MODULE
is stored into the CRl re~ister and hence over-writes the overflow value previously stored in CRl.
3 Assume RBl2 of the REVOL~E ~DULE flbw is now entered ~ ` . '' .,~ , '~
....

llZ7767 1 followin~ RB10. The true ~ignal at thc P4 output of the P4 flip flop in coincidence with the true signals at the CLK
output and the OVL output causes a true signal at the RM5 output of the REVOLVE MODULE which sets the D2GO multi-vibrator in the DECODE II MODULE to a 1 state, therebycalling the DECODE II MODULE so that it too reads an occurrence value from the same input line as the DECODE I MODULE obtained its occurrence value. If this is a merge operation initiated by the CHANGE MODULE, DECODE II will be reading a line - --0 which is different from the line being read by the DECODE I MODULE.
The D2MEND monostable in the DECODE II MODULE is in state 0 causing a true signal at the D2MEND output. The true signal -at the RM5 output of the REVOLVE MODULE in coincidence with the true signal at the D~MEND output indicates that the decoded occurrence value is not ready in the DECODE II MODULE
for the REVOLVE MODULE and causes the clock suspension logic 422 to again apply a false signal to and disable the gate 416 from supplying clock pulses and the operation of the REVOLVE
MODULE i8 suspended. After the DECODE II MODULE provide~
the occurrence value, it returns control to the REVOLVE
MODULE by removing the true signal at the D2MEND output of the D2MEND monostable. This enables the gate 416, allowing clock pulses to again be formed at the CLK and CLR
output, enables the P5 flip flop to be set to a 1 state, and enables flip flop P4 to be reset to 0.
The true signal at the P5 output of the P5 flip flop ;
in coincidence with a true signal at the ~ output of the EOF2 flip flop in the DECODE II MODULE causes the selection 3C circuit RDS2 to couple the occurrence value from the DECODE II
': ` . ~' ~", - , " ~ , I" ~ ~ .,, " ~ "~

11;~7767 MODUL~ to the inEormation input of the CR2 register. The true signal at the P5 output in coincidence with the following pulse at CLK causes the value to~be stored into the CR2 register. It should be noted that if this is not a merge operation, the ~alue obtained from DECODE II MODULE is an actual occurrence value in the same input line of the iso-entropicgram and constitutes the unshifted occurrence value which will be compared with the shifted value now contained in the CRl register. It should be noted that should the EOF2 flip flop in the DECODE II MODULE be in a 1 state, the end of file has been reached by DECODE II MODULE and therefore no occurrence value is being provided by DECODE II MODULE.
Accordingly, the RDS 2 selection circuit, responsive to the true signals at P5 and EOF2, couples the output of the switches 406 to the input of the CR2 register, causing the 2's complement of -1 to be stored in the CR2 register.
The checking of flip flop EOF2 and placing a -1 in CR2 if EOF2 is in a 1 state is necessitated by the following.
If in a merge operation, the DECODE I and DECODE II MODULES
are reading different lines from different MEMORY MODULE
areas. In case the DECODE II MODULE finishes reading first, the -1 in CR2 will force the DECODE I MODULE to pass the remainder of its occurrence value to the ENCODE MODULE via RB20, RB23, RB24.
RB16 of the REVOLVE MODULE flow is now entered where the states of the EOFl and EOF2 flip flops of the DECO~E I and DECODE II MODULE5 are checked. If both flip flops are in a 1 state, indicating that both DECODE I and DECODE II MODULES
.
have reached the end of file (i.e. the end of the input line of the iso-entropicgram), RB17 of the REVOLVE MODULE flow .

``` llZ7767 is entered and the true signals at the outputs P5, EOFl and ~iOF2 cause a true signal at the RM9 output which sets the ELAST flip flop in the ENCODE MODULE to a 1 state.
Additionally, the following pulse at CLK in coincidence with the true signals at P5, EOFl and EOF2 cause a true signal at the RM7 output which in turn sets the ENGO one-shot multi-vibrator to a 1 state, thereby calling the operation of the ENCODE MODULE. This causes the ENCODE I ¦
MODULE to encode and store the last of the occurrence values of the new iso-entropicgram line into the MEMORY MODULE.
Assuming that either the EOFl or the EOF2 flip flop in the DECODE I and DECODE II MODULES is 0, thereby indicating that either DECODE I or DECODE II MODULE has reached the end of file,RB20 of the REVOLVE MODULE flow is entered where the shifted occurrence value in CRl is compared with the unshifted value in CR2. It should be noted that the registers CRl and CR2 contain absolute binary coded values, indicating directly the shifted and unshifted occurrence values. This comparison operation is an important part of the REVOLVE MODULE operation as it is a key part of the exclusive ORing process. To this end, the shifted and unshifted occurrence values of the input line must be sorted into decending order of magnitude. Those shifted and unshifted occurrence values which are equal are dropped.
This then exclusive OR's the shifted and unshifted occurrence values and cau~es a revolve from one line to the next in the iso-entropicgram.
Referring to RB20 of the REVOLVE MODULE flow, the true -signal at the P6 output causes the RDS3 selection circuit to couple the CR2 register to the ALU and causes the ALU to : .

llZ7767 compare the content: of the CRl and CR2 registers. If the shifted value contained in CRl i8 greater, a true signal is formed at the G output. This causes RB23-RB30 of the REVOLVE MODULE flow to be entered where the shifted value contained in CRl is encoded and stored into the MEMORY MODULE
by the ENCODE MODULE and the DECODE I MODULE reads its next occurrence value from the same input line, the next ;
occurrence value is combined with the content of register DN to form a shifted occurrence value, and the shifted occurrence value is stored in register CRl.
Consider in more detail the operation during RB23 and RB24.
The true signals at the G output of ALU and at the P6 output causes the RDS4 selection circuit to couple the shifted occurrence value contained in the CRl register to the output thereof, which goes to the input of the EI register of the ENCODE MODULE. A signal is formed at the E output of the inverter circuit 403 when the values compared are -- not equal. The true signals at outputs P6 and E cause a true signal at the RMll output of the REVOLVE MODULE which, in turn, causes the EDS6 selection circuit in the ENCODE
MODULE to couple the output from RDS4 to the EI register.
The true signals at P6, E and CLK energize the L input of the EI register of the ENCODE MODULE, causing the occurrence value contained in CR2 of the REVOLVE MODULE
to be loaded into the EI register. The true signal at the outputs P6, E and CLX also cause a true signal at the RM7 output of the REVOLVE MODULE which, in turn,sets the ENGO multi-vibrator to a 1 state, thereby calling the operation of the ENCODE MODULE as described above. Once called, the ENCODE MODULE converts the shifted value obtained ~ ` " . ' ' '~'' ~27~7~;7 from th~a CRl rcgister to hybrid Eorm and stores it in the MEMORY MODUL~.
If, during the true signal at the P6 output both the EOFl and EOF2 flip flops from the DECODE I and DECODE II
MODULES are in a l state, a true signal is formed at the RMl4 output of the REVOLVE MODULE which, in turn, causes the MLNl and MLN2 registers of the DECODE I and DECODE II MODULES
to be loaded with the value contained in the MEN3 register of the ENCODE MODULE. This is done since the complete input line will have been processed by the REVOLVE MODULE and the new iso-entropicgram line which is now in the area designated by the MLN3 register of the ENCODE MODULE
forms the new input line and is next to be processed by the DECODE I and DECODE II MODULES in order to revolve to the next line of the iso-entropicgram. This operation allows subsequent lines in the iso-entropicgram to be formed from the new iso-entropicgram line just formed by the REVOLVE MODULE. L
Continuing with RB24 of the REVOLVE MODULE flow, the true signal at the RM7 output in coincidence with the true signal at the ~ output of the ENCODE MODULE causes suspension logic 422 to suspend the operation of the ~ ;
REVOLVE M~DULE similar to that discussed above until the ENCODE MODULE has compIeted its encode function and removes the true signal at the EMEND output. After the suspension has ended and the gate 416 is again enabled by the clock suspension logic 422, the following pulse at CLK causes flip flop P7 to be set to a 1 state and flip flop P6 is reset to 0. The 1 state of the P7 flip flop is used as a time delay ~; in the system. A time delay is needed in order to allow the ¦~ 30 ENCODE MODULE to complete its operation before the decode.
, . :' ' ' "

.. ,- :

moclules are called. This is needed in this system since all the modules operate serially. However, this need not necessarily be the case as the system could be designed so that all the modules operate in parallel.
RB25-28 are now entered. A true signal at the P7 output again causes the selection circuit RDS3 and the ALU to compare the shifted and unshifted values, respectively, contained in registers CRl and CR2. Since the values have not changed, the shifted value contained in register CRl is the larger and hence a true signal is again formed at the G output of ALU. The true signal at the P7 and G
outputs causes the flip flop P8 to be set to a 1 state at the following pulse at CLK. Additionally, the true signal -at the P7, G and CLK outputs causes a true signal at the RM4 output, thereby again calling the DECODE I MODULE, causing it to read out the next lower actual occurrence value in the same input line from the MEMORY MODULE. As before, the true signal at the RM4 output in coincidence with the true signal at DlMEND from the DECODE MODULE causes the clock suspension logic 422 to disable the gate 416 and suspend the operation of the REVOLVE MODULE until DECODE II
MODULE removes the true signal at DlMEND, indicating that it has now completed its decode operation and is now providing its next lower actual occurrence value of the input line. During RB27 the true signal at the P8 and EOFl outputs causes the RDSl selection circuit to couple the next lower occurrence value from register DOl of the DECODE I
MODULE to the information input of CRl and the following pulse at CLK causes the CRl load circuit to store the value into the CRl register. Similar to that described above, in I - .

7767 ~-`

1 ¦¦ nncc:tion wlth the true slgnal at P3, ehould the EOFl flip flop of the DECODE I MODULE be in a 1 state, providing a true signal at the EOFl output, the DECODE I MODULE
would have reached the end of f ile, RB30 would be entered and hence the 2's complement of a -1 represented by the switches 404 would be stored in register CRl rather than the output f rom the DECODE I MODULE.
Continuing with the operation during RB27-RB28, the true signal at the P8 output causes the P9 flip flop of -:

the control counter 413 to be set to a 1 state and RB28 of the REVOLVE MODULE is entered. The true signal at the P9 output causes the RDS3 selection circuit to couple the ~ -power of 2 value contained in the DN register to the ALU
and causes the ALU to add the content of the CRl and DN

lS registers and form a new shifted occurrence value at the -output OP. --~ -As explained with pulse P4, if overflow occurs during ~ -the addition of CRl and DN, a signal is formed at OVL . ~:.
indicating a right shift to an iso~entropicgram column value which cannot be represented by the DPM. The value is therefore ignored. Accordingly, if output OVL i3 true, the logic P9.OVL is true, causing flip flop P8 and P9 to be set to 1 and 0 states, respectively, at the following CLK
pulse and a signal i8 to be formed at output RM4 during 2~ the CLK pulse P9, and DlGO of the DECODE I MODULE is set.
The DECODE I MODULE reads the next lower occurrence value as explained above. However, if the addition does not produce overflow, OVL is true, causing logic P9.OVL to become true and the following CLK pulse sets flip flops P6 and P9 to 30 ~1 and 0, respectively, and control returns to RB16.

..

~lZ77t;7 1With the new occurrence value ~rom ~he input line now read from the MEMORY MODU~E and the shifted value contained in the CRl register, RB16 and RB20 o the REVOLVE
MODULE flow are reentered. The true state at the P6 output of the P6 flip flop again causes the content of registers CRl and CR2 to be compared, as discussed above, to determine which is the larger. If the new shifted occurrence value contained in register CRl i~ the larger, RB23-RB30 are again entered where the larger value contained in CRl is sent to the ENCODE ~DULE for conversion to hybrid for~ and writing in the MEMDRY MDDULE and the DECODE I M~DULE i9 again cslled, causing the next lower value occurrence value of the same input line to be read from the MEMDRY ~CDULE, combined with the value in DN to form ~ shifted occurrence value and stored in regi~ CRl.
A88ume that during RB20, during the true ~ignal at the P6 output, the ALU detects that the content of the unshifted occurrence value at CR2 i8 larger than that of the shifted occurrence value contained in register C~l. The ALU ncw forms a true signal at the L output causing RB21-RB22 to be entered.
During RB21-RB22 the true signal at the P6 ard L
outputs causes the RDS4 selection circuit to couple the unshifted occurrence value contained in register CR2 to the ENaoDE ~DULE and the true ~ignals at the P6, ~ and ~SR outputs cause a true 3ignal at the RM6 and RM7 outputs ; -wh~ch, in turn, cause the unshifted occurrence value ln CR2 to be stored into the I register o~ the ENOODE MODULE
and cause the ENCODE MODULE to be called, Thus called, the ENCODE MODULE encodes the unshifted occurrence value from register CR2 to hySrid form and causes it to be stored , . ,~, -176- ;

` 1~27767 into the MEMORY MODUL~ in the new iso-entropicgram line beln~ formed there.
As discussed above, the true signal at the RM7 and ~MEND outputs again cause the clock suspension logic 422 to suspend the operation of the REVOLVE MODULE. When the ENCODE MODULE indicates that it has ended its operation by removing the true signal at the EMEND output, the suspension ends and the clock causes the P7 flip flop to again be set to a 1 state, forming a true signal at the P7 output which again causes the RDS3 selection circuit and the ALU unit to again compare the shifted and unshifted occurrence values contained in the CRl and CR2 registers.
Since the value in CRl is still smaller, a true signal is again formed at the L output and RB12 is entered.
During RB12 the true signals at the P7, L and CLK
outputs cause true signals to be formed at the RM5 output which, in turn, sets the D2GO one-shot to a 1 state thereby calling the operation of the DECODE II MODULE, causing it to read the next lower occurrence value from that which it originally read from the MEMORY MODULE and provides it for storage into the CR2 register.
The true signal at thè D2MEND output from the DECODE II
MODULE again causes the operation of the REVOLVE MODULE to be suspended until the DECODE II MODULE provides the next occurrence value. Once the next occurrence value is provided by the DECODE I~ MODULE and the true signal i9 removed at the D2MEND output, the clock suspension logic 422 again terminates the suspension of operation of the REVOLVE MODULE and the following pulse at CLK in coincidence with the true signals at P7 and L cause the P5 flip flop to again be set to a l `
state where during RB14 the next lower occurrence value from o ~
l~Z776~

1 the D~CODE I MODUL~ is stored into the CR2 r~gist~r, as described above.
Assume now that RB20 of the REVOLVE MODULE f low occurs and the P6 flip flop is in a 1 state and the shifted occur-rence value contained in CRl is equal to the unshifted occur-rence value contained in CR2, thereby causing the ALU to form a true signal at the E output thereof and inverter 403 forms a false signal at E. According to the excl~lsive ORing procedure, it is necessary to delete both the shifted and unshifted occurrence values in the CRl and CR2 registers from the new iso-cntropicgram line being formed. Accord-ingly, the ALU forms a false signal at the E output in coincidence with the true signal at the P6 output. The logic P6.E.CLR is now false and therefore the pulse at CLX
15 does not cause a true signal at RM7 and hence does not cause ~-the ENGO multi-vibrator in the ENCODE MODULE to be set. The true signal at the P6 output, hovever, causes the P7 flip flop to be set to a 1 state where the ALU again compares the content of register~ CRl and CR2 as discussed. Since the values in CRl and CR2 are still equal, the ALU forms a true signal at the E output. The true signal at the E output in coincidence with the true signal at P7 sets the P3 flip flop to a 1 state, thereby causing RB7 through RB20 of the -REVOLVE MODU~E flow to again be entered where both the DECODE T and DECODE II MODULES are called, causing respective new occurrence values of the same input line to be provided to the REVOLVE MODULE.
This process continues until during RB16 it is detected -that both the EOFl and EOF2 flip flops of the DECODE I and DECODE II MODULES are true, indicating that both DECODE I and . , ~ .
-178- ~
':,, ':

D~CODE II MODULES have reached the end of the input line.
When this occurs, true signals are ormed at the EOFl, EOF2 and P5 outputs, causing a true signal to be ~ormed at the RM9 output which in turn sets the ELAST flip flop in the ENCODE MODULE which, in turn, causes the ENCODE MODULE
to store any remaining occurrence values in hybrid form in the MEMORY MODULE as described in connection with the ENCODE MODULE.

D. Example of Operation.
Consider now an actual example of operation for the REVOLVE MODULE. Table 4-B herein gives an example of the way in which one revolves from one line to another in an iso-entropicgram. Using this same example, consider the way in which the present embodiment of the invention revolves from line 2 to line 7. Before the REVOLVE MODULE is called, the following preliminary steps are taken:
1. The MLNl register of the DECODE I MODULE ~nd the MLN2 register of the DECODE II MODULE are stored with the physical length of line 2 of the example which physical length is normally obtained from the IPRF.
2. Line 2 of the example, namely, event occurrence vector 0, 1, 3, 8, 9, 10,11 is stored in hybrid coded form in one of the memory areas of the MEMORY MODULE.
3. The numbex of lines to be revolved, i.e., 5, is loaded into the DELI register of the DELTA MODULE
`~ as described above.
The sequence of~operation following these initial ~;

conditions is as follows:

- llZ7767 RBl RS = 0 DELFST = 0 ; initialize DELTA MODULE
RB2 DELGO = l ; yet largest component power of 2 DN = DELO = 4 RB3 DlFST = D2FST = 1 ERFST = l ; initialize DECODE AND
ENCODE MODULES
RB4-RB5 DELEND = 0:,DlGO = 1 ; get first value from ~.
DECODE I MODULE -.
DOl = 11 .
RB7-RBll CRl = DOl = ll ; load value from DECODE
MODS into CRl CRl (15) = CRl(ll) +
DN(4) ; simulate the right shift OVL = 0:,RB12 ~:
RB12-RB14 RS = l . ; set merge indicator D2GO = 1,EOF2 = 0 ; call DECODE II MODULE ^ -CR2 = DO2 = 11 ; load the output into CR2 ~`.
20 : RBl6 EOFl(a).EOF2(0) = 0 `: ~
, RB20 ; REVOLVE process not . :;
finished yet ......
RB20,RB23, : -~ :RB24 ~ CRl(15)~ CR2(11):, RB23 .
EI - CRl - }5 ; transfer CRl to ENCODE
MODULE
ENGO - 1 ; call the ENCODE MODULE
~R 25-RB29 DlGO = l ~ ; call DECODE I MODULE -: . CRl = D~l = 10;
. EOFl = 0~ ; get next value ` ~ - ~

1 CRl(14)~-CRl(10) + DN(4) ; simulate the right ~hift OVL = 0 ,, go to RB16 R~16 EOFl.EOF2 = 0 , RB20 RB2C,RB23 RB24 C~.1(14~ ~ CR2(1~ .
EI = CRl = 14 ; write out through 14 call ENCODE
RB25-RB29 DlGO = 1 ; call DECODE I MODULE
CRl = DOl = 9, EOFl = 0 -CRl(13~ = CRl(9) + DN ; simulate the shift OVL = 0 ,RB16 RB16 EOFl.EOF2 = 0 .RB20 RB20,RB23, R~24 CRl C131 ~ CR2(11),, .
EI = CRl = 13 ; CRl sent to ENCODE MODULE
call ENCODE CENGO = 1 ~
RB25 - RB 29 set DIGO = 1 ; call DECODE I MODULE ~. .
CRl = DOl = 8, EOFl = Q ; get next value CRl(121 = CRlc8~ + DNC4) ; simulate the right shift OVL = 0 ,,RB16 : -RB16 EOFl~EOF2 = 0 , RB20 RB20, RB23, RB24 CRl(121 ~ CR2(11) , ; simulate the XOR
EI = CRl -` 12 ; CRl sent to ENCODE MODULE
ENGO `8 1 ; call ENCODE MODU~E
:RB25 - RB29 DlGO ; call DECODE I MODULE
CRl = DOl = 3, EOFl = 0 ; :
: CRl(7~ =` CRlC3) + DN~4) ; simulate the shift , ~ . 30 ~ OVL = 0 , RB16 , ~ . ` , ; - 181 - ;
~7 .

` l~Z7767 1 RBL6 EOFl.EOF2 = 0 ,', RB20 CR2(11)~ CRl(7) ; XOR `
RB21,RB22 EI = CR2 ~ 11 ; send CR2 to ENCODE MODULE
call ENCODE (ENGO=1) ; activate ENCODE MODULE
RB12-RB14 call DECODE II ; activate DECODE II MODVLE
CR2 = DO2 = 10,EOF2 = 0 ; store result in CR2 RB16 EOFl.EOF2 = O .'.
RB20 CR2(10) ~ CRl(7) ; simulate XOR -RB21, RB22 EI = CR2 = 10 ; output CR2 call ENCODE
RB12-RB14 call DECODE II ; get next value CR2 = DO2 = 9,EOF2 = 0 ;
RB16 EOFl.EOF2 = 0 RB20 CR2(9) ~ CRl(7) RB21, RB22 EI = CR2 = 9 ; output CR2 call ENCODE
RB12-RB14 call DECODE II ; get next value CR2 = D02 = 8,EOF2 = 0 ; -RB16 EOFl. EOF2 = 0 `
RB20 CR2(8) 7 CRl(7) ; XOR
RB21,RB22 EI = CR2 = 8 ; output CR2 call ENCODE ; --RB12-RB14 call DECODE II ; read next value ~-CR2 = DO2 = 3, EOF2 = 0 ; from DECODE II MODULE
RB16 EOFl.EOF2 = 0 -Ra20 CRl(7)~ CR2(3),', ; simulate XOR
RB23,RB24 EI - CRl - 7 ; output CRl ;
call ENCODE
~; RBZ5-RB29 call DECODE I
;~ 30 CRl = DOl = 1, EOFl = 0 CRl(5) = CRl(l) ~ DN(4) ; simulate shift ..
OVL = 0,~

,....
'' "
` ? ' ,~Y ~

~ 7767 ' J

1 r~B16 ~OFl.EOF2 o O ,, r~B2o cr~l t5)~ CR2(3) ; simu~ate ~OR
RB23, R~2~ EI ~ CP~l ~ 5 ; output Cl~
call ENCODE
5 RB25-RB29 call DECODE I ; read ne7:t value . CRl ~ DOl ~ O, EOFl = O
CR1~4) = CRl(O) + DN(4) ; simulate shift.
OVL ' O .', RB16 EOFl,EOF2 G O ~
RB20 CRl(4)~ C~2(3) ; simulate YOR
RB23, RB24 EI c CRl ~ 4 ; output CP~l call ENOODE
RB25, RB26, RB30 call DECODE I ; end of file reached CRl ~ -1, EOFl ~
RB16 EOFl.EOF2 - O ; revolve not done RBZO CR2(3)~ CRl( ~ OR
RB21, RB22 EI - CR2 ~ 3 ; output CR2 ~ .
call ENCODE ; ~:
20 ~B12-RB14 call DECODE II ; get next value Cr~2 - D02 ~ 1, EOF2 - O
RBl~ EOF:l.EOF2 - O
RB20 CR2(1)~ CRl(-l) ; keep outputting CR2 untiI
E0F2 3 1 .
2 RB21, RB22 EI - CR2 ~ 1 call E~CODE
RB12-RB14 .. call DECODE II ; read in next value CP~2 ~ D02 - a . RB16 EOFl.EOF2 - O ; not finished yet 3 r~20 CR2(~ C~

' " ,-, - ~ ,~, . : .. ., , ; . .

` l~Z~67 RB21,RB22 EI = CR2 = ~ ; output CR2 call ENCODE
RB12,RB13 RB15 call DECODE II ; end of file reached CR2 =-1, EOF2 = 1 RB16-RBl9 EOFl.EOF2 = 1:, set ELAST ; write out last value call ENCODE ; to MEMORY MOD
MLNl, MLN2 = MLN3 ; length of new line ; stored in DECODE I and DECODE II MODS ~
- .-At this point the revolve operation is not comple~e. Line ; ;
6 in the iso-entropicgram has been formed and stored in ~ -hy~rid coded form in the MEMORY MODULE. The decimal occurrence values of line 6 are 15, 14, 13, 12, 11, 10,

9, 8, 7, 5, 4, 3, 1, ~. This line is next revolved down one line to line 7 as follows:

RB2 call DELTA ; get next component power of 2 from DELTA MOD -DN = DELO = l,DELEND = 0 RB5,RB7-R~10 call DECODE I ; read the first value CRl = DOl = 15,EOFl CRl (16) = CRl(15) + 1 ; simulate the shift OVL = a :. .' RB12-RB14 call DECODE II ; get unshifted version . -CR2 = DO2 = 15, EOF2 = 0 ; -.
~` RB16 EOFl.EOF2~=-0 , ~
~ -.
~ 30 RB20 CRl(16) ~ CR2(15) ; XOR -. '' .~,, - :

llZ7767 1 R~2~, r~B74 EI - CP~l ~ 16 ; ~his vaJ.ue (J.6) ~lill be clip~ed by ENCODE I~IODULE
call ENOODE ~50DULE
RB25-r~B29 call D~CODE I iIODuLE ; rca~ ne~:t value CRl ~ DOl - 14, EOFl ~ O ;
CRl(15) o CRl(14) + 1 ; simulate the shift ' OVL ' O . ,' RB16 EOFl.EOE2 ~ 0 ,, RB20 CRl - CR2 - 15 ,, RB5, RB7-RB10 call DECODE I MODU~E ; read another value CRl - DOl - 13, EOFl - O ; .
CRl(14) ~ CR1~13) ~ DN(l); simulate the shi~t ~ -OVT - O .`.
RB12-RB14 call DECODE II ~DuLE ; ~ -CR2 ~ D02 ~ 14, EOF2 ~ O ;
RB16 EOFl .EOF2 ~ O .`, RB20 CRl - CR2 - 14 .......... ; XOR
~B5, RB7-P~B10 call DEC~D~ I M~DuLE
CRl - DOl - 12, EOFl - O;
C81(13) - CR1~12) + DN(l); shift OVL - O .', ,~
RB12-RB14 call DECODE II ~X~UIE ; read DECODE II ~ULE
CR2 - D02 ~ 13, EOF2 - O ;
RB16 EOFl.EOF2 - O .'. :
2 RB20 CRl - CR2 - 13 :. ; XOR
RBS~ RB7-RB10 csll DECODE I ~DuLE ; ~ :-CRl ~ DOl ~ 11, EOFl ~ O; read DECODE I ~D
: CRl(12) ~ CRl(ll) -~ DN(l); shif~ .
OVI.~ O .
~3 P~B12-RB14 call DECODE II ~DULE
. ,.

~::

C: ~.l.Z77~7 1 CR~ ~ D02 ~ 12, EOF2 ~ O
RB15 EOFl.r,OF2 ~ O
RB~O Cr~l ~ CR2 - 12 ; XOR
r~B5, r~B7-n~B9 call DECODE I ~IODULE ; read CRl ~ DOl - 10, EOFl - O
CRl(ll~ - CRl~10) -t- DN(l); shift ~ :
OVL ~ O .~.
RBl2-P~Bl~ call DECODE II r~DULE
CR2 3 D02 -- 11, EOF2 -- O
RB16 EOFl ~ EOF2 ~ O
RB20 CRl ~ CR2 ~ 11 ; XOR
RB5, RB7-RB9 call DECODE I MoDuLE
CRl Q DOl ~ 9, EOFl ~ O ; read CRl(10) -- CRl(9) ~ DN(l); sh~ft OVL - O .'.
RBl~-RB14 call DECODE II ~WLE ; read CR2 - D02 - 10, EOF2 o O ;.-RBl6 EOFl.EOF2 ~ O .'.
RB20 CRl ~ cr2 ~ 10 :. ; XO~
RB5, RB7-P~B9 call DECODE I ~LE .
CRl ~ DOl ~ 8, EOFl - O
CRl(9) ~ ~Rl(8) ~ DNtl) .-:.
OVL ~ O . ~,,, ¦ nB12-RB14 call DECODE II ~qIJLE
2S CR2 ~ D02 - 9, EOF2 ' ` :~
RB16 E~Fl.EOF2 - O .
RB20 CRl - CR2 - 9 .'. ; XOR -.
RB5, RB7-RB10 ca~1 DECODE I ~lIJLE
CRl ~ DOl a 7, EOFl Q O ; read 3 CE~1(8) ~ CRl(7) ~ DN~l) :', .
.. ' . -186- ~;

r ` 1~27~f~7 1 RI3l2-RBl4 call DECODE II MODULE
CR2 = DO2 = 8, EOF2 = 0 RBlG EOFl.EOF2 = ~ .
RB20 CRl = CR2 = 8 ; XOR
5 RB5,RB7-RB10 call DECODE I MODULE
CRl = DOl = 5, EOFl = a ; read CRl(:6) = CRl(5) + DN(l~ ; shift OVL = 0,', RB12-RB14 call DECODE II MODULE
lQ CR2 = DO2 = 7, EOF2 = 0 RB16 EOFl.EOF2 = a RB20 CR2(7~ CR1~61~:
RB21-RB22 EI = CR2 = 7 ; send CR2 to ENCODE MODULE
call ENCODE MODULE ; output it RBI2-RB14 call DECODE II MODULE ; read DECODE II MODULE again CR2 = DO2 = 5, EOF2 = a RB16 EOFl.EOF2 = 0 .
RB20 CR1(61~ CR2~5~.
RB23-RB24 EI = CR1 = 6 ; send CRl to ENCODE MODULE
2~ call ENCODE MODULE
RB25-RB2~ call DECODE I MODULE ; read CRl = DOl = 4, EOFl = a ; -CRl(5~ - CR1(4l + DN(l~ ; shift -.
OVL = 0 .
RB16 EOF~.EOF2 = 0.', . .
RB20 CRl = CR2 - 5 ~ ; XOR
RB5,RB7-RB10 call DECODE I MODULE
CRl = DOl ~ 3, EOFl = O ; read CR1~41 = CR1~3~ + DN~l~
OVL = 0.'.

~ .

RB12-RB14 call DECOD~ II MOD
CR2 = DO2 = 4, EOF2 = 0 RB16 EOFl.EOF2 - 0 RB20 CRl = CR2 = 4............ ; XOR
RB5,RB7-RB9 call DECODE I MODULE ; read CRl = DOl = l,EOFl = 0 CRl(2) = CRl(l) + DN(l) - ~ -OVL = 0 RB12-RB14 call DECODE II MODULE
CR2 = DO2 = 3, EOF2 = 0 RB16 EOF:l.EOF2 = 0 .
RB20 CR2(3)~ CRl(2);. ; XOR - ~
RB21-RB22 EI = CR2 = 3 ; output CR2 -: :
call ENCODE MODULE . ; ~
RB12-RB15 call DECODE II MODULE ; read DECODE II MODULE :. .;.
again .:.^
CR2 = DO2 = 1, EOF2 = 0 ; -- .
RB16 EOFl.EOF2 = 0 .. ~ .
RB20 CRl(2)~ CR2(1) ; XOR ~: .
RB23-RB24 EI = CRl = 2 ; output CRl ~ .
call ENCODE MODUI.E ; ;~.
RB25-RB29 call DECODE I MODULE .
CRl = DOl = 0, EOFl = 0 ; read DECODE I MODULE
CRl(l) = CR1(~) + DN(l) ; shift ..
OVL = 0 ~
RB16 EOFl~EOF2 - 0 :, RB20 CRl = CR2 = 1 .', ; XOR
RB5,RB7,RBll call DECODE I MODULE ; read CRl = -1, EOFl = 1 ; EOF reached DECODE I -MODULE .
RB12-RB14 call DECODE II MODULE
CR2 = DO2 = 0, EOF2 = 0 ; :

~ , ~iZ7767 1 RB16 EO~l.EOF2 - 0 :.
RB20 CR2(~) ~ CR1(-11,', ; XOR
RB21-RB22 EI = CR2 = ~ ; ou~put CR2 call ENCODE MODULE
RB12, RB13, RB15 call DECODE II MODULE
CR2 = -1 EOF2 = O ; EOF reached DECODE II MDDULE
RB16 EOFl.EOF2 RB17-RBl9 set ELAST ; output last value from ENCODE MODULE ~.
call ENCODE MODULE
MLN1, MLN2 = MLN3 : reset lengths RB2-RB4 call DELTA MODULE ; get next DELTA value DN = 0 DELEND = 1 -reset DECODE I and II, .
ENCODE MODULES
DELEND = 1 . .
RB6 RS = 1 . EXIT .-Upon EXIT the MEMORY MODULE contains line 7 of the iso- ~:
entropicgram of Table 4-~ which in absolute decimal occurrence values is 7, 6, 3, 2, O.

' ' . .
:

,:

30~ ~

- 189. -:: ~

~. A _ ' ~ 112'77t;~

1 VI I I~EVOLVER
The portion of tlle DPM SYSTEM including the MEMORY, E~ICODE,DECODE I and II, DELTA, and REVOLVE MODULES forms an iso-entropicgram revolver. Fig. 19 is a block diagram of the iso-entropicgram revolver.
The iso-entropicgram revolver revolves a received binary coded input line signal to a new line signal in the iso~
entropicgram for the input line. The MEMORY MODULE forms ~-a means for storing a received input line. As 2xplained above, the MINI COMPUTER with user program causes ~n event occurrence vector, or some other binary coded number, to be -stored into an area of the MEMORY MODUT ~ . Though not -;
essential to the present invention, in the disclosed -embodiment the number is stored in the MEMORY MO~ULE in . ., .. :

15 hybrid code. The number which forms the input line comprises -a binary coded signal representing one or more actual occurrence values from a group of decreasing monotonically ordered possible occurrence values. The actual occurrence ~ -values correspond to what has been referred to as event-times and the possible occurrence values are all of the event-times which are within the width of tle iso-entropicgram.
The DELTA MODULE forms a means for forming a signal indicating the number of lines the received input line signal i8 to be revolved.

The REVOLVE MODV~E forms a new line -~ignal ~orming means and includes means such as the CRl and CR2 registers, the DN
register, the RDS2 selection circuit, the ALU, and the control counter depicted in Fig. 17 which is responsive to the number of lines signal indication provided in the DELO reg~ster by 3 the DELTA MODULE and the input line signai stored in the MEMORY

, l~Z77t;7 MODUL~ for forming a binary coded signal corresponding to the received input line shifted relative to itself by the number of possible occurrence values identified by the number of lines indication signal.
The new line signal forming means also includes means such as the CRl, CR2 and DN registers, the RDS3 selection circuit, the ALU and the control counter of the REVOLVE MODULE, the ENCODE, DECODE I and II and the MEMORY MODULES for exclusive ORing (XORing) the occurrence values represented -by the received input line signal and the shifted input line signal for forming a resultant signal representing one or more ~ ;
occurrence values in monotonical value order.
By way of example, the resultant signal is coupled through the RDS4 selection circuit to register EI of the ENCODE MODULE
which then converts the absolute coded value of the occurrence values in the result back to hybrid code for storage in the MEMORY MODULE. The new line signal forming means also includes means such as the ALU and its OVL and OVL output circuits and the related portions of the REVOLVE MODULE
which are operative during RB5, RB8, RB9, RB10, RB25, RB27, RB28 and RB29 for eliminating the shifted occurrence values from the resultant series of occurrence values which are not within the group of possible occurrence values making up the width of the iso-entropicgram.
According to a preferred embodiment of the invention, the DELTA MODULE receives a signal representing the total number of lines to be revolved and contains internal means for converting such representation into one or more signa~ representing one or mbre of its component powers of ~. --:~ ' ' , .' ~ :

(~
1~27767 1 Also prcferably, the means for shiftin~ includQs means such a~s the ~LU, the CRl, CR2 and DN registers and the DECODE I and II MODULES which are operative during RB5, R38, RB9, Rslo and RB25-RB28, for responding to a component power S of 2 signal, received as input to the DN register for forming a shifted line signal corresponding to one of the input line signals. The occurrence values represented by the shifted --line signal represent the occurrence values of the line - -signal received as input shifted by the number of possible ;~
occurrence values designated by the component power of 2 signals stored in the DN register. The exclusive ORing means includes means such as the CRl and CR2 registers and the ALU operative during such flow boxes as RB20, RB21, ;
RB5 and RB23 for exclusive ORing the occurrence values represented by a line signal received as input by the shifting means and the corresponding shifted line signal for forming a corresponding resultant l~ne signal.
In this connection it will be noted that the unshifted and shifted values successively stored in the CRl and CR2 registers are ordered into monotonical value order and those values which axe found to be equal ~indicated by a true signal at the E output of the ALU) are dropped or eliminated.
In order to revolve from one line Across successive lines in an iso-entropicgram, the switching matrix ~yet to be des-cribed) forms a means for coupling the input line signal and the resultant line signal, formed as a result of the exclusive ORing, as an inpu~ to the means for shifting described ~
above. Additionally, the connection from the DELO register -3 in the DELTA MODULE to the DN register in the REVOLVE MODULE
and the load control for the DN register forms a means for (~ ~
~Z7767 1 couplin-~, as input, to th~ means for shifting one o~ the com~onent powers of 2 signals fer operation on each one of the line signals which are received as input by the shifting means.
Preferably, the means for shifting includes the ALU and the RDS3 selection circuit of the REVOLVE MODULE for combin-ing the value of each component power of 2 signal stored -in the DN register with each actual occurrence value stored in the CRl register. :
According to a preferred embodiment of the invention, the input line signals are stored in a composite code such as the hybrid code and first and second decoders such as the DECODE
I and II MODULES are operable independently for separately providing an individual actual occurrence value signal repre- -sentative of each occurrence value of the input line signal.
The decoders each provide the actual occurrence value signals in the order of the values in the input line signal.
Also preferably, the resultant signals are encoded by means such as the ENCODE MO~ULE from the actual occurrence value code back to the composite code before the result i~
stored in the MEMORY MODU~E.

. .

:.

(~
~ 1~27767 1 VIII. SEE~ MOD ~.E
. G~neral D~crip~ion The SEED MODULE takes an occurrence vector and locates the 3hortes~ line of the occurrence vector in its iso-entropic~ram.
The shortest line is referred to as the seed line, T~lough the seed line can be located by revolving the occurrence vector line by line through i~s iso-entropicgram, noting the length of each line and lool;ing for the shortest line, such an approach would be time consu~ing. Therefore it is desirable to m~ni~ize the seed finding time in data processing equipment.
Additionally, as discussed above, information is actually stored in memory in encoded or hybrid coded form which further reduces the size of the stored information.
Generally speaking then the disclosed embod$~.nent of the invention locates seeds as follows, An event occurrence vector, to be converted to 8eed form~ is ~tored in the ME~O~Y MODULE and i8 pre3ented to a seed finding machine which include~ the sFEn, ENCODE, DECODE I and II, DELTA and 20 REVOLVE ~DDVLES.
The revolves, including the E~CODE, DECODE I and II, DELTA
and REVOLVE MODULES~ revolve the input line down through the lines of the iso-entropic~ram and a~ thi~ is done each line i~ presented to the ENCODE MODULE ~or encoding to hybrid orm, 2 The physical length o~ each line i9 noted and the encoded or hybrid coded line thatis physically shortest in len~th is the one selected as the seed line.
According to a preerred embodiment of the invention, seed findin~ employs the s~n MODULE which receive~ as 3 input, primarily, an event occurrence vector signal formin~ an . -19~- . .

(~
llZ7767 1 input line 9 ignal o~ an iso-en~ropic~ram and a si~nal ~hat represents tL~e iso-entl~oplcgram ~idttl for sucll input line. The even~ occurrence vector or input Line siOnal represents actual occurrence values out of a group of possible occurrence values arran~ed in a decreasing incre~ental value order from a large~t to à smallest val~e.
The SEED ~IODULE computes the difference between the largest two occurrence values represented by the input line and computes the difference between ~he value represented by the width signal and ~ e largest occurrence value in the input line.
The largest of the two differences indicates the number of lines to be revolved in the ~so-entropicgram. The S~ED I~DDULE
calls the REVOLVE MODULE, cauQing it to revolve the input line signal down the number of lines indicated by the lar~est difference. The new line sign31 (in hybrid code) is then checlced agains~ the original input line signal and the shorter is lcept a3 the possible seed line. The above procedure i9 then repeated using the possible seed -~
line signal as the inL~ut line signal. The ne~ly revolved line signal is compared against the retained possible seed line signal and the shorter is again retained as thè ~
possible shortest line. This operation i~ repeated until ~ -the REVOLVE ~DULE has revolved over all possible line~
in the iso-entropicgram. At t~t time,the possible seed line i8 retained in the E~CODE ~DULE as the seed line.
The right hand side of Table 4-B indica~es an example of this implementation of the SEED ~XDULE.
. .

~Z77~i7 1 n . comPonen~: s Refer now to Fi~s. 20 and 21. Tlle SEED MODULE has the following input registers, each containlng ei~ht flip 1Ops for storing 8 binary coded bits: OMOC, SDN, SLI~, SLN, S~
S~LI~ TO, Tl and T3. Additionally, a two bit, two flip flop register OAR is provided. The registers ONOC, SLINE, S~, S~I, TO and Tl are formed of register type SN74100 disclosed at page 259 of the above TTL book and the registers S2~W and , '~
SDN are formed of registers of type SN7~116 disclosed at page 261 of the above TTL book where a true signal at the L
input caus~s the 8 bits of information at the upper input ,,, to be stored therein, Additio~ '.ly, the s~nw and SDN
registers are responsive to a true signal at tbe CLR inpu~
for resetting or clearin~ to O. The other registers in the 15 system are characterized in that all registers in t~ SEED '- ' MODULE are o~ the type that the output signal follows or '-reproduces the information input signals during the presence - ', of a true clock signal at the clock or load ~) input. ''' The register retains at its output and stores the signals 2 being applied at its information input when the true signal at the clock or load input terminates. The T3 ' ' register is formed of an SN4174 type register disclosed in the above TTL book where the leading ed~e or true excursion of the pulse at L loads and retains the then 2 existing information input signals even though the in~ormation input signals chan~e before the true p~tlse at L terminates. This is done since during the true signal at P2 it i9 only desired to strobe the initial signals from DOl into register T3. Tlle regi~ter O~R is formed of ~o flip 1Ops of the same ,type as the rèset of the flip ~ . '.

' ? ~1~7767 ~ ) 1 flops ~ ose lower left side cl.ock inpu~ 19 connec~:ed to design~ed L input and wllose inputs are connec~ed to upper le~t side information inputs.
The SEED ~IODUI.T~ also has ~Lip f1ops SCE, CNG, S~ and a control counter 513 having flip f1ops PO to P10, Each of these 1ip flops are of the same type SN7~74 disclosed above under Conventions and Co~ponents Used in the Figures.
Selection circuits SDSl-SDS6 are provided for 8ating any one of the infonmation input signal9 indicated along the upper side of each selection circuit to the output responsive to a true signal spplied to one of the control inputs at the side of the selection circuits. These selection circuits are o~ the sa~e type as that disclosed above in the section Conventions and Components Used In the Figures.
An arithmetic unit ALU i8 provided for adding, subtrac~ing and comparing the information ~ignals applied at the two inormation inputs indicated along the upper side of the ALU. The arithmetic unit ALU i8 of the same type a~ that di~closed above in the section Conventions and Components Used in the Figures. An OR gate 516 has its inputs connected to the G and E output3 of the ~LU and forms a true signal at the GE output when a true 8ignal i9 formed in either the a or E output. ~n addition, the SEED ~DULE has conventlonal OR gating circults 516, 517 and 518 and a conventional ~ND
gating circuit 520. ~dditionally, the SEED ~DULE has logical gating circuits which form true and alse signals enabl~ng the operation of many of the circuits sho~n in - -the SE$D ~DULE. These gatiDO circult~ are indicated 3 by logical equation ~or simplicity. ~ logical signal ;:

~77~7 I inver~r 52G is connec~ecl bet~een the clocl; C~l output of ~D ~te 520 ~nd tlle inpu~ ~o tllc CL~ ou~put ~or Eorm~n~
pulst!s betw~en the CLIC pul!es.
The SEED ~ODULE also has one-sho~ multi-v~brators SI~GO
and S~E~ as well as a clocl; 512. The clock 512 i~ a source of re~ularly recurrin~ true clock pulses as indicated, The one-shot multi-vibrators re responsive to a true signal ~ -applied at the input indica~ed along the left hand side --for triggering to a L state where a true signal i9 ormed at an unprimed output. The one-shots remain in a 1 state for a time ~n~erval equal to that be~ween the beginn~ng of two successive clock pulses from the clock 512 and then returns to an 0.
The SEED MODULE has three sets of switches 526, 528 and 530. The switches 526, 528 and 530 are mechanical or electronic switches which represent, respectively, the decimal values 1, 2 and 3 in binary coded orm as 01, 10 and 11, ~espect~vely. ~ -Table 16 lists the primary registers, flip flops and one-shots and identifies the~r primary prpose.
Similar to other modules, the control inpts and outputs are indicated along the right hand side of Flg. 20 an~ the information inputs and outputs are indicated by large solid lines ~180 along the right hand side.
. '.

2S C. Detailed DescriPtion Consider now the detail9 o~ organization o~ the SEED
~: ~XDULE, ~aklng particular reference to the schematic and bloclc diagram of Figs. 20 and 21, and tbe s~Fn ~DULE flow dia~ram of Fig. 2~. The flow diagram contains blocks ~; 30 indicat~ng the sequence of operation The symbols S~l ~ .
,., ", -19~- .
,. , .

~-~ r) i~z7767 1 throu~ll snl8, shown next to tllC bloclcs, are used ~o identlfy the ~)o~:es in the ~lo~ dl~ram, The symbols desi~nst~n~ the various ~lip flops o the control counter 513 ~re also shown in parentheses ad~acent the various bloclcs to help relate the operation indicated in each box of the flow with the state of the control counte. 513.
Initially, the OR gates 516 and 517 receive true signals from the MDNIT output of the MINI COMPUTER which causes flip .~:~
flops PO-P10 and SCE to be reset te 0 states. Subsequent :.
true signals formed at SME~D by one-shot S~ND cause OR gate ~
517 to reset fllp flops PO-P10 to 0. ~:
Table 11 shows the primary inputs to the ~EED MODULE as well -as the inputs to the ENCODE, DECODE I and II, DELIA and ~EVOLV%
MODULES making up the seed finder. The initial inpu~s :
come principally from the IPRF ~ig.52 ) and the ~MORY MDDULE. .
Accordingly, the MINI CaMPVIER, in th~ manner described herein-after, .~irst loads the IPRF and the ME~RY MODULE with the ;.
required initial input information. To this end the MINI
C~MPUTER initially stores an event occurrence vector, in -20 hybrid code, into MEMORY MODULE area 1. This event occurrence vector i8 the input line for an iso-entropicgram and at the beginning of the operation of the seed finder forms what i8 currently assumed to be the seed linc.
To be explained in more detail, the lnput or current 2S line may not necessarily be line O o lts iso-entropicgram :.
and accordingly the number of the input line as well as the width value for the iso-entropicgram are initially stored by the ~INI COMPUTER into registers LINE ~ and HW of the IPRF ~Fig.52 ). The length o~ the input line is variable 3 and hence a length value specif~ing the number o~ words .:
.' '.

~ 199 . ~` ` .
.,'; ., ~
, ~
"`y~ ?~ .~

l~Z7767 1 in this ~nput Line i9 stored ~n re~ister LINE # of the IPRF.
~ fter the IPRF and ~RY ~DULE area l ~re loaded, the SEED ~DULE is called by the ~IINI COMPUTER or tl~e CHAN OE MCDULE
by formin~ sign21s a~ the USER and C~I2 outputs, respectively A true signal at either of these outputs causes the OR gate 518 tQ apply a true signal to the one-shot SMGO, triggering it to a 1 state causing a true signal at the SMGO output, The true signal at the SMGO output sets the SCE flip flop to a 1 state. The output from clock suspension logic 522

10 is initially true. Therefore, the true signal at the SCE -output of the S OE flip flop enables the AND gate 520 to couple clock pulses from the clock 512 to the CLK output, which in turn causes an ~nverter 526 to form pulses at the CLK output. The 0 state of the flip flops P0 to P10 causes true signals at the ~ outputs, thereby cau~ing the flip flop P0 to be reset to an 0 state at the following pulse at CLK, thereby causing SBl of the SEED MODULE flow to ~e entered.
During SBl of the flow during the true signal at P0 output, the input parameters for the SEED ~DULE are stored into their proper registers. During the true signal at the PO output of the SEED MODULE, the initial input parameters for SEED MODULE are al8o enabled and clocked into their proper registers. Additionally, the SWITCH M~TRIX i8 set 2 80 that the REVOLVE ~IODULE when called for the irst time will cause the DECODE I and II MODULES to read the input -~
line from the ~RY MODULE area 1 and cause the ENCODE
MODULE to write the revolved or new line into the MEMORY
MODULE area 2.
\ 3 It should be noted that the CHANOE MODULE forms a true (~ f) - i~Z7 767 1 siznal a~ tile Cll4 output, thcreby setting the CNG 1ip Lop to a 1 s~at~ only whcn the CI~NGE MODULE i9 the calling module. ~e~errin~ ~o the rigllt hand side o Fig. 20, true signals at- the PO, CNG and ~ER outputs cause true si~nals at the S~l, S~I2 and S~13 outputs to the SI~IT~I~TRLY and also cause ~nput para~eters to ~e loaded into the ENCODE, DECoDE I and II, and DELTA ~ULES in the manner and from the sources discussed above for each of these modules.
A true signal is only formed at the outputs SMl, SM2 and SM3 when the MINI CO~UTER i9 ~he calling module.
Thus, assuming that the ~IMI COMPUTER i9 the calling module, true signal~ are formed at the SMl, SM2 and SM3 outputs.
The true signal at SMl causeg flip flops Sll, S22 and S31 to be set to 1 in the SWIrCH MATRIX. The true s~gnal at SM2 causes the length value ~Nl in IPRF to be gated to registers MLNl and MLN2 of the DECODE I and II ~DULES
and the pulse at SM3 actually causes the length value to be loaded into the regi~ters MLNl and MLN2 and into register -EHW of the ENOODE 2~0DULE. Additionally, the true signal ~;
at output PO resets the SMB flip flop to an 0 state. The true signals at PO, ~ (CHAN OE MODULE i9 not the calling ~-module) cause the SDS6 selection matrix to couple the line -number in the LINE # register of the IPRF to the information input of the SMLl register. Note that if the CHAN OE MODULE
were the calling module, the true signals at CNG and PO would cause the switchlng circuit SDS6 to couple the line numSar rom the C.INE register of the CHANGE MODULE to the register SMLl. During the true signal at the PO output, the pulse at ~ cau3e~ the line number from SDS6 to be stored into register 3 S~l and causes the S2~W register to store the i~o-entropicgram .. . . .
, '~:

~7 7 6 7 1 width s~nal rom th Il~ re~ister o the Irr~F ~i~.52 ).
Tllus, the SMLI rc~ister contains th~ line number of the input line (stored in ~IIORY MODULE area 1) and the S~IW
register contains the iso-entropicgram width value.
The true signa1 at PO causes flip flop Pl to be set to a 1 state. There~ore, also during SBl of the SEED ~IODULE flo~, the true signal at the Pl output causes the selection circuit SDS7 to couple the length value from register MINl of the ~ -DECODE I ~DULE to the information input of re~ister SLN.
Additionally, the true signal at Pl causes the SDN register to be reset or cleared to O and causes the SMB flip flop to be set to a 1 state. The 1 state of the SMB flip flop causes a true si$nal at the ~ output to be removed and thereby remove the true sign~l at the S~I10 output. As explained above, the signal ~M10 goes to the DECODE I ~DULE, and when false, inhibits the count down of the phys~cal length of the input line in MLNl. The SEED MODULE is about to become operative during SB2 through SB5 for causing the DECODE I MODULE to do a read on the input line from the MEMnRY MODULE only for the purpose of reading the largest two occurrence values of the input line and the count down of MLNl is inhibited during this operation because the DEOODE I ~IODULE will later be called to go back to the `
beginning of the same input line to again read the same 2S occurrence values, At this point in tlme~ the input line is retained as the current possible seed line since this i8 the only line considered to this point. The register SLINE stores the number of the current possible seed line. Accordingly, the 3 true si~nal at the Pl output causes the SDS5 selection c' ~
~Z7767 1 circuit to couple the input line nu~lber rom re~ister SM~.l to the inormation inpu~ of register SL~ and the tru~
signal at the ~ output causes the line number to be loaded into register SLINE.
Additionally, it i~ necessary to prevent the SWITCH ~TRIX
fro~ allowing the ~MORY MODULE area l containin~ the input line to be ove~ritten since this line is to be retained as the current possible seed line. In order to insure that the SWITCH M~TRIX retains the input line in MEM~RY MODULE area l, the true signal at the Pl output causes the SMS flip flop to be set to a l state which in turn causes a true signal to be formed at the SM5 output of the S D MODULE. The SM5 output in turn is connected to the SWIT OE M~TRIX and a true signal at SM~ n con~unction with RM12 from the --REVOLVE MODULE causes the SWITCH ~TRIX to prevent overwriting of ME~RY MODULE area l. ~
During SBl, SB2 of the SEED MODULE flow i8 entered. -Durin~ SB2, the true signal at the Pl and ~g outputs causes a true signal at the S~I6 output which in turn calls the DEOODE I MODULE by setting the DlGO one-shot to a l state.
m e DECODE I MODULE then commences its operation of obtaining the largegt occurrence value from the input line in MEMORY
MODULE area l. The true ~ignals at the outputs Pl, ~1~ and ~nFE~n- t~rom the DECODE I MCnULEj causes SM6 to be true and the clock suspen~ion logic 522 removes the true signal at thc corresponding input of gate 520 and stops clock pulses -- -- from being ~rmed at the CLX a~d CLK outputs, thereby ~: suspend~ng operat~on of the SEED ~ODULE while the DECODE I
MCDULE completes its operation and provides a decoded occurren~e value.
, , -'.`:'`,'"'' -203- ~
,. ..

(-' o 1~27 76 7 1 Ater the DECOn~ SODI~.E provid~s the l~rgest occurrence value from the input line stored in ~IIORY ~IODULE area l, the true signaL of Dll~ s removed, thereby c~u9 ing the cloctc suspension lo~ic 522 to again apply a true si~nal at the corJasponding input of gate 522 enabling pulses to be formed at the CLK and CLi~ outputs.
The true signal at the Pl output, together with the true signal at the E~l output, causes the flip flop P2 to be set to a 1 state. The true s~gnal thus formed at the P2 output in coincidence ~ith a true clock signal at output ~1~ causes this largest occurrence value from regl~ter DOl of the DECODE
I ~DULE to be stored lnto the T3 register. Note that should a true signal be formed at the EOFl output, a false signal is formed at the E~I output and, hence, the flip flop P10 would be 8et to a l state rather than the P2 flip flop.
If EOFl is set, there is no meaningful output rom DECODE I
MODULE. As a result, the output from the DECODE I M~DULE
would not have been stored lnto register T3. Hence, state SB16 of the SEED MDDULE flow would be entered from SB3, During SB4 of the flow, the true signal at the P2 output also causes the SDSl and SDS2 selection circuits to couple the iso-entropicgram width value from reglster S~W and the largest occurrence value from the DOl register of the DE~ODE I MODULE to the inputs of the ALU and causes the A~U to ~ubtract the large~t occurrence value rom the width value. The resultant difference formed st the OP
output of the ALU is coupled to the in~ormation input of register Tl by the SDS4 selection circuit, under control of output P2, and the true signal at the P2 output causes the 3 difference signal formed nt tle OP output to bc stored into -20~-f~ ~
~,~,Z7767 l reg~ster Tl at tlle follo~ing puLse ~t CLK. Th~s~ ollowin~
SB4 o the S~D ~OnULE flow, tlle large~t o-curr~nce value is con~ained in regi~ter T3 and the register Tl contain~
the di~ference bet~een the iso-entropicgram width value and the largest occurrence value of the input line.
SB5 of the SEED ~IODULE flow is then entered and true signals are formed at the outputs P2 and CLIC thereby forming a true signal at the SM6 output which again calls the DEOOD~ DULE by setting DlGO to a L state. The 10 MARl register of the DECODE I MDDULE has now been counted ~-up by 1 address, thereby fonming the address o~ the next to the largest occurrence value of the input line contained in MEMORY M~DULE area l. Thus, the DECODE I MODULE now reads out the next to the largest occurrence value and stores it in its DOl regi~ter. I~ile this takes place, the true signals at the P2, ~g and Dl~ND outputJ again cause the ~-clock suspension logic 522 to disable the AND gate 520 thereby terminating the pulse at CLK, When the DECODE I ~-MODULE has completed its operat~on thereby providing the next to the largest occurrence value in its register DOl, the true signal is removed at the ~IRER~ output thereby causing the clock suspension logic 522 to enable the AND
gate 520 to start causing pulses at CLK and ~g.
The true signal at the P2 and E~FI output al80 causes the ~lip flop P3 to be set to a 1 atate at the following pulse at CLK. If EOFl is set, then flip flop PlO is set to l.
The signal at the P3 output causes the SDSl and SDS2 selection circuits to couple the largest occurrence value in register T3 -~
and the next to the largest occu rence value ~rPm ~e~ister D01 3 ~ECODE I ~DDULE) to the in~ormation inpu~ of the ALU and . '"''''"':
.,: ..

(~ ~
~ 7767 1 causes tl~e ALU ~o subtrac~ tho ne~:t to ~he l~r~est occurrence v~lue from ~he l~rgest occurrence v~lue ~nd forma correspondin~
di~ferenc~ sivn~l at the OP output.
SB7 of the SEED I~IODULE flow is now entered, The true signal at the outputs P3 and Z~ causes the register TO to store the difference signal. Thus, at this point in time, the register TO contains the difference between the largest two occurrence values o~ the input line, and the reg~ster Tl contain~ the difference signal representing tl-e difference be~?een the width value and ~he largest occurrence value.
Again, note that should the DECODE ; ~DULE be at the -end of a fiIe and a true ~ignal be formed at the EOFl output, a true signal is not formed at the E~SI output.
He;lce, the flip flop P3 would not have been set and instead the flip ~lop P10 would have been set to a 1 state, causing SD16 of the SEED MWDULE flow to be entered.
Assume now that true ~ignals are formed at the output P3.
The P4 flip flop i9 set to a 1 state causing SB8 of the SEED
MODULE flow to be entered. During SBS, a true signal i9 formed at the P4 output. The true signal at the P4 output causes the difference bet~een the largest two occurrence values of the input line, contained in register TO, and the difference between the width value and the largest occurrence value, contain~d in register Tl, to be coupled 2 through selection circuits SDSl and SDS2, respectively~ tc the information inputs of ALU and causes the ALU to compare the two difference va,lues. Note eareully that should the diference between the largest two occurrence values contained ~ -in register Tl be greater) a true signal i~ formed at the G
3 output o ~L~U and the contents of register Tl remain unchanged.
", ~ -206-,~ 7~'~67 l However, sllould ~he difEerenc~ b~ een ~llc widtll vnlue and the lar~s~ occurrence valu~ in re~is~er To be lar~er, a true si~nal is formed at tLIe L output of ~LU. A true ~i~nal at the P4 and L outputs causes tl~e selection circui~ sDS4 to couple the content o~ the reg~ster TO to t1Ie infsrmation input of register Tl and the true signal3 at the P4, L and ~-~-K autputs cause the content of register TO to be stored -into register Tl. Thus, it now can be seen that register Tl stores the larger of the diference between ~he largest two lO occurrence values of the input line and the difference -~
between the iso-entropicgram width value ~nd th¢ largest ~-occurrence value. Note ~hat the larger of the difference values now contained in Tl i~ the number of iso-entropicgra~ -lines by which the input line stored in the ME~RY ~IODULE
is now to be revolved.
The true signal at the P4 output cause~ the P5 flip flop to be set to a 1 state at the following pulse at CLIC, thereby causing the SB9 of the SEED ~DULE ~low to be entered. ~-The regi~ter SDN is used to accumulate and keep track of the total number of lso-entropicgram lines revolved by the REVOLVE ~DULE. Thus, during SB9, the number of lines next to be revolved (the l~rgest difference s~gnal) contained ln register Tl i9 added to the content o~ re~ister SDN. The first time through SB9 the register SDN con~ains O. To be ~;
2S explained in more detail, durlng SBlO the total lines revolved contained in register SDN i9 compared with the iso-entropicgra~ -width value contained in register SMHW to determine when the number of lines revolved e~ceeds the width value for the iso-entropicgram.
~3 To thl~ end, the true signal at the P5 output causes . .'.'.

-"-\
1~277 67 1 selection circui~s SDSl and SDS2 to co~ple ~he conten~ o registers SDN and Tl to the in~ormation inputs of the ALU, and causes tl~e ALU to add the values to~e~her and orm a sum.
If no overflow occurs, OVL is true and the logic P5.CLK.~VL
becomes true and stores the sum into register SDN. Note that if an overflow occurs, the signal at ~9~ will be false, preventing the result at the output of OP bein~ stored baclc into SDN. Also if overflow occursj it i~ necessary to clear the width value in register S~W to 0 90 that the subsequent compare during P7 will cause a GE condition ~hich will in turn cause P10 to be set to 1 and terminate the operation. It is de~red to terminate because if overflow occurs, an ~tte~pt i~ being made to revolve to a line wh~ch i8 not within the iso-entropicgram for the input line.
lS The true ~ignal at the P~ output causes the flip flop P6 to be set to a 1 state at the following pulse at CLK.
The true signal at the P6 output causes the SDSl and SDS2 selection circuits to couple the line number value containe~
in register S~l and the number of ltnes to be revolved value contained in register Tl to the inr'ormation inputs of the ALU and cau~es the ALU to add the values together and ~orm ~ -the sum at the OP output. The true ~ignals at the outputs P6 and ~g cause the SDS6 selection circuit to couple the sum to the inormation input o SMLl and to store the sum into register SMLl. Thus, register SMLl now contains the number of lines revolved relative to the number of the input line. Note that should over~low have occurred, the sign bit at the output o~ ALU is disregarded because this amounts to an addition~l module of the iso-en~ropicgr~m length.
` 3 . ~ ~

11~7'^~67 The true sign~l at the P6 output causes the P7 flip flop to be set to a 1 state responsive to the following pulse at CLK and causes SB10 of the SEED MODULE flow to be entered.
During SB10, the number Qf lines revolved value is compared with the width value as described in connection with SB9.
If the number of lines revolved value contained in register SDN is greater than the iso-entropicgram width value contained in register SMHW, the SEED MODULE goes to SB16-18 following which the operation of the SEED MODULE exits. An exit is taken at this point in the operation since the REVOLVE MODULE
will have revolved across all lines in the iso-entropicgram.
If the number of lines revolved value contained in register SDN is less than the iso-entropicgram width value contained in register SMHW, meaning that the SEED MODULE has not revolved across all lines of the iso-entropicgram, SBll ~ ;
through SB14 of the SEED MODULE flow are entered.
Assume during SB10 that the number of lines revolved value , ;
contained in register SDN is less than the width value l~
contained in register SMHW, the true signal at the P7 output causes the SDSl and SDS2 selection circuits to couple the number-of lines revolved value ~register SDN) and the ,-width value (register SMHW) to the information inputs of the ~ ;
ALU and causes the ALU to compare the two values forming a true signal at the L output. The true signal at the L output of the ALU in coincidence with the true signal at the P7 output causes the P8 flip flop to be set to a 1 state at the following CLK pulse and SBll of the SEED MODULE flow is entered.
During SBll, the number of lines to be revolved value contained in register Tl is sent to the DELTA MODULE which ¦ - -in turn forms the component powers of 2 of ~his value :: . ,'-,'''`., . ' $ ``',' 1~27767 b~ginning with the largest component power of 2 as discussed above in connection with the DELTA MODULE. To this en~, the true signal at the P8 output causes a true signal at the SM7 output which in turn causes the DELS selection circuit in the DELTA MODULE to couple the largest difference value from register Tl to the information input of the register 302 in DELI. A true signal at the P~i output of the SEED MODULE
in coincidence with the true signal at the CLX output causes a true signal at the SM8 output which in turn causes the ; -`
load circuitry of register 302 in DELI to store the larger difference value from register Tl into register 302 of DELI.
SB12 of the SEED MODULE is now entered. The true signals at the outputs P8 and CLK also cause a true signal at the SM9 output which in turn calls the REVOLVE MODULE by setting the REVGO one-shot to a 1 state. The REVOLVE MODULE in turn calls the DELTA MODULE as discussed above and the REVOLVE
MODULE and DELTA MODULE in conjunction with the DECODE I, DECODE II and ENCODE MODULES revolve the input line, contained in MEMORY MODULE area 1, down the number of lines indicated by the largest difference value sent to the DELTA
MODULE. During this operation, the true signal at the P8 and REVEND output causes the clock suspension logic 522 to again disable gate 520 and thereby suspend the operation of the SEED MODULE~ After the designated number of lines have been revolved by the REVOLVE MODULE, the true signal is removed at the REVEND output, thereby causing the clock suspension logic 522 to again enable gate 520, thereby enabling a clock pulse to again be formed at the CLK and CLK outputs in the SEED MODULE. The followin~ pulse at CLK
causes the flip flop P9 to be set to a 1 state, thereby causing ':

~ - 210 -~ , . .

SB13 o the S~ED MODUL~ flow to be entered. The true s.ignal at the P9 output of the control counter 513 in the SEED MODULE
causes the SDSl and SDS2 selection circuits to couple the length value (number of words in the hybrid coded line written into the MEMORY MODULE by the ENCODE MODULE) contained in register MLN3 of the ENCODEM~DULE to be gated to one input of the ALU and causes the length of the original input line which length value is contained in register SLN to be gated to the other input of ALU and causing the ALU to compare the two values. If the length of the new line as indicated by register MLN3 is smaller than the current seed line as indicated by register SLN, the ALU forms a true signal at the L output indicating that MLN3 is less. This causes SB15 of the SEED MODULE flow to be entered where the content of register MLN3(which is smaller) is stored into the SLN -register. If, on the other hand, the length value for the new line (in register MLN3) is equal to or greater than the length value of the original input line (in register SLN), true signals are formed at the G or E outputs of the ALU, causing the OR gate 516 to form a true signal at the GE output.
This causes SB14 of the SEED MODULE flow to be entered.
In this manner, the smallest of the length values for the ;
original input (current possible seed) line (register SLN) or for the new line (register SLN3) is retained in register SLN.
Consider now the actual operation in this regard. Assume -~
that the length of the new seed line is smaller and hence a true signal is formed at the L output of the ALU during the true signal at P9. The SDS7 selection circuit couples the length value from register MLN3 of the ENCODE MODULE to the information input of register SLN and the following pulse at ~lZ7767 CLIC in coincidence with the true signals at P9 and L
cause the load circuit of register SLN to store the length value from register MLN3 into register SLN. Additionally, since the new line is now shorter, it is necessary to store the line number of the new line into register SLINE.
Accordingly, the true signal at P9 causes the SDS5 selection circuit to couple the line number value for the new line from register SMLl to the information input of register SLINE
and the true signals at the P9, L and CLK outputs cause the load circuit of register SLINE to store the line number value.
Additionally, the true signals at the outputs P9, L and CLK
cause the SMS flip flop to be set to a 1 state which, as discussed above, causes a true signal at the SM5 output thereby indicating to the SWITCH M~TRIX that the new line stored into the MEMORY MODULE area 2 should be retained as the poss-ible seed line. Following SB15, SB14 of the SEED
MODULE flow is entered and the true signal at the P9 output causes the SMB flip flop to be set to a 1 state, thereby removing the true signal at the SMB output. This is required since the DECODE I MODU~E is going to read the new line for computing the larger of the difference between the largest two occurrence values of the new line and the difference between the width value and the largest occurrence value.
The lack of a true signal at the output SM~ and hence at the output SM10, causes the DECODE I MODULE to prevent the MLNl register of the DECODE I MODULE from being counted dcwn.
Return to SB13 of the SEED MODULE flow and assume that a control signal is formed at the GE output of OR gate 516, -~
indicating that the length value of the new line is equal to ~ -or larger than the current possible seed line contained in llZ7~767 re~ister SLN. This causes SB14 of the SEED MODULE flow to be elltered, skipping SBl5 and accorclingly, the current seed length value register SLN and its current seed line number value in register SLINE remain unchanged. Likewise, flip flop SMS remains unchanged, thereby causing a false signal at the SMS output and, hence, at the SM5 output of the SEED MODULE, thereby signalling the SWITCH MATRIX that the new line contained in MEMORY MODULE area 2 can be overwritten and need not be saved. The true signals at the P9 and P9.CLK
outputs cause true signals at the SMll and SM12 outputs.
At this stage the first revolve has just been completed and the new line is in the MEMORY MODULE area designated by the S31 flip flop in the SWITCH MATRIX. Though the description has been made up to this point for only the first or input line stored in the MEMORY MODULE, the same general operation takes place if a new current seed line is formed. In this latter case, during SB13 the new seed ;
- line may be stored in any one of the MEMORY MODULE areas. ~
The area will be specified by the true state of one of -flip flops S31, S32 and S33 as more fully described in connection with the MEMORY MODULE and the SWITCH MATRIX.
The S31 signal has to be relayed to the Sll, l ``
S12, Sl3 flip flops of the SWITCH MATRIX before the DECODE I MODULE can read the new current seed line. At the same time the existing information must not be modified in the MEMORY MODULE areas designated by the S21, S22, S23, or S31, S32 or S33 fli-p flops. Thus, a true signal is formed at the SMll output. This inhibits the clock signal to flip flops S21, S22, S23, S31, S32 and S33. The true signal at SM12 then clocks the proper information from S31, S32, S33 ..

~ .

77~7 to Sll, S12, S13 in the SWITCH MATRIX. When all is done, S2i, S3i ii = 1,2,3) in the SWITCH MATRIX are unaltered, whereas Sli (i= 1,2,3) is able to gate the information from the new line to the DECODE I MODULE. Also since the rest of the system remains unchanged, when REVOLVE is called and a true signal is formed at RM8, the operation proceeds as normal.
True signals at the P9 and CLK outputs cause a true signal at the SM4 output which causes the gate 228 to set flip flop DlFST to a l state in the DECODE I MODULE and cause a true signal at the SM6 output which calls the DECODE I MODULE
by setting the DlGO one-shot to a l state.
Following SB14, SB2 of the SEED MODULE flow is again entered. The true signals at the P9, CLK and DlMEND outputs again cause the clock suspension logic 522 to suspend the operation of the SEED MODULE until the DECODE I ~ODULE has completed its operation and provides the largest occurrence value in register DOl. Note that the DECODE I MODULE now reads the current possible seed line which is contained in . ~
the MEMORY MODULE area and which was found by the SEED MODULE
during SB13 to be the shortest. After the DECODE I MODULE has ;
completed its operation and is forming the largest occurrence value of the current possible seed line, the true signal is removed at the ~ output, and the clock suspension logic 522 again enables the gate 520, allowing a pulse to be formed at the CLK output. The true signal at the P9 and ~r output in coincidence with the true signal at the CLK output causes flip flop P2 to again be set to a 1 state. The resulting true signal at the P2 output causes the SB2 of the SEED MODULE flow to again be entered where the largest occurrence value is stored in register T3 and the difference ~ ~.

~Z7767 between the wid~h value and ~he laryest occurrence value is stored via the SDS4 selection circuit into register Tl.
The operation during SB3 through SB15 is again repeated as discussed above, this time utilizing the current possible seed line which was previously determined during SB13.
Assume now that during SB10 it is found that the total number of lines revolved value contained in register SDN is equal to or greater than the iso-entropicgram width contained in register SMHW. The ALU then forms a true signal at either the G or the E output, causing the OR gate 516 to -form a true signal at the GE output. The true signals at the P7 and GE outputs in turn cause the flip flop P10 to be set to a true state, thereby causing SB16 of the SEED
MODULE flow to be entered.
During SB16, the number of the current possible seed line contained in register SLINE is compared with the width value contained in register SMHW. Ifthe number of the current possible seed line value in register SLINE is larger, then SB17 is entered, whereas if it is less, SB18 is entered.
Consider now the details of the above operation. The true signal at the P10 output causes the sDSl and SDS2 selection circuits to couple the current possible seed line number value contained in register SLINE and the width value contained in register SMHW to ~he information input of the ALU for comparlson. Assume that the current possible seed line value is larger. The ALU forms a true signal at the G or E output which in turn causes the OR gate 516 to form a true signal at the GE output and 5B17 is entered. Additionally, the true signal at the P10 output ~

. .
1~ .

~ \
~1~7767 causes the ALU to orm the difference between the current possible seed line value contained in SLI~E and the width value contained in register SMHW and forms a difference value at the oP output. The true signal at the P10 output also causes selection circuit SDS5 to couple the difference value from ALU to the information input of the register SLINE.
The true signal at the P10, GE and CLK outputs causes a load circuit to store the difference value into the register SLINE. Note that the current line number value stored in register SLINE during SB17 is the seed line number less the iso-entropicgram width value. That is, the current possible seed line contained in SLINE is greater than the iso-entropicgram width value, the REVOLVE MODULE has revolved past ~he end of the iso-entropicgram and it is therefore necessary to subtract the width value from the current possible seed line value in order to determine the actual number of the seed line. This operation is taken to ensure that the current possible seed line value contained in --register SLINE lies within the bounds of the iso-entropicgram.
If a revolve has taken place past the end of the iso-entropicgram, then line values are contained in register SLI~E which are greater than the iso-entropicgram width.
However, these values would be inaccurate and to find the value of the actual seed line value it is necessary to subtract the width value from the line value to arrive at the true number of the seed line.
Following SB16 or SB17 of the SEED MODULE flow, SB18 is entered. The true signals at the P10 and CLX outputs -cause the load circuit for the ONOC register to be activated and store the number of occurrences that have appeared in the -'~

~;.~, . ' o 11~:'7767 1 possibl~ s~d line rom r~ister ~NOC of tha ~NCODI~ MOD~LE
into register ONOC.
It should be not~d that true signals occur at the P9, L
and CLK outputs during S~15 when the new iso-entro~icc~ram line is found to be shorter than th~ current possible seed line. The true signals at the P9, L and CLK outputs cause the register OAR to load values corresponding to MEMORY
MODULE areas 1, 2 and 3, respectively, from switches 526, ~-~
528 and 530. The one ,which is selected is determined by the outputs S31, S32 and S33 of the corresponding flip flops in the SWITCH MATRIX which indicate the output area in -the MEMORY MODULE currently being used for the new }ine.
. ,~. . .
D. Example of Operation `-Consider now an example of operation of the SEED MODVLE and related portions of the DPM forming the SEED ~ODULE. Assume that the SEED MODULE is to revolve down through the iso-entropicgram ~ -shown in Table 4-B discussed above in I.GENERAL DESCRIPTION. -Assume that the input line to be revolved is line 0; thus the -revolve will revolve from line 0 to line 2 and then to line 7.
~ines 0, 2 and 7 broken down into 7 bit words with a 0 bit indicating absolute word code and a 1 bit indicating hybrid word code at the lefthand end are as follows:
10001110 ) ' '`:`.:'`' 2 00011010 ) hybrid line 0 ;~
01110101 ) length = 3 `~
:: 10001011 ) ,.' 00000111 ) hybrid encoding of line~2 00011010 ) length = 3 words `;
~3 10000111 ) hybrid encoding of line 7 01011001 ) length = 2.

-217- `
, ---` 112'7~67 l The su~sequent sequence o~ operation of the se~d finder .i9 as follows:

Input to the SEED MODULE is.
from "LINE NO" of IPRF line # of the seed (01 to SMLI iso-entropicgram width (16) to SMHW ~-from HW of IPRF
from MLNl of DECODE ~ MODULE length of input line ~3). to SLN .:
from DOl of DECODE I: MODULE line (:O~ in MEMORY MODULE area l :
~ ' sequence of control SBl-SB14, SB2-SB13, SB15, Sgl4, .
SB2-SB10, SB16-SB17 SBl SDN = O
SMLI = 0 SLINE ~O~ = SMLI(O) assume beginning line # and length are SEED and initialize modules;
SLN = 3 DlFST = l SB2 call DECODE I MODULE
CRl = DOl = 14 EOFl = 0 SB3 EOFl = 0 , SB4 SB4 TI(21 = SMH~ C16~ - CRl(14) difference between iso-entropicgram width and largest occurrence value;
SB5 call DECODE I MODULE
DOl = 12 EOFl = O
SB6 EOFl = O :, SB7 SB7 T0~2) = CRlCl4~ DOl(12~ diference between the two largest occurrence values;
' ~` - llZ7767 l SB8 Tl(2) = M~X(I~l(2),T~) th~ maxlmum of these dif~erences;
SB9 SDN(2) = SDN(~ rl(2) how far revolved;
SMLI(2) = SM~I(O~ ~ Tl(2) line position in the iso-entropicgram SBl0 SDN(2)< SMHW(l6l , go to .
SBll SBll DELI(:2)~- Tl(:2) largest to DELTA MODULE input;
SBl2 The REVOLVE MODULE is called and creates line No. 2 of the ~:
lQ iso-entropicgram SBl3 SLN(3) = M~N3(3~ .',go to SBl4 the possible shortest seed line is not less than 2; therefore iso-entropicgram line 2 is not : ~ :
considered as a seed line;
go to SB2 reset the DECODE I and II MODULES
DlFST = l ::
SB2 call DECODE I MODULE read the largest occurrence; - -CRl = DOl = ll EOFl = 0 SB3 EOFl = ~ :,go to SB4 ;- ;
20 SB4 Tl(5~ = SMHWC16) - CRl(ll~ difference between iso-entropicgram width and largest occurrence;
SB5 call DECODE I MODULE
DOl - l0 EOFl - 0 . .

: ' ` :.
_ 21~ -: ' ,''`

.
. .. .. ..... ... -. ~ ~. . -~ r) ~127767 1 ';~G EOFl ~ O .~o to SB7 SB7 T0(1) ~- Cr~l(ll) - DOl(10) di~crence be~ween ~he two larzcs~ occurrences;
SB8 Tl(5) = MAX(Tl(S), T0(1) ) number of lines to be revolved;
SB9 SDN~7) = SDN(2) ~ Tl(5) number of lines revolved; .
SMLI(7) = SMLI(2) ~ Tl(5) position of the seed line :
a~er the revolve;
S~10 SDN(7) < S~n~(16).', go to SBll 10 SBll DELI(5) = Tl(5) number of lines to be revolved to the DELTA
MO~ULE;
SB12 line 2 is now revolved down 5 lines to line 7 by the REVOLVE MODULE - the fonmat and length of this line were given in the input discussion SB13 SLN(3) ~ MLN3 (2) , . SB15 SB15 SLN(2) - MLN3(2) . save new ~sa-entrop~cgram SLINE(7) ~ SMLI(7) line as possible shortest iseed line;
20 SB}4 DlFST - 1 reinitialize DECODE I ~ ~:
and II MODULES - inhibit . :
~ go to SB2 the overwriting o~ the :
: seed line in the MEMORY ~ :;
MODULE area; .
2S SB2 call DECOVE I MODUIE
CRl ~ DOl ~ 7 EOFl - O
;: ;'-':.
. ~ ' '.
:`: 3 . -.
~ ` . -:: -220-., ,.

~Z'^~767 1 IX. S~D FINl~r~R
__ ~ riefly, an electronic data processing SEED FINDER or data compactor has been disclosed. The compactor is for a coded occurrence signal, such as an event occurrence signal, which represents actual occurrence values out of a group of possible occurrence values. The possible and actual values are arranged -~
in a monotonical, preferably decreasing, value order. Memory ~ `
means such as the MEMORY MODUEE stores such a coded occurrence signal. Means such as the DECODE I and DECODE II MODULES

form a first signal representing the stored coded occurrence signal. Means such as the seed finder of Fig. 26 responds to the first signal for selectively forming, for each different first signal, any one of a set of equivalent signals, the set including such first signal. Each equivalent signal is lS related to another one by an exclusive OR of the values thereof and the values thereof relatively shifted. The means for forming equivalent signals further includes means for enabling one or more of the equivalent signals to be sequentially formed. In thls connection the SEED MODULE, including its control counter, enables a coded occurrence signal such as an event occurrence signal to be revolved ;
through its iso-entropicgram.
Means such as the SLN register of the SEED MODU~E and the MLN3 register o~ the ENCODE MODULE store and form a 2 signal indicative of the length o~ the occurrence ~ignal -and the equivalent ~ignals. Means is provided for forming a signal identifying the equivalent signal which is associated with the shortest length signal. In this connection the SEED MODU~E is operative during SB13 of its flow for comparing 3 ~he length of the value stored in the MLN3 and SLN registers . ."', (~ r~

~Z7767 1 to dct~rmin(~ whi~ is ~h(~ ~L1mal].c~t: . The ~3ic3n;l1 in r~glstcr SLN indic~tes the length o~ the short~st ~ecd to th~t po~nt and th~ content of register MLN3 indicates the l~ngth o the line value being stored in the MEMORY MODULE from thc 5 ENCODE MODULE.
The purpose of the seed finder is to locate the seed of an event occurrence vector. Stating it differently, an event occurrence vector signal is to be revolved through its - -corresponding iso-entropicgram until an equivalent signal 0 is found that is shortest in lèngth. The iso-entropicgram has a set of unique but equivalent signal sets which include the input or event occurrence vector. Each signal set is related to another one in the set by an XOR of the value thereof and the value thereof relatively shited by one possible occurrence value. In a preferred embodiment of the invention the shortest length is that which is shortest when stored in hybrid coded form in the MEMORY MODULE. --Fig. 23 is a block diagram showing the internal control/
data flow for the seed finder. The ENCODE, DECODE I and II, REVOLVE, DE~TA, and SEED MODULES shown in Fig. 23 in conjunction with the MEMORY MODULE and the SWITCH MATRIX
(not shown) are a part of the DPM system depicted in Fig. 1 and function together as a data compactor.
What has been disclosed is a data processing method for compacting a line signal which represents actual occurrence values out of a group of possible occurrence values, the possible and actual occurrence values being arranged in monotonical value order. An example of the line signal in the disclosed embodiment of the invention is an event occurrence vector which is stored in 3 memory in hybrid coded form (see Table 9). However, it will .~' ` . ' ,.
-222- ~ ~
``'" .
.

` ~Z7767 be understood the line signal might be in other codes within the concepts of the invention under consideration.
The steps are as follows. Such a line signal is stored in a memory such as the MEMORY MODULE, as the possible shortest line signal. In this connection, the SEED MODULE applies a signal to the MEMORY MODULE which ~tores an event occurrence vector (whose seed is to be found), and the SEED MODULE applies a signal to the SWITCH MATRIX causing the appropriate switches to be set identifying area 1 as the one containing ''' lQ the current shortest line signal (i.e., the seedl. ' The SEED MODULE responds to the values of the possible ''~
shortest line signal for forming at least one signal l , representative of a total number of lines to be revolved.
Such an operation takes place during SB8 when the largest of the two different signals contained in registers Tl and l -~
TO is transferred to register T1. In this connection, register TO contains the difference between the values represented by the last two occurrence values at one end (i.e., the largest end~ of the shortest line signal and 2a register Tl contains the difference between the values l , represented by the maximun length (,iso-entropicgram width~
signal stored in register SMH~ and the occurrence value at one end Ci.e. largest occurrence value~ of the possible shortest line signal.
The steps include the step of responding to the total number of lines to be revolved signal for forming one or more incremental revolve signals representative of the incremental numher of lines by which a revolve is to be , '~, -effected. In this connection, the DELTA MODULE breaks ' -3a the total number of lines to be revolved into 'its component - -X ' ~'~

` ~Z7767 powers of 2 thereby speci~ying the actual increments by' which the revolve is to be effected.
Continuing with the method is the step of revolving the input line, which ;nvolves th.e step of forming a resultant incremental line signal representing the value of the possible shortest line signal exclusive OR'd with the value of the ~
possible shortest line sïgnal shifted by the number of : ~, occurrence values specified ~y one of the incremental '''~
revolve signals. This step i5 accomplished by the REYOL~E
MODULE during the revolve portion of the operation disclosed in connection with,5~12 of the SEED MODULE flow. The step of revolving further includes the step of enabling the resultant incremental line signal to be used in the preceding step for exclusive ORing, using another one of the incremental revolve signals. In this connection, after each exclusive OR, the result ifi stored into th,e MEMORY MODULE and the DELTA
MODULE provides the next component power of 2 signal which is then used for exclusive ORing the result formed by the REVOLVE MODULE. This operation is repeated until all of the incremental powers of 2 have been used in the revolve process by the REVOLVE MODULE. Further included in the step of revolving is the step of storing the final incremental line signal, after all of the incremental revolve signals have been used. In this connection, the final line signal stored in the MEMORY MODULE during the revolve process is identified by the OAR and t~e SWITCH MATRIX. The length.of the stored possible shortest line signal ~contained in regi~ter SLNI .
and the length.of the new incremental line signal contained :~
in register MLN3 of the EWCODE MODULE are compared and the 3a ALU of the SEED MODULE forms a signal indicating the shortest ' ~ .:

xi one duri~g SB13 oE the S~ED MODULE flo~. Suhsequently, the preceding steps are repeated utilizing the lin~ signal which is indicated to be the shortest one. In this connection, note that following SB13, SB14 and SB15 may then be entered following which SB2 is reentered where the repeat operation takes place.
Preferably, thP steps also include that of combining values represented hy a series of the total number of lines to ~e revolved signal to thereby form a further signal representing a line number value for the stored possible shortest line signal. This is accomplished using the ALU
and registers SMLl and Tl of the SEED MODULE during SB9.
Preferably, the step of forming a resultant incremental line signal involves the step of combining the values represented by the possible shortest line signal in one of the incremental revolve signals to form a corresponding shifted signal. Inthis connection, the absolute occurrence values provided by the DECODE II MODULE are combined ~ith the incremental power of 2 values from the DELTA MODULE -to form a shifted value by the REVOLVE MODULE. The step -~
of forming a resultant incremental line signal further comprises the step of exclusively ORing the values represented by the shifted and unshifted possible shortest line signals to form the resultant incremental line signal.
In terms of apparatus, there has also been disclosed a data compactor for an input line signal (i.e. event occurrence ~-vector) which represents actual occurrence values out of a group of possible occurrence values. The possible and actual occurrence values are arranged in an incremental, preferably decreasing, value order. Included is memory means such as .' .

. - :.
P.~ ~

th~ MEMORY MODUL~ for ~toring th~ input line signal.
Decoding means such as the DECODE I and II MODULES convert a line signal stored in the memory means including the stored input line signal from a first compact code (i.e.
hybrid codel to a second expanded code ti.e. absolute code).
Means including the SEED and DELTA MODULES are responsive to a converted line signal from the decoding means for forming one of a selected number of value signals. The number of value signals correspond to such signals as the component power of 2 signals provided from DELO in the DELTA MODULE. Means such as the REVOLVER is responsive to one of the number value signals and the corresponding converted line signal from the decoding means for further converting the concerted line signal, as a function of the num~er value signal, to a modified but equivalent line signal. This process is effected in the REVOLVER
through the exclusive ORing process. Encoding means, such .... .. . . .
as the ENCODE MODULE, converts the equivalent line signal from the second to the first code for storage in the memory 2Q means. Included is means such as the OAR, the ALU and SLN
and MLN3 (ENCODE MODULE~ for selecting one of the equivalent sets of signals. During SB13 the shortest one, in hybrid code,is selected. The ALU of the SEED MODULE in combination ~ ;
with the MLN3 register of the ENCODE MODULE and the SLN
regi~qter of the SEED MODULE are operative during SB13 for forming a signal indicating the shorter of the original stored line signal and the equivalent line signal.
The control counter of the SEED MODULE is operative following SB14 to ena~le the foregoing means such afi the -3Q DECODE I and II, SEED, DELTA, and ENCODE MODULES and the `

~lZ7767 REVOLVER to repeat their operation. However, means is responsive to the shorter indication signal for enabling the decoding means to decode the shorter one of the stored original line signal and the equivalent line signal during the repeat. In this connection, either SBl4 is entered directly or SBl5 is entered followed by SBl4 depending on the result of the comparison by the ALU during SBl3.
During SB15 the memory area number in the OAR register is changed if necessary to identify the MEMORY MODULE area containing the possible shortest seed line before entering SB14 where the DECODE I and II MODULES are called to decode the possible shortest line signal. It will also be noted in connection with the SWITCH MATRIX that the flip flops of the SWITCH MATRIX are appropriately set to identify the ~ `
MEMORY MODULE area containing the possible shortest seed line.
Preferably, the decoding means involves à first decoding means and a second decoding means (such as DECODE I and II ;
MODULES) to enable the actual occurrence values of a line signal to be provided to the REVOLVER at different rates -upon demand. It will be noted that the repeat operation enabled by the control counter of the SEED MODULE going from `
SBl4 back to SB2, et seq, will be repeated until the original input line has been revolved completely through its iso-entropicgram, thereby insuring that the shortest equivalent new line signal (seed) has been formed. Means i9 provided for disabling the repeat enabling means after the shortest of the equivalent new line signals has been formed. To this -end, the value of the current number of lines revolved `
relative to the input line is stored in register SDN and -~
..

'' '`, ~-- llZ7~67 is compared with the iso-entropicgram width value contained in register SMHW by the AhU o the SEED MODULE, during SB10.
If the current number of lines revolved relative to the input line contained in register SDN is the greater, then SB16 et seq., is entered where the operation of the SEED MODULE is subse-quently exited.
It will also be noted that the DECODE I and II and MEMORY MODULES form a means for storing and retrieving the input line signal which is to be compacted.
It should also be noted that means is provided for - combining the value of the successive number of lines to be revolved signal in such a way as to for~ a line number for the shortest line. This function is provided by means such as the ALU, the SMLl, Tl, and SMHW registers and the ALU
during SB 7 and SB17 of the SEED MODULE flow.
' . . ~
X. CHANGE MODULE
A. General Description. ~-Section I. GENERAL DESCRIPTION describes a method whereby changes may be made in an occurrence vector. ;
These changes include insertions, deletions and the addition of new information. A deletion removes an occurrence value from an event occurrence vector. An insertion adds an occurrence value to an event occurrence vector~ An addition 2S of new information may be the addition of new occurrence values to an existing event occurrence vector or the addition of new event occurrence vectors.
~;~ According to a preferred embodiment of the invention ~ ~ , .
changes may be made to an event occurrence vector at any ~ ` . .

, llZ7767 line numb~r of its iso-entropicgram. Preferably, the change is applied to the seed line and the resultant changed line is then revolved until the new seed is found.
Describing the change operation in more detail, a seed which is to be cha~ged is defined in terms of a line number, a line value, and a length of line value. The change vector is composed at the input line for its iso-entropicgram (line 0) and includes an occurrence value for each insertion, for each deletion, and for each new addition that is to be made in the seed.
Generally, the method followed is as follows:
(l) rotate the change vector in its iso-entropicgram down to the line number corresponding to that of ~
the seed which is to be changed. This will pro- ``-vide a revolved change vector having a line number - ~ the same as that of the seed, a change value and a length the same as that of the seed;
(2) merge the occurrence values of the line values in the seed and change vector by exclusive ORing the two -together.
More specifically, the operation involved is as follows.
The line value of the change vector, in hybrid code, is placed in MEMORY MODULE area l. The line value of the seed is placed in MEMORY MODULE area 2. The change vector is revolved down to the same line of the iso-entxopicgram as that of the seed.
At this point, the change vector is defined in terms of the line number of the seed, the line value for the change vector and the length of the seed. The merge operation ir.volves XORing the line value of the seed and the line value of the changed vector resulting in a changed line value. The changed seed is '', `
X ' ' "'' '7'767 then defined in terms of the line number for the ariginal seed, a changed line value and the length of the seed.
The changed seed is then revolved down to its seed.
Fig. 24 is a schematic and block diagram of the CHANGE
MODULE which enables the above operation. Fig. 26 is the internal control/data flow for the seed line changer, which is a portion of the overall DPM system. It will be seen from this figure that the CHANGE MODULE makes use of the ENCODE, DECODE I, DECODE II, DELTA, REVOLVE, and SEED MODULES
as well as the MEMORY MODULE, the SWITCH MATRIX and IPRF
in its operation.

B. Components The CHANGE MODULE, Fig. 24 has two 8 bit 8 flip flop registers CLINE and CLN. Both of these registers are of type SN74100 disclosed in the above TTL book, having the same characteristics as those described above.
In addition, the CHANGE MODULE has a control counter 613 with flip flops Pl-P4. Flip flops Pl-P4 are the same type disclosed in Section I. GENERAL DESCRIPTION, F. Components.
The CHANGE MODULE has a generalized clock control circuit 700, The generalized clock control circuit 700 is described in more detail in the subsequent section entitled "Generalized Clock Control Circuit".
The CHANGE MODULE also has clock suspension logic 622 connected to the CS input of the clock control circuit 700.
As described with respect to the ENCODE MODULE, logical -equations are used to indicate gating required to control various circuits and to generate various signals, all ~-indicated in the CHANGE MODULE.
'. .

, ' ' ~;r . ' ~ .

o r) 1127'767 l Depicted ~long the right h~nd side o the C11ANGE MODUL~

Fig. 24 are input and output control lines and information inputs and outputs. The information inputs and outputs are depicted by heavy lines.

C. Detailed Description Reference should be made in the following discussion to the CHANGE MODULE schematic of Fig. 24 and the CHANGE MODULE

flow diagram of Fig. 25. The following discussion will des- -cribe the CHANGE MODULE using an example of a specific seed line and change line in order to provide a better understanding -of the system. The specific example is that given hereinabove in I. GENERAL DESCRIPTION w~th respect to Tables 9-A and 9-~.

As noted, the CHANGE MODULE when combined with the ENCODE, l5 DECODE I, DECODE II, DELTA, SEED and MEMORY MODULES, the ~ --SWITCH iMATRIX and IPRF, forms a seed line changer. The seed line changer sub-system of the DPM is depicted in the ~-`
general block diagram of Fig. 26 (the MEMORY MODULE, SWITCH -MATRIX and IPRF are not shown).
Initially, the MINI COMPUTER forms a true signal at the output MINIT, thereby applying a true signal to the IP input of the clock control 700. The true signal at the input IP

causes a true s1gnal at the iMR output which resets flip flops Pl-P4 of the control counter 613 to 0 wlthout a clock pulse. The MEMORY MODULE areas l and 2 and ~INE # and LNl and LN2 of the IPRF initially are loaded by the MINI COMPUTER
with the inputs illustrated in ~able l1. Thus, the values for the examples of Tables 9-A and 9-9 which are now stored are as fOl10WR
~3C
~ ' '': .

~ -231-:~127767 MEMORY MODULE area 1 3 6 8 9 11 12 MEMORY MODULE area 2 0 6 12 LINE # 6 LNl 7 The MINI COMPUTER then forms a true signal at the CNGO output causing the clock control 700 to start forming its clock pulses at the CLK and CLK output.
At the first true pulse at the CLK output, the logic ~ . is true and the flip flop Pl is set to a 1 state, thereby forming a true signal at the Pl output. The true signal at the Pl output causes the CLINE register to couple the line number of the seed from LINE # of the IPRF to the output of the CLINE register.
The true signal at the Pl output also causes a true signal at the CM4 output of the CHANGE MODULE whiah in turn ~-goes to the DECODE I, DECODE II, SEED and DELTA MODULES, and the SWITCH MATRIX. The true signal at CM4 causes the CNG ~
flip flop in the SEED MODULE to be set to a 1 state where -gates 218 and 226 couple the length of line value for the change vector from LNl of IPRF to the registers MLNl and -MLN2 in the DECODE I and DECODE II MODULES; causes the selection circuit DELS to couple the line number of the . .
seed from the output of the CLINE register of the CHANGE
MODULE to the i~put of register 302 in DELI of the DELTA ;`
MODULE; and causes flip flops S31 and S23 in the SWITCH MATRIX
to be set to 1 states. The 1 states of flip flops S31 and ~-, . . .
S23 cause the DECODE I and DECODE II MODULES to read from MEMORY MODULE area 1 and the ENCODE MODULE to write into ~30 MENORY MODULE area 3. To be explained, when the true signal , . .

.; , . .
~ i , , .

~ ,Z'7767 at Pl terminates, the CLINE reyister storea the line number from LINE # of the IPRF.
Subsequently, a true signal is formed at the CLg output of the clock control 6Q2, thereby causing the logic Pl.CLK
to be true, there~y forming true signals at the CM3, CM5 and CM6 outputs. The true signal at the CM3 outputs causes the length of line Yalue from LNl of IPRF to be stored ~-into the MLNl and MLN2 registers of the DECODE I and II
MODULES: causes the length of seed line from LN2 of IPRF
to be stored into the CLN register in the CHANGE MODULE:
and causes the line number from the output of the CLINE ; ~-register of the CHANGE MODULE to be stored into the register -302 of DELI in the DELTA MODULE: and causes the one-shot REVGO in the REVOLVE MODULE to be set, thereby calling the operation of the-REVOLVE MODULE.
In addition, a true signal is now formed by the logic Pl.REVEND.CLK in the clock suspension logic 622, thereby causing a true signal at the CS -input of the clock control 700. ~
The true signal at input CS causes the clock control 700 to ~ -suspend the clock pulses at CLK and CLK, thereby suspending operation in the CHANGE MODULE until the operation of the REVOLVE MODULE is complete and removes the true signal at ;~
REVEND so indicating. `
Using the example shown in Tables 9-A,9-B, the following conditions now exist:
(1I register MLNl (DECODE I) contains the length of the line value for the change vector (MLNl = 71;
(2) register MLN2 (DECODE II) contains the length of the line value for the change vector (MLN2 = 72;
(3) register DELI (DELTAI contains the line number of .,',,',".,;.
.
.. . .
. .

11;~7767 the s~d lin~ value (DI~LI = G);
1 (~) CNG ~lip flop (SE~.D) is in a 1 state;
(S) flip flops S31 and S23 (SWITCII M~TRIX) are in ~ 1 state;
(6) MEMORY MODU1E area 1 contains the change line value signals (MEMORY MODULE area 1 = 1,3,6,8,9,11,12);
(7) MEMORY MODULE area 2 contains the seed line value signal (MEMORY MODULE area 2 = 0,6,12);
(8) register CLINE (CHANGE) contains the line number of the seed line value (CLINE = 6);

(9) register CLN (CHANGE) contains the length of the line value of the seed (CLN = 2);
(10) REVO~VE MODULE has been called.
Following its call, the REVOLVE MODULE forms a true signal at the RM8 output, thereby indicating that the SWITCH MATRIX
has been clocked~ Since fl~p flops S31 and S23 of the SWITCH MATRIX had been et previously, this results in the setting Sll, S21 and S33 of the SWITCH MAT~IX. Thus, the ¦ DECODE I and II MODULES will read from MEMORY MODULE area 1 ~
and the ENCODE MODULE will write to MEMORY MODULE area 3. - ;
The true signal at the RM8 output of the REVOLVE MODULE
sets the flip flops Sll, S12 and S33 in the SWITCH MATRIX
to a 1 state. Additionally, the input SM5 to the REVOLVE
MODULE is false, indicating that the current line value in -MEMORY MODULE area 1 is not'to be kept as a posslble seed.
2 ~he signal at RM12 output of the REVOLVE MODULE causes the SP flip ~lop in the SWITC~ MATRIX to be reset to 0. -Therefore, the fîrst pass of the REVOLVE MODULE causes the change vector to be revolved down four lines to line 4 of its ~ , ' ~ 3 : ::
~ -234-,.~:~

l~Z'776~

1 iso-cntropicgram and the revolved line value o~ the change vector is now stored in MEMORY MOD~LE area 3 as spccified by the 1 state of flip flop S33. Thus, the revolved line value stored in ~lEMaRy MODULE area 3 now contains the absolute values 1, 2, 5, 7, 9, 11, 12, 15 and the line value 4 is stored. ;
At this point, the register MLN3 of the ENCODE MODULE
contains the length value for the revolved change line value now stored in MEMORY MODULE area 3 (i.e., a length 0 cf 8). The REVOLVE MODULE then forms true signals at the -~
RM14 and RM10 outputs, thereby causing the length value contained in MLN3 of the ENCODE MODULE to be enabled to the input of the registers MLNl and MLN2 of the DECODE I and II MODULES and stored. ~ -The REVOLVE MODULE then embarks on a second pass through its flow. At this point in time, flip flops S33 and S21 in the SWITCH MATRIX are in a 1 state; therefore, when the REVOLVE MODULE forms a true signal at its RM8 output it causes the flip flops S13, S23 and S31 in the SWITCH MATRIX
to be set to a 1 state. The 1 states of these flip flops cause the DECODE I and II MODULES to both read the revolved change line value contained at MEMORY MODULE area 3 and cause the ENCODE MODULE to write the resultant revolved line value into MEMORY MODULE area 1.
It should be carefully noted at this ~uncture that although reading and writing is taking place in MEMORY MODULE areas 3 and 1, ME~ORY MODULE area 2 contains the origilal seed line value and it remains there unaltered at this point~
A true signal is subsequently formed at the RM12 output of 3 the REVOLVE MODULE which causes the SP flip flop in the SWITCH

::' MAT~IX to b~ resct at an 0 state. The REVOLVE MOUDLE then revolves the revolved change line value (i.e., 1, 2, 5, 7, 9, 11, 12, lS) down two lines from iso-entropicgram line 4 to 6, and the ENCODE MODULE writes the new revolved change line value in MEMORY MODULE area 1. Thus at this point in time (conclusion of this second pass of the REYOLVE MODULE~, MEMORY MODULE area 1 contains the revolved change line value 1, 6, 12 (see h. of Table ~.Al. Additionally, the length value of the new revolved change line value is contained in register MLN3 of the ENCODE MODULE.
Subsequently, the REVOLVE MODULE forms a true signal at the RM14 and RM10 outputs, causing the value to be stored :.
from register MLN3 into register MLNl and MLN2 of the ^ :~
DECODE I and II MODULES.
The DELTA MODULE has now provided all of the component powers of 2 of the total number of lines to be revolved for the change line and therefore th.e REVOLYE MODULE .
terminates ïts operati`on and forms a false signal at its REVEND output. Th.i.s causes logic Pl.REVEND in clock suspension logic 622 to become false which causes the clock control 700 to again form pulses at CLK and CLK.
The next true signal at the CLK.output resets the P9 flip flop to a ~ state and sets the P2 flip flop to a 1 state .
in the control counter 613, thereby forming a true signal at the ~2 output, -.
The true signal at output PC causes a true signal at the CM2 output of the CHANGE MODULE which causes the length ~2~.
of the seed line value in the CLN to be coupled to the input.
of MLN2 of the DECODE II MODULE. . :
The true signal at P2 also causes a true signal at the CMl ~ - 236 -~127767 output to the SWITCII MATRIX thereby inhibiting any input to the S21, S22 or S23 flip flops.
When the pulse is ormed at the CLK output, the logic P2.CLK becomes true, which in turn causes a true signal at the CM6 and CM8 outputs of the CHANGE MODULE.
The true signal at the CM8 output causes the MLN2 ~ -register in the DECODE II MODULE to be loaded with the ~ -content of the CLN register. Thus the length 2 of the seed - -line value (in MEMORY MODULE area 2) is stored in the MLN2 register of the DECODE II MODULE. -The true signal at CM6 causes the clock control 70a to suspend the clo~k in the CHANGE MODULE. It also causes the REVGO mono-stable to be fired in the REVOLVE MODULE
thereby initiating the revolve process.
Note that nothing was loaded into DELI of the DELTA
MODULE. This will cause the REVOLVE MOUDLE ~ mærge or XOR
the seed line value and the change line value.
The REVOLVE MODULE forms a true signal at the RM8 output ~ causing Sll and S33 flip flop in the SWITCH MATRIX to be set to 1. Also the RM12.CMl logic becomes true, causing the S22 flip flop in the SWITCH MATRIX to be set. This :
indicates that the DECODE I MODULE will be reading from MEMORY MODULE area 1, the DECODE II MODULE will be reading -from MEMORY MODUhE area 2, and the ENCODE MOUDULE will be writing to MEMORY MODULE area 3.
Upon completion of the merge operation, the REVOLVE
MODULE forms a false signal at the REVEND output which causes the logic P2.REVEND.CLK to go false which, in turn, causes the clock control 700 to again form pulses at the CLK and CLK outputs. ~
~ .
- 237 - `
':
.
.. ` , ~iZ'7'767 .
~rlle n~xt true slgna~. at the CLIC ou~put rese~s the P2 flip flop to a 0 ~tate and set~ the P3 1ip flop to a 1 state in the control counter 613, thereby forming a true signal at the P3 output.
When the pulse is formed at the CLK output, the logic P3.CLK becomes true, which in turn forms a true signal at the CM2 output of the CHANGE MODULE. The true signal at the CM2 output sets the SMGO one-shot in the SEED MODULE to a 1 state, thereby cal~ing the operation of the SEED MODULE.
The SEED MODULE then commences its operation of locating the seed in the manner described hereinabove with respect to the SEED MODULE.
To this end, the SEED MODULE causes the new seed line value contained in MEMORY MODULE area 3 to be revolved through -its iso-entropicgram and locate the seed which, in the case of the disclosed embodiment, is the line from the ENCODE MODULE which has the fewest number of words. The SEED MODULE causes the line value of the seed value to be saved in the MEMORY MODULE in the area specified by OAR
of the SEED MODULE. At the time the true signal is formed at the CM2 output, the logic P3.SMEND.CLK becomes true, :.
thereby forming a true signal at the CS input to the clock control 700 which again causes the clock control 700 to terminate its pulses at the CLK and CLK outputs and suspend the operation of the CHANGE MODULE. :~
When the SEED MODULE has completed its seed finding operation, its register OAR ldentifies the MEMORY MODULE area containing the line value of the new seed; its register SLN -contains the length of such line value; its register SLINE
contains the line number value of such line value, and ':

.
: ~:.'.

(~
~ 7767 1 its rccJister ONOC contains the number of occurren~cs in such line value. When the SE~D MODULE completcs it~
operation, a true signal is formed at the SMEND output from the SEED MODULE, which in turn causes a false signal at the SMEND output. This causes logic P3.SMEND.CLK to go false and causes the clock control 700 to start forming its pulses - -at CLK and CLK.
The following pulse at CLK resets the P3 flip flop to a 0 state and sets the P4 flip flop to a 1 state in control counter 613.
The true signal at the P4 output cause~ a true signal at the MT input of the clock control 700 which, as discussed above, sets a one-shot in the generalized clock control 700 which in turn causes true signals to be formed at the MR
and FC outputs. The true signals at the MR output of the clock control 700 cause all of the flip flops including T4 of control counter 613 to be reset to 0. The true signal at output FC causes the CNGEND output of the CHANGE
MODULE to turn true and signals the calling module that the 20 operation of the CHANGE ~ODULE is complete. `
. :. "

D. Exam~le of Operation An example of the operation of the CHANGE MODUIE in the seed line changer will now be given in 8ymbolic notation 25 using the example depicted in Tables 9A and 9B. ~he --corresponding blocks in the flow diagram are shown along the left hand side.
The following is expected as input: ;
CLINE - 6 Line number of the seed line value;
; 3 HW = 8 Iso-entropicgram width;

~127767 1 LNl = 7 Length of line value for the change vector;
LN2 Length of the line value for the seed;
DELI = 6 Llne number of the line value for the seed;
Change line value In MEMORY MODULE area l;
1,3,6,8,9,11,12 where 6,12 are deletions;
the remainder insertions; -Seed line value In MEMORY MODULE area 2;
0,6,12;
Sequence of control is CBl - CB5;
CBl initialize clock proper information into the proper registers;
CLINE = LINE # =6 seed line number;
CLN = LN2 length of seed line value; .
CB2 DELI(6) = CLINE(6) number of lines to revolve to DELTA MODULE:
call REVOLVE MODULE revolve the change vector down to ~ .
same line number as the seed line; :
CB3 MLN2 ~~ CLN load the length register with - -the length of the line value of the seed; set DECODE II MODULE to read reset DECODE II MODULE from MEMORY MODULE area 2; ~
CB4 call REVOLVE MODULE the change line value and the --seed line value are XOR'd with the . .
result as shown in h of Table 9-A;
CB5 SMLI - CLINE line number value clocked to SMLI
CNG = 1 of the SEED MODULE, CNG flip flop - set; :
call SEED MODULE the new seed is located; -~

~ .

~lZ7767 HALT
output taken from the SEED MODULE
SLINE = 5 (seed line number) OAR = MEMORY MODULE area which contains the seed SLN = 1 (see line value length) ONOC = 1 (number of occurrences in seed line value) ''.','. ~.

~ .

.~ . .

~ . .
~: 30 "~

: X ~ " .

l~Z7767 Xl S~D LINE CH~NG~R
-From the foregoing description of the CHANGE MODULE it will be understood that the ENCODE, DECODE I and II, REVOLVE, D~LTA and SEED MODULES depicted in Fig. 26 in association with the MEMORY MODULE and the SWITCH MATRIX ~not shown) form a Seed Line Changer which allows a seed to be changed ~-without revolving it back to the zero or input line of the corresponding iso-entropicgram. The seed line changer forms an electronic daia processing system for changing an occurrence - --value signal, such as a seed, utilizing a change value signal ~
such as a change vector. The aforementioned occurrence and , ;
change value signals each represent an actual occurrence value out of a group of possible occurrence values, the possible and actual occurrence values being arranged in monotonical, -;~
preferably decreasing value order, as depicted in Tables 1 and 2. Means such as the MEMORY MODULE area 1 is provided l -`
for storing the occurrence value signal which is to be changed. Means such as the CLINE register of the CHANGE
MODULE is provided for storing a line number signal in association with the stored occurrence value signal. The line number signal stored in register CLINE specifies the number of the line of the line value of the seed.
Means such as the MEMORY MODULE area 2 stores the change occurrence signal (i.e., the change vector) which specifies the changes in the values of the stored occurrence value signal. Means such as the REVOLVER depicted in Fig. 19 form~ a means for responding to the change occurrence value signal for selectively forming, for each different change value signal, any one of a set of equivalent signals, the set including such occurrence value signal. Each equivalent `.''-~Z7767 signal wi~hin eacll set is uni~ue and i8 related to anotherone by an exclusive OR of the values thereof and the values thereof relatively shifted. Included in the foregoi.ng means is means for forminy any one of the equivalent signals in a set as specified by a received number of lines signal. Means such as the SEED and DELTA MODULES respond to the stored line number signal for applying a number of lines signal to the equivalent signal forming means. It will be -.
recalled in connection with the DELTA MODULE that the DELTA MODULE forms a number of lines signal in the form of component powers of 2 of the total number of lines .-to be revolved. :. :
Further included is means such as the REVOLVER for .
exclusive ORing the values represented by an equivalent , .-signal and the occurrence value signal to thereby form the changed occurrence value signal.

XII. GENERALIZED CLOCK CONTROL
_ . _ Individualized clock control circuits have been .
disclosed for the previously described ENCODE, DECODE I, ,. -DECODE II, REVOLVE, DELTA and SEED MODULES. However, it i.
should be noted that a generalized clock control circuit .
may be employed. T~erefore, with respect to the CHANGE -MODULE just de.~ribed and other modules subsequently to I .
be disclosed in connection with.the DPM SYSTEM, a general~
ized clock control 70Q shown in Fig. 27 will be u9ed.
Specifically, the generalized clock control circuit 700 includes one-shot multi-vibrators 7a2 and 704, a flip flop 708, OR gates 712 and 714, an AND gate 718 and logical signal inverters 72Q and 722, all of the same types disclosed ~ - 243 -llZ7767 ~or thc ~NCOD~ MODUL~. ~ source of regular recurring clock pulses 701 provides clock pulses to one input of the AND gate 718. The clock control 700 has input circuits IN, CS, IP and MT and has outputs MR, CLK, CLK and FC. Modules subsequently to be disclosed only disclose the clock control 700 in block form with the prior mentioned input and output circuits.
The one-shots 702 and 701 are of the same type disclosed for the ENCODE MODULE and, responsive to a true signal at the input at the left side, are triggered to a 1 state where a true signal is formed at the output indicated on the right hand side. The one-shot remains in a 1 state for a time interval equal to that between the beginning of two successive clock pulses from the source of clock signals 701 and then automatically resets to a 0 state where a false ` -signal is formed at the corresponding output. ~-The flip flop 708 is a conventional flip flop of the same type disclosed hereinabove with respect to the ENCODE
MODULE. The one-shot 702 has its input connected to the IN
- input and the IN input is the one which receives a true signal whenever the corresponding module is called. A true signal at the IN input triggers the one-shot to its 1 state, causing its output to go from a false to a true signal. The OR gate 712 also has inputs connected to the output of one-shot 704 l and to the IP input. The IP input is the one which receives -a true signal whenever it is desired to reset the control counter in the corresponding module. Additionally, the one-shot 704 has its input connected to the MT input of the clock control 700. The MT input receives true signals whenever the corresponding module has completed its function.
.. I ..
Thus, a true signal at the MT input causes the one-shot 704 _ 244 ~
' ,,~, z~67 to ~ set to a 1 statc~ which, ln t~rn, applies a true si~nal at the I~C outL~ut, thcreby indicatin~ that th~
function of the corresponding module is complete. The true signal at FC is also applied to the OR gate 712.
Whenever any of the inputs to the OR gate 712 receives a true signal, a true signal is formed at the MR output.
The MR output is connected to the control counter in the . ~-corresponding module and resets each of its flip flops to .~ ;
a 0 state when a true signal is applied. -The AND gate 718 is connected to the CLK output and is .
connected through the logical signal inverter 722 to the .
CLK output of the clock control 7Qa. The gate 718 is an ; .
AND gate which has one input connected through the logical signal inverter 720 to the CS input, a second input to the .. ~ -unbored output of the flip flop 7a8, and a third input connected to the clock 701. The CS input is the one which. ..
receives true signals from the clock suspension logic of the corresponding module. The flip flop 708 is set to a 1 . state which, in turn, applies a true signal to the gate 718 whenever a true signal is formed eith.er at the control counter reset circuit IP or the end of function input MT. As a result, the AND gate 718 causes true clock pulses to be .
formed at the CLK and CLK outputs whenever the CS input is .~
false (due to a false condition for the corresponding clock suspension logic~i and the flip flop 7Q8 h.as been set to a 1 state and a pulse occurs from the clock 701. The logical signal inverter 722 inverts the clock signals at CLK, forming the complement thereof at the CLX output. .

~ ~' j! .. ~

`' ~lZ7767 XIII. o~Tr~uT MOD~L~
t A. G~neral Description _ The OUTPUT MODULE operates in conjunction with other portions of the DPM SYSTEM generally depicted in Fig. 34 for performing two functions. The first is to cause a simple retrieval or decompaction ~ype of operation wherein an event occurrence vector which is represented by one of the non-input lines (usually the seed) is revolved back to the input line of its iso-entropicgram. The second is called the DEL function and causes a check to determine if an event occurrence vector which is represented by a non- -input line (usually a seed~ contains particular actual occurrence values back at the input line of its iso-entropicgram. Signi- -ficantly, the second function is done without revolving the non-input line clear back to the input line of its iso-entropicgram.
Briefly, the operation of the OUTPUT MODULE in carrying out the retrieval or decompaction function is as follows: -an event occurrence vector, at one of the non-input lines of its iso-entropicgram (usually the seed), is represented by a line value signal and a line number signal. The OUTPUT MODULE determines the difference between the value of the line number signal and the width of the iso-entropicgram. - -The difference thus identifies the number of lines required to revovle the line value signal back to the input line of its iso-entropicgram. The difference is then provided to the DELTA MODULE which forms signals representing its component powers of 2 beginning with the largest (as discussed -above). The REVOLVE MODULE then causes the line value signal to be revolved in its iso-entropicgram by the specified number ~ - 246 -:

, . :

~ 7767 of lines baclc to ~he input line of the iso-entropiccJram.
Consid~r now the operation for the D~L furlcti.on. A
reference line (in hybrid coded form) is stored int~e M~MORY
MODULE and represents one or more test values. Each test value identifies an actual occurrence value whose present is to be checked in a line of an iso-entropicgram. ~owever, the given line to which the test is to be applied is one of the non-input lines of its iso-entropicgram (usually the seed). Also the presence of an occurrence value is desired at the input line, not at the non-input line.
The DEL function allows the presence of an occurrence value, at the input line, to be determined without revolving a given line ~usually the seed) clear back from its non-input line to its input line.
The given line (usually a seed) is represented at its .
non-input line by a line value signal and a line number signal.
.
The OUTPUT MODULE utilizes the same hardware and method described for the regular output and finds the difference between the values of the line number signal and the width of the iso-entropicgram. The DELTA MODULE then determines the integral powers of 2 of the difference beginning with the largest. The largest integral power of 2 is saved and the line value signal is revolved by the number of lines specified by the remaining integral power ~or powers) of 2 to form a revolved line value signal to determine if the occurrence value identified by the test signal is present. The revolved signal is examined and .
information as to the presence of an occurrence value, equal to the line value, is exclusive OR'd with information as to the presence of an occurrence value which is displaced from . .

. . .

the one uncler test ~y the value of the saved signal. If either occurrence value exists in the revolved sign~1 then the actual occurrence value under test exists at the input line. The chec]cing and exclusive OR is performed by forming an absolute coded value representing each actual occurrence value of the revolved line value signal, from largest to smallest, until one is found that is equal to or less than the value of the test occurrence value. If equality exists, a signal is stored in a flip flop representing a 1. Other-wise a 0 is stored. The test occurrence value is thendecreased by the largest component power of 2 signal which has been saved. The absolute coded values representing the actual occurrence values of the revolved line are then continued to be formed beginning with the next one in order until one is found whose value is equal to or less than the decreased test occurrence value. If equality exists the 1 or 0 signal previously stored in a flip flop is complemented. Otherwise the previously stored 1 or 0 signal is left unaltered. If the result of the last -complement is a 1, the actual occurrence value under test exists at this input line. If the result is a 0, the actual occurrence value under test does not exist in the input line.

: .
B. Components Figs. 28-31 show a schematic and block diagram of the OUTPUT MODULE. Included are registers OHW, ORl, ORTl, OLINE, OR2, ORSN, ORT2, ORT3, OLN and OAR, all 8 bit or 8 flip flop registers of type SN7410Q described hereinabove with re-spect to the ENCODE MODULE. The only exception as to size . j , is register OAR wllich contain~ 2 bits or ~lip flops o~ storaye.
A150 included are selection circuits DS3, DS6 and DS7.
These are convent.ional selection circuits of the type and operating in the manner discussed hereinabove in section I.F.
CONVENTIONS AND COMPONENTS USED IN FIGURES.
Also included are switches 810 and 812. The switches 810 and 812 are conventional mechanical switches or other circuits which.form a 2 hit coded signal at the respective switch output representing a hinary coded 1 and 3, respectively.
Also included are flip flops DELOP, SS, SW, and Pl-P10.
Flip flops Pl-P10 are a part of the control counter 813 for the OUTPUT MODULE. The flip flops are of the same type and have the same characteristics as that described hereinabove in section I.F.
The OUTPUT MODULE includes an arithmetic unit ALU of the same type disclosed hereinabove with respect to section I-B.
~he OUTPUT MODULE also has an AND gate 8a2, an exclusive OR gate 804, and a conventional OR gate 805. The exclusive OR
gate 804 is of the type wherein a true signal is formed at its output whenever a true signal i5 formed at either one, but not ~:
at hoth, of its two input~ simultaneously.
The OUTPUT MODULE contains a generalized clock control 700. : .:
The generalized clock control i5 described in detail hereinabove .~
in sect;on X. GENERALIZED CLOCK CONTROL. ~: .
5imilar to the ENCODE MODULE, the OUTPUT MODULE also has gating which i5 depicted hy logical equation for controlling various input circui.ts and output circuits of the OUTPUT MODULE.
Included among the logic gates is a clock suspension logic 822 for controlling the suspension of the clock formed by the clock 3~ control 7Q0.
:

~ 249 ~
. ~. .

` ` ~1;~7767 Tlle input and output control lln~s and the inEormation inputs and outputs of the OUTPUT MODULE are depicted along the right hand side of Figs. 3~ and 31.
Table 17 at the end of the specification lists the various register~ and flip flops and gives the general purpose of each in the OUTPUT MODULE.

C. Detai-led Description Reference should primarily ~e made in the following dis-cussion to the OUTPUT MODULE schematic and block diagram of Figs.28-31 and the flow of Fig. 32. Consider now a detailed descrip-tion of the OUTPUT MODULE during its "regular output" operation.
The f~regular outputl' operation of the OUTPUT MODULE is the ~-retrieval or decompaction operation which is to revolve any line of an iso-entropicgram, preferably the seed, back to the 0 or input line.
Initially, a control signal is formed at the MINIT output of the MINI COMPUTER/ thereby causing the following to be reset to 0: flip flops DELOP, OPSW and P1-P10. The MINI COMPUTER then loads MEMORY MODULE area 1 with the line value of the seed which is to be revolved back to its iso-entropicgram input line (or 0 -~
line) and the IPRF is loaded as follows:
LNl with the length of the line value of the seed;
BW with the width of the iso-entropicgram for the ~5 seed;
LINE # with the line number of the line value for the seed ~ -~
Also, flip flop DELOP of the DMP INTERFACE is set to 0 to indicate a "regular output". If set to 1, DELOP indicates a -~

DEL function.

.: , -'"" ', X " ~

l~Z7767 Sinc~ flip flop DELOP in the DPM INTERFACE MODULE i9 in a 0 state, a false signal is ormed at the SET DELOP output and therefore flip flop DELOP in the OVTPUT MODULE remains in a 0 state. E`lip flop DELOP being in a 0 state indicates a "regular output" operation. It will be noted that the generalized clock control circuit 700 has its input IP connected to output MINIT
and is responsive to the true signal at MINIT for forming a true signal at the MR output which, in turn, resets the flip flops Pl-PlQ to 0.
Within the OUTPUT MODULE, the true signal at Pl causes the ORSN register to ~e cléared to a. The true signal at the CLK
output causes the logic Pl.CLK to become true which causes the register OLINE to store the LINE NO (see line number from IPRF~. - -Subsequently, the true signal at the CLK output causes the logic Pl.CLK to ~ecome true which, in turn, causes the following~
in the OUTPUT MODULE, register OHW stores the iso-entropicgram width from HW of the IPRF; and a true signal at the output OMl;
also, register ORT3 stores the length of the line value of the -change vector, if one exists, from LN2 of the IPRF. It should ~e noted that the length of reference line from LN2 is only of interest during the DEL operator function which will be discussed in more detail hereinafter.
The true signal at the OMl output causes the registers MLNl and MLN2 of DECODE I and II MODULES to store the length of the line value for the seed from LNl of the IPRF and causes registers EBL and ETL and EIR to store the value from BL and TL and IR from the IPRF.
OB3-OB6 of the OUTPUT MODULE flow revolves the line value in MEMORY MODULE area l through its corresponding 3~
"'.' - 251 - ~

. . .
X

iso-entropicgram to its input or n line. The reYolve is done in two steps to help implement the D~L unction and for clipping, which will be explained in more detail a~ter completing the description of the "regular output" function.
The number of lines through which the line value must be revolved to reach the input line is the difference between the iso-entropicgram width in OHW and the line number of the line value in OLINE. This value is computed during OB3. -Using the DELTA MODULE, the largest component power of 2 --la of th~t difference i~ determined and stored in register ORSN during OB5 and the remaining component powers of 2 ~ -~
are represented by the value left in DELI of the DELTA MODULE. ~
It w~ e recalled that the number of lines equal to all ~ -component powers of 2 must be revolved before the input line will ~e reached. However, again to help implement the DEL
function, the OUTPUT MODULE first causes the REVOLVE MODULE ~
to revolve the line value through the remaining lines to be -revolved designated by the value remaining in DELI of the DELTA MODULE (OB6) and later OB8 revolves the revolved line value through lines equal to the largest component power of 2.
Return now to the actual operation.
OB3-OB6 of the OUTPUT MODULE flow is used for revo~ving the line value in MEMORY MODULE area 1 toward the input line of its iso-entropicgram and to determine the largest component power of 2 for storage in the register ORSN for use during the DEL function. OB2 of the OUTPUT MODULE flow is used to - -check the content of register OLINE to see if it is 0. -Register OLINE contains the line number for the line value stored in the MEMORY MODULE. If the line number is 0, it is 3Q not necessary to revolve the line value since it is already ~ .
.~.*. ,, 1~2'776~

at l:he input row. Ilence, OB3-OB6 can be skipped. ~rherefore~
if the content o~ OLINE is 0, a true signal is formed at the output OLo o~ the OLINE register. Also, the DEL function is not being performed and flip flop DELOP is in state 0 .
and a signal is formed at output DELOP. The logic Pl.OLo.DELOP
becomes true and the following pulse at CLK resets flip flop P2 to 0 and sets flip flop P-10 to 1, causing OB7 of the OUTPUT MODULE flow to ~e entered, thereby skipping the revolve steps of OB3-OB6.
a However, return to OB2 and assume that the line value is not at Q and hence register OLINE does not contain a line num~er of a and OLo i5 true. The true signal at CLK is formed while a true signal is formed at the Pl output.
A true signal is formed at the OLo output of register OLINE
(there~y indicating that its contents are 0) and the logic Pl.OLo is true and the pulse at CLK resets the Pl flip flop to 0 and sets the P2 flip flop to 1.
At this point, the OUTPUT MODULE forms a true signal at the P2 output and OB3 of the OUTPUT MODULE flow is entered.
As mentioned, OB3-OB6 are used to partially revolve the line value of the seed toward the 0 or input line OL its iso-entropicgram. During OB3, the difference between the seed line number contained in register OLINE and the iso-entropicgram -width contained in register OHW is computed. This difference is the actual number of lines by which the seed's line value contained in MEMORY MODULE area 1 must be revolved in order to get its input line. Thus, in the OUTPUT MODULE, the true signal at the P2 output causes selection circuits DS4 and DS5 to couple the content~of registers OHW and OLINE to the ALU
3Q and causes a true signal at the S input of ALU. The ALU

_ 253 ~

.... .
~ .'. . . .

~llZ77ti7 1 orms a si.~nal at its or output, representing the difference betwe~n the iso-entropicgram width and the seed line number con-tained in registers OH~ and OLINE. The true signal at P2 also causes the DS6 selection circuit to couple the difference 5 signal from the OP output of ALU through to its.output. :.
The true signal at the P2 output also causes a true signal -at the OM2 output of the OUTPUT MODULE. The true signal at OM2 causes the output from the DS6 selection circuit to be coupled in the DELTA MODULE through the DELS selection ~-10 circuit to the DELI register. The true signal at CLK causes `.:
true signals to be formed at the OM3 and OM4 outputs of ~he :`
OUTPUT MODULE. The true signal at the OM4 output causes the DELI register to store the difference value from selection .~.. -circuit DS6 of the OUTPUT MODULE into its shift register 302. . :-15 The true signal at OM3 calls the DELTA MODULE by triggering : ~.
the DELGO multi-vibrator. The DELTA MODULE then computes .-the highest component power of 2 of the difference value `~`
~OHW - OLINE) and forms it in its register DELO in the manner ..~ ..
described for the DELTA MODULE.
Before the DELTA MODULE completes its operation it forms . .
a true signal at the DELMEND output. The true signal at the P2 output, together with true signals at the DELMEND and CLK ~ :
: outputs cause the logic P2.DELMEND.CLK to become true in the . :`
clock suspension logic 822. This causes the CS input to the :`
clock control 700 to become true and thereby suspend the : : pulses at the CLK and CLK outputs. The DELTA MODULE ` -continues, as described hereinabove, to determine the largest ~ .
~: component power of 2 of the difference value stored in the DELI register, and when this is complete,. control is returned`
3 back to the OUT~UT MODULE.
~ .
,'`~''' . -254~
'`':' 'T.' ,. ~ .;

llZ7767 When the D~LTA MODULE ha~ finished, control is returned back to the OUTPUT MODULE by the DELTA MODULE by orminy a true signal at the DELMEND output, thereby forming a false signal at the DELMEND output. The false signal at the DELMEND output causes the clock suspension logic 822 to form a false signal at the CS input to the clock control 700 which, in turn, causes clock pulses to be formed at the CLK and CLK outputs. The first pulse at CLK causes the flip flop P2 to be reset to 0 and causes flip flop P3 to be set to a 1 state. -At this point, OB5 of the OUTPUT MODULE flow is entered, output P3 being true. The true signal at P3 causes register ORSN to store the largest component power of 2 from register DELO in the DELTA MODULE. OB6 of the OUTPUT MODULE flow is now entered. After all component powers of 2 are formed, a true signal is formed at the output DELEND of the DELTA
MODULE. The true signal formed at the DELEND output of the DELTA MODULE and the P3 output of flip flop P3 (OUTPUT MODULE) sets the DD flip flop in the OUTPUT MODULE to a 1 state.
The logic P3.DELEND is true, causing a true signal at the OM5 output which, in turn, triggers the REVGO one-shot in the REVOLVE MODULE, causing the REVOLVE MODULE to revolve the value line contained in MEMORY MODULE area 1 through the number of lines of its iso-entropicgram specified by ;
the remaining lines to be revolved signal contained in the DELI register of the DELTA MODULE after computing the largest -component power of 2. As diRCUsSSed above, the remaining line~
to be revolved can be represented by the following:
isoentropicgram width (HW) - line number (OLINE) = largest component power of 2 (ORSN). During the operation of the REVOLVE MODULE, the true condition of logic P3.REVEND.DD

~ - 255 -... . .
.. . .

~'77~7 1 cause-; the cloc~ susp~nsion logic 822 to form a true signal at the CS input of the clock control, thereby causin~ the cloc]; control to disable further pulses at the CLK and CLK output. Finally, when the REVOLVE MODULE
finishes its operation (i.e., revolved the line value through a number of lines equal to HW-OLINE-ORSN), the REVOLVE
MODULE forms a false signal at the REVEND output, thereby -~
causing the logic P3.REVEND.DD

/ ;~
' / '''''`;;',', ~3 :`. '~:, . I -256-` ~lZ7767 of the clock suspension logic 822 to become false and enable clock pulses at CLK and CLIC. Additionally, the logic P3.DELOP
is true, thereby setting flip flop Pl0 to a true state and resetting flip flop P3 to a 0 state at the following pulse at CLK.
At this point, true signals are formed at the Pl0 output and OB8 of the OUTPUT MODULE flow is entered. The true signal at P10 causes the OPSW flip flop to be set to a 1 state to indicate that clipping may take place, if required, in the ENCODE MODULE. Clipping may only take place during the production of the original occurrence vector and at no other time, otherwise errors may result during the revolve operation.
During the true signals at P10 and CLK, true signals are formed-by the logic Pl0, (Pl + P10) CLK, P10.CLK, causing --~
true signals at the outputs OM2, OM4, OM5 of the OUTPUT
MODULE. The true signal at P10 causes the selection circuit DS6 to couple the largest component power of 2 from register ORSN to register DELI in the DELTA MODULE. The true signal at OM5 calls the REVOLVE MODULE which, in turn, revolves the revolved line value contained in the MEMORY MODULE down the remaining number of lines specified by the largest component power of 2 stored in DELI of the DELTA MODULE.
The true condition of logic Pl0.CLK.RE~END causes clock suspension logic to disable clock pulses at the CLK
and CLK outputs of clock oontrol 700. When the REVOLV~
MODULE completes its operation, the signal at REVEND goes false and alock suspension logic 822 again causes clock control 700 to form pulses at CLK and CLK. One of the flip flops S31 ~ .
and S33 in the SWITCH MATRIX is true, indicating the MEMORY

MODULE area containing the revolved line value and the selection . ~

. . . .

circuit DS7 co~tples the coded signal from the corresponding switch to the information input of register O~R. The true condition o the logic P10.REVEND causes the register OAR
to store the signal so that it will identify the MEMORY
MODULE area containing the revolved line value. The revolved llne value is now the input line of the iso-entropicgram.
Note that the MLN3 register of the ENCODE MODULE now contains the length of the revolved line value. The true ~
condition of logic P10.REVEND also causes register OL~ to - -`
store the length of the revolved line value from register ~-MLN3 of the ENCODE MODULE.
The true condition of logic P10.REVEND also causes a `
true signal at the MT input of clock control 700 which in ; -turn causes a true pulse at output OUTEND and at M7, thereby signalling an end of the OUTPUT MODULE operation and terminating further pulses at CLK and CLK and resetting control~:
counter 813 to 0.
With the detailed description of the "regular output"
operation for the OUTPUT MODULE in mind, consider now the DEL function.
As discussed above, the DEL function is to check for the presence of an occurrence value in the input line using one of the non-input lines of the iso-entropicgram. The `
sequence of operation re~uired for the DEL function is briefly set forth under section XI-A above.
Additionally, the MINI COMPUTER loads the MEMORY MODULE
area 1 with the line value of the seed tnon-input line) and loads MEMORY MODULE area 2 with the change vector. The change vector is in hybrid coded form and represents one or aplurality of occurrence values, each of which identifies ' '"`.

~lZ7767 an occurl^ence value in the input line for the seed which is to be checked for presence. In other words, i~ the change vector represents occurrence values 2, 6 and 8, each one of occurrence values 2, 6 and 8 in the input line for the seed is to be checked for presence. The DEL function allows this checking operation to be performed without revolving the non-input line value of the seed back to the input line of the iso-entropicgram.
In addition, the IPRF is loaded as follows: -LN2 with the length of the line value of the change vector;
LNl with the length of the line value of the seed;
HW with the width of the iso-entropicgram -for the seed;
LINE# with the line number of the line value for the seed.
Also flip flops DELOP of the DPM INTERFACE MODULE is set to 1 to indicate a DEL function operation. This causes a true signal at the SET DELOP output of the DPM INTERFACE
MODULE thereby setting the DELOP flip flop to a 1 state, indicating that the DEL function is to be performed.
The operation of the OUTPUT MODULE is then called by the MINI COMPUTER by forming a true signal at the OUTGO, I
thereby triggering the clock control 700, causing it to ``
reset the control counter 813 and start forming pulses at the CLK and CLX outputs. The operation during OBl through OB6 of the OUTPUT MODULE flow is identiaal to that described hereinabove with respect to the "regular output" operation and will not be repeated.

~ - 259 -X ' . ~ :

~ ssume now that the opcration of the OUTPUT MODULE
during the D~L function has progressed through 0~6 of the OUTPUT MODULE flow similar to that described above. At this point the following has taken place: the di.fference between the iso-entropicgram width (O~W) and the line number (OLINE) has been computed and sent to DELI in the DELTA
MODULE; the largest component power of 2 of this difference has been determined by the DELTA MODULE and the result has - ~-been stored in register ORSN of the OUTPUT MODULE; the :
REVOLVE MODULE has revolved the line value of the seed down a number of lines in its iso-entropicgram where the number ;
of lines is equal to the remaining number of lines after the largest component power of 2 (e.g. OHW - OLINE - ORSN).
In other words, the original seed line value has now been revolved through its iso-entropicgram until it is within a number of lines from the input line which equals the largest component power of 2 contained in ORSN. ~ ~ .
However, in contrast to the operation during the regular l: -output, the operation during the DEL function has flip flop 1-DELOP in a l state and therefore, during OB7, when a true signal is formed at the P3 output of flip flop P3 of the control counter 813, the logic P3.DELOP is true and the ~
following pulse at CLK resets flip flop P3 to O and sets l ~ :
flip flop P4 to a 1 state.
The MINI COMPUTER forms a true signal at output OUTGO
which causes a true signal at the IN input of the clock control 700. Subsequently, pulses are formed at the CLK and CLK
outputs of the clock control 700. l -The outputs Pl-P10 are now in a O state, causing the -:: . :
30 logic Pl + P2 + PlO to be true. The following pulse .:
,.

"` ~lZ77~;7 at CLIC sets flip flop Pl to a 1 ~tate, thereby forminy a true signal at the Pl output. Block OBl of the OUTPUT
MODULE flow is now entered. During OBl, the ENCODE, DECODE I
and II and DELTA MODULES and the SWITCH MATRIX are initialized , S thereby gating information to the proper registers. To this end, the true signal at the Pl output causes the OUTPUT
MODULE to form a true signal at the output OMl6. The true signal at the output OM16 causes the following action in the DECODE I and II MODULES: gates 218 and 220 of DECODE I and a data selector DDSl of DECODE II couple the length value from LN2 of IPRF to registers MLNl and MLN2, respectively;
in the ENCODE MODULE BL (bottom limit) and TL (top limit) from IPRF are coupled through their respective data selectors to the input of registers EBL and ETL. .
. 15 The logic Pl.CLK becomes true, causing a true signal at output OMl which in turn initializes the DELTA MODULE
by setting DELFST. A true signal at Pl also initializes the SWITCH MATRIX.
OB9 of the OUTPUT MODULE flow is now entered and a .
true signal is formed at the P4 output, which in turn causes true signals at the following OUTPUT MODULE output circuits:
OM6, OM8, OM21. The true signal at the OM6 output causes an inhibit signal from inverter 1444 in the SWITC~ MATRIX
while a clock signal is formed at the OM7 output of the -OUTPUT MODULE. The reason for the-inhibit signal will be explained in detail in connection with the SWITCH MATRIX.
However, in general terms the current revolved line value is now stored in either area 1 or area 3 of the MEMORY MODULE
and must now be read by the DECODE I MODULE during the ;
subsequent operation by the OUTPUT MODULE. Also the SWITCH

.

~ '.

-1 M~TRIX remains set so that tlle D~CODE II MODUL~ re-reads the chan~ vector from M~MORY MODULE area 2 and the ENCODE
MODUL~ writes into the other one of areas 1 and 3 where the revolved line value is not stored. Accordingly, the inhibit signal prevents the setting of the SWITCH MATRIX
from being changed for the DECODE II MODULE but permits a change in setting for the DECO~E I and ENCODE MODULES
during the subsequent clock at the OM7 output of the OUTPUT MODULE, Thie true signal at the OM21 and OM8 outputs initializes thc DECODE I and II MODULES by setting the DlFST and D2FST
flip flops therein to 1 states. Additional~y, the true signal at P4 sets the OPSW flip flop to a ~ state, thereby indicating that the clipping function may pow be performed lS by the ENCODE MODULE and causes the register ORT2 to store the length value from register MLNl in the DECODE I MODULE
into reg~ster ORT2 of the OUTPUT MODULE. Register MLNl in the DECODE I MODULE now contains the length of the revolved line value and this value must now be saved in register ORT2 to eniable a re-read of this line value.
The following pulse at the CLK output causes flip flop P4 to be reset to 0 and flip flop P5 to be set to a 1 state, thereby causing OB10 of the OUTPUT MODULE flow to be entered.
During OB10, a true ~ignal is formed at the P5 output of the control counter 813. The true signal at the PS output causes true signals at the OM10 output of the OUTPUT MODULE.

The true signal at the OM10 output causes flip flop S22 in the SWITCH MATRIX to be set to a 1 state, thereby indicating that the DECODE II MODULE is to read frQm MEMORY MODULE area 2 ` 3 (where the change vector is stored) and causes a selcction 77~7 circ:uit in th~ DECODE II MODULE to enable the length o~
the line value for the change vector contained in register CFT3 to be coupled through to the information input of register MLN2 in the DECODE II MODULE.
The following pulse a~ the CLK output causes the logic P5.CLK to become true and true signals are formed at the OMll and OM20 outputs of the OUTPUT MODULE. The true signal at the OMll output calls the DECODE II MODULE
by setting its D2GO one-shot multi-vibrator and causes the register MLN2 in the DECODE II MODULE to store the length of reference line from register ORT3.
The true signal at P5 also causes OBll of the OUTPUT
MODULE flow to be entered. It is during this block that the DECODE II MODULE is called, thereby causing the first occurrence value from the change vPctor to be provided.
The logic P5.D2END.CLK forms a true signal at the CS
input of the clock suspension logic 822, thereby causing the clock control 700 to suspend further clock pulses. `
After the DECODE II MODULE has finished its operation of reading and decoding the first occurrence value from the -change vector, the true signal at the D2END output of the DECODE II MODUL~ goes false, causing the clock suspension logic 822 to remove its signal from the CS input of the clock control 700, thereby enabling clock pulses to again be formed at the CLK and CLK outputs.
If, during the operation of the DECODE II ~ODULE, it was found that the last occurrence value from the change vector had previously been read and that no additional occurrence values could be provided, the DECODE II MODULE sets its EOE2 flip flop to a 1 state, thereby causing a true signal at the .~ : " '.

: l~Z77~7 EOF2 output. The true signal at P5 causes the flip flop P6 to be set to a l state and flip flop P5 is reset to a 0 state at the following pulse at CLK and OB27 is entered.
During OB27 of the OUTPUT MODULE flow, the true signal at the P6 output, together with true signals at the EOF2 and CLX cutputs causes the logic P6.EOF2.CLK to become true, thereby forming a true signal at the OM15 output which in -turn causes the ENGO one-shot to be set, thereby calling the operation of the ENCODE MODULE. In addition, the logic P6.EOF2 is true, forming a true signal at the OMl8 output, thereby causing the ELAST flip flop in the ENCODE MODULE
to be set to a l state indicating that this is the last call on the ENCODE MODULE and that the last entry from the input line, if any, is to be written out into a MEMORY MODULE area in hybrid coded form. To be explained in more detail the ~
values so written out are in hybrid coded form and represent -the occurrence values, identified by the change vector, which ` - ~"
... ,.:: .
are present at the input line of the seed.
Continuing with the operation, the true signal at the P6 output causes the flip flop P7 to be set to a 1 state and flip flop P6 is reset to a 0 state at the following pulse at CLK, causing OB29 to be entered. ~ -During OB29 of the OUTPUT MODULE flow, registers OAR
and OLN contain values identifying the MEMORY MODULE area containing final output and the length of this area and the OUTPUT MODULE is exited.
However, consider now the operation assuming that the last occurrence value from the reference line has not been read and that the signal at the EOF2 output is true and consider the operation following OBll after the DECODE II

llZ7767 MODULE has bee~ called to provide the next occurrence value from the change vector, The true signal at the P5 output at the CLK following the clock suspension causes flip flop P6 to be set to a 1 state and flip flop P5 to be reset to a 0 state, thereby causing OB12 to be entered.
The true signal at the P6 output causes the selection circuit DS3 to couple the occurrence value (from the change vector) in the DO2 register of the DECODE II MODULB to the information input of the OR2 register, and causes the -register OR2 to store the occurrence value. Additionally, the true signal at P6 causes the ORTl register to store the same occurrence value into register ORT1.
The true signal at the P6 output also causes the flip flop SS to be set to a 1 state and the flip flop SW
to be reset to a 0 state. Flip flop SS is set to a 1 state and will subsequently be reset to 0 to indicate that the first pass through OB18 and OB20 is about to be undertaken. , -To be explained, the ne~t time through OB18 and OB20, flip flop SS will be in a 1 state. The flip flop SW is used to indicate if an occurrence value, corresponding in value to the occurrence value from the change vector, is present at the input line corresponding to the revolved line. As previously explained, an occurrence value is present at the input line if the revolved line value in the MEMORY MODULE, being read by the DECODE I MODULE, has an occurrence value equal either to the occurrence value from the change vector or equal to the occurrence value from the change vector minus the largest component power of 2 in the register ORSN. In actual operation, the flip flop SW is used to exclusive OR

~lZ7767 the presence of an occurrence value in the revolved line value equal to the occurrence value from the change vector with the presence of an occurrence value in the revolved line ~hich is equal to the same change vector occurrence value less the largest component power of 2. In order to cause the flip flop SW to perform its exclusive ORing function, it is initially set to a 0 state and, to be explained in more detail, the flip flop SW will end up in a 1 state if the exclusive OR results in a true condition, whereas it ends up in a 0 state if the exclusive OR is a false condition.
OB13 of the OUTPUT MODULE flow is now entered. The true signals at the P6 output and the EOF2 output (the -latter indicates that the DECODE II MODULE has not reached the end, or last occurrence value, of the change vector) and the true signal at the CLK output causes the logic ; :
P6.EOF2.CLK to become true, thereby forming a true signal at the OM12 output. The true signal at the OM12 output of the OUTPUT MODULE causes the DlGO one-shot in the DECODE I
MODULE to be set, thereby calling the operation of the DECODE I MODULE, causing it to read the first occurrence value from the revolved line value. The logic P6.DlMEND.CLK
is true, thereby causing the clock suspension logic 822 to disable the clock control thereby suspending further pulses at the CLK and CLX outputs. When the DECODE 1 MODULE has provided the occurrence value from the revolved line value, a false signal is formed at the DlMEND output from the DECODE I MODULE, thereby causing the logic P6.DlMEND.CLK
to become false, thereby causing the clock suspension logic -3~ to enable the clock control 700 to commence forming pulses ~ ' .

at the CIIK and CLIC outputs. Assume that the DECODE I MODULE
has not reached the end of the revolved line value and hence a true signal is not formed at the EOFl output and a true signal is formed at the EOFl output. The true siynal at the P6 output causes flip flop P7 to be set to a 1 state and P6 is reset to a 0 state at the following pulse at CLK, 1 ;
thereby causing OB14 of the OUTPUT MODULE flow to be entered.
During OB14, a true signal is formed at the P7.CLK
output of the control counter 813 which causes the register ORl to form at its output the occurrence value which was read from the revolved line value by the DECODE I MODULE.
When the signal at P7 is removed, the register ORl will retain and store the value, which is a characteristic of the register.
OB15 of the OUTPUT MODULE flow is entered. During OB15, 1-the true signal is still formed at the P7 output. The true signal at the P7 output causes the selection circuits DS4 and DS5 to couple (1) the line value occurrence value from register ORl, and (2) the test occurrence value (from the reference vector) from register OR2 to the inputs of the 1-ALU. Initially, the true signal at the P7 output causes l~
the compare (C) input of the ALU to be activated, thereby ~ -causing the ALU to compare the two input values. It should be noted that three possible conditions may result from the compare. These possible conditions are as follows: (1) ORl = OR2; (2) OEl ~ OR2; and ~3) ORl C O~s. It will be recalled from the theoretical discussion that the revolved line value of the delta is to be aligned so that its rightmost or largest occurrence value, contained in ORl, is aligned with the rightmost oocurrence value in the line of the iso-, ~ - 267 -.. ..

~r` .

`-` ~ 11~7767 entropicgram to which it is applied. If the rightmost occ~rrence valu~ i9 equal to the test occurrence value, the contents of OR1 = OR2 at this point, and the two lines are aligned and the state ~0) of flip flop SW is exclusive OR'd with 1 and therefore is set to a 1 state. Thus, if the ALU forms a true signal at the E output, one input to the AND gate 802 is true. Additionally, at this point, output -:
EOFl from the DECODE I MODULE is false. Hence, a true signal is ~ormed by the logic P7.EOFl at the other input, causing AND gate 802 to-form a true output. The flip flop SW forms a false signal at the SW output and hence the exclusive OR
gate 804 forms a true signal at the upper side input of flip flop SW. Additionally, since the ALU forms a true signal at the E output, the OR gate 805 forms a true signal at the LE output. Therefore, the logic P7. (LE + EOFl).CLK -~is true and the exclusiue ORing flip flop SW is set to a 1 state corresponding to the true input from exclusive OR -gate 804.
Assume a non-aligned condition where the occurrence value (from the revolved line) contained in ORl is greater than (~ ) the test occurrence value contained in register OR2. The ALU will form a true signal at the G output but will not form a true signal in either the L or E output.
The gate 805 will therefore form a false signal at the LE ~`
output, causing the logic P7.(LE + EOFl) .CLX to be false and flip flop SW will remain unchanged. Additionally, if OR V OR2, a decision cannot be made and values must be read from the revolved input line until a decision can be :~
made, i.e. OR1C OR2. Accordingly, the logic P7.EOFl.G

will be true and hence flip flop P7 will be reset to a 1 state, :':.:. -:.

i~Z7767 cau~;ing 0~13, OBl~ and OB15 o~ the OUTPUT MODULE ~low to be re-cntered where the DECODE I MODULE provldes the next lower occurrence value from the revolved line value.
It should be noted that ~he DECODE I MODULE provides the occurrence values from the revolved line value in decreasing value order. Accordingly, the DECODE I
MODULE will be moving through the revolved line value in a direction toward the smaller values to bring the line value into alignment with the larger occurrence value contained in the OR2 register.
Assume that during PB15 the third condition is found where the occurrence value from the line value in OR1 is less than (~) the test occurrence value (from the reference line) contained in OR2. Under these conditions, the occurrence value from the line value is less than (C) the occurrence value from the reference line contained in OR2 and hence lies to the left of the position under test.
This means that it is no longer necessary to look for the test occurrence value because the revolved line value does not l-~
contain the occurrence value. Therefore, the occurrence value in the revolved line value which is to the left of the one under test (OR2) by the number of occurrence value specified by the largest component power of 2 contained in register ORSN is next to be checked for presence. This is done by incrementally decrementing the value in register OR2 by the value in register ORSN and by causing the DECODE I
MODULE to continue providing the occurrence values in the revolved line value in sequence.
To this end, OB16 of the OUTPUT MODULE flow is entered.
The second time through the status of flip flop SW is not . ".

, , .. - ~ :' . :

known but it is to remain unchanged. Therefore, its state is XOR'd with 0. To this end, the output E from the ALU
is false and the gate 802 ~orms a ~alse input to the OR
gate 804 causing the exclusive OR gate in turn to apply a false signal at the upper left side of the flip flop SW.
Hence, during OBl6, the exclusive OR flip flop remains unchanged. Following OB30, or following OBl6, a true signal is formed at the P7 and LE outputs. This causes the logic P7.(LE + EOFl) to become true and the following pulse at CLR
resets flip flop P7 to a false state and sets the flip flop P8 to a l state, thereby causing OBl7 to be entered.
The true signal at the P8 output causes OBl7 to be entered. The leading edge of the true pulse at P8 triggers the SS flip flop from a l to a 0 state. OB18 is now entered where the state of the SS flip flop is checked. Since the SS flip flop is now in a 0 state indicating that this is ,:
the first pass through OB18 et seq., fo~ the particular test occurrence value from the reference line contained in OR2, OB24 and OB25 of the OU$PUT MODULE flow are entered.
During OB24 and OB25, the test occurrence value in register OR2 is modified to a test occurrence value which is to the left of the test occurrence by the number of occurrence values specified by the value in ORSN. In other words, it is necessary to form a test occurrence value signal which identifies the next occurrence value in the line o the ;
delta iso-entropicgram which corresponds to the largest component power of 2 in register ORSN.
Considering the above operation in more detail, the l-true signal at the P8 output causes the selection circuits -DS4 and DS5 to couple the test occurrence value from register ` ' , .

~Z77~7 OR2 through to the left input of th~ ~LU and couple the largest component power of 2 from register ORSN to the right hand input of the ALU. The true signal at P8 also causes the ALU to subtract the content of ORSN from OR2 and form 5 a difference value signal at its output OP. If the result is greater than or equal to 0, which is the usual case, the resultant difference signal has not resulted in a value which is to the left of or off the end of the iso-entropicgram.
To be explained in more detail, should the difference signal have resulted in a value which is less than 0 (OR2C 0), a position off the end of or to the left of the iso-entropicgram would result and OBl9 would be entered.
Assume that the difference is equal to or greater than 0 (OR2~ 0). The true signal at the P8 output causes flip flop 15 P9 to be set to a 1 state and flip flop P8 to be reset to 0 at the following CLK, thereby causing OB20 to be entered.
The true signal at the P8 output causes the difference ~ -signal formed at the output of ALU to be coupled through the DS3 selection circuit back to the input of register OR2 and ^~
20 the true condition of logic P8.SS.C~R causes register OR2 to store the difference value. Thus, OR2 now contains the orginal test occurrence value decreased by the largest component power of 2 contained in register ORSN. , -During OB20, true signals are formed at the P9 and SS
25 outputs (i.e. flip flop SS i9 in a 0 state), thereby causing OB26 to be entered.
If during OB26 the content of register OR2 is equal to or greater than (~ ) 0, meaning that it is still within the wldth of the iso-entropicgram, then it is necessary to l -re-enter OB14 et se~. where the new test occurrence value _ ~Z7~67 contain~d ill register OR2 is compared against the occurrence value from the revolved line value stored in ORl, to detcrmine whether they are equal. To this end, a true siynal i9 formed at the OR20 output o~ the OR2 register, indicating that the 5 OR2 register is not 0 and the logic P9.SS.OR20 becomes true and the following pulse at CLX triggers the P7 flip flop to a l state and resets the P9 flip flop to a false state, thereby causing OB14 of the OUTPUT MODULE flow to be entered.
During OB14/ a true signal at the P7.CLK output again causes the register ORl to store the next occurrence value from the revolved line value which is still stored in register DOl of the DECODE I MODULE.
During OBl5, register ORl contains the occurrence value from the revolved line value and register OR2 contains the test occurrence value. As discussed above, should the -values contained in ORl and OR2 be equal, OB30 is entered.
If flip flop SW is now in a 1 state, the AND gate 802 and the exclusive OR gate 804 will apply a true signal to the exclusive ORing flip flop SW, causing it to change to a ~
state. A 0 state of the SW flip flop at this point indicates that the revolved line value contains occurrence values equal to those designated by both the test occurrence value from the reference line and the calculated occurrence value -which the ORSN positions to the left. This indicates that an occurrence value equal to the test oc¢urrence value from the reference line is not present in the input line of the iso-entropicgram for the seed. If, on the other hand, the comparison during OB15 reveals that the occurrence value -from the revolved line value contained in ORl is greater than ~`
~ ) the value contained in register OR2, the OUTPUT MODULE, -;`-. ~

~ -' . .
' -- :-77~7 throu~h the D~CODE I MODUL~, has not ~et reached the position in the revolved line value corresponding to that now specified by register OR2, Accordingly, OB13 is again entered where the DECODE I MODULE is again called, causing the next occurrence value from the revolved line value to be provided and during OB14, stored in register ORl.
It will be noted that OB13 is re-entered with flop flop P7 in a true state, the logic P7.EOFl.G causing flip flop P7 to be reset at the pulse at CLX.
This operation continues causing occurrence value after occurrence value in the revolved line value to be ;
provided by the DECODE I MODULE until one is stored in ORl which is equal to or less than the computed test occurrence value stored in register OR2. If an equality is found, then OB30 is entered where, as discussed above, the exclusive OR flip flop is complemented. If an entry is stored in register ORl that is less than the value in register OR2 before an equality is detected, OB16 of the OUTPUT MODULE flow is entered where the SW flip flop remains in its previous state. The 0 state of the SW flip flop then indicates that the occurrence value under test is not present at the original input line. If SW flip flop is in a 1 state, the occurrence value under test is present.
If during OB15 it is found that the content of ORl is equal to (E) or less then (L) that of register OR2, the OR gate 805 orms a control signal at the LE output.
The true signal at the LE output causes the logic P7.(LE + EOPl) to become true and flip flop P8 is set to a 1 state and flip flop P7 is reset to a 0 state at the following pulse at ~-CLK as described above. ---.:
,, . ".

~z~767 0~17 is now entercd for ~he second time. The true signal at the P8 output causes the SS flip flop to be reset rom a 0 to a l state, thereby indicating that this is the second pass through OBl8 et seq. The 1 state of the SS flip flop and the true signal at the SS output causes OB19 to he entered where the state of the SW flip flop is checked.
If the SW flip flop is in a l state, OB22 is entered.
During OB22, the true signal at the P8 output causes the OMl3 output of the OUTPUT MODULE to be true and thereby ~-~
enable the appropriate circuits in the ENCODE MODULE in preparation for causing the ENCODE MODULE to write out the -occurrence value contained in ORTl. The test occurrance value from the reference is still in register ORTl where it was stored during OBl2. -During OB23, true signals are formed at the SS and SW -outputs and the following pulses at CLK causes the logic P8.SS.SW.CLK to become true which in turn forms a true signal at the OMl4 output, thereby calling the ENCODE MODULE.
The true dignal at the P8 output causes the flip flop ; -P9 to be set to a l state and flip flop P8 is reset to a 0 ~
state at the following pulse at CLK and OB20 is entered. -Assuming that the flip flop SS is in a l state, a true signal is now formed by the logic P9.SS causing the output `
circuits OMl7 and OM21 from the OUTPUT MODULE to be true. ; --The true signal at the OMl7 output is applied to the DECODE~ I MODULE, aausing its MLNl counter to be set to the value contained in register ORT2 in the OUTPUT MODULE. ~
(DlFST causes MARl to be reset on the first call to~-DECODE I). It will be recalled that ORT2 contains the length ~
of the revolved line value. Additionally, the - :

- 274 - ~
, true si~nal at the OM21 output sets the DlFST ~lip 10p in the D~COD~ I MODULE. Thus, the DECODE I MODULE has now been set so that its next call will cause it to again start reading the beginning of the revolved line value to use for a further test occurrence value from the reference line.
OBll of the OUTPUT MODULE flow is now re-entered and the true signal at the P9.SS.CLK logic causes a true signal at the OMll output. The true signal at the OMll output causes the DECODE II MODULE to again be called, this time reading out the next test occurrence value from the reference -line designating the next occurrence value in the input line of the iso-entropicgram to be tested (if any). The value is stored in registers ORTl and OR2 during OBl2 as discussed -above for the first test occurrence value from the reference line.
The sequence of operation discussed above is then repeated to determine whether there is an actual occurrence value in the input line of the iso-entropicgram specified by the test value contained in registers ORTl and OR2.
If so, the occurrence value is encoded by the ENCODE MODULE
and stored in the MEMORY MODULE. This operation continues until the last test occurrence value of the reference line has been read by the DECODE II MODULE and processed.
After this occurs, the operation of the OUTPUT MODULE
returns from OB21 to OBll at which time it is found that the EOF2 flip flop in the DECODE II MODULE is in a l state, indicating that the last test occurrence value from the `
reference line has been read. A true signal is now formed at the EOF2 output causing OB27 and OB28 to be entered where the true signal at P6 causes the ENCODE MODULE to ~ ' . .

'' ~Z77~7``

1 be called for the last time and th~ lsst encoded vslue, if any, is stored in the MEMORY MODULE, D. ExamPle of OPeration r~
The following i5 an example o~ the "regular output"
operation of the OUlPUT MODULE, using the example of Table 4-B, Symbolic notation i8 used to indlcate the sequence of operation.
The line value of the ~eed is a~sumed to be in MEMDRY
10 MDDULE area 1 and in hybrid code iY a~ follow3: :
10000111~ occurrence values 7, 6, 3, 2, O, -~
010110015 physical length - 2 :-The following is stored iD the IPRF: : :
- LINE - 7 Jeed line number;
HW - 16 iso-entropicgram widths LNl ~ 2 phy~cal longth of ~eed line value;
TL - 16 top clipping limit; - ;:
. BL - O bottom clipping limlt;
IR - O interval value; `;~ -.
2 DELOP - O DEL funct~on n~t reque~ted. :~ -8equence of control OBl-OB8: -OBl OPSW - O turn off cllpping f/f;
ORSN - O cl-ar; ~ -OHW - HW-16 iso-entropicgram wldth;
O~INE~LINE
- 7 ~--d line number;
: . .082 OLINE f O
:, go to OB3 OB3 DELI(9?~OHM(16) ----OLINE ~7) DELI contain~ the number of line~ ~eed line value must be revolved to get original input;
. . ..

-27~- ~

" llZ7767 t)~l call DELT~ MODULE DELTA MODUL~ generates highest D~O = 8 component power of 2 in 9 which is 8 and DELI contains the remainder of 1 upon return;
OB5 ORSN = DELO = 8 save the result in ORSN;
OB6 call REVOLVE revolve the seed line value down the number of lines remaining in DELI, in this case, generate line 8;
OB7 DELOP = 0 ,-, go to OB8 OB8 DELI = ORSN = 8 turn on the clipping;
call REVOLVE function and revolve down ORSN
OPSW = 1 (8~ llnes; -OB9 O~R = output area which contains the event's original occurrence vector; :
OLN = 3 the length of this area HALT. ~ .

The following is an example of the DEL operation of ::
,' . the OUTPUT MODULE using the example of Table 4-B. Symbolic i ' .~:~
notation is again used to indicate the sequence of operation. ~ ^-The content of IPRF is as follows: -. ,~ ~ . . .. .

:
: ~ - 277 - :
:: :' ': :

/~

~ 1 27 7 6 7 TL ~ 16 BL -- O
S IR ' O
LNl ~ 2 ~--LN2 - 4 phy~ical length of reference line ;-.
DELOP - 1 to ind~cate the DEL function.
MEMORY MODULE area 2 contains the following hybrid coded repre~entation of seed line value: :
10000111 ~ occurrence values 7, 6, 3, 2, O, : ::
010l1001 ~ phy~ical length ~ 2;
MEMORY ~DDUL~. area 1 contains the following hybr~d coded representation of the reference line:
' 15 10001100 0001000 . . , , ., ,, ~,.".
, 10000011 10000000 test occurrence value~ 12, 8, 3, 0 : ` -Intermediate seed line result line 8 of i~o-entropicgram ~rable 4-B):
10001000 ~ .'' ' 01101010 ~ occurrence value~ 8, 6, 4, 2, 1, 0 :
¦ 000001 ) l ngth - 3;

. .,;
.': . ' ',-'.
. . :".
.~
. . .. .
. ' . , ' ....
... . ",:'''.

( ~
l:lZ7767 1 Sequence of control:

OBl-OB6 same as for example of regular output given above, At this point, line 8 of the iso-entropicgram has been generated.
OB7 l)ELOP - 1 .. OB9 OB9 iDitlalize DECODE I, II and ENCODE M~DULES;
. ~J?ST - DZFST = 1 OB10 Set S22 iD SWIT~H ~ATRIX; aQsure DECODE II reads from proper area; : :
MI~2~r0RT3 - 4 length of reference li~e; - :
OBIl call DECODE II read a column index; .
lS D02 - 12 EOFl - O ~co be checked;
'. SS - 1 SW - O ' - ' ' . . 0B12 OR2 - ORTl - 12 save the ~alue read; ~ :
OB13 call DEC4DE I read a value from llne 8 of the DO~. - 8 EOFl ' 0 i80'-eDtropiCgram;
20 OB14 ORl - 8 save it;
OB15 ORl(8)~ OR2(12) ~
go to OB16 . ~ti~ulat- XOR;
OB16 SW,(O) ~ SW,tO) ~OR 6 OB17 SS ~ O
:U OB18 SS - O . 8 to OB24 OB24 OR2(4) ~ OR2(12) - ORSN~8) - .
next position to be checked;
. .
. . ''' :.
~ ~ . . ~ ,, " ~ .
'. . ., . ~ .',.
. -279- `

llZ7767 j ?
. ' ', ,.

1 OB25 OR2(4) > O.'. go to OB20 OB20 SS - O :.go to OB26 OB26 OR2(4) ~ O ., go to OB14 OB14 ORl - DOl - 8 OB15 ORl(8) ~ OR2(4).-. go to OB13 OB13 call DECODE I
DOl - 6 EOFl - O
OB14 ORl - DO1 - 6 OB15 ORl(6) > OR2(4) :,go to OB13 - --10 OB13 call DECODE I
DOl - 4 EOFl - O ~ `~
OB14 oRl ~ DOl - 4 . . . .:
OB15 ORl - OR2 - 4 .go to OB30 ~ -. OB30 SW(l) - SW(0) ~ 1 lS OB17 SS - 1 . OB18 SS - 1 :. go to OBl9 . OBl9. SW - 1 :.go to OB22 .
OB22 EI(12) - ORTl(12) wrlte out the t-~t occurrence ~ ~5 20 OB23 call ENCODE -;
0820 SS - 1 :.go to OB21 OB21 MINl - 3 r~80t the DECoDE I MoDULE;
DlFST - 1 OBll ¢~11 DECoDE II
D02 - a EOF2 - O . :.
OB12 SW - O SS - 1 ~
OR2 - ORTl - 8 :
- ' ' ~.
., ' ' , ,:'', a ' ' .:
, ,. ' ' ' .. -280- -. , . , ; ''.
~ ,. ", ~

c~
~2`7767 1 OB13 ~et DECODE I
DOl - 8 EOFl - O
OB14 ORl - DOl ~ 8 OB15 ORl(8) - OR2(8).-. go to OB30 5 OB30 SW(l) - sw(d) ~ 1 OB17 SS ~ O
OB18 SS - 0, go to OB24 ~`
OB24 OR2(0) - OR2(8) - ORSN(8) ~
OB25 OR2 - O :, go to OB20 ~;
10 OB20 SS ~ O :. go to OB26 ;
OB26 OR2 - O :, go to OB14 OB14 0~1 - 8 OB15 oRi(8) ~ OR2(0) :, go to OB13 OB13 DECoDE I
DOI ~ 6 EOFl - O
OB14 ORl - DOl - 6 OB15 0Rl(6) ~ OR2(0) :,go to OB13 OB13 call DECODE I
DOl - 4 EOFl - O
20 OB14 ORl - DOl - 4 OB15 ORl(4) ~ Oa2(0) , go to OBl3 OB13 cali DECoDE I
DOl - 2 EOFl - O
OB14 oRl - DOl - 2 OBlS OR1(2) ~ OR2~0) .', go to OB13 OB13 call DECODE I
. DOl - 1 EoFl - O -. ' ,~
,, . , ' ' ' ' ' ' ' ' ~ 3a . - -~, ~
. , ~.

~.~Z7767 1 OB14 ORl ~ DOl - 1 OB15 QRl ~ OR2 .'. go to OB13 OB13 call DECODE I
DOl ~ 0 EOFl - 0 5 OB14 ORl - DOl - O
OB15 ORl - OR2 .'.go to OB30 OB30 SW(0) ~ SW(l) OB17 SS ~
OB18 SS - 1 :, go to OBl9 OB19 SW - 0:. go to OB20 8 does not appear as an OB20 SS ~ 1 :. go to OB21 oc~urrence in input line . --OB21 MLNl - ORT2 - 3 reset decode to glve~ point;
. DlFST - 1 -OBll c811 DECODE II
lS D02 - 3 EOF2 - O
: OB12 SS - 1 SW - O
OR2 - ORTl - 3 OB13 call DECODE I -. DOl - 8 EOFl ~ O
20 OB14 oRl - DOl - 8 OB15 ORl(8) ~ OR2(3) .go to OB13 OBl~ - OB14 - OB15 ~ loop repeat8 untll th~ 2 ~
. sead from th~ ~Jo--ntropicgram . . ~ne number 8s ~:
. ~2S OB14 oRl - DOl - 2 081S oR1(2) ~ 0R2~3) . go to OB16 . . .. --: .
: . . ' ' ' ' ' - ' . , ' ' " ' ' .
~ 3a . . . .
. ' , 1~7767 1 OB16 SW(O) ~ SW(O) 0 p OB18 SS - O .'.go to OB24 OB24 Oa2(-5) - OR2~3) - ORSN(8) if OR2 19 negativo, then 5 OB25 OR2(-5) ~ O :. go to OBl9 we need not oonsider OBl9 SW - O .'. go to OB20 further;
OB20 SS - O .', go to OB26 OB26 OR2(-5) < O :,go to OB21' OB21 MLNl - ORT2 ~ 3 10 OBll call DECODE II
Do2 - O EOF2 - O

OR2 - ORTl - O
OB13 call DECoDE I
lS DOl ~ 8 EOFl - O ~
OB14 ORl - DOl - 8 ~-OB15 ~R1(8) ~ oR2(0).-. go to 0813 OB13-OB14-OB~5 tho DECaDE I loop rapeat 8 until the ~ value i8 read 20 OB14 ORl - DOl - O
OB15 oRl(O) - oR2(0) :. 8 to OB30 ~ -OB30 SW(l) - SW~O) e i OB18 S8 ~ O :, go to OB24 -OB24 OR2~-8) - oR2(0) - oRSN(a) OB2S OR2~-8) ~ O :.~o to OBl9 : - ' . ' , ' , ' '~", ".
'~' . ' ' ' "'~
` ~a ; . ' ' . , ' ~., ' (~
llZ7767 l OBl9 SW ~ l :.go to OB22 OB22 EI - ORTl -.0 OB23 call the ENCODE MODULE
OB20 SS - O :. go to OB26 S OB26 OR2(-8) ~ 0:- go to OB21 OB21 MLNl - ORT2 - 3 reset DECODE I;
DlFST - l OBll call DECODE II - ;
DO2 - O EOF2 - 1 .'.go to OB27 ~-10 OB27 set ELAST -.
OB28 call ENCODE
OB29 oAR - output area written by ENCODE
OLN - length of th~s area HALT
. ~5 otrrPuT aAR _ , .
OLN as descrlbed above ~

actual output 10001100 12 ::
. . 10000000 0 ~.
The ~08~ occurrence values stored in the ~EMORY MODULE
20 output area 1, in hybrid code, are now a8 follow~: :

. 10001100 (oaou~rence values of 12) --10000001 (occurrence value of 0) Thl~ indicates that of tost occurronc- valuos 12, 8, 3 and 0, 2~ ln th r-feronc- lln , only 12 and 0 appoared ln tho orlglnal lnput lin- of tho l-o-ontroplcgram.
. , ~ ' , ' :

. .' ~. -284-. ~Z7767 f 1 X1V. DATA CO~ACTION AND RETRIEV~L MACHDNE
It will be recognized from the foregoing description of the SEED MODULE and OUTPUT MODULE in con~unction with the REVOLVE, DELIA, ENCODE, DECODE I and II MODULES depicted in S Fig. 34, that a data compaction and retrieval machine has been disclosed. The data compaction retrieval system forms a sub-part of the overall DPM SYSTEM. The data compaction and retrieval system has several features. Specifically, the OUTPUT MODULE in con~unction with the ENCoDE, DECODE I, 10 DECCDE II, REV~LVE and DELTA MNDULES, forms an output machine which retrieves compacted information that has been retrieved ineo iso-entropicgram form of representation. ~-Specifically, an electronic data processing systemis disclosed for retrieving a desired coded signal from a representat~on in the form of a line value signal, a line numSer signal and a length signal. The line value signal represents a line of an i~o-entrop~cgram, eliminatlng ~-leading zeros. The line number designates the line in the iso-entropicgr~m for the line value Jignal. The length ~ignal 13 equal to the width of the iso-entropicgram which in turn is equal to the length of the line valuo signal without excluding leading zeros. So as not to confuse the length with the storage space, the length signal would be ~qual to the total number of po~sible occurrence values 2S in the 11ne of the ~so-entropicgram which in turn is equal to the largest possible occurrance value in a line of the 1so-entropicgram~ The data processing system in~ludes a memory, ~uch as the MEMDRY MODULE, for storing the line ; value sig~al. Mean~ such as the OLDNE register of the 3~ OUTPUT MDDULE ~tores the line number signal. Means such as I
-2~5-.'"', 'i ' ., :,' "~ ,"' ~

l~Z7767 1 the OHW register of the OUTPUT MCDULE stores the length signal. Means such as the ALU of the OUTPUT MODULE forms a difference signal corresponding to the difference in values represented by the ~tored line number signal and the stored length signal. Means such as the REVGLVER, discussed hereinabove, responds to the provided line Yalu~ signal and a provited number signal for forming any one of a set of equivalent signals. The set includes the line value signal.
Each equivalent signal within a set is unique and i8 related to another one by an exclusive OR of the values thereof, and the values thereof relative shifted. The formed equivalent slgnal represents the desired coded signal. Means such as the DECODE I and II M~DULES
proviaes a line value slgnal to the means for forming a equivalent signal which corresponds in value to that stored in the memory means. Means suoh as the DELTA ~ODULE provides to the means for forming an equivalent signal i number value signal corresponding in value to that of the difference signal. ~-The ENOODE M~DULE prov~des signals from the memory means ~MEMDRY NODULE) to the equivalent signal formlng means QKEVO~E~). The means for providing a number valu~
signal, i.e., tho DEITA M~DULE, comprises meanJ for forming as the number value signal one or more signals representativ-of ~ compon~nt powers of 2 of the difference Jignal.~
Pr~ferably, the equivalent signal formlng moans, i.e., the REVOL~ER, includes means such as the ALU REVOLVE MODULE
for comblning the provided number ~ignals with the provided line value s~gnal to form a further signal which corresponds to th- shifted signal.formed by tbe REVOLVER. Additionally, the ALU and aJ~ociated logic ~Eorm.a mean~ for combining the . ', .~ `.
. -286--~
11;~7767 1 line value signal and the further signal to form the equivalent signal. Pre~erably, the line value signal has on~ or more actual occurrence value signals out of a group of possible occurrence value signals. The pos~ible S and actual occurrence value 8ignal~ are arranged in aD
~ncremRntal, preferably increasing incremental, value order.
With such a signal representation the mean~ for forming an equivalent signal includes means such a~ the ALU of the REVOLVE MODULE for combining the value repre~ented lO by the provided number value signal with each of the ~-value~ represented by the occurrence value signals of tbe line value to form a further signal, and the ALU
and associated control and logic of the XEVDLVE MDDULE
form a means for exclus1ve ORing the value~ represented lS by the provided line value signal and the further signal to fo~m the equivalent signal.
It will be recalled that in the REVOLVER the means for exclusive ORlng involves the ALU control and logic of the REVDLVE M~DULE for sorting the occurrence value signal~
represented by the provided line value signal and the further signal into an incremental value order.
Additionally, those occurrence value signal~ which are qual are deleted. Th- ALU control unit and a~sociated logic of tho REVOLVE MODULE sort the values representing thQ further~ignal and the ocourreno~ valu~ signals from the provided line value signal to form a series of ~occurrence value signals arranged incrementally ~n the order of the values thereof. Dur~ng the psoce~s of ~orting, those occussence value signal~ which are outside of the width of the iso-entropicgrsm, ~.e., not among the -~
possible occurrence values, are eliminated. `-.....

2~767 1 As indicated above, the SEED MODULE ~nd OUTPUT MODULE
in association with the other modules of Fig. 34 orm a data compaction and retrieval system. The data compaction and retrieval system is actually an electronic data processing system for both compacting a coded signal and for retrieving a compacted ~ignal. Included in this system is a memory means such as the MEMORY MODULE for storing and making available coded 8igaal8 for compaction and retrieval. Means such as the REV~LVER of Fig. 19 respond to a 10 codedsignal and a provided number signal for forming any ` --one of a ~et of equivslent signals~ The ~et includes the coded signal. Each equivalent signal within a set is unique and related to another one by an exclusive OR of ~he values t~ereof and $he values thereof relat~ve shifted.

Decode means such a~ the DEOODE I and II MDDULES decodes a co~ed ~ignal for eompaction or a coded signal for retrieval from the memory means from a first eode to a second expanded code for the means for forming equivalent signals. In this connection it will be recalled that the DECODE MODULES deeode oeeurrenee vectors from hybrid eode to the expanded absolute coded form represent~ng oeeurrene~ values. Eneode mean~, such as the ENCODE M~DULE, eneodes the equivalent signal from the second eode to the f~rst eode for storage ~n the memory means. Means ~ueh a~ the SEED MODULE 1~ respons~ve to at least a portion of the deeoded signal for eompaetlon for ~orming a total Dumber value signal whieh represents a quantity of the equivalent ~ignals. In this connection the larger of the largest and next large~t oecurrence value differenees stored in the register Tl designate~ the total number of .~ . ' ' , . ' ' ' ' ' (~

llZ7767 1 lines by which a revolv~ is to be taken.
Means such as the OLINE register of the OUTPUT MODULE
stores a line number s~gnal sssociated with a coded signal for retrieval. Means such as the OHW regi~ter of the S OUTPUT MODULE stores a length signal assoclated wi~h the stored line number signal. The OUTPUT MODULE forms a means for forming a different ~ignal representing the difference in values of the stored line number signal and the stored length ~ignal. Means ~uch as the DELTA MODULE provides the number signal to the equivalent signal forming means ~REVDL~ER).
Specifically, the DELTA M~DULE forms a means which is responsive to either the total numbor value signal, for a compaction, or the difference signal, for a retrieval, for forming, corresponding thereto, the number signal.
In this connection the number signal is one or more signal~ -representing the component powe~s of 2 of the total num~er valuo signaI or the difference signal.
Preferably, the compaction and e~pansion provided by the DECODE I and II and ENCODE M~DUIES are provided in the system. ~owever, thls further compaction would not be essential within the broader concepts of the pre~ent invention. In thl~ connectlon then the DECODE I and II
and ENCODE MODULES form, ~roadly, a mean~ for providin~ cod~d ~lgnal~ corre~ponding to tho~- available from tho m~mory 21 m~ans and corresponding to those from th- mean~ for forming oquivalent signals to the other.
Th~ OUTPUT MODUiE in con~unction with the REVOLVE, -DEOODE I and II, REVO~VER, DE~TA and ENCODE MODULES, provide the DEL funct~on described above. The DEL function allow~
a test to be mad- to determino whether an actual ocourrence ' . ' ~
-289- ~

( ~:) ( J
-~
~Z~67 1 value is present in an input line of an iso-entropicgram given one of the non-input lines. Broadly, the steps include the steps o~ forming a line representing the non-input line.
The formed line signal represents one or more actual occurrence values of the possible occurrence values making up each line of an iso-entropicgram. This step corresponds to OB6 of the OUTPUT MODUhE flow. During 0~5 of the OUTPUT MODULE flow a length signal i~ formed representing the number of lines of -displacement in the iso-entrop~cgram between the non-input 1 line and the input line. A test signal is formed during OB12 representing the value of an absolute occurrence value in the input line to be checked for presence. The test signal corresponds to an occurrence value in a test vector.
During OB~4 the value- represented by the te~t signal 1 and the length signal are combined to form a further test ~ignal identifying a further occurrence ~alue for tast. ~his ~_ep corresponds to forming a further one of the occurrence values in one of the lines of the inverted DEL ~Table 9-C).
During~OB15 in the first pass, the value of the test signal is compared with the values of the formed line signal for equality, i.e., a predetermined relation. During OB15 in the second pass the value of the further test signal is compared with the values of the formed line signal for oquality, also a predetermined relation. A prodetormined 2 signal ls formed during OBl9 by causing the flip flop SW to be in ~ 1 state responsive to the results of both of the~e 'tests of comparing. When the 8W flip flop is in a 1 state following both comparison~, the occurrence value specified by the test signal is present in the input line. Due to 3C the exclusive OR gating to the input of the SW flip flop ~ llZ7767 1 detection of equality in one step of comparing and the detection of inequality in the other step of compar~ng is required for the flip flop SW to end up in a 1 ~tate and thereby indicate the presence of the occurrence value at the input line. If both tests produce equality or inequality, the SW flip flop ends up in a O state, thereby -indicating the lack of the presence of the occurrence value in the input line.
In terms of the system, involving the DEL function, an electronic data processing system is di~closed for checking for the presence of an actual occurrence value out of a ~eries of possible occurrence values arranged in an incremental value order. The checking is for the presence of the actual occurrence value in the input value line of the iso-lS entropicgram utilizing one of the non-input lines of the same iso-entropicgram. There is di~closed memory means such as the MEMORY MODULE for ~toring a line value signal representat~ve ;
of a non-input line. Means such as the OLINE register stores a line number signal corresponding to the stored line value ~0 signal. Means such as the OHW register store~ a length -signal. Means such as the A~U of the OUTPUT MODULE forms a difference signal corresponding to the difference in values represented by the stored line number signa? and the stored length ~ignal. Means such as the REVOLVER respond~ to a provided line value ~ignal and a provided number signal for forming any one of a sQt of equivalent signals. The set includes the line value signal. Each coded signal within a s-t is unique and related to another one by an exclusive OR
of the value~ thereof and the value~ thereof relative shifted.
3C . ' ' ' , ' .`' .:~, ' .' ' ,.
-291- ~-(~

~127767 1 Means such as the DELTA MODULE respondg to the difference s~gnal for forming a first signal representing the largest component power of 2 of the difference and for forming a second signal representing the remaining component power of 2 of the difference. Means such as the ORSN register in the OUTPUT MOD~LE stores the largest component power of 2 signal.
The DELTA MODULE provides the remaining component power of 2 signal and the line value signal to the means for forming an equivalent signal ~EVO~VER) thereby causing an equivalent signal to be formed. Means such as the ORTl register forms a means for storing a test ~ignal representing the value of the absolute occurrence value in the input line to be checked for presence. Means such as the ALU of the OUTPUT
MODULE forms a means for combining the values represented by ' 1 the test signal and the length signal to form a further test signal identlfying a further occurrence value for test.
Means such a~ the A~U of the OUTPUT MODULE compares the value -, ¦ of the test ~ignal with the value of the formed equivalent signal for a predetermined relation. The ALU and the a~sociated timing and logic additionally forms a means for comparing the value of the further te~t ~ignal with the ~ ' v~lue~ of the fonmed equivalent signal for a predetermined r-lation,. Nean~ ~uch a- the SW flip flop i~ operative ¦ during OBl9 ~nd re~pon~ive to the re~u$ts of both of the predetermined relation- to ther~by indicate the pre~ence of an actual occurrence value in the input line corresponding to the test signal.

' , , ~ ' .
30 I . ' :'.
. . , , ' .
I -292- ' -(~
-~

~ 7~67 _-A. General Description The general purpose of the PIPE MODULE is to help in the process of locating requests for data out of a large mass of data provided in the data base. The data base disclosed herein is arranged, by way of example only, into paragraphs, each of which in turn contains sentence~, each of which in turn contains words, each of which in turn contains characters. The request may be a word, a phrase, a sentence, or a paragraph.
If a request is always in the data base exactly, it is no problem to retrieve the requested information from the data base. The inexactness between the request and the data base may come about because of mis~pe}ling of words, ~- -transposing of words, or may be caused ~ust by a lack of 15 knowledge by the requestor a~ to the exact wording in the data base. For example, the request word ~SITN may be a misspelled word such as "THIS~. Problems arise where there i~ an inexact relation between the request and the data base. -- -The PIPE MODULE and the BRIGHTNESS MODULE cooperate in 20 locating those requests which are exactly or inexactly contained in the data bas-.
The purpose of the PIPE MODULE then is to deter~ine whether the request is located in the data base exactly ~r inexactly. To lo¢ate inoxa¢t requests from the data base, tho 2S PIPE MODU~E requests or determine~ which entries ~occurrences) in the data base oould be uf3ed for further ~election criteria ~ -employed by the BRIGHTNESS MODULE. Thus, the PIPE NODULE ;~-selects those entries in the data base which would be candidates --for processing by the BRIGHTNESS MODULE. These candidates are then used by the BRIGHTNESS ~ODULE to select the best possible candidate for the request. ~-~

-293- ~

~127767 1 ~efore considering the theory of the PIPE MODULE, the following terminology should be carefully noted. An "event" is composed of primitive elements which lie between two ~delimiters". For example, in the letter layer 0 of Table 1, the events are letters. "Event time", also called ~possible occurrence positionn, identifies a possible relative position or value in a data base for an event or delimiter occurrence value. An "event occurrence vector" represents event occurrence values, each of which identifies the event time at which an event has occurred. An "entry" is a series of primitive elements, i.e., letters which lie between two delimiters which identify the beginning of two successive entries. For example, in the letter layer 0 an entry such as ~T~IS~ is a word composed of a series of letters between the two delimiters positioned at event times 0 and 5.
Considering the theory of the PIPE MODULE in more detail, the PIPE MODULE employs a selection criteri~ for indicating to the requestor those possible entries in the dsta b~se which might be a response to a re~uest. Two selection criteria are employed by the PIPE MODULE and are as follows.
The fir~t selection criteria is a ~pipe width~ (PW).
Tho pipe width 1s an offset value which identifies how far to the right or to the~left ~ahove or below) each particùlar possible occurrence value an actual occurrence value may lie for purposes o~ the piplng function. Those whlch fall vithln + the ~pipe width~ ~PW) are called ~hits~.
.
,.

a . '.''~.
~ . -294- ` ~
,...

, ~

(-~' f`
~Z~767 1 The second criteria is the relationship of the length of the request ~LN~Q)'to the number of hits within each entry in the data base. The second criteria is important in determining a meaningful number of hits in a data base entry before the entry should be considered as a candidate for the BRIGHTNESS MODULE function~ The relationship between the length of the request ~LNRQ) and the number of hits is determined by a "threshholdn . value which represents the minimum number of hits before -.10 a data base entry is con~idered by the BRIGHTNESS MODULE
for processing.

3a ,/ - - - , ...
'.'' .' ' , ~277f~7 1 The importance of the ~econd criteria becomes evident by considering the following example. Assume the data base contains the word "THIS" and the request word i9 "BIG". It i5 apparent that the I in BIG lies at a position within -1 of the position of the I in THIS. Bowever, it i~ quite apparent that one would not select the word THIS to be sent to the BRIGHTNESS MODULE since there are four entries in the word THIS and only one hit. -' The rest of the theory of the PIPE MODULE is best understood by reference to an actual example. Assume the data base depicted,in Table 1. Also assume a reque t ~ ' ' occurrence vector THIS. The first step is to pull out the event occurrence vectors for the events T~IS from the data base of Table 1. Table 18 sets out the decimal values of the event occurrence values for each of the events THIS. Table 18 also shows the event occurrence vectors for THIS lifted out from the data base of Table 1 in columnar notation. Table 18 on the right ~ide show~ the actual occurr-nce values, in decimal form,, of the event occurrence values in each event. The f~rst step is to find out whether the reguest is in the data base exactly or inexactly. To this end, ~bias~ values are ~ssigned to the event occurrence vectors identified by a request. Incre~sing valued bias values are assigned -to the event occurronce vectors starting wlth the numbor 0.
For example, in the reguo~t word THIS, the event occurrence vectors for the events T R I S are ,~
~e-pectively a signed b~as values 0, 1, 2 and 3. The bias values are then ubtFacted from event occurrence values in `30 . ~ .. ' .~ . ' . "
-29~- ,, ~Z77~7 the corresponding event occurrence vector. The results are "biased event occurrence values".
Table 19, in columnar notation,depicts each event ccc~rrenoe value in the data base of Table 18, decreased by its bias value.
Thus, the bias value for the event "t" is 0 and the correspond-ing event occurrence values remain unchanged. The bias value for the event "h" is 1 and the corresponding event occurrence values are decreased by 1 or moved left one place. The bias value for the event "i" is 2 and the corresponding event occurrence values are decreased by 2 or moved left two places.
The bias value for the event "s" is 3 and the corresponding event occurrence values are decreased by 3 or shifted left three places. -It will now be apparent with reference to Table 19 that each of the event occurrence values between the delimiters for -event time 0 and 5 will be shifted so that they line up at event time 1. This then gives four hits in event time 1 which is :
exactly the length of the request word "this". Therefore, -~
, . -.':
an exact entry exists in the data base for the request word :-"this". It should also be noted that the biased occurrence -values for the word "this" in the datà base are all lined up at event time 1 which is just one event time away from the delimiter in event time 0 and are therefore associated with ~
the beginning delimiter at event time 0. The resultant biased -event occurrence values are depicted at the right of Table 19 ;~-in decimal form. -Consider now another example where there is an inexact match between the request and the data base. Assume that the request is the word "SIT". First, the event occurrence vectors for the delimiter and the events S, I and T are pulled out of the :

~' ' -.
:, ~i ~) ~27~67 1 data base of Table 1 as depicted in Table 20. The right hand side of Table 20 depicts, in decimal form, the event occurrence values in the event occurrence vectors for the events S I T.
Next, the bias values 0, 1, and 2 are assigned for the events 5 S I T and the bias values are subtracted from each of the -occurrences in the corresponding event occurrence vectors.
Thus, the bias value for the event S is 0 and the corresponding event occurrence values remain unchanged. The bias value for the event I is 1, and the corresponding event occurrence values are decreased or shifted to the left by 1 and the bias value 2 for the next event is 2 and the corresponding event occurrence values are decreased or shifted to the left by 2.
The resultant biased event occurrence values are depicted -~
in decimal form on the right side of Table 21.
With respect to the event T, it should be noted that the circled occurrences were bia~ed or shifted below the beginning delimiter for their entry. It is necessary to tag or ~omehow identify each event occurrence ~alue which is shifted past th corresponding beginning delimiter and hence no longer represents the entry in which it origlnally appeared.
It is now necesRary to sati~fy the second criteria, that -i8 ~ to rel~te th~ length of the request (LNRQ) to the number of hlts in the data ba~e. Thi- 1- accompli~hod by as~umlng a ~total pipe ~idth" of twice the ~pipe width~ (PW) and 25 associating the center of the ~total pipe width~ with the ;
rightmost event time in the entry under consideration; counting the number of hits within the ~total pipe width~; retaining the number of hit_; and mGving onto the lower event times to the left, one by one, and for each event time, counting the number of hit_ within the ~total pipe widthn.
:` ..
-~98-f'~

li27~7 1 Using the biased event occurrence values of Tables 21 and 28, the first test is made on the biased event occurrence values appearing between event times 10 and 15. The test is depicted in Table 22. It is assumed that the "pipe width"
(PW) is 1, and hence the "total pipe width" is 2. Thus, the test starts with event time 14 and the possible biased event occurrence values between + 1 of 14 are checked. It will be noted that there is a biased event occurrence value at event time 13 for the event S, hence there is a hit value of 1 for event time 14. Event time 13 is then tested. Thus, in effect, the ~total p$pe width" is slid one place to the left so that -it is now centered on event time 13. Again, the number of hits within the ~total pipe width~ are computed. There is a hit -for the event S at 13 and a hit for the event T at 12 and ;
15 hence the number of hit~ for event time 13 is 2. This same `
process 1s repeated for event ~imes 12 and 11, resulting in hits of 2 and i for event times 12 and 11. :-For simplicity, if two pipe center~ are found with the . .....
same number of hits, the first one encountered is selected as 2 the center. Thus, with reference to the lower part of Table 22, event time 13 is selected as the one with the largest number of hit~. To be explained in more detail, these values are sent to tho BRIGHTNESS MO~ULE for processing.
~vent time 10, containing a delimiter, is ~klpped, and 2 event time 9 is next selected as the next plpe center.
Referring to Tables 1 and 23, it will be ~een that this portion of the data base deals with the word ~a~ and there are no hits for the request S I T.
Referring to Tables 1 and 24, the pipe center i8 next slid over the delimiter 8 and tests are performed at event ' '. '',"','~:

. 299 1~7~67 1 t.~mes 7 and 6. Two hits are found for the center at event time 6, whereas only 1 is found at event time 7. Event tlme 5 i8 skipped over and event times 4, 3, 2 and 1 are elected as centers. It will be noted that for the center at event time 3, 2 hit~ are again found. It should also be noted that for each of the tests depicted in Tables 22-25, the occurrence value in the ending delimiter had no effect on the rightmost pipe test.
The reason for this will become elear when considering the operation of the PIPE MODULE. The three entries for the word~ :
"test", "isN and "this" are then passed to the BRIGHTNESS
MODULE whieh makes a decision a~ to whieh is the best hit for the request S I T. Before considering the operation of the BRIGHTNESS MODULE, eonsider in more detail precisely how . the PIPE MODULE earries out the foregoing operation. .. .
Within the concepts of the present invention, it is ~ ~.
possible to form a mcdule that operates in parallel and looks .. v rtieally down aeross eaeh entry in a data base array such a~ that in Table 1. The diselosed ~mhodiment of the present ~.
invention involves a PIPE MODULE which does not look down 20 vertically across each entry but 1nstead looks at the entries ~erially by occurrence value and entry. To this end, the PIPE MODULE is arranged to keep traek of the left shifted or biased event oeeurrenee values. This i~ accomplished by atoring in the PIPE/BRIGHTNESS MEMORY, ~P/B MEMORY) eàeh different biased oecurrenee value and a ~hit eount~ equal to the number of times the biased event oeeurrence value occurs.
In other words, in subtraeting the bias value from each event oecurrence value in the same event oeeurrenee veetor, the same ~.
biased occurrenc~ value may occur more than once. By ~toring 3~ each different biased event occurrence value and its hit count, : -300-~27767 1 it is E~os~.ible to )ccep tr.~ck o tlle number of times it ha~
occurred simply ~y ur~L~in~ the hit count by 1 wh~ncver a further one is encount~red.
Referxing to the example shown in Table 19, the following will be noted. At event time 1, the biased event occurrence value for the entry "THIS" are all lined up at event time 1 and hence -- ,'-, event time 1 can be assigned a maximum hit count of 4. It will ,-~' "
also be noted that the length of the request (LNRQ) for "THIS" ~ -is 4 and therefore is exactly the same as the hit count. This '---10 indicates that the entry appears exactly in the data base. -~
Thus, instead of placing one row beneath the other as depicted in Table 19, the PIPE MODULE disclosed herein utilizes the , approach where information is represented by biased actual event -~--occurrence values and hit counts., One further condition should ' ' 15 be noted. If the biased event occurrence value is less than , , or passes across a beginning delimiter for the corresponding entry, a decision is made as to whether it is included or is -' -~
not included wlthin the corresponding entry. For example, ' in Table 21, the biased event occurr~nce values -1 and 9 for the event T are less than the beginning delimiter values 0 and 10, respectively. A rule has been laid down that if a ,' biased event occurrence value lies within the "pipe width~
of the lowe~t event occurrence value in an entry and its ''~
value i~ less than the beginning delimiter for the corresponding entry, then use a biased occurrence value equal to the beginning delimiter for the entry. This i9 an artificial value which ~' avoids computational problems relating to those biased event ' occurrence valucs which slide into another entry from their original entry. ~ ' 3 ~ ,~
,: , -301- ,,", ,',"'::`

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Claims (10)

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. An encoder for converting to hybrid form a received series of absolute words in a decreasing value order comprising:
a) means responsive to received previous and current absolute words for forming an output signal indicative of the difference therebetween;
b) means for indicating absolute or bit string form of hybrid output comprising 1) means for indicating a preselected minimum difference between successively received absolute words for absolute form of output, 2) means for comparing the minimum difference indication and the previous and current difference signal and for indicating the value of the first being greater than, or less than or equal to the latter;
c) means for providing absolute form outputs comprising 1) means operative in response to said less than or equal to indication for outputting the stored current absolute word and an absolute flag; and d) means for providing bit string form outputs comprising 1) means responsive to said greater than indication for forming a set of ordered signals comprising a binary bit of one value separated by the number of binary bits of a second value corresponding to the value of said previous and current difference signal, and 2) means for selectively outputting said set of signals in association with a bit string flag and in a predetermined relation to an outputted absolute word.

2. An encoder for converting to hybrid form a received series of absolute coded words in decreasing value order, comprising:
a) a current register for storing a currently received absolute word;
b) means for storing a received absolute word in said current register;
c) a previous register for storing a word received prior to the word in said current register;
d) means for transferring a word from said current register to said previous register;
e) means responsive to the stored previous and current absolute word for forming an output signal indicative of the difference therebetween:
f) means for retaining the previous and current difference signal;
g) means for indicating absolute or bit string form of hybrid output comprising 1) means for indicating a preselected minimum difference between received absolute words for absolute form of output, 2) means for comparing the minimum difference indication and the retained previous and current difference signal and for indicating the first being greater than, or less than or equal to, the latter;
h) means for providing absolute form outputs comprising 1) means responsive to said greater than indication for outputting a signal representing the stored current absolute word and an absolute flag; and

Claim 2 cont'd i) means for providing bit string form outputs comprising 1) means responsive to said less than or equal to indication for forming a set of ordered signals comprising a binary bit of one value separated by the number of binary bits of a second value corresponding to the value of said retained previous and current difference signal, and 2) means for selectively outputting a signal representing said set of ordered signals in association with a bit string flag and in a predetermined relation to an outputted absolute word.

3. The encoder of claim 1 wherein the hybrid form comprises a series of words and said means for forming a set of ordered signals comprises:
a) counter means;
b) a bit string word forming register;
c) means operative in response to said indication for enabling said counter means to count through a sequence of states corresponding in number to the retained current and previous difference signal;
d) means for indicating completion of the last mentioned counting;
e) means for shifting the content of said bit string forming register one bit position in the direction of the least significant bit thereof for each said last mentioned counter means states; and f) means responsive to the last mentioned completion signal for inserting a bit signal of predetermined value at the most significant end of the bit storing register content and wherein said means for outputting comprises means for selectively outputting the content of said bit string word forming register.

4. The encoder of claim 3 comprising means for entering a first occurrence in a new bit string word under formation comprising:
a) means for storing a signal representing the number of binary bits remaining to be filled in a bit string word being formed;
b) combining means for forming a signal representing the difference between the value of the remaining number of binary bits to be filled signal and the previous and current difference signal;
c) means for comparing the value of the previous and current difference signal and the remaining binary bits to be filled signal for indicating the first is greater than or equal to, or less than the latter;
d) means responsive to said less than indication for retaining the difference signal from the combining means as the number of bits needed in the next bit string word to enter the current absolute word;
e) means operative in response to said greater than or equal to indication for enabling said counter means to count through a sequence of states corresponding in number to the retained number of bits needed in the next bit string word signal;
f) means for indicating completion of the last mentioned counting;
g) means for shifting the content of said bit string forming register one bit position in the direction `
of the least significant bit thereof for each said last mentioned counter means states; and h) means responsive to the last mentioned completion signal for inserting a bit signal of predetermined value at the most significant end of the bit storing register content.

5. The encoder of claim 3 comprising means for filling out the bits of a bit string word being formed when no further occurrences can be entered therein, comprising:
a) means for storing a signal representing the number of binary bits remaining to be filled in the bit string word being formed;
b) combining means for forming a signal representing the difference between the value of the remaining number of binary bits to be filled signal and the previous and current difference signal;
c) means for comparing the value of the previous and current difference signal and the remaining binary bits to be filled signal for indicating the first is greater than. or equal to, or less than the latter;
d) means operative in response to said less than indication for enabling said counter means to count through a sequence of states corresponding in number to the value of the stored remaining binary bits to be filled signal;
e) means for indicating completion of the last mentioned counting; and f) means for shifting the content of said bit string forming register one bit position in the direction of the least significant bit thereof for each said last mentioned counter means states.

6. An encoder according to claim 2 having a clipping means, the clipping means comprising:
a) means for storing an upper limit value and a lower limit value; and b) means for comparing a current absolute word with said upper and lower limit values and indicating if the current absolute word is out of the bounds defined by the limit values.

7. An encoder according to claim 6 comprising an interval adjusting means comprising:
a) means for storing an interval value;
b) means responsive to an indication that the current entry is out of bounds for incrementally changing the stored upper and lower limit value by the value of said stored interval value; and c) means for enabling said comparing means to repeat the comparing, using the incrementally changed upper and lower limit values and current entry.

8. A decoder for converting hybrid coded signals to absolute coded word signals, the hybrid signals represent-ing a series of occurrence values of decreasing value, the hybrid signals comprising a series of received binary coded word signals including at least one absolute coded word and a bit string word, the bit string word represent-ing an occurrence by the number of bits of displacement of a bit of predetermined value from an absolute word in the series of hybrid words, a hybrid word comprising a flag signal indicating the type of word, comprising:
a) absolute word outputting means comprising means responsive to an absolute word flag signal of a received hybrid word signal for outputting the received word signal; and b) absolute word signal forming and outputting means comprising 1) means responsive to an absolute word signal and each said bit of predetermined value in a subsequent bit string word signal of a received hybrid signal for forming an absolute word signal indicative of actual value of each said bit of predetermined value, and 2) means for outputting each said formed absolute word signal.

9. A decoder for converting hybrid coded signals to absolute coded word signals, the hybrid signals represent-ing a series of occurrence values of decreasing value, the hybrid signals comprising a series of received binary coded word signals including at least one absolute coded word and at least one bit string word, the bit string word representing an occurrence by the number of bits of displace-ment of a bit of predetermined value from an absolute word in the series of hybrid words, a received word comprising a flag signal indicating the type of word, comprising:
a) absolute word outputting means comprising means responsive to an absolute word flag signal of a received word signal for outputting the received word signal; and b) absolute word signal forming and outputting means comprising 1) shift register means for storing a received bit string word signal, 2) means for repeatedly enabling the shifting of the content of the shift register means one bit position in the direction of the least significant bit of the bit string word signal, 3) means for providing an indication when a bit signal indicative of said predetermined value arrives at a preselected position with respect to the shift register means, 4) counter means, 5) means responsive to a flag signal indicating a received absolute word signal for setting (Claim 9 Cont'd) said counter means to a state relative to a reference state corresponding to the value of such absolute word signal, 6) means for enabling said counter means to count one state towards said reference state for each such shift of said shift register means, and 7) means responsive to said indication of a bit for outputting a signal corresponding to the state of said counter means.

10. The decoder of claim 9 wherein the absolute word forming means additionally comprises means for adjusting said counter means for bits, not of said predetermined value, which remain in said shift register means after the last bit of predetermined value in a received word comprising:
a) additional counter means;
b) means for indicating the maximum number of bits in an absolute word for output;
c) means for selectively setting said additional counter means to a state relative to a state corresponding to said indication of the maximum number of bits in an absolute word;
d) means for enabling said additional counter means to count one state relative to the set state thereof towards said reference state for each said shift of said shift register means;
e) means for providing an indication of the occurrence of said reference value of said additional counter means;
f) means responsive to the flag signal of a received bit string word signal and the lack of the last mentioned indication for further enabling both said counter means and additional counter means to count toward the reference states thereof; and g) means responsive to the last mentioned indication for terminating further enabling of count of said counter means and additional counter means.