CA1123107A - Data processing apparatus and method with encoded system bus - Google Patents

Abstract

ABSTRACT OF THE DISCLOSURE
A data processing apparatus including a processor unit and one or more storage units, and input/output control-ler units by a common system bus. The system bus includes a system operation code field and an associated system informa-tion field. A system operation code is encoded to designate the function and nature of the information in the associated system bus information filed. Synchronous clocking is typi-cally employed on the system bus to insure time synchroniza-tion throughout the data processing apparatus. The system operation code represents many different types of information.
For example, when the system bus is connected for transfers between the storage unit and other parts of the system, the system operation code is encoded to specify that the associ-ated system information field contains either a storage unit address or storage unit data. Access control apparatus is provided for allocating access to the system bus among the various units connected to the system bus.

Description

BACKGROUND OF THE INVENTION
The present invention relates to the field of in-struction-controlled digital computers and specifically to the system hierarchy and the interconnection of the basic units forming the data processing system.
Instruction-controlled digital computers operate upon data to carry out desired data manipulations. A group of instructions form a program. The program normally has its instructions sequentially executed, one or more at a time, to carry out a complete data manipulation.
High-speed data processing systems generally in-clude one or more storage units for storing data and instruc-tions, a channel apparatus for communicating with input-output devices, a console for operator communication with the data processing system, and a processor for instruction handling and execution.
In typical data processing systems, information is supplied to and from the input/output devices from and to the remainder of the system through a storage unit. Instructions are fetched from the storage unit by the processor unit. The fetched instructions are decoded to form control signals for controlling the execution of the instructions and for control-ling various parts of the system. During the execution of instructions, additional information may be transferred from or to system storage units to be used in the data manipulation specified by the ;.nstructions. The results of data manipula-tions are typically placed back in the storage unit and com-municated to input/output devices.
In establishing a hierarchy for data processing sys-tems, economy of cost and speed of performance are paramount A-33069/DEL -2- ~

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considerations. Additionally, flexibility of system operation is important in order to permit the system to be compatible with previously designed data processing systems as well as to be compatible with future systems yet to be designed. The cost of the system is related to the number and type of cir-cuits employed and the performance of the system is related to the speed with which the system can execute groups of instruc-tions or programs. The cost/performance ratio is a measure-ment representing the merit of the system. ~he lower the cost/performance ratio, the greater the merit of the system.
Data processing systems are made to operate faster to achieve higher performance by employing faster circuits, but faster circuits are generally more expensive than slower circuits. Data processing systems also are made to operate faster to achieve higher performance by employing a plurality of units operating at the same time. In general, the more operations which can be simultaneously performed, the greater the speed with which the data processing system can execute groups of instructions. In order to carry out operations sim-ultaneously, redundant circuitry can be employed but such re-dundancy necessarily increases the cost of the system.
A lower cost/performance ratio for a data processing system can be obtained by appropriately selecting and inter-connecting the system units in accordance with some system architecture. For example, lower-speed, higher-capacity main stores are frequently interfaced with lower-capacity, higher-speed buffer stores to obtain a higher overall storage access time than that available from the lower-speed main store alone and also to obtain a lower system cost than that available using only higher-speed buffer stores. Many similar selec-tions in system architecure can be made to obtain data pro-cessing systems with an improved cost~performance ratio.
While many system architectures are known there is still the cost/performance ratio for data processing systems.

SUMMARY OF THE INVENTION
The present invention is a data processing apparatus and method therefor. The apparatus includes an encoded system bus interconnecting a plurality of functional units such as storage, processor and input/output units. The system bus has a field for a bus operation code and a field for associated bus information. The associated bus information has a function determined by the bus operation code. The encoded system bus carries many different types of system information at differ-ent times in order to service the needs of the different units connected to the system bus.
In operation, one of the units connected to the sys-tem bus broadcast information to other units by accessing the system bus, by providing a bus operation code to specify the nature of the bus information, and by supplying the bus infor-mation to the system bus. One or more of the units connected to the system bus accept the bus operation code and the asso-ciated bus information. Access control means is provided for controlling access to the system bus by the various units.
The access control means operates in a predetermined manner to determine which one of the units has priority to the system bus at any given time.
In a typical configuration of the present invention, a processor unit and one or more storage units and input/out-put units are all interconnected by an encoded system bus.

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Whenever a transfer of information between one of the units and another one of the units is required, the broadcasting unit acquires access to the system bus. A11 of the other units are then partially receiving units which monitor the system bus to determine if the broadcasting unit has broadcast a bus oepration code which they can accept. For example, when the processor unit desires to fetch information from the storage unit, the processor unit broadcasts a bus operation code to specify a storage unit fetch along with the associated bus information in the form of a storage unit address. The stor-age unit accepts the bus operation code and interprets the associated bus information as a sotrage unit addresss. The storage unit thereafter accesses the data from the location specified by that address and places the accessed information in the information field of the system bus for broadcasting to other units. The storage unit also broadcasts a bus operation code to identify the nature of the information in the informa-tion field as data. ~he unit that requested the fetch of data interprets the data appearing on the system bus as the re-quested data.
In one typical embodiment of the present invention, the bus oepration code field includes eight binary bits de-fining up to 256 operation codes. The associated bus informa-tion field typically includes thrirty-two bits. The operation codes are conveniently classified in terms of the units which are intended to accept the associated bus information.
The encoded system bus of the present invention and the connected units have an architecture which allows the same system bus to be employed for a number of different types of information transfers. By using a system bus in this manner, the number of interface connections between the various units forming the data processing apparatus are minimized thereby providing an economical system. I'he bus operation codes of the system bus are transparent both to user program i~struc-tions (target or macroinstructions) as well as to any microin-structions. In one embodiment, target instructions are speci-fied and include, for example, the IBM System 370 instruction set. In a microinstruction mahcine, sets of microinstructions are executed to execute each target instruction. When the present system bus is employed, a three level architecture results which provides both flexibility and an improved cost/performance ration.
The foregoing and other objects, features and advan-tages of the invention will be apparent from the following more particuarl descriptions of preferred embodiments of the invention, as illustrated in the accompanying drawings.
Brief Description of the Drawinqs Fig 1 is an overall block diagram of a digital com-puter employing the encoded system bus of the present inven-tion.
Fig. 2 is a schematic block diagram showing further details of the system bus and the modules of the processor unit of the Fig. 1 computer.
Fig. 3 is a schematic block diagram of the system bus interface whic:h connects units to the system bus in the computer of Fig. 1.
Fig. 4 depicts a schematic block diagram of a typi-cal one of the processing unit interfaces which interconnect the processor modules of Fig. 2.

~23~a:37 Fig. 5 depicts a schematic: block diagram of the data flow portion of the processor module 0 of Fig. 2.
Figs. 6, 7 and 8 each depicts an electrical schema-tic diagram of a portion of the control and other circuitry associated with the processor module 0 of Fig. 2 and the in-terfaces of Figs. 3 and 4.
Fig. 9 is a schematic block diagram depicting the interconnection of the system bus interface of Fig. 3 with the storage unit of Fig. 1.
Figs. 10 and 11 each depicts an electrical schematic diagram of a portion of the control circuitry within the Fig.
9 apparatus.
Fig. 12 depicts a timing diagram representing the operation of the system bus of the present invention.
Detailed Description In Fig. 1, a schematic block diagram of a digital computer is shown. The digital computer includes a processor unit 34, a storage unit 35 and a plurality of input/output (I/O) units 36. The units 34, 35 and 36 are interconnected by a system bus 37.
Input/output units typically include controllers and channels for communicating with input/output devices such as magnetic tape units, magnetic disc units and other periphe-ral units used with digital computers. In a typical system, an operator console is connected through one of the input/out-put units 36.
The syst~em bus 37 connects to each of the units of Fig. 1 through a separate interface for each unit~ Particu-larly, the processor unit 34 includes a processor unit system bus interface 34-1. The storage unit 35 includes a storage 3~

unit system bus interface 35-1. Each of the I/O units 36 includes a corresponding system bus interface 39.
The system bus 37 has an information field which is typically 32 bits wide. The system bus information field car-ries information of different types between the various units of Fig. 1. The system bus 37 also includes a bus operation code field which in one embodiment is 8-bits wide. The opera-tion field is encoded to specify the different types of infor-mation that are carried on the information field of the system bus.
Examples of the information which is transferred over the system bus are instructions, addresses of data in the storage unit, and the actual data itself. All of the informa-tion which is generally transferred between a processing unit, a storage unit and input/output units in a computer system are transferred over the encoded system bus of the present inven-tion.
A typical system bus operation commences when one of the units connected to the system bus has a need to utilize the system bus. The processor unit, the storage unit and the I~O
units are all capable of requesting access to the system bus.
Any unit wishing to access the system bus generates a bus request signal. Since more than one unit may request access to the system bus, priority circuitry is included to establish priority among the units connected to the system bus.
If no unit of higher priority is requesting access to the system bus and if the system bus is not currently busy, then a unit seeking access to the system bus will access and take control of the system bus.

When a unit has taken control of the system bus, the unit generates a bus busy signal indicating that the system bus is busy and hence that no other unit can obtain access until the particular unit is finished with its operations on the system bus.
After having acquired access to the system bus, the unit will perform some operation with the system bus. In order to perform an operation, a unit will place information in the information field and will encode an op code field to specify what the nature of the information in the information field is. For example, if the processor unit employs the system bus to fetch information from the storage unit, the op code field will specify a fetch operation and the information field will specify the address in the storage unit from which the information is to be fetched.
Further details of the system bus and its operation in the system will be described after the following descrip-tion of typical units connected to the system bus.
Processor Unit - Fiq. 2 In Fig. 2, the processor unit 34 of Fig. 1 is shown in one preferred embodiment formed of a number of different processor modules including the modules 40-0 through 40-60 One or more of the modules 40-0 through 40-6 connect to the system bus 37 through a system bus interface (SB IF). In Fig.

2, the system bus interfaces 47-0, 47-1 and 47 6 correspond to the system bus int:erface 34-1 of Fig. 1 and each connects to the system bus 37. The system bus interfaces 47-0 through 47-6 employ substantially identical circuitry so that other mod-ules within the processor unit of Fig. 2 may be connected to the system bus 37 in the same way if desired.

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Each of the processor unit modules 40-0 through 40-6 of Figure 2 are interconnected by three processor unit buses.
Specifically, the processor unit buses include the 32-bit con-trol bus, CB(0-31), the 32-bit data bus, ~B(0-31), and the 10-bit control lines, CL(0-9).
In the embodiment of Figure 2, the processor module 40-4 is a sequencer which controls the sequencing of microin-structions. The details of the processor module 4 and its interconnection through the processor unit buses is described and claimed in the copending Canadian application Serial No.
337,230 entitled COMPUTER AND METHOD FOR EXECUTING TARGET
INSTRUCTIONS filed October 9, 1979. The sequencer processor module 40-4 does not connect directly to the system bus 37.
The sequencer module 40-4 controls the sequencing of microinstructions and the execution of target instructions.
Each target instruction is typically fetched from the storage unit 35 of Figure 1 through the system bus interface 35-1 asso-ciated with the storage unit and onto the system bus 37. From the system bus 37, each target instruction is transferred through the system bus interface 47-0 into the processor module 40-0 of Figure 2.
From module 40-0, target instructions are broadcast over the processor unit data bus 43 ~o the sequencer module 40-4 and the other modules of Figure 2. The sequencer module 40-

4 thereafter generates sequences of microinstructions which are executed by the processor unit 34 to result in the execu-tion of each target instruction.
System Bus Interface - Figure 3 In Figure 3, a typical system bus interface is shown.
The system bus interface of Figure 3 is typical of the system bus . ~ : , . ..

~2~7 interfaces 34-1, 35-1 and 39-0 through 39-N of Fig. 1. Also, the system bus interface of Fig. 3 is typical of the system bus interfaces 47-0, 47-1 and 47-6 of Fig. 2.
In Fig. 3, the major components of the system bus are the 32-bit information field SY BUS(0-31, the 8-operation code filed BS OP(0-7), and various explicit signal lines 213.
The signal lines include the priority lines PRIORITY 2, PRIOR-ITY 4, BUS REQUEST IN, BUS REQUEST OUT, PRIORITY 1 REQUEST, PRIORITY 2 REQUEST, and PRIORITY 4 REQUEST. Additional lines include CANCEL, SYSTEM RESET, SURPRESS I~TERUPTS, MEMORY BUSY, CONTROLLER ADDRESS, MACHINE CHECK, DISPLAY SYNC, DISPLAY BUS, BUS BUSY, UNIT BUSY and ACKNOWLEDGE which connect to the bidi-rectional drivers 2040 An additional signal, -CLOCK, is dis-tributed throughout the system to each of the units to provide for accurate The -CLOCK signal is connected as an input to the clock unit 64. The clock unit 64 is a conventional device for providing clock signals at the frequency determined by the -CLOCK signal. In one embodiment, the -CLOCK signal has a 100 nanosecond period.
Tne clock unit 64 delays the -C~OCK signal and otherwise provides conventional clock signals for distribution In Fig. 3, the bus -SY BUS(0-31) connects to the bidirectional driver circuit 202. Driver 202 inverts each of the 32 lines and connects them as an input to the latch circuit 205. In a typical embodiment, the latch circuit 205 includes an input latch (IN LAT) 206 which latches the data from the -SY
BUS(0-31) bus under control of the ~SB IN signal. When latched, the inforMation from circuit 206 is available on the 32-bit system bus latch in bus ~SB LCH IN, which connects to ~23~7 other circuitry 31 in the system bus interface or in other associated circuitry in the storage unit connected to the sys-tem bus interface.
Inform~tion to be transferred out onto the system bus -Sy BUS(0-31) connects from the driver 202 through a gate 202-2 for each of the thirty-two l:ines. The information in-puts to the NAND gates are connected from the 32-bit +SB OUT
bus which connects from the latch circuit 205. The data on the +SB OUT bus is gated to the -SY BUS(0-31) bus only when the control gate 202-1 is enabled. Gate 202-1 is provided with the -ENABLE DR and the -INT ENABLE signals which are generated by the interface/unit circuitry 31.
The +SB IN bus from the latch circuit 205 typically connects from a 32-bit output latch (OUT LAT) 207. Latch 207 latches data from the +SB LCH IN bus under the control of +SB
OUT signal. The +SB LCH OUT bus is derived from the circutiry 31.
In Fig. 3, the 8-bit -BUS OP(0-7) bus carries the bus operation code field and connects to a bidirectional driver 203. Bidirectional driver 203 is like the drivers 202 and 204. Data from -BUS OP(0-7) is connected through driver 203 to the latch circuit 208 including the 8-bit input latch OP IN LAT 209. Latch 209 latches the 8-bit bus op from the -BUS OP(0-7) bus under control of the +OP IN signal from the circuit 31.
In a similar manner, bus ops from the functional unit 31 are stored in the 8-bit output latch (OP OUT LAT) 210 under control of l:he +OP OUT signal. When latched in buffer 210, the bus operation field is available for gating out to ~23~

the -BUS OP(0-7) bus under control of the -ENABLE OP DR and the -INT ENABLE signals.
The 8-bit ~LCH OP OUT (0-7) lines from the buffer 209 connect to a system bus operation decoder 212. The de-coder 212 functions to decode the system bus op latched in the bufer 209. Decoder 212 typically has a unique decoding for each of the units to which the system bus interface of Fig. 3 is connected. The outputs from decoder 212 prvide signals to the functional unit 31 for specifying the nature of the infor-mation on on the system bus -SY BUS(0-31). The functional unit 31 determines whether or not to accept information of the specified nature.
The signal lines 213 similarly are or can be bidi-rectional and connect to the drivers 204. The drivers 204 convert the bidirectional lines on the left to the pair of unidirectional lines on the right. For example, the -CANCEL
line on the left of drivers 204 connects as the +CANCEL OUT and the +CANCEL IN lines on the right. The names of the signals on the right correspond to the names of the signals on the left with the additional designation OUT (representing signaIs transmitted out to the system bus) and the designation IN
(representing signals received in from the system bus). The OUT and IN signals from the drivers 204 connect to the func-tional unit 31.
In Fig. 3, the lines 214 connect to a priority cir-cuit 215. The priority circuit 215 for each of the system bus interfaces like that of Fig. 3 establishes the priority among the units which are connected to have access to the system bus. Priority circuit 215 is connected to the functional unit 31 for transferring the priority information.

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Processing Unit Interface - Fig. 4 In Fig. 4, further details of a typical processing unit interface are shown. The processing unit interface of Fig. 4 is typical of the interfaces 46-0 through 46-6 for each of the process unit modules 40-0 through 40-6 of Fig. 2. Each of the processor unit interfaces are interconnected by the 32-bit control bus 42, the 3~-bit data bus 43 and the 10-bit control lines 44.
In Fig. 4, the 10 control lines 44 connect as inputs to a buffer 58 and are named -BUS LOAD UVC, -BUS mSTORE DIS-ABLE, -BUS EXEC UVC, +BUS READY, -BUS CLOCK, +BUS RUNNI~G, -BUS CHECK STOP, -BUS INT, -BUS COMB STATUS, and -BUS CONSOLE
FLAG. The signals on the lines 44 are latched in the buffer 58. The signals from the lines 44 are inverted by the buffer 58 to provide control signals for the particular processor module. The control signals have the same name as on bus 44 but without the word "BUS" and they have opposite polarity.
In addition to the input signals from the lines 44, NAND gates 69-1 through 69-5 provide output connections to the lines 44 where lines of an identical name (ignoring "BUS" and "OUT") are connected through the gates 69. Gates 69 are en-abled to connect the "OUT" signals to the lines 44 under con-trol of +he +INTERNAL ENABLE signal from the microinstruction decoder 66. The +CONSOLE FLAG OUT signal is provided by NAND
gate 73 which receives the +~(0) and ~mADR EQ signals.
In Fig. 4, the interface includes a clock unit 64 including two parts 64-1 and 64-2. The clock unit part 64-1 receives the +CLOCK signal from the buffer 58 and responsively provides 18 clock lines 74 with various delayed clock signals.
The clock unit 54 provides the clock signals on lines 74 under 3~ 7 control of the -READY signal from the buffer 58. Clock unit 674 is a conventional device for providing clock signals at the frequency determined by the +CLt)CK signal from buffer 5B.
In one embodiment, the +CLOCK signal has a 100 nanosecond per-iod. The outputs from the clock unit 64 include the nine clock signals +~(0, 10, 20, ..., 80). Those nine signals have the same period as the +CLOCK signal . The +~(0) signal is a signal which has, in a particular example, a ~0 nanosecond delay after the +CLOCK signal. The +~(10) signal is delayed ten nanoseconds after the +0(0) signal. In a similar manner, each of the signals +~(20), +0(30), ... +~(80) are successive-ly delayed by increments of ten nanoseconds from the preceed-ing signal. The nine clock signals -~(0), -0(10), -0(20), ...
-~(80) have the same timing as the +~(0), +0(10), +0(20), ...
+~(80) signals with the inverted sign. The 18 output signals from the clock unit 64 are availablle for distribution throughout the associated processor module whenever the -READY
signal is a logical 0.
The clock unit part 64-2 is a delay device which delays the +CLOCK signal by 10 and 20 nanoseconds to provide the +(CLK +10) and the ~(CLK +20) signals, respectively, on lines 74-2 irrespective of the logic level of the -READY sig-nal. The +L READY signal is the -READY signal invented and synchronized with the +CLOCK signal.
In Fig. 4 the 32-bit control bus 42, CB(0-31), con-nects as an input to the buffer 59. Buffer 59 latches the information on bus 42 under control of the +~(0) clock signal from the clock unit 64. The 32-bit output from the buffer 59 forms the microinstruction bus, mI(0-31), which is connected throughout the associated processor module. In particular, ~ !~23~

the microinstruction bus from the buffer 59 is ~onnected as an input to the microinstruction decoder 66. The microinstruc-tion decoder 66 functions to decode selected fields from the microinstructions bus for providing decoded output signals.
The microinstruction decoder 56 is enabled to perform decoding upon being enabled by the +I~TERNAL ENABLE signal from an ul-travisor unit 65.
When enabled, the decoded output from decoder 66 provides one or more of the following output signals: the six-teen lines 16 -SEL(D0-D15); the sixteen lines -SEL(B0-B15);
the eight lines -UNIT SEL(0-7); the sixteen lines -SEL(S0-S15); the eight lines +FUNCtl-8); the eight lines -FUNC(1-8).
In Fig. 4, the control bus 42 also connects as an input to the ultravisor unit 65. The ultravisor unit 65 func-tions to perform various supervisory functions throughout loaded into the ultravisor unit 65 under control of the +LOAD
UVC signal from the buffer 58. Upon loading the control in-formation from the control bus 42, the ultravisor unit 65 pro-vides those signals as an output on the 32-bit ultravisor con-trol bus +UVC(0-31). Additionally, upon the +~X~C UVC si~nal from the buffer 58, the ultravisor unit 65 functions to pro-vide scan in or scan ouu signals on the 8-bit bus -SCAN IN (0-7J or on the 8-bit bus -SCAN OUT (0-7).
In Fig. 4, the control bus 42 connects to the buffer 60. Buffer 60 stores the information on control bus 42 to provide the output data on the microstore data in bus, mS
DI(0-31). When the -CTL MAST signal is present, the buffer 60, storing information from the microstore data out bus, mS
DO(0-31), makes that information available on the control bus 42.

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In Figure 4, the data bus 43 is bidirectional and re-ceives output data from a source buffer 160. The source buf-fer 160 gates data onto the data bus 43 under control of the -GATE DATA OUT signal from the microinstruction decoder 66.
Source buffer 160 is loaded with data from the 32-bit SOURCE
BUS 62, +SB~n-31). The SOURCE BUS 62 and the RESULT BUS 63 each typically connect throughout the corresponding processor module to provide a source and a result data path for trans-mitting data throughout the module and onto the data bus for transmission to other modules within the processing unit.
Further details of the ultravisor unit 65 and the microinstructions decoder 66 are shown and described in the above mentioned application Serial No. 337,230 entitled COh~UTER AND METHOD FOR EXECUTING TARGET INSTRUCTIONS with particular reference to Figures 5 and 6 therein. Additionally, said copending application describes the interconnection of the sequencer processor module 40-4 with the processor unit interface 46-4. The sequencer processor module 46-4 does not have a system bus interface and does not connect directly to the system bus 37 as indicated in Figure 2. Also, it will be noted that the processor unit interface 46-4 in said copending application does not include all of the decoder outputs from the microinstruction decoder 66 nor does it employ the source buffer 160 within the processor unit interface described in connection with Figure 4 of the present application. It will be recognized, however, that the processor unit interface in said copending application is a subset of the circuitry which comprises the generalized processor unit interface of Figure 4 in the present application.

I Fetch Processor Module 0 - Figs. 5 through 8 In Fig. 5, a schematic block diagram of the data flow of the I fetch processor module 40-0 of Fig. 2 is shown.
In addition to the data flow of Fig. 5, the processor module 0 includes the processor unit interface 46-0 like that of Fig. 4 and a system bus interface 47-0 like that of Fig. 3.
The function of the processor module 0 is to fetch target instructions from the storage unit 35 over a system bus 37 and then to broadcast the fetched target instructions over the processor unit bus 42, 43 and 44 for use throughout the processor unit 34 and each of its modules.
As indicated in Fig. 5, the processor module 40-0 connects to the +SB LCH IN(0-31) bus 217 and the +SB LCH OUT
(0-31) bus 218 which forms part of the system bus interface of Fig. 3. In a similar manner, the processor module 40 0 of Fig.

5 connects on the right-hand side of Fig. 5 to the result bus 63, RB(0-~1), and the source bus 62, SB(0-31), which form part of the processing unit interface of Fig. 4.
In Fig. 5, the data from the +SB LCH IN (0-31) bus 217 of Fig. 3 connects as an input to the four 32-bit buffers 226, 227, 228 and 229. Buffers 226 and 227 form the buffer A
and buffers 228 and 229 form the buffer B. Buffer A and buffer B each store a double word from the storage unit 35 organized on double-word boundaries. Transfers between the storage unit 35 of Fig. 1 and the buffers A and B of Fig. 5 are on a double-word boundary basis. Since the bus 217 is 32 bits wide, buffer A and buffer B are each loaded one-half at a time on a single word basis. Specifically, buffers 226, 227, 228 and 229 are each loaded from the bus 217 under control of the +LDA(0-31)~

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+LDA(32-63), +LDB(0-31), and +LDB(32-63) signals from the con-trol of Fig. 7.
Although the data stored in buffers A and B of Fig.
5 are organized on a double-word basis, use of that data by the comput~r of the present invention follows the IBM System 370 format which requires that data be available on a byte basis (8 bits). The -SEL A control lines ~-SEL A(0-15); -SEL A(16-31); -SEL A(32-47); -SEL A(48-63)] enable the data to be se-lected out from the buffers A and B into the multiplexor 230 on a byte basis. Multiple~or 230 selects the data bytes from either buffer A or buffer B under control of the +ALIGN S0/Sl signals derived from a 2-bit register 248 which stores the bits 29 and 30 of current program count.
Multiplexor 230 has its output segregated into three fields, namely, the op code field of bits 0 through 7 and the 24 higher order bit-s 8-31 and the higher order bits 32-63 of the double word Erom buffer A or buffer B.
Multiplexor 231 selects the op code from the field 0-7 of multiplexor 230 or from the sub~titute op code register 234 under control of the +SEL SUB OP CODE signal from an inter-rupt unit 24g. The interrupt unit 249 is any conventional circuitry for initiating an interrupt. For example, unit 249 can be initiated in response to a decoded output from decoder 66 of Fig. 4. The substitute op code register 234 is loaded from the result bus 63 under control of the -SEL Dl signal from decoder 66 of Fig. 4. Selection gates 232 select the field 8-31 from the multiplexor 230. The 32 bits of information spe-cified by the multiplexor and selection gates 231 and 232 are gated onto the source bus 62 under control of the -SEL S0 signal. Alternatively, the field 32-63 from multiplexor 230 ~23~

is selected by the selection gates 233 under control of the -SEL Sl signal. The operation of the buffers A and B (226, 227, 228 and 229), the multiplexor 230, the multiplexors 231 and the selection gates 232 and 233 is to select the target in-struction from the appropriate byte fields of the two double words from the storage unit and displace that target instruc-tion on the source bus 62. The source bus 62 of Fig. 5 con-nects as an input to the source buffer 160 of Fig. 4 from where it is connected to the data bus 43 and broadcast throughout the processor unit of Fig. 2 to each of the processor unit modules.
In Fig. 5, the main store address of the current target instruction is specified by a current program count.
The current program count appears on the 24-bit bus 250, +CUR
PC(0-24). The program count is gated onto the bus 250 from either the register 235 or the register 236. ~egister 235 is loaded from the result bus 63 under control of the -SEL D3 signal. The bits RB(8-31) are selected from the 32-bit bus 63. The contents of the register 235 are gated onto the +CUR
PC (8-31) bus 250 under control of the -SEL NEW PC signal from Fig. 6. Register 236 stores the output from an adder 237.
Adder 237 adds the current program count f rom the bus 250 to two bits +ILC0 and +ILCl. rhe addition in adder 237 functions to select the proper byte alignment for the current program count to account for the fact that words are accessed from the storage unit on a double word boundary basis. The byte cor-rected address for the program count is stored in the register 236 under control of the +PC STROBE signal. The contents of the register 236 are gated onto the current progr~m count bus 250 under control of the +SEL NEW PC signal.

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The contents of the current program count bus 250 are latched in the register 240 under all conditions. Addi-tionally, the contents from bus 250 are latched in the regis-ter 241 under control of the +PC STROBE signal and are latched in the register 244 under control of the ~BUF CLOCK signal.
The register 241 operates the current program count to the source bus 62 under control of the -SEL S4 signal on bits SB(8-31). Register 240 operates to gate the current pro-gram count from register 240 onto the source bus 62, SB(8-31) under control of the -SEL S3 or -SEL Sl signals. A register 239 is provided to gate all 0's to the source bus 62 bits SB(0-7) under control of a -HI ZERO signla produced as a logical OR
of the -SEL Sl, -SEL S2, -SEL S3 or -SEL S4 signals.
The current program count bus 250 also connects as one input to an adder 243. The function of adder 243 is to add 8 to the current program count to form the double-word address of the next program count. The next program count (increased by hex "8" or binary "1000") is stored in the register 245 at the same time that the current program count is stored in the register 244 all under control of the +BUF CLOCK signal. T~le contents of register 244 are gated out as the bus address to bus 218 from the register 244 under control of the -SEL ad-dress from register 245 under control of the -SEL PC +8 signal from register 245. If desired, the high-order 13 bits from register 244 or 245 may be translated by a translation look-aside buffer and be subject to dynamic address translation in the unit 246. Such translations do not form part of the pre-sent invention and can be carried out using any conventional technique. Alternatively, the unit 246 may be eliminated all together when no translations are to be performed. The ad-3~

dress on bus 218 forms the bits ~SB LCH OUT (8-28) connected to the latch 207 in Fig. 3. That address is gated onto the system bus when the driver 202 in Fig. 3 is enabled and from there is operative to address a storage location in the stor-aqe unit 35.
In Fig. 5, the register 238 is laoded with the op code from the result bus 63, bits RB(8-11) under control of the -SEL B6 signal. Register 238 connects the high-order 4 bits, +OP LCH OUT (4-7), of the op code via bus 220 as the input to the op code out latch 210 of Fig. 3. The information from register 238 specifies the nature of the information to be gated to the system bus from the bus 218 of Fig. 5.
In accordance with the present invention, the pro-cessor module 0 of Fig. 5 functions to provide information onto a system bus 37 of Fig. 1 via bus 218 together with an op code from bus 220 to specify the nature of the information.
In Fig. 5, the register 242 has the bits 29 and 30 in the field 8-31 determined by the length coun~ signals +FLC0 and +FLCl. The length count as determined by the bits 29 and 30 is gated with the other information to specify a program count on the source bus 62, bits SB(8-31) under control of the -SEL S2 signal.
While the various control signals required to carry out the data flow generally indicated in connection with the above description can be implemented in any conventional man-ner, one typical preferred embodiment of such control is de-scribed in connection with the circutiry of Figs. 6, 7 and 8.
I Fetch Module 0 Control C rcu1tr~ - Figs. 6, 7 & 8 The general operation of the control circuitry of Figs. 6, 7 and 8 is to cause a double word of information to be A~33069/DEL -22-~L~23~7 accessed from the storage unit 35 and placed in buffer A tbUf-fers 226 and 227 of Fig. 5) whenever buffer A is empty and similary to place a double word in buffer B ~buffers 228 and 229 of Fig. 5) whenever buf~er B is empty. When no other conditions indicate otherwise, the current program count from ~egister 244 is employed as the address from which a double word is accessed for a first one of the buffers A or B and the program count from register 245 is employed as the address from which a double-word is accessed for a seocnd one of the bu.fers A or B. If during the processing of information (for example target instructions) target instructions accesse~ in this way, a branch or other condition indicates that some other program count other than in registers 244 or 245 is required, the new program count is generated and the buffers A
and B are appropriately loaded with new counts, the old counts in buffers A and B being discarded.
In Fig. 6, operations are commenced whenever the processing unit interface of Fig. 4 (the one associated with the processor module 0 of Fig. 2) causes a module select sig-nal to be decoded. In Fig. 4, the module select sisnai is ti~
S~L from the microinstruction decoder 66. Each of the differ-ent moaules in Fig. 2 functions to decode the microinstruction bus, bits +mI(9-11) to drive a unique associated with a par-ticular processor module. Each processor module has a switch set to select a unique one of the decoded outputs.
In Fig. 6, when the processor module 40-0 is the active one, the +MOD SEL signal is input to the D-type flip-flop 251 and storecl there by the clock signal at +~50). The Q
output from the flip-flop 251 enables the NAND gate 252. The other input to the gate 252 is derived from the inverted -SEL

~i~23~11)7 Bl signal which is one of the decoded outputs from the micro-instruction decoder 66 of Fig. 4. The -SEL B1 signal is a decoded one of the microinstruction bits mI(20-22~. When the microinstruction thus specifies processor module 0 and the Bl function, the gate 252 is satisfied and its output is inverted to provide the signal +LATCH CUR PC for latching the current program count. The program count is,for example, the number which specifies the address in the storage unit 35 in Fig. 1 of the current target instruction. The +LATCH CUR PC signal en-ables the NAND gates 253, 254 and 256. The gates 253 and 254 function to compare the bit 28 of the current program count which appears on bus 250 of Fig. 5 with the bit 28 of the next program count which appears on bus 249 of Fig. 5. The compari-son made by gates 253 and 254 occurs whenever the ready condi-tion is indicated by a 0 for the -READY signal which is in-verted and input to the gates 253, 254 and 255. The +CUR PC 28 and +NXT PC 28 signals are also inverted and input to the gates 253 and 254, respectively. When bit 28 of the current program count and next program count are different, it signifies that the contents of a double-word buffer A and ~ ir. ~is. 5 has been emptied. If the output of NAND gate 253 is a 0, it signifies that the A buffer has been emptied and if the output of NAND gate 254 is a 0, it signifies that the B buffer has been emptied. Gate 255 is satisfied under the conditions that the program count has been altered and gate 256 is employed when an interrupt is tc be taken (e.g. unit 249 of Fig. 5 renders -INT TAKEN a 0) and hence a new program count is to be strobed. Gate 255 is enabled whenever -READY and -SEL D3 are both 0. Gate 256 is enabled whenever +L READY is a 1. The outputs from all gates 253-256 are clocked into the bank of ~23~C~7 four ~-type flip-flops 258 by the ~CLOCK +30 signal.
The NAND gate 280 receives the -A EMPTY, and the -PC
ALTERED signals and an enable signal from the NA~D gate 271.
Whenever the A buffer is emptied or the program count is al-tered, when enabled by gate 271, gate 280 is satisfied to provide a 1 to the J input of the ~K flip-flop 289 to set the +RQST A signal to a 1 thereby designating that buffer A of Fig.
5 is requesting a double word of information.
The NAND gate 281 has the -B EMPTY and the -PC AL-TERED inputs and is A~TERED inputs and is enabled by the NAND
gate 270 output. When gate 281 is satisfied, it provides the J
input to the JK flip-flop 290 to set RQST B on the Q output to a 1. Such a designation indicates that the B buffer in Fig. 5 is requesting a new double word of information.
The NAND gate 282 receives the inverted output of gate 280 and the ~A AVAIL signal from the gate 261. The func-tion of gate 282, with its output inverted, is to reset the request A flip-flop 289 with a 1 on the K input and the Q
output. Similarly, NAND gate 283 receives the +B AVAIL signal and the inverted output of gate 281. The inverted output of gate 283 sets the K input and the Q output of the JK flip-flop 290 to a 1. The significance of this operation is that once an available signal is generated by gates 261 or 263, the request flip-flops 289 or 290 are reset to have their outputs no longer indicate that a request to fill buffers A and B is being made. Flip-flops 289 and 290 store the appropriate re-quest or reset signals under control of the -CLOCK signal.
The NAND gate 284 is connected to the Q outputs of flip-flops 289 ancl 290 to provide the -BUS RQST signal which connects to the AND gate 303 of Fig. 7. That signal is in turn ~23~7 propagated by gate 303 as the -BUS REQ OUT signal which is propagated as one of the signals on the system bus 37 of Figs.
1 and 2. This signal ls then utilized to communicate to the system bus that the processor module 40-0 of Fig. 2 has ac-quired the system bus. AND gate 303 will cause its output, -BUS REQ OUT to go form a 1 to a O if -BUS REQ IN was previously a 1. If -BUS REQ IN was previously a 0, then -BUS REQ OUT will remain a 0, meaning that some other unit already has access to the system bus.
The D type flip-flop 291 of Fig. 6 stores the state of the current program count double-word bit 28 by receiving the ~CUR PC 28 line on its B input. Flip-flop 291 is clocked by the +BUF CLOCK signal. The Q output of flip-flop 291 en-ables a NAND gate 285 and the Q output enables a NAND gate 286.
When program count bit 28 is a 1, gate 285 is enabled, and when a 0, gate 286 is enabled. The AND gate 287 receives the Q
output of flip-flop 289 and the output from gate 285 to pro-vide the +A SELECTED signal to indicate that the A buffer of Fig. 5 is to be selected. Similarly, the AND gate 288 receives the Q output of flip-flop 290 and the output from gat~ 286 to provide the +B SELECTED signal to indicate that the B buffer of Fig. 5 is to be selected. The output from AND gate 287 is connected to the D input of the flip-flop 2780 Flip-flop 278 delays the signal until clocked by the +CLOCK signal to pro-vide the +DEL SEL A signal on its Q output. Similarly, the D
type flip-flop 279 receives the +B SELECTED signal on its D
input and provides the +DEL SEL B signal on its Q output. The output signals from flip-flop 278 proYides an enable input to AND gates 261 and 262 and the output from flip-flop 279 pro-vides an enable input ~or AND gates 263 and 264.

, 3~ 7 The gates 261 and 263 receive as inputs the +AVAILA-BLE signal from the available flip-flop 314 of Fig~ 7. The available signal indicates that the double word is available and the +ACQUIRED signal indicates that the double word has been acquired as signified by the output from the acquired flip-flop 315 of Fig. 7.
In Fig. 6, the +A AVAIL signal output from gate 261 is connected to the J input from flip-flop 292 and stored there under control of the -CLOCK ~50 signal. Similarly, the output from the AND gate 263 is connected to the ~ input of flip-flop 293 at the same clock time. The Q outputs of flip-flops 292 and 293 indicate the -A IN PROG and the -B IN PROG
signals, respectively. Flip-flops 292 and 293 are both reset at the clock time by the +END FETCH signal which indicates the end of a fetch operation.
The Q output of flip-flop 292 is the -A IN PROG
signal which is one input to the NAND gate 277. Gate 277 also receives the -RQST A signal to provide the -BUF A CUR signal that a double word is being requested for buffer A of Fig. 5 and that the information is available. Similarly, the ~AND
gate 276 receives the -RQST B signal and the -IN PROG signal to provide the -BUF B CUR signal on its output for indicating when a B buffer request is being made and the information is available.
In Fig. 6, the register 267 stores the 20 bits of data from the +DA1'A BIT (8-27) bus derived from the bus 217 of Fig. 5. Similarly, register 268 stores the same information derived at a different time. Information is stored in regis-ter 267 by the clock signal output from the NAND gate 265. The information is stored in register 268 under control of the 3~7 clock signal from the NAND gate 266. Both gates 265 and ~66 are enabled by the +CLOCK +40 signal. Gate 265 is enabled by the +PH2A signal and the gate 266 is enabled by the +PH2B
signal, each derived from the bank of phase flip-flops 348 of Fig. 8.
In Fig. 6, comparator 269 compares the contents of either register 267 or 268, depending on the state of the +DATA BIT (28) with the present contents of the bus 217. When those contents are the same, comparator 269 provides the +MATCH signal for indicating .
In Fig. 6, the NAND gate 270 provides its output to indicate when the information on the bus 217 matches the in-formation in the register 267 whenever a store operation is indicated. Whenever a match occurs, it indicates that the address of the information stored in A and B registers of Fig.
5 is the same address as that of the information to which a storage operation is being made. Since a storage is being made to the double word in the A or B register, it indicates that the A ro B register is having its information altered and hence the information stored therein is no longer valid.
Under this condition, gates 270 and 271 connect as inputs to gates 280 and 281 for initiating a reqeust to update either the A or B register as the case may be so that it will then contain the correct information.
Also, the -A ALTERED signal is input to the K input of the JK flip-flop 294 and the -B ALTERED signal is input to the K input of flip-flop 294. The J input associated with the -A ALTERED signal is +PH3A and the J input associated with the -B ALTERED signal is +HC3B. The Q outputs from the flip-flops 294 together with the ~MATCH signal from comparator 269 are ~L~2~

input to the AND gate 275. The flip-flops 294 are clocked by the -CLOCK signal. The operation of the gate 275 and the Flip-flops 294 is as follows. If the comparator 269 determines that the double-word address or the information in the A and B
buffers of Fig. 5 matches the current contents of one o~ those buffers, gate 275 will indicate that the match occurs by a 1 for the +FETCH MATCH output unless a store operation is to occur. If a store operation is to occur, the STORE OP signal is input to the gates 270 and 271 and one of the flip-flops 294 has a 0 on its Q output disabling the gate 275. Unless a store operation is to occur, a match of the address corresponding to the contents of one of the buffers A or B causes the +FETCH
MATCH signal to be a 1.
In Fig. 7, the NAND gate 305 has as inputs all of the signals required to allow requested information to be availa-ble. Those signals are as follows. The inverted -BUS RQST
signal which signifies that the processor module 40-0 of Fig.
2 is requesting access to the system bus. The inverted +MEM
B~SY OP OUT signal meaning that the memory (storage unit 35 of Fig. 1) is not busy. The inverted +BUS BUSY OUT signal meaning that the system bus is not busy with any other unit.
Gate 305 also receives an input from the AND gate 304. Gate 304 is satisfied only when the Q output from flip-flop 314 is a 1, meaning that the flip-flop is not in an avail-able mode providing a 1 on the Q output and when -PC ALTERED is a 1 meaning that l:here has been no command to change the pro-gram count. If all these conditions are satisfied with logi-cal l's input to gate 305, gate 305 produces a logical 0 output which is clocked into the flip-flop 314 to provide a 1 on the Q
output for the +AVAILABLE signal. The +AVAILABLE signal en-3~37 bles the gates ~61 and 263 of Fig. 6 as previously described.
The D-type flip-flop 315 has its D input connected from the output of the NAND gate 31)6. Gate 306 receives the +ENT VALID signal from the translation look-aside buffer 246 of Fig. 5. If the unit 246 is not employed, then the +ENT
VALID siqnal may be connected to a logical 1 When employed, the +ENT VALID signal indicates that a requested entry in the unit 246 is present. If the entry is not present, then the output from gate 306 is a logical 1, but otherwise is a logical 0. Failure to find a proper entry in the unit 246 has the effect of terminating operations which would otherwise tran-spire after the +AVAILABLE signal becomes a logical 1. The NAND gate 318 is connected to recieve the Q output from the flip-flop 315 and the AND gate 319 is connected to receive the Q output of flip-flop 315. If no termination is required as indicated by a 0 output from gate 306, then the Q output of flip-flop 315 enables gate 319 and the +ACQVIRED signal is a logical 1. If an operation is to be texminated, the 1 output from gate 306 appears as a 1 input to AND gate 318 which pro-duces a 0 for the ~SCRUB signal. Flip-flop 315 is clocked by the +CLOCK +50 signal. The +AVAILABLE signal is inverted to provide the -ENAB~E DR and the -ENABLE OP DR signals, which connected to enable the output drivers 202 and 203 of the system bus interface of Fig. 3.
In Fig. 7, the bank of D-type flip-flops 209 receive the 4 bits +OP IN(0-3), from the drivers 203 of Fig. 3. The contents of the op code are stored by the +CLOCK signal in the flip-flops 209. The outputs from the flip-flops 209 are input to a decoder 212 which is formed by the NAND gate 307 and the NAND gate 308. For store operations, the +OP IN(0-3) bits are A-33069/DE~ -30_ 3~C~7 1100. NAND gate 307 will detect such a code and provide the ~STORE OP signal which is input to the NAND gates 270 and 271 of Fig. 6.
The NAND gate 308 functions to detect 1111 for the bits +OP IN(0-3) which indicates the presence of data on the system bus when the -DATA OP signal from gate 308 is a 0. When data is present on the system bus, the -DATA OP signal enables the NOR gates 32B, 329, 330 and 331.
In Fig. 7, after the gate 319 generates the +AC-QUIRED signal which, through the operation in Fig. 6, allows the +B ACQUIRED or the +A ACQUIRED signal to be generated and returned to Fig. 7. Those signals are connected to the J
inputs of flip-flops 316 and 317 which are clocked by the -CLOCK signal to indicate that fetching is in progress. Flip-flop 316 indicates a -FETCHING B signal on its Q output and flip-flop 317 provides a -FETCHING A signal on its Q output.
The Q output from flip-flop 317 enables the NOR gates 328 and 329 and similarly, the Q output from flip-flop 316 enables the NOR gates 330 and 331. The JK-type flip-flop 321 stores a 1 in response to the +DATA OP~signal at the -CLOCK +20 time. Gates 328 and 330 are also enabled by a 0 for the -FIRST WORD signal derived from the Q output of the flip-flop 321 and gates 329 and 331 are enabled by a 0 for the -SECOND WORD signal derived from the Q output of the flip-flop 321. Flip-flop 321 is clocked by the +CLOCK +20 signal to place the + DATA OP signal on its J input a~d the ~ACQUIRED signal on its K input. The operation of flip~flop 321 is to select the first word (-FIRST
WORD equal 0) when the +ACQUIRED signal occurs after a data op code appears on the op code bus t+DATA OP equals 1). When the first word has been acquired, flip-flop 321 is switched to ~231~7 produce a 0 for the -SECOND WORD. In this manner, the outputs are selected from the gates 328 through 331 when each of the appropriate inputs are all 0's.
Gate 328 produces the +I.DA(0-31) signal, gate 329 produces the +LDA(32-63) signal, gate 330 produces the +LDB(0-31) signal, and gate 331 produces the +LDB (32-63) signal.
These signals cause the data on the system bus to be latched into the buffer A or buffer B of Fig. 5 in the appropriate locations.
In Fig. 7, the program read only memory (PROM 301) is a conventional device for providing predetermined outpu~s as a function of addressing inputs. The addressing inputs are -BUF A CUR, -BUF B CUR, and +CUR PC(28-30) derived from the bus 250 of Fig. 5.
The PROM 301 provides the selection signals -SEL
A(48-63), -SEL A(32-47), -SEL A(16-31) and -SEL A(0-15) as a function of the current program count bits 28 through 30.
In Fig. 7, the PROM 301 generates a -TARGET CURRENT
signal whenever at least one word of the target instruction is current. That signal is propagated to the gate 309 without inversion. The PROM 301 provides the +SYNC2 signal whenever at least two words of the target instruction are current. The PROM 301 generates the +SYNC3 signal whenever three words of the target instruction are current. The AD0 and ADl signals from Fig. 5 designate the length of the current target in-struction, namely, one, two or three half words.
In Fig. 7, the -TARGET CURRENT, +SYNC3 and +SYNC2 signals indicate the number of half words of the target in-struction which are current. If one half-word is current, then -TARGET CURRENT is a 1 and if none, then that signal is a :~Z3~C~7 0. If two half-words are current, the +SYNC2 is a 1 and if three half-words aare current then ~SYNC3 is a 1. The +AD0 and +ADl signals from Fig. 5 specify the number of half-words which comprise the length of the current target instruction.
If +AD0 and +ADl are 00, the instruction length is one half-word. If they are 01 or 10, then the instruction length is two half-words, and if 11, then the instruction length is three half-words. Gates 310 detects whether or not the three half words are current. Gates 311 and 312 detect whether or not two half-words are current when required. ~ate 309 specifies when only the one half-word is current and required. In order for the current operation to proceed, a 1 must be output from any one of the gates 309 through 312. Any 1 will cause the output from the NOR gate 371 to be a 0. That 0 is loaded into the D-type flip-flop 313 by the +CLOCK +30 signal. The 0 from the Q
output of flip-flop 313 is then input to the NOR gate 322.
Gate 322 also receives the microinstruction bus bits ~mI(l9-22) from Fig 4 which specify the address of a register. Gate 322 is satisfied if all the inputs are 0 to produce a 1 output.
The significance is that the number of half-words of the tar-get instruction are current and the target instruction regis-ter being addressed by bits of bus mI(19-22). If these condi-tions occur when the +MOD SEL signal indicates that processor module 40-0 is being selected during the broadcast mode as indicated by ~BROADCAST, the NAND gate 323 is satisfied to produce a 0 output. That 0 output in turn forces the NAND gate 324 output to a 1 where it is communicated by the +INT ENABLE
signal to cause +BUS READY to ~e a 0.
In Fig. 8, the D-type flip-flops 348 are connected together to form a timing chain for timing operations after ~3~:37 the +ACQUIRED signal has been provided from Fig. 7. The flip-flops are clocked by the ~BUF CLOCK signal and provide condi-tions under which the fetch operation is te~minated. The phases will be stepped to +PHASE 2, +PHASE 3 and +PHASE 4 in successive +BUF CLOCK cycles. The +PHASE 4 signal will enable the NAND gates 353 through 356. Those gates, when enabled, look at the stored values in the D-type flip-flops 352 of the +CANCEL OUT, +CANCEL ACKNOWLEDGE OUT, +BUSY OUT and +MACHINE
CHECK OUT signals, respectivley. Also, the D-type flip-flop 351 stores the +BUS BUSY OUT signal under control of the +BUF
CLOCK signal to produce on the Q output the +DELAY BUSY sig-nal which is inverted and input to the NAND gate 359. Gate 359 also receives the Q output of the JK-type flip-flop 373.
Flip-flop 373 has its J input controlled by the output from the AND gate 353 and its K input by the +PHASE 2 signal. Flip-flop 373 is set by the -CLOCK signal to enable gate 359 pro-vided the +ACKNOWLEDGE OUT signal is a 1 and the +CANCEL OUT
signal is a 0 at the +PAHSE 4 time. If the +BUS BUSY OUT
signal is a 0, gate 359 becomes enabled to provide a 0 forcing the output of NAND gate 357 to a 1. If the process of fetcning A or B is occurring, then AND gate 360 causes an abnormal end to the fetch by providing a 1 for the +FCH AB END signal. That 1 is clocked into the appropriate flip-flop 348 and provides the +DEL AB END signal which when inverted through gate 350 causes the 0 for a -AB END signal.
In Fig. 8, the NAND gate 354 senses a 1 for the +CANCEL OUT signal as stored in the flip-flop 35~ and again through NAND gate 357 will cause an abnormal end signal to be propagated. SimiLarly, if +ACKNOWLEDGE OUT is stored as a 0, the Q output of flip-flop 352 will be a 1 satisfying NAND gate A-33069/DEL -34~

~231 037 355 and again through NAND gate 357 causing an abnormal end signal to be propagated. A 1 for +BUSY OUT is detected by gate 356 and again propagated by gate 357 to cause a fetch abnormal end. All of these conditions cause a fetch for the A or B
buffer of Fig~ 5 which is otherwise attempted not to be suc-cessfully carried out.
Another condition under which the fetch attempted is ended is controlled by the counter 347. The counter 347 is enabled to count under control of the +FCH AB signal which indicates that fetching for the A or B buffer is under way. If the +ACQUIRED signal does not reset the counter 347 before some predetermined time, a -NO DATA signal is provided which again through the NAND gate 357 causes an abnormal end to be propagated.
In Fig. 8, the AND gate 344 detects when no request is present for the A buffer, but fetching for the A buffer is under way. Gate 344 generates the +DOING A signal which en ables the NAND gates 362 and 364. In a similar manner, AND
gate 345 detects when a fetching for the B buffer is under way and no request for the B buffer is present to generate the +DOING B signal. The +DOING B signal enables the NAND gates 363 and 365. Gates 362 and 363 are satisfied to establish an unacknowledge condition. If any of the gates 362, 363, 364 or 365 are satisfied to produce a 0 output, the 0 is stored by the +CLOCK +50 signal in the corresponding flip-flops 366. Simi-larly, if a program count is to be altered, the -PC ALTERED
signal is stored in the D-type flip-flop 346 as a 0 so that the Q output of flip-flop 346 sets all the Q outputs of flip-flops 366 to 0. A 0 for any of the Q outputs of flip-flops 366 forces the corresponding one of the NAND gates 367 or 36~ to a ~LZ3~

1 output indicating that an exception for the A buffer or B
buffer has occurred. The +A EXCP signal and the +~ EXCP signal from gates 367 and 368 are input to the PROM 369 for use in generating the correct address information for the +ILC 0, +ILC 1, +FLC 0 and +FLC 1 signals. The PROM 369 additionally includes as inputs the +AD0, +ADl, +CUR PC(28-30), -BUF A CUR
and -BUF B CUR signals. The +AD0 and +ADl signals input to PROM 369 are stored by a ~PC STROBE signal in the JK-type flip-flop 370. The outputs from the PROM 369 together with the +AD0, +ADl signals and the Q and Q outputs from the flip-flop 370 address a second PROM 374. The PROMS 369 and 374 include logic for appropriately selecting the +ILC 0, +ILC 1, +FLC 0 and +FLC 1 signals which connect to the adder 237 and to the register 242 of Fig. 5 for establishing the correct byte ad-dress within the double word for the A and B buffers.
In Fig. 8, the AND gates 377 and 378 receive as inputs all the conditions that are necessary for generating the -SEL PC line from the NOR gate 380. The conditions are that an update not be in progress and that the B buffer be selected when the program count bit 28 is a 1 or tna the A
buffer be selected when the program count bit 28 is a 0.
In a similar manner, the AND gates 382 and 383 re-ceive all the condiitons in which the -SEL PC +8 signal is generated. The signal is generated whenever an update is not in progress and the program count bit 28 is a 1 when the buffer A is selected or that the program count bit 28 is a 0 when the buffer B is selected.
Storaqe Unit - Fig. 9 In Fig. 9, further details of the storage unit 35 of Fig. 1 and its interconnection with the system bus interface of Fig. 3 is shown.

~3~7 In connection with the storage unit 35 of Fig. 1, the system bus interface of Fig. 3 is modified in minor detail to conform with the 64-bit wide interface with a memory unit 404. In Fig. 3, the latches 205 are duplicated to provide for the 64 bits of data. More particularly, the +SB IN(0-31) bus 401 from the drivers 202 connects to a latch 206-1 and to a latch 206-2, each 32 bits wide. Latch 206-1 has data stored from the bus 401 under control of the t+ LOAD DATA IN(0-31) signal. Similarly, the latch 206-2 has data stored from the DUS 401 by the +LOAD DATA IN(32-64) line from the control 405.
The outputs from the latches 206-1 and 206-2 connect as an input to the bidirectional dirvier 406, which is the same type as the driver 202 in Fig. 3. The output from driver 406, connected to receive the data from latches 206-1 and 206-2, connects to the memory unit 404 and is a 64-bit wide bus 408. Information carried from the memory unit 404 over the bus 408 through the driver 406 is gated under control of the -GATE DATA TO STORAGE signal from the control`405 onto the 64-bit wide bus 409. Bus 409 is split into two parts and con-nected as inputs to the latches 207-1 and 207-2 which are the equivalent of the latch 207 in Fig. 3. The outputs from latches 207-1 and 207-2 connect as inputs of the latch 207-1 whenever the -GATE DATA OUT(0-31) signal is a logical 0 and selects the output from latch 207-2 whenever that signal is a logical 1. The selected data from the latches 207-1 and 207-2 appears as the +SB O~T(0-31) bus 402. The control 405 in Fig.
9 generates the -ENABLE DR signal for enabling the control gate 202-1 in Fig. 3 for connecting the information on the +SB
OUT(0-31) bus to the system bus output -SY BUS(0-31).

~3~

In Fig. 9, the control 405 also provides the +OP OUT
and +OP IN signals for storing the bus op code in the latches 209 and 210 of Fig. 3. The output Erom the latch 209 connects as an input to the system bus op code decoder 212. The op code decoder functions to detect the nature of the information on the system bus. Control 405 also generates the -INT ENABLE and the -ENABLE OP DRIVE signal for enabling the output drivers and the bidirectional drivers 203 of Fig. 3.
Further details of the control 405 are shown and described in connection with Figs. 10 and 11.
Storaqe Unit Control - Figs. 10 and 11 In Fig. 11, the output decoder 212 decodes the bus op bits +LCH OP OUT(0-3) to detect the presence of either a 1100 or a 1101 code that means that either a fetch or store operation is to occur, respectively. When either such opera-tion is to occur, the line 466 from decoder 212 is a 1 which enables the NAND gates 427, 278 and 429. 5ates 427, 428 and 429 are also enabled by the inverted -STORAGE CARD SELECTED
signal which is a signal from the memory unit 4Q4 indicating that the address to be accessed is a location within the mem~
ory unit.
The NAND gate 427 thus enabled, examines the output of AND gate 422 which is a -BUSY signal for indicating when the storage unit 35 o~ Fig. 1 is busy. Gate 422 provides a busy signal under a nwnber of conditions. One condition is the -REFRESH BUSY indication from the Ql output of a D-type flip-flop 417. This output indicates that a refresh operation is pending or in progress and is utilized when the memory unit 404 of Fig. 9 is one requiring refresh operations. The Ql output from flip-flop 417 is established by the Dl input which ~23~

connects from NOR gate 447. NOR gate 447 receives the +RE-FRESH PENDING and +REFRESH IN PROGRESS signals from the Ql and Q2 outputs from the JK-type flip-f:Lop 432.
The AND gate 422 provides a 1 for the -BUSY output in response to a 1 for the -REAL OP BUSY signal from the AND
gate 423. A 1 from gate 423 indicates that a storage operation is not in progress or pending, or such storage operation has not been started. The AND gate 423 receives as one input the Q5 output from the D-type flip-flop 431. The Q5 output fol-lows the D5 input which is connected to the output of NOR gate 443. Gate 443 senses the +STORAGE OP PENDING and +STORAGE OP
IN PROGRESS signals from the Q2 and Q3 outputs of flip-flops 432.
AND gate 423 also receives an input from the AND
gate 425. Gate 425 senses the Ql and Q2 outputs of the flip-flops 431 which in turn are set by the Dl and D2 inputs which are the signals -START NEW STORAGE OP from NAND gate 427 and -SET STORAGE OP PENDING from NAND gate 428, respectively.
Provided the control unit is not busy with any of the operations previously described, the -BUSY signal from AND
gate 422 will be a logical 1 thus enabling NAND gate 427 and producing a logical 0 for the signal -START NEW STORAGE OP. At the positive going transition of +CLOCK signal, the 0 from gate 427 is stored on the Ql output of flip-flops 431. If the -BUSY signal is a 0 meaning that the storage unit is busy at a time when the decoder output on line 466 occurs, then gate 427 cannot be satisfied and NOR gate 421 examines the inverted -REAL OP BUSY signal output from AND gate 423. If a real stor-age operation is not occurring, the inverted output of gate 423 will be a 0 and NOR gate 421 will be satisfied to produce a ~3~:)7 1 output which then satisfies NAND gate 428 causing -SET STOR-AGE OP PENDING to be a logical 0. If a real operation is occurring, then the inverted output from gate 423 will be a logical 1 and the NAND gate 429 is satisfied to produce a 0 for the -SET UNIT BUSY signal which is input to the D3 of the flip-flops 431.
The Q1, Q2 and Q3 outputs of flip-flops 431 are sensed by the NAND gate 426. If any of those signals is a logical 0, the NAND gate 426 is forced to a 1 and that 1 is stored in the Q2 output of flip-flops 470. The Q2 output of flip-flop 470 is the ~ACKNOWLEDGE OUT signal which connects to the system bus interface of Fig. 3.
The Q3 output of flip-flops 431 is inverted and con-nects to the D1 input of flip-flops 470. The Ql output of flip-flops 470 is the +UNIT BUSY OUT signal which connects to the system bus interface of Fig. 3.
The +BUS BUSY OUT signal connecting to the system bus interface of Fig, 3 is generated by the NOR gate 420. Gate 420 generates a 1 for that signal whenever the -REAL OP BUSY
signal from the gate 423 is a 0 (indicating a real storage operation) and whenever the output from a NAND gate 419 is a 0.
Gate 419 receives the Q2 output from the flip-flops 417. That output is a 1 whenever the D2 input is stored to a 1 by the output of a NAND gate 434. Gate 434 has a 1 output whenever there's no storage oyeration in progress as indicated by a 0 for the Q3 outpul of flip-flops 432 or whenever the output from NOR gate 433 is 0. Gate 433 has a 0 output whenever there is a storage op pending as indicated by the Q3 output of flip-flops 432 or the -7 state of the decoder 454 in Fig. 10 has not been reached. If the output of gate 433 goes to a 1, and a .:

3~ 7 storage operation is in progress, the output of yate 434 goes to O which has the effect of resetting the Q4 output to 0 which again will cause the output of gate 434 to return to a 1. A 1 from gate 434 is stored in the Q2 output of flip-flops 417.
That 1 on the Q2 output enables the NAND gate 419. The other input to gate 419 is the +B~S OP 3 signal inverted from the Q8 output of flip-flops 417. The Q8 output is stored from the AND-OR-INVERT gate 418. The gate 418 causes the OP 3 bit to be stored in Q8 as a function of the output from gate 423. If the storage unit is busy with a real storage operation, then the 0 from gate 423 is inverted to cause the gate 418 to store into D8 of flip-flop 417 the same state that was on Q8. If the output from gate 423 is a logical 1, meaning not busy with a real storage operation, then gate 418 causes a new op 3 bit from line 467 to be stored into the D8 input of flip-flops 417.
The effect of the operation of gates 418 and 419 is that during a bus op code of a store (1100) or a fetch (1101) bit 3 is a 0 and hence the output of gate 419 is a O so that the output from gate 420 is a 0. However, when the op code is data ~1111), bit ;~
3 is a 1 and hence gate 41~ is satisfied to produce a 0 output.
That 0 satisfies NOR gate 420 causing its output to be a logi-cal 1 for the signal +BUS BUSY OUT.
In Fig. 11, NOR gates 415 and 416 receives the +CLOCK signal. Gate 415 also receives the output of AND gate 425. Gate 425 provides a 0 output unless both -START NEW STOR-AGE OP and -SET STORAGE OP PENDING have been stored with l's on the Ql and Q2 outputs of flip-flops 431. If either of those outputs are 0, the output from gate 425 is 0 and the output from NOR gate 415 is a logical 1. The 1 provides a +LOAD DATA
IN(0-31) signal which stores data into the latch 206-1 of Fig.

9. A 0 from gate 425 is stored via the D3 input of flip-flops 417 to provide a 0 for the Q3 output of flip-flops 417. There-fore, on the next clock cycle, the 0 from the Q3 output of flip-flops 417 enables the +LOAD DATA IN(32-63) signal is a 1 which in turn latches data into the latch 206-2 of Fig. 9.
In Fig. 11, the signal from gate 425 is inverted and input to the NOR gate 414. Gate 414 receives its other input from the NOR gate 413. Gate 414 connects to the D4 input of flip-flops 417. The Q4 output from latches 417 connects as the other input to the NOR gate 413 and provides the +CANCEL
~ATCH signal to the NOR gate 453 of Fig. 10. If either the +CANCEL OUT signal from the system bus interface or the +CAN-CEL LATCH signal is a 1, then the output from NOR gate 413 is a 0 which enables the NOR gate 414 with a 0. If the output from gate 425 is also a 0, indicating that no new storage operation is to be started and that no storage operation pending is to be set, the output i-rom gate 414 is a 1 which is input to the ~4 flip-flop 417 making the Q4 output a logical 1 to generate the +CANC L LATCH signal for cancelling operations.
In Fig.ll, the +SYSTEM RESET IN signal from the sys-tem bus interface of Fig. 3 connects to the D5 input of the flip-flops 417 to provide the Q5 output, +SYS RESET. In Fig.
11, the -SYSTEM BUS BIT(0) connects to the D7 input of .he flip-flops 417 to provide the Q7 output, +BUS BIT(0).
In FigO 11, the refresh timer 472 counts +CLOCK
pulses and provides an output which connects to the Jl input of the flip-flops 432. Refresh timer 472 provides an output pulse with a frequency which is adequate to refresh the memory unit 404 of Fig. 9 whenever a memory requiring refreshing is employed. If the memory unit 404 does not require refreshing, ~l;23~7 then all of the circuitry associatecl with the refreshing oper-ation may be eliminated.
In Fig. 11, whenever the Jl input to the flip-flops 432 is set to a 1, the Ql output is clocked to provide the 1 for the +REFRESH PENDING signal. The ~1 output enables the NAND gate 442. Gate 442 is also enabled by the inverted +STOR-AGE OP IN PROGRESS signal from the Q3 output of flip-flop 432 and from the -START NEW signal from the Ql output of flip-flop 431. The function of the NAND gate 442 is to set the Q2 output of flip-flops 432 to provide a 1 for the ~REFRESH IN PROGRESS
signal whenever a refresh is pending and a storage operation is not in progress and a new storage operation is not to be sta~ted. The inverted Q2 output from flip-flops 432 provides the -REFRESH signal which connects to the memory unit 404 to refresh the memory and to the gl input of flip-~lops 432 to reset the Ql output to 0.
In Fig. 11, the Q2 output from flip-flops 431 con-nects when inverted to the J3 input of flip-flops 432. The Q3 output from flip-flops 432 provides the ~STORAGE OP PENDING
signal which is input to the NOR gate 443, the AND gate 444 and the NAND gate 437. Gate 443 provides a 0 output whenever there is a storage operation pending or in progress.
The gate 444 provides an output whenever both a storaqe operation is pending and there is one in progress and gate 445 provides a 1 output whenever there is both a refresh operation pending and in progress. A 1 from either of the gates 444 or 445 forces the NOR gate 446 to have a 0 output which connects to the D4 input of the flip-flops 431. The Q4 output of flip-flops 431 provides the -START PENDING OP sig~
nal.

~3~7 In Fig. 11, the NAND gate 437 is enabled with a 1 from the NOR gate 437 whenever there is no refesh pending or in progress. Gate 437 is also enabled whenever there is both a storage op pending and in progress. When gate 437 is thus satisfied, it provides a 0 output and forces the output from NAND gate 438 to a 1 which provides the +SET STG OP IN PROG
signal which connects to the J4 input of the flip-flops 432.
In Fig. 11, the NOR gate 435 detects whenever there is no refresh pending and whenever the -7 signal from the decoder 454 of Fig. 10 is enabled as a 0. Under those conditions, gate 435 is switched to a 1 output, which together with a 1 for the +REFRESH IN PROGRESS signal satisifes the NAND gate 436. A 0 output from the gate 436 connects to the R2 input of the flip-flops 432 and resets the +REFRESH IN PROGRESS signal to a 0.
In Fig 10, a counter 450 is present for controlling the se~uencing of the memory unit controls. Whenever a new storage operation is to be commenced, the -START NEW signal clears the counter 450 to all 0's. The QA, QB and QC outputs are input to a decoder 454. The all 0 count resulting from a clear causes the 0 output of decoder 454 to be a logical 0.
The NOR gate 457 is enabled by the 0 output and if a -REFRESH
signal is a 0 calling for a refresh, the output of gate 457 is a 1. That 1 is detected by NOR gate 461 causing counter 450 to be parallel loaded to a six count (110) and on the next clock cycle, that six count is counted to a 7 (111). Decoder 454 has its -7 output a logical 0. The -7 output from the deocder 454 connects to the Fig. 11 circuitry and operates in the manner previously explai.ned. Also, the -7 output is inverted and connected to the Jl input of the JK-type flip-flops 455. The ~2~ 7 Ql output of flip-flop 455 switches from 0 to l to remove the ROW ADDRESS STROBE unless the -START PENDING OP or the -START
NEW OP is a logical 0. Similarly, the 1 output from the Ql output of flip-flop 455 forces the -COLUMN ADDRESS STROBE sig-nal to a 1.
The -7 output from decoder 454 reconnects to the K2 input and resets the Q2 output to a 0 so that the -WRITE STROBE
is a 1.
In Fig. l0, the NOR gate 456 is enabled by a decode of the l output of decoder 454. The 0 on the l output of decoder 454 enables the NOR gates 456 and 458. If a storage operation is in progress and the store is not full, the output of NAND 449 is a 0 which satisfies the NOR gate 456 to provide a l output. That 1 output connects to the J3 input of flip-flops 455 and causes the Q3 output to go to a 1. The l output from Q3 enables the -GATE DATA FROM STORAGE signal as a 0 and enables the NOR gate 465 with a 0. With -CLOCK a 0, gate 465 is satisfied to produce a l for the +LOAD DATA OUT signal. The 0 for the l output of decode 454 also enables the NOR gate 458. If at that time, all bytes in a double word are to be employed (-FULL STORE equals 0) the -FUL1 STORE signal is out-put from gate 475 which senses the all l's condition of +LCH OP
IN(4-7) when a storage operation is in progress (e.g. between t7 and tll of Fig. 12), gate 458 is satisfied to produce a 1 which causes the counter 450 to skip ahea~ to the six count (110) by passing all the intermediate counts.
If the counts are not bypassed, the next decoded count of the counter 450 by the decoder 454 is the 3 output.
When the 3 output is a 0, the NOR gates 459 and 46Q are en-abled. The NOR gate 459 senses the output from the AND gate ~ ~ ~l-J~

448. If a storage operation is in progress and the +BUS OP(3) bit indicates that a fetch is called for, gate 448 is satis-fied to produce a 0 output which in turn satisfies the NOR gate 459 to produce a 1 for the +FET signal. The one for the FET
signal causes the NOR gate 461 to produce a 1 and load a six into the counter 450. The ~FET signal also connects from Fig.
10 to Fig. 11 to the NOR gate 430 and the D7 input of the flip-flops 431. That 1 when clocked into the flip flops 431 ap-pears as a 1 on the Q7 output which is inverted to provide a 0 for the -GATE DATA which is inverted to provide a 0 for the -GATE DATA OUT(0-31) signal. At the same time, the 1 to the NOR gate 430 causes a 0 to be stored on the Q8 output which is the -ENABLE DR signal.
In Fig. 10, the next cycle of the counter 450 causes the +FET signal from the NOR gai~e 459 to go to a 0. In Fig.
11, the +FET signal being a 0 satisfies the NOR gate 430 to produce a 1 and causes the Q7 output to be a 0 which is inverted to form a 1 for the -GATE DATA OUT(0-31) signal. The 1 from tne Q7 output of the flip-flops 431 causes the NOR gate 430 to provide a 0 output which again appears at the Q8 output of the flip-flops 431 causing -ENABLE DR to remain a 0.
The combination of the -GATE DATA OUT(0-31) signal being first a 0 and then a 1 causes in Fig. 9 the multiplexor 410 to first select data from the latch 207-1 and then from the latch 207-2. During both cycles, the -ENABLE DR signal from the Q8 output enables the output control gate 202-1 in Fig. 3.
Therefore, the data on the +SB OUT(0-31) bus 402 is gated out to the system bus, -SY BUS(0-31). In Fig. 3, the -INT ENABLE
signal is connected to a "0" level and hence can be ignored for purposes of the storage unit.

3~ ~7 In Fig. 10, the AND gate 452 detects a partial store condition, which will satisfy the NOR gate 460 on the decoded 3 output from decoder 454. NOR gate 461 will again cause the counter 450 to be loaded to a six count (110).
; The NOR gate 462 detects the output of the gates 460 and 457 and is used in the manner previously described.
Summary of Operation A summary of the operation of the present invention will be described in connection with the wave forms of Fig.
12. In Fig. 12, the signals identified along the left-hand margin correspond to the line identification employed though-out the Figs. 1 through 11.
The -CLOCK signal is generated at a common point in the system, for example, in one of the processor modules 40-0 through 40-6 of Fig. 2. The -CLOCK signal is propagated throughout the system and serves as the fundamental timing source. Information appears on the system bus 37 in Fig. 1 synchronously with the -CLOCK signal.
In the particular example of Fig. 12, the system bus is encoded with a bus op code between t5 and t7 for storing information. The -BUS OP(0-7) code for a store has the bus operand bits +BUS OP(0-3) encoded as a hexidecimal C(binary 1100) with the lower-order bits (+BUS OP4-7) encoded with a 4-bit storage protection key designated X.
Between t5 and t7, the information on the 32-bit bus 37-1 of Fig. 3 is a corresponding address for the storage unit 35 of Fig. 1 at which the store operation is to occur. In the two clock cycle following the store op code between t5 and t7, the +BUS OP(0-3) field contains a hexidecimal F (binary 1111) indication which specifies that the system bus information 3~Q~

field contains the data which is to be stored. The low-order bits +BUS OP(4-7) contain a field which marks the parituclar bytes within the data word on the information bus, -5Y BUS(0-31) which are valid. The F data code appears in the example of Fig. 12 in the clock period between t7 and t9 and ag~in between t9 and tll.
The corresponding information field on the -SY
BUS(0-31) bus contains the data field DATA(0-31) between t7 and t9 (a first word) and the data field DATA(32-63) between t9 and tll (a second word).
In a typical example of the Fig. 12 operation, the bus op codes between t7 and tll are generated by one of the processor modules of Fig. 2 which obtains access to the system bus 37 of Fig. 2 and particualrly the information field -SY
BUS(0-31) and the operation code field, -BUS OP(0-7), 37-2 of Fig. 3. In response to such operation codes and information fields on the system bus, the storage unit 35 of Fig. 1 re-sponds to accept the address and data.
In Fig. 12, the +CLOCK signal is the signal gener-ated in the storage unit and interface of Figs. 9, 10 and 11 in response to the -CLOCK signal of the system bus.
In Fig. 11, it is assummed that the bus operation code of CX between t5 and t7 is decoded by the bus op decoder 212 of Fig. 11 to provide a logical 1 on the line 466 input to the NAND gate 427. It is assumed that all other conditions enabling gate 427 are present so that the -START NEW STORAGE
OP signal is a 0. On the next positive going transition of the +CLOCK signal, at approximately t6+, the output of gate 427 is stored in the flip~flops 431 to provide a ~1 output.
For purposes of the present example, that Ql output 3~

makes the -START NE~ signal a 0 which connects to the clear input of the counter 450 in Fig. 10. It is assummed that the -7 has previously disabled the counter 450 causing the counter 450 to hang after 7 count (111). The 0 for the -START NEW
signal clears counter 450 thus causing the -7 output from de-coder 454 to remain a 1. The 1 for the -7 decoded output connects to the NOR gate 433 in Fig. 11 forcing its output to a 0. That 0 forces the NAND gate 434 to a 1 which in turn appears on the D2 input of the flip-flops 417 at t6+. The t6+
positive going transition of the +CLOCK signal appears on the Q2 output which is inverted to a 0 as an input to the NOR gate 424. At the same time, the output from the AND gate 423 switches to a 0 so that the output of NOR gate 424 is a 1 for the +MEMORY BUSY OUT signal which is inverted to form a 0 for the -MEMORY 8USY signal on the system bus. The -MEMORY BUSY
signal appears as a 0 at approximatley t7 in Fig. 12 and re-mains that way until approximately tl5.
In Fig. 12, the -BUS BUSY signal is maintained a 0 between t5 and t9 by the processor module 40-0. The +BUS BUSY
OUT signal in Fig. 11, however, is the output of NOR gate 420 and it remains a 0.
In Fig. 11, the Ql output from the flip-flops 431 is a 0 for the -START ~E~ signal which connects as an input to the NAND gate 463 in Fig. 10. Gate 463 has its output forced to a 1 which is invert~d to 0 for the -ROW ADDRESS STROBE signal as shown at approximatley t7 in Fig. 12. On the next negative going transition of the inverted +CLOCK signal at t8, the 0 for the -START NE~ signal clears the counter 450 causing the seventh decode of the decoder 454 to remain a 1. That 1 is inverted to a 0 for the Jl input of the flip-flop 455 causing ~L23~37 the Ql output to go to 0 and to enable the NOR gate 464 in Fig~
10. At the same time, the -STORE OP IN PROG signal is also a 0 so that the output from gate 464 is a 1 inverted to a 0 for the -COLUM~ ADDRESS STROBE which is shown approximately at t8 in Fig. 12.
In Fig. 12, the -WRITE ';TROBE occurs three -CLOCK
pulses after the -START NEW signal clears the counter 450 at approximately t8 or at approximately T14. The three clock pulses cause the counter 450 to provide an input to the de-coder 454 which enables the three decoder output to a 0 which in turn enables the NOR gates 459 and 460. Since a fetch is not occurring, gate 459 is not satisfied and produces a 0 output. It is assumed, however, that conditions are present for the gate 460 to be satisfied with -PARTIAL STORE a 0 output from the NAND gate 452. Gate 452 has a 1 for the +STORAGE OP
IN PROGRESS signal and a 1 for the -FULL STORE signal. Since a store operation has been indicated, the bus op code bit 3 position is a 0 and hence -BUS OP (3) is a 1, thereby satisfy-ing gate 452. Accordingly, the output from NOR gate 460 is a 1 and that 1 causes a 0 output from NOR gate 462. The 0 output from gate 462 satisfies the NOR gate 453 to provide a 1 to the J2 input of the flip-flops 455. During that clock pulse, the Q2 output of flip-flop 455 goes to a 1 so that -WRITE STROBE
goes to a 0 at approximatley tl4 time. The 1 output from the NOR gate 460 also causes the output of NOR gate 461 to go to a 0 to enable the load input of the counter 450. On the next negative going -C`LOCK signal, counter 450 is stepped from the loaded six count to the seventh count causing the seventh de-coded output of decoder 454 to go to a 0. The Q2 output of flip-flops 455 goes to a 0 and the -WRITE STROBE goes to a 1 at 3~'~fq approximately tl6. At the same time, the Ql output of flip-flops 455 goes to a 1, so that the --COLUMN ADDRESS STROBE goes to a 1 at tl6 as does the -ROW ADDRESS STROBE under the as-summed conditions.
In Fig. 12, the -GATE DATA FROM STORAGE goes to 0 at approximatle~ tlO follo~ing the Q3 output of the flip-flops 455. The Q3 output is switched to a 1 in repsonse to the output from the NOR gate 456. NOR gate 456 is enabled with a 0 from the decoded 1 output of the decoder 454 one -CLOCK cycle after the counter 450 is cleared to all 0's at approximately t8. When the counter 450 counts to the next count, the gate 456 has its output returne~ to a 0 and Q3 follows it so that the -GATE FROM STORAGE signal returns to 1 at approximately tl2.
In Fig. 12, the -ACKNOWLEDGE signal is switched from a logical 1 to a lo~ical 0 at approximately t9. Prior to t8, the outputs Ql, Q2 and Q3 from the flip-flops 431 have all been logical l's so that the output from gate 426 has been a logical 0 and the ~ACKNOWLEDGE OUT from the Q2 output of flip-flops 470 is a 0. When Ql goes to a lofcial 0 at approximately t8, the output of NAND gate 426 goes to a 1. On the next positive going transition of +CLOCK, at approximately t8+, the 1 is clocked into the flip-flop 470 and Q2 goes to a 1 for +ACKNOWLEDGE OUT at approximately t9 as shown by the 0 for -ACKNOWLEDGE in Fig. 12.
At t6+, the Ql output of flip-flop 431 is a 0 which forces the output from NAND gate 438 to a 1 as an input to J4 of flip-flops 432. The t7+ transition of ~CLOCK, as inverted, stores the 1 on the Q4 output of flip-flops 432. Therefore, at t7+, the output of NOR gate 443 ~oes to a 0. That 0 becomes ,~ . .

stored on the Q5 output of flip-flops 431 at t8~. Therefore, at t8+, the -REAL OP BUSY output of AND gate 423 and the -BUSY
output of AND gate 422 each go to 0. In reponse thereto, the -START NEW STORAGE OP signal output f:rom NAND gate 427 goes to a 1. That 1 is stored on the Ql output of flip-flops 431 at tlO+. In response thereto, gate 426 goes to 0 which is stored in flip-flop 470 at tl2+ causing -ACKNOWLEDGE to return to 1.
While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that those changes in form and details may be made therein without de-parting from the spirit and the scope of the invention.

Claims (2)

WHAT IS CLAIMED IS:

1. A data processing apparatus comprising, a system bus having an operation code field for transmitting an encoded system operation code and having a system information field for transmitting associated system information where the associated system information has a function determined by the system operation code, one or more first unit connected to said system bus, said first units including means for generating system operation codes for transmission by the operation code field of said system bus and including means for generating associated system information for transmission by the in-formation field of said system bus, one or more second units connected to said systems bus, said second units including means for accepting a predetermined system operation code and associated system information from said system bus and including means for decoding the predetermined system operation code to perform a function with the associated system information, access control means for controlling the access of said units to said system bus.

2. The data processing apparatus of claim 1 wherein one of said first or second units is a storage unit connected to said system bus for transferring information between said storage unit and the other of said first and second units.