CA1117204A - Integrated switching and transmission network - Google Patents
Integrated switching and transmission networkInfo
- Publication number
- CA1117204A CA1117204A CA000310754A CA310754A CA1117204A CA 1117204 A CA1117204 A CA 1117204A CA 000310754 A CA000310754 A CA 000310754A CA 310754 A CA310754 A CA 310754A CA 1117204 A CA1117204 A CA 1117204A
- Authority
- CA
- Canada
- Prior art keywords
- link
- time
- modules
- module
- switch
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q11/00—Selecting arrangements for multiplex systems
- H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
Abstract
ABSTRACT OF THE DISCLOSURE
An integrated switching and transmission network comprises a digital switching system for transfering communication information without congestion. The switching consists of one-way switch modules which are connected through two-way time division multiplex transmission links to link modules each including a control unit for establishing communication paths within an associated line group as well as for controlling the switch in cooperation with the control units of other line groups. Each of the switch modules is allotted to two of the two-way links and comprises a time stage and a signalling logic circuit. The input of each module is connected exclusively to one way of one of the two-way links, whereas the output of each module is connected to the other way of the other two-way link. For the reliable control of the network, transmitting control units generate signals. Each signal addresses one of the signalling logic circuits, which converts the signal to an operation signal by which the associated time stage is operated or to a signal intended for the receiving control unit. Furthermore, control messages are transferred between the control units through the time stages. The time stages carry out the required time inter changes for the transfer of said control messages and communication information between the line groups.
An integrated switching and transmission network comprises a digital switching system for transfering communication information without congestion. The switching consists of one-way switch modules which are connected through two-way time division multiplex transmission links to link modules each including a control unit for establishing communication paths within an associated line group as well as for controlling the switch in cooperation with the control units of other line groups. Each of the switch modules is allotted to two of the two-way links and comprises a time stage and a signalling logic circuit. The input of each module is connected exclusively to one way of one of the two-way links, whereas the output of each module is connected to the other way of the other two-way link. For the reliable control of the network, transmitting control units generate signals. Each signal addresses one of the signalling logic circuits, which converts the signal to an operation signal by which the associated time stage is operated or to a signal intended for the receiving control unit. Furthermore, control messages are transferred between the control units through the time stages. The time stages carry out the required time inter changes for the transfer of said control messages and communication information between the line groups.
Description
~7Z~
The present invention relates to an integra-ted swi-tchiny and transmission network comprising line groups. Each line group is connected to an associated link module containing a transmitter and a receiver. Each link module is connected to an associated link connection consisting of a first link and at least a second ¦
link in order to transfer, in time division multiplex form, digital communication- and signal information from the transmitter to a congestionless digital switching system containing a matrix of r identical switch modules and from the switching system to the 10receiver. The switching system carries out space interchanges and time interchanges in order to switch digital information which is transferred by means of the mentioned link connections between arbitrary time division multiplex channels.
In a telecommunication system similar switch modules are used to provide switches which are easy to handle and which enable the capacity of the system to be expanded during normal operation.
The switch module only enables the system to be expanded if a module has been so constructed from the beginning that its properties can remain unchanged independently of the switching capacity o e the
The present invention relates to an integra-ted swi-tchiny and transmission network comprising line groups. Each line group is connected to an associated link module containing a transmitter and a receiver. Each link module is connected to an associated link connection consisting of a first link and at least a second ¦
link in order to transfer, in time division multiplex form, digital communication- and signal information from the transmitter to a congestionless digital switching system containing a matrix of r identical switch modules and from the switching system to the 10receiver. The switching system carries out space interchanges and time interchanges in order to switch digital information which is transferred by means of the mentioned link connections between arbitrary time division multiplex channels.
In a telecommunication system similar switch modules are used to provide switches which are easy to handle and which enable the capacity of the system to be expanded during normal operation.
The switch module only enables the system to be expanded if a module has been so constructed from the beginning that its properties can remain unchanged independently of the switching capacity o e the
2~switchin~ system. Switch modules which are included in frequency division multiplex telecommunication systems and which only perform space intershanges have been well known for a long time. Such analogue switch modules form stages interconnected by means of con-nection link groups which during an expansion of the system are modified by adding additional modules. 5witch modules, however, which are included in time division multiplex systems are more r `~ difficult to provide because normally both space interchanges and time interchanges occur to transfer information between su~scribers' lines connected to the time division multiplex switch- and trans-3Q mission system. Similar modules can only be provided if one module carries out both types of interchanges.
It is known to use time division multiplex switching ~17~
, , .
systems whlch, for example, are indicated as "time-space-time"-- or "time-space-space-time"- or "space--time-space"- systems, the indication showing in which turn information coming in to the switching system in time division multiplex form is transferred between time stages to carry out time interchanges and between space stages to carry out space interchanges.
A known module switch for time division multiplex digital information, which is described in "Colloque International de Commutation Electroni~ue, Paris 1966, pages 513-520", mainly contains similar modules each switching between a number of input llnks and a number of output links, the time division multiplex format, i.e. the number of time slots per frame, being different for different types of links, and the space interchanges within a module being obtained by means o~ an inter-nal multiplex format having at least as many time slots as there are information channels coming to the module. Time division multiplex links arranged between the modules have the same function as the mentioned connection link groups, one group being constituted by one single link connection having a time division multiplex format which guarantees that connections are established without congestion.
In Canadian ~atent No. l,068,80~, issued December 25, 1979 ~Braugenhardt et al, a "time-time"-switching system is described which makes use of input modules which through a single common time division multiplex connection are connected to output modules. Thanks to said common time division multiplex ` connection a space stage is avoided and compared to the first mentioned known module switch, improved handling possibilities are obtained. When a module defect occurs the faulty module is replaced by a faultless module without affecting the switching capacity of the other modules. During an expansion of the system, further input- and output modules are connected to the ~1~L7Z~
-' mentioned common time division multiplex connection, if required during operation.
.
- 2a -Besides the above mentioned points concerning the modules forming the switching sys-tem,the way in which the paths through the switch are established, i.e. the control of the switch, plays an impoxtant part in the reliability and the ; profitability of a tele-communication system. It is known, for example fr~m the above mentioned publications, to control a digital time division multiplex switch by means of a central computer, which receives from subscribers' lines or from remote concentrators control signals defining an order for establishment of a connection. The computer finds, owing to the mentioned control signals the addresses, indeces, time slots, connection link numbers and so on which, depending on the chosen switching system, have to be transferred to the time- and space stages and the modules of the switch in order to establish the in-structed connection. In the oldest time division multiplex ~
systems an extra control communication system was arranged Eor ~;
the connection of the computer. In modern and improved -time multiplex systems, for example the digital "time-space-time"-system being described in the Canadian patent No. 1,001,27~
issued Dec. 7, 1976 (Edstrom et al), a relief of the computer is aimed at, at the same time as the mentioned control cummunica-tion system as far as possible is included in the time division multiplex information transferring system.
The purpose of the present invention is to achieve an easily handled and an easily expandable IST (Integrated Switchin and Transmission)-network whose congestion free -~ "space-time"-switching system comprises identically designed switch modules which are controlled in a decentralized manner without an extra control communication system and completely without a centrally arranged control unit or computer.
Accordingly the present invention provides in an integrated switching and transmission network comprising ~r-~ ~
~ 3 ~
117Z~L
a plurality of line yroups connected to a congestion free digi-tal switching system comprsing identical switch. modules, through respective link modules each containing a transmi-tter and a receiver and through respective link connections each containing a first link and at least a second link for transferring in time division multiplex form digital communication information and ~ signal information from the transmi.tter to the switching system : and from the switching system to the receiver respectively, ~ said switching system carrying out space interchanges and time 10 interchanges to switch between arbitrary time division multiplex channels for digital information which is transferred by means of said link connections, wherein the improvement comprises that each of a first group of said switch modules is associated with a respective pair of said link modules and has, . ~
through said link conenctions its input connected to the :~ transmitter of one of said associated pair of link modules and ` its output connected to the receiver of the other of said associated pair of link modules, that each module of said first ~ group of switch modules comprises a -time stage means for 20 carrying out time interchanges of the communication information being switched between the associated transmitter and the associated receiver, that each module of sai.d first group of switch modules further comprises a signalliny logic means for converting signals received from the associated transmitter ; to operation signals which control the associated time stage, as ` well as to signals intended for the associated receiver, that ~ the switching system lacks a connection between the input of one and the output of another of said switch modules, that said signalling logic means of the switch modules lac~ connections to any central control unit included in the switchin~ system, and that each link module comprises a control means for establish-; ing communication paths within the line group associated with ~ 4 _ .. .
7Z~4 ; that link module and, in cooperation with the control units of other line groups, for controlling the switching sys-tem upon , establishing connections between that line group and said other line groups.
The invention will now be described in more detail ; by -i I
:`' . - 4a -~L7Z~L
way of e~ample only, in which:
Fig. 1 is a block diagram of an IST-network, Fig. 2 shows a synchronizing clock for use with the IST
network;
Fig. 3 shows a time stage of a switch module;
Fig. 4 shows three signal receiving units which are included the signalling logic circuit of a switch module; and - Figs. 5 and 6 each show a signal converting unit.
Fig. 1 showsn linegroups LGl-LGn between which telecom-munication connections are achieved by means of n link modules ; LMl-LMn and a digital switching system comprising at least n~-n switch modules S~ ach link group, for example LGl, is associated J~
with a link module LMl comprising a transmitter Tl and a receiver r Rl which through time division multiplex links Lal and Lbl are respectively connected to switch modules SMl/2 - SMl/n, which are shown in rows in Fig. 1, and switch modules SM2/1 - S~ln/l which ` are shown in columns. The time division multiplex links transfer in time division multiplex form digital communication- and signal information from the link modules to the digital switch and vice versa.
; The IST network which is shown in Fig. is simplified in order to clarify the description and, only those network components which are needed to explain the present invention are shown. The ~ time division multiplex synchronization of the IST network, for ; instance, is indicated by means of only one clock CL which is connected to all switch modules so that the receiver Rl-Rn receive ~ the information coming from the switching system during synchronous ; frames. Within each link module a frame synchronization is performed ~-~
so that also the lnformation being transferred from the transmitters 3Q Tl-Tn to the switch is synchronous. In practice the synchronization conditions are not so ideal but phase displacements and so cal~ed plesiochronous information transmissions to the switch occur owing ~ .7;~
. ,, to the fact that in larger networks the link modules are allocated one clock each. It is, however, known to synchronize the informa-- tion coming to the switch for example by -taking the fastest clock and arranging phase compensation circuits in the link modules or by making use of so called "pulse stuf~ing" arrangements to avoid information losses. For convenience it will be assumed that the link modules, link connections and switch modules form an ideally synchronized system.
A time division multiplex format is, as known, mainly defined by its frame frequency, which is, for example 8 k~z, and I -by the number of time slots per frame period; for example, there may be m groups of 32 time slots in each frame. In each time slot an information unit is transferred, which in a digital system con-sists of a digital word consisting of a number of bits, for example 8. Most time slots in a frame period are allotted to the communica-; tion information but a few time slots, for example 2 within a 32-time slot group, are reserved for the purpose of synchronization ! ~.
and signalling. It is assumed in the proposed IST-network that the synchronization does not demand a time slot in each frame period but that so called idle signals indicating that there is no need for signalling within a given time slot group are used as synchroni-zation signals so that the few time slots which would normally be ; required for synchronization can be used for digital signals and signal messages as will be described in more detail in relation to the communication channels of a 32-time slot group, which channels may partly be intended for pulse code modulatedspeech transmissions and partly for data communication.
It is known in an IST-network to use both parallel and serial transmission and to vary between time division multiplex formats having different multiples of 32-time slots. It is assumed for the network shown in Fig. 1 that the same format and transmission principle is used for the links La, ~b. Known parallel serial or ~17Z~
serial parallel converters, if any, are included in the link- and switch modules of the network and are not shown in ~ig. 1. Addi-tionally analog/digital- and digital/analog converters can be arranged either in the subscri~ers' equipment or in the link ~odules, but these are not shown as they do not form part of the present invention. Also, concentrators (not shown) may be included in the link modules if a line group comprises a greater number of f~
subscribers' lines than there are time slots in the time division fff multiplex format being chosen for the link connections.
In Fig. 1, each link module comprises at least one control unit CU which is allotted to a line subgroup. Each control unit controls the allotting of a number of time slots to the respective link pair ~ax/Lbx; for example one of the mentioned m 32-time slot groups, to transfer the communication information of the subgroup and associated signal information to and from the switch. In Fig. 1 a system is shown which is so extended that only one control unit is arranged in each link module except in the link module LM2 which comprises m control units CU2,1 - CU2,m, and so that the line group LG2 consequently comprises m subgroups LSG2,1 - LSG2,m. The men-tioned m control units have the use o~ a 32-time slot 3roup each, i.e., altogether they have the use of all of the time slots of the link pair La2/Lb2. The link module LM2 comprises a concentrator not shown in Fig. 1 if one of the mentioned line subgroups comprises > 30 subscribers' lines, because by means of the associated control unit 30 lines a~ most can be connected at the same time in time ~ division multiplex ~orm for example to the link connection La2.
A control unit included in a link module is designed in such a way that it controls the establishment of connections within its own line subgroup. If the link module only comprises one con-3Q trol unit the switch does not necessarily need to comprise a switch module switching between the time slots on the link pair connected to this link module but the link module can contain, in this case, : ~h~7;~
, ~
an internal switch to achieve in-ternal subgroup connections.
Furthermore,if thesubscribers~lines of this subgroup each have a separate connection to the link module, the internal switch con-stitutes a space stage. The advantage of having an internal switch is that the subgroup internal communication connections on the associated link pair do not make use of time slots intended for communication information nor time slots intended for signal infor-mation. Thus an increased switching capacity is obtained. As, on the other hand, the communication information of the subgroup is nonetheless converted into time division multiplex digital infor-mation which is switched through the switching system to other link modules, and as the internal switch required in the link module mostly cannot be designed simpler than a switch module, the greatest 9 possible uniformity of the IST-network is obtained if the switching system comprises n2 equal switch modules. Switch modules, for example SM2/2, connected through a link pair La2/Lb2 to the assoc-iated link module LM2 each must, however, always be provided if the link modules comprises > 1 control units because connections between subgroups belonging to the same line group, ~or example between ~SG2,1 and LSG2,m, can be connected only through the switching system. In the switch shown in Fig. 1 the modules S~l/l, S~ln-l/n - 1 and SM/n have been ommitted and it is assumed that the link modules LlIl, LMn - 1 and LMn contain internal switches which are not shown.
A control unit included in a link module is furthermore designed in such a way that it, together with contro] units of other subgroups, controls the swltch when establishing external connec-tions between its own subgroup and the other subgroups of the same line group whereby the time slots intended for signal information are used. This means in other words that the control intelligence of the whole IST-network is distributed over the decentralized control units. Each of the modules of the switch comprises a time stage TS and a signalling logic S~ stage, which are completely %~
passive and without intelligence of their own. Each module, besides -the clock CL/ in order to achieve synchronism, is connected exclu-sively on the input side to one of the transmitters Tl - Tn and on the output side to one of the receivers R Rn. Thus the switch is not provided with any intelligent central control unit. The decen-tralized control units of the link modules obtain their intelligence for example by means of programs stored in memories. The stored program controlled control units do not need to be described in detail in relation to the present invention. When establishing the external connectionsthe mostimportant functionsof thecontrol unitsof ~he proposedIST network thatis thesignalling eitherbetween control units or between a control unit and a switch, are obtained by means o~ computers known per se, such as Motorola's micro computer M6800~ r programmed in a suitable manner.
. ! -The signalling between two control units aims at inter-changing messages which are coded for example according to a signal system having the CCITT-designation X-25. The structure of the signal system does not need to be described in detail in order to understand the present invention but it is sufficient to mention ~0 that each message unit is coded in such a way that the receiving control unit knows when all of the message unit, consisting of an ; individual number of digital words, has been received. Furthermore the structure of the signal system is such that an interchange of message units in both traffic directions results in both control units knowing whether a communication connection is not to be .-established through the switching system is to be established or is to be released by means of addresses and time slots, which have been obtained due to signalling between two control units. In the proposed IST-network the messages of the signal system are trans-mitted during one of the time slots intended for signal information,below called time slot 1~. In order to transmit a message unit for example from -the control unit CU2,m to the control unit CUl, the _ g _ 1~7Z~
,_ , .
switch module SM2/1 must perform a time in-terchange from time slot 16 within the 32-time slot group allotted to the control unit CU2,m to the time slot 16 within the 32-time slot group allotted to the control unit CUl, a so called 16-16 interchange. The operation of the switch module will be described below. Before the control unit CU2,m starts transmitting the mentioned message unit, it has to know that neither the switch module SM2/1 being ordered by for example the control unit CU2,1 nor one of the switch modules SM >
2/1 being ordered by one of the control units CU > 2 is carrying out any 16-16 time interchange to transfer another message to the ; control unit CUl.
In order to achieve a reliable message communication, the control unit CU2,m transmits first during the second of its time slots intended for signal information, below called time slot 0, a call signal addressed to the control unit CU1. The address to the control unit CUl also defines the only switch module SM2/1 through which the call signal has to be transferred. A control unit trans-mits the call signals one at a time, indicating that the transfer of the intended message uni-t has to be finished before this control unit transmits a new call signal.
Owing to call signals which a control unit has received during its allotted time slot 0, this control unit transmits answer signals one at a time during its time slot 0, indicating that the transfer of the intended message unit by means of the respective call signal has to be completed before this control unit transmits a new answer signal concerning another call signal. In the assumed signalling example the control unit CUl transmits, according to the mentioned "one at a time"-rule, an answer signal addressed to the control unit CU2,m. The address to the control unit CU2,m also defines the only switch module SMl/2, through which the answer signal has to be transferred.
The mentioned "one at a time"-rule concerning calls and ... .. .
z~
answers renders the following acknowledgemen-t operations possible:
A call signal is continuously repeated until the associated answer signal has been received. When the received call signal ceases the called control unit knows that its answer signal has arrived at the calling control unit. Also an answer signal is repeated at least until the first word of the message unit has been received. When the answer signal ceases the calling control unit knows that the -mentioned 16-16 connection works reliably. There are, however, maximum times to how long the call- and the answer signals are transmitted. If no answer signal or no message work has been re- ;
ceived after the maximum time the waiting control unit yenerates an alarm signal.
` When the called control unit, the control unit CUl 9 according to the example, has received the whole message unit during its time slot 16, it transmits to the calling control unit, the control unit CU2,m according to the example, during its time slot 0 a signal the contents of which indicate that the message unit either is correctly received or has to be retransmitted. The ; mentioned "correctly received"- and "retransmission"-signals are modified answer signals having the property in common that they do not have to contain the address of the called control unit/ because due to the "one at a time"-rule the calling control unit knows that such answer signals have to come from the called control unit. The mentioned acknowledgement principle is also used to complete the transfer of the message unit in a reliable manner. The called control unit continuously repeats the mentioned "correctly received"-signal The calling control unit answers hy continuously trans- !
mitting a "correctly received"-signal to the called control unit.
When the called control unit receives the "correctly received"-signal it completes its "correctly received"-transmission. When the calling control uni-t no longer receives "correctly received"-signals also the calling control unit completes its transmission.
~7Z~
The mentioned signalling process results in a single message unit being reliably transferred in one traffic direction.
In order to achieve a message interchange an equivalent process is repeated for the other traffic direction, whereby the two con- ~
trol units change their roles.
Besides the mentioned "one at a time"-rule there is a first priority rule according to which a control unit has to answer received call signals before it as the calling control unit starts or continues a message interchange. The mentioned first priority rule prevents too large an accumulation of unanswered call signals.
The mentioned maximum time valid for call signals is determined with reference to the fact that a contrQl unit can be called by all the other control units of the IST-network during the same frame period.
~ Queuing problems are obtained not only in the called control unit but also in the concerned switch modules and the concerned link connection in order to transfer the call signals from the switch to the called control unit. Furthermore the mentioned types of answer signals share in the queuing of signals addressed to a control unit J
but due to the "one at a time"-rule there is maximum one signal of answer type together with a number of call signals. The solution af the mentioned queuing problem will be described below.
During frame periods, which are neither occupied to trans-fer the hitherto explained signals of call- or answer type nor establish signals or release signals being explained as Eollows, the time slots 0 on the link connections of the IST-network are used to transfer the above mentioned idle signals.
~ The signalling between the control units and the switch aims at establishing or releasing the mentioned 16-16-connections between the control units, as well as ml,tl - m2,t2 connections which are included in communication connections between the sub-scribers' lines. Thus, the switch performs time interchanges from the time slot 16, being allotted a transmitting control unit, to 1~7 , ~, the time slot 16, being allotted a receiving control unit, as well ; - as from the time slot tl associated with the 32-time slot group ml in question, during which the communication information in question .... .
; is received by the switch, to the time slot t2 associated with the 32-tlme slot group mZ in question, during which the switch transmits the mentioned communication information.
As will appear from the explanation of the passive func-tions of the switch the above mentioned call signals are used to establish the mentioned 16-16-connections. In order -to establish an ml,tl - ml,t2-connection, a control unit, for example CU2,1, the nl-number of which is 2, transmits an establish signal during its allotted time slot 0 which at the same time defines the 32-time slot group ml=l of the control unit. The establish signal contains an establish code as well as an n2-number, for example n2=2, to address the only switch module 1n question, the switch moduie SM2/2 according to the example. The establish signal contains furthermore the mentioned time slots tl and t2 as well as an m2-number, for example m2=2, to indica~e the receiving subgroup of the subscribers' lines and its 32-time slot group including the mentioned time slot t2.
According to the example the establish signal indicates a one-way communication connection from a subscriber's line of the subgroup LGS2,1 (nl=2, ml=l) to a subscriber's line of the subgroup LGS2,2 ~ ;
(n2=2, m2=2). The signalling logic of the receiving switch module SM2/2 converts the establish signal into operation signals by means of which the time stage of this switch module establishes the ~i .
intended connection. The establish signal, owing to its n2-number, r does not influence any other time s~age in another switch module.
~n this elegant manner the space in-terchanges of the switch are carried out without conventional space stages and without special space interchange signals.
In order to release an ml,tl - m2,t2-connection a control unit transmits during its allotted time slot 0 a release signal .7;Z~
. .
defined by means of a release code, the mentioned release signal ; differing from an establish signal only by the fact that an infor-~. mation of a tl-time slot is unnecessary. A release of a 16-16-- connection is signalled to the switch either by means of the above mentioned "correctly received"-acknowledgement signal or by means of a release signal containing t2=16.
The mentioned signals generated by the control units each comprise, as the message units of the signal system, a code and r~ variables in question such as the mentioned nl,n2- and ml, m2-number addresses and tl, t2-time slots. In a larger system having for example ~ link modules each comprising 32 control units, in order to switch in a congestionless manner and without need for concentra-tors between about 8000 subscribers' lines, the signals cannot be each defined by means of only one digital word comprising 8 bits.
In IST-time division multiplex systems, so called multi frames are introduced to transfer such signals comprising several words, .~
whereby multi frames having a constant or a varying number of frame periods exist. In connection with the explanation of the working manner ofthe switchthe mentionedknown multi frame technique will to the necessary extent be referred to.
; Below, principles are described concerning the passive operation of a signalling logic circuit in one of the switch modules ~ of the proposed IST-network. The signalling logic circuit comprises - receiving units only reacting to the associated n2-number address and respective signal code, and comprises converting units which convert signals coming to the switch module to the mentioned opera-. ., ,, ._ ~_ tion signals and to signals going out from the switch module. The converting units for treating the call signals decide, according to a cimple second priorit~ rule, which of the call signals coming at 3Q the same time and addressed to the same receiving control unit is converted into an operation signal to establish respective 16-16-connection to this control unit, and into a call signal going out to this control unit. The converting units for treating signals of "~ the above mentioned answer types have a simpler design than the call converting units. Due to the above mentioned "one at a time"-rule it is sufficient if the receiving control unit receives the answer code while a converted call signal has -to give information from which control unit of which link module the call comes. The treatment of the answer signals does not demand any priority rule.
- A receiving control unit, for example C~2,2, receiving signals from switch modules SMl/2-SMn/2 shown in column in Fig. 1, at the same time can be called through all switch modules of respec-tive column (n2=2) and can receive an answer through one of the switch modules of the column. If the receiving control unit is connected to the mentioned column of switch modules by means of a common time division multiplex link, according to the example and Fig. 1 link Lb,2 a multi frame hasto be decided concerning the time slot O of the receiving control unit. Within this multi frame, for example the switch modules of the column and consequently the calling link modules are associated with an nl-frame period each to transfer call signals, and with a frame period com~on to all of the switch 2Q modules in a column to transfer signals of answer type. The men-tioned common frame period is not needed if the mentioned call- and answer converting units are modified so that an answer signal inhibits a call signal. Each switch module then transmits during a time slot O only one signal, eitl~er an answer type signal or a call signal. If, furthermore, a separate time division multiplex link is arranged for each of the switch modules, in order to trans-fer information to respective link module, one avoids the mentioned multi ~rame forming concerning signals going from the switch. In an IST-network modified by means of the mentioned separate links, 3Q which will be explained in connection with Fig. 6, one obtains a quicker signalling process having shorter maximum times than the system shown in Fig. 1 having the mentioned common links Lb.
72~
. . .
Fig. 2shows thecommon clock CL ofthe switchingsystem, men~
tioned at the beginning,in orderto generatea time divisionmultiplex format comprising 32 time slot groups each having 32 time slots.
A frame period lasting f=125 ~s comprises 32 x 32 time slots so that the duration of each time slot, p is approximately 122 ~s.
The time slots are designated by means of two numbers 0 < m ~ 31 -0 < t < 31. The time slot 0-0 starts a frame period, precedes the frame period 0-1 and follows the last time slot 31-31 of the previous frame. The clock defines the time slots by means of pulse series shown in Fig. 2, whicll are generated in a known manner, for example by means of a shift register. It is assumed that the IST-network uses the parallel transfer principle, therefore there is no dividing bit within the time slots. The clock is provided with an output 0 which according to Fig. 2 transmits a pulse series which within each time slot comprises a pulse and an interval. The 0-pulses are needed in order to avoid, in a known manner, coincidence in the writing- and reading operations described below in connection with the time interchanges. The clock is driven by an oscillator OS, the basic frequency of which is 23 5 5 1 kHz ~16 MHz.
Fig. 3 shows a time stage known per se to perform time interchanges within the mentioned 32 x 32 time division multiplex format. The time stage mainly comprises an information memory IM
and an address memory AM. The writing inputs of the information memory are through an AND-gate Gl and through 32 x 31 AND-gates G2 connected to the link La,nl for incoming information. During the ~-pulses of a frame, communication- and message information arriving during the time slots m 1 to m-31 is written in associated locations of the information memory, while signals arriving during the time slots m-0 are not registered in the information memory. Thus, the ' 30 communication information and the message information transferred on the link La,nl is registered in all of the switch modules con- ~
nected to the link, the mentioned switch modules forming a row in - 16 ~
Fig. 1. The address memory AM has its reading outputs connected to a time interchange decoder TDEC through 32 x 31 AND-gates G3, the mentioned decoder addressing the information memory during the 0-intervals for reading to the link Eb,nl/n2 going out from the switch module. The nl- and n2-designation defines respectively, according to Fig. 1, the transmi-tter Tnl and the receiver Rn2 assoc-iated with the time stage.
In Fig. 3 it is assumed that the time interchange decoder receives the addresses 31-1 and 0-16 respectively during the time slots 0-31 and 31-16, while during the other time slots the addresses m 0 are transferred, which do not occur in the information memory.
The communication information ki registered in the information memory during the time slot 31-1 is transferred during the time r~
slot 0-31 to the link Lb,nl/n2, and the message information mi registered during the time slot 0-16 is switched to the time slot 31-16, but the remaining information registered in the information memory i5 not transferred to the outgoing link. The address memor~
AM has its writing inputs connected, through an opera-tion decoder - ODEC and through AND-gates G4 activated during the 0~pulses, to the operation inputs 01 and 02 of the time stage.
Fig. 4 shows signal receiving units SRU-C, SRU-A and SRU-E, which are included in the signalling logic of a switch - --module SMnl~n2 and which receive call- answer- and establish signals ` registered in a signal register SREG. For the above mentioned ; release signals and signals of answer type the signalling logic comprises further receiving units corresponding to the mentioned receiving units SRU-E and SRU-A and therefore not shown in Fig. 4.
The mentioned signal register SREG registers by means of an OR-gate G5 and an A~JD-gate G6 during the time slots m-0 idle-, - 30 call, answer-, and establish- or release signals coming from the link La,nl. Each call- or answer signal consists of two digital words, the first of which contains besides respective code C or A, ~1~L7Z~
.
-~an n2-number in order to address the switch module SMnl/n2, and of which words the second contains an m2-number to address one of the receiving control units connected to this switch module. An esta-blish signal consists of four digital words, the first of which contains besides the establish code E, an n2-number to address the switch module SMnl/n2, and of which words the second, third and the fourth contain the above explained m2-, t2- and tl- establish -information respectively.
The signal receiving units each comprises a code register CREGr AREG and EREG to constantly store the mentioned C-n2-, A-n2-and En2- information respectively. ~urthermore the signal receiving units each contain a comparator CC, AC and ED, the one input of ~hich is connected to the respective mentioned code register CREG, ~ ¦~
AREG and EREG and the second input of which is connected to the mentioned signal register SREG. Each of the mentioned comparators has its output connected to 32 AND-gates G7, which are each activated during a test pulse, according to Fig. 4 the time slot 0-20, 1-20 ... 31-20, and whose outputs are each connected to a first shift stage of shift registers S~l which are clocked by means of the clock 2a pulses 0-0, 1-0 .... 31-0. In correspondence to the number of words o~ the signals the mentioned shift registers contain two or four ; shift stages. Thus, for example, the other shift stages are acti-vated between the second and the third 0-pulse after that test pulse during which the connected gate G7 is activated. The second, third and fourth shift stages of the mentioned shift registers SH are each connected to a first input of an AND-gate G8 whose second input is connected to the signal register SREG and whose third input is activated coincidently with that gate G7 which is connected to the respective shift register. The outputs of the mentioned gates G8 constitute the outputs CM2, ~2, EM2, ET2 and ETl of the signal receiving units, from wllich the above mentioned m2-, t2- and tl-numbers aretransmitted. The receiving unit SRU-A for answer signals 13L~L7;Z~
:
; is provided with a common output A~12 while the receiving units SRU-C and SRU-E Eor call- and establish signals are provided with separate outputs CM2 and EM2, ~T2, ETl, which each are alloted to a transmitting control unit defined by means of an ml-number. The receiving unit SRU-E for establish signals is furthermore provided with outputs M which are activated by means of AND-gates G9 during a ~irst operation pulse occurring after a respective -test pulse and, -according to Fig. 4, constituted by that m-30-pulse which coincides with the activation of the fourth shift stage of the respective shift register.
Fig. 5 shows a converting unit for establish signals comprising first operation registers OREGl and AND-gates GlO. The mentioned first operation registers are connected to the mentioned outputs EM2, ET2 and ETl of the receiving unit SRU-E but also com- -prise register parts to constantly store the ml-number of the respective transmitting control unit. The mentioned gates G10 associated with the respective ml-number have their inputs connected to the mentioned output M of the receiving unit SRU-E and to the mentioned first operation registers OREGl and have their outputs connected to the mentioned operation inputs Ol and 02 of the time stage in such a manner that the ml-tl-operation information is written during the 0-pulse of the rnentioned first operation pulse in memory locations of ~he address memory A~`1 of the time stage, the location addresses being defined by means of the m2-t2-operation information.
Fig. 6 shows a combined converting unit ~or call- and ànswer signals. The m2-numbers obtained from the receiving unit SRU-A for answer signals through the mentioned output A~12 are decoded by means of an answer decoder ADEC and "l"-set bistable flip-flops FF. An "l"-set flip-flop indicates that the associated m2-control unit shall receive an answer signal and activates the first input of an AND-gate Gll associated with the same m2-number, ~7;~
the second input of which is activated during the time slot 0 of the same m2-number and the third input of which is connected to an answer register REG-A which constantly stores an answer code A.
The "0"-setting oE the flip-flops is achieved by means of reset pulses associated with respective m2-number, 10-pulses according to Fig. 6. The outputs of the mentioned gates Gll are connected to the link Lb,nltn2 going out from the switch module.
The m2-numbers obtained from the receiving unit SRU-C
for call signals through the mentioned outputs C~12 are decoded by means of call decoders CDEC, which are associated each with an ml-number for transmitting control units. The mentioned call decoders have -their outputs connected to priority devices PC-0 to PD-31 each associated with an m2-number for receiving control units. Each priority device selects, according to the above mentioned second priority rule, one of the control units which, during a frame, calls the associated receiving control unit. Each priority device is provided with outputs CMl associated with an ml-number each and of which outputs a maximum of one is activated between two successive priority pulses occurring after the test pulse of the time slot 2Q group m=31 and whlch priorit~ pulses, according to Fig. 6, constitue 31-30-pulses. The mentioned outputs CMl are each connected to an AI~D-gate G12 and an AND-gate G13. The mentioned gates G12 transfer in an activated state outgoing call signals through ~ND-gates G14 to the link Lb,nl/n2 going out from the switch module SMnl/n2. The mentioned outgoing call signals containing besides`a call code C, the m-l number of the calling control unit are constantly stored -- -- .
in call registers R~G-C. The mentioned gates G13 transfer in an activa-ted state ml-16-operation information through AND-gates G15 to the operation input 01 of the time stage. Each priority device PD associated with an m2-number, furthexmore, has all of its outputs connected to an OR-gate G16 the output of which is connected to the 7Z~9L
,. . ~.
first input of an AND-gate G17 which in an activated state trans~ers m2-16-operation information to the operation input 02 of the time stage. The mentioned operation information ml-16 and m2-16 being constantly stored in second operation registers OREG2 is u~ed to establish 16-16-message connections. ~oth inputs of a-gate G12 or of a gate G13 are associated with the same m-number. Furthermore, the mentioned gates G17 each have a second input connected to that - register of the mentioned second operation registers OREG2 which stores an m-number corresponding to the m-number of respective priority device.
The mentioned gates G14 are opened during the time slot 0 of the respective receiving control unit provided that a call but no answer is to be transferred to the receiving control unit. If an outgoing call signal is transferred to the receiving control unit, the gates G15 and G17 associated with the respective m2-number are opened during a second operation pulse associated with the respec-tive time slot group, the m2-5 pulse according to Fig. 6.
The mentioned gates Gll and G24 are controlled without the above mentioned multi frame ~orming as it is assumed that the men-2~ tioned link Lb,nl/n2 separately connects the switch module S~nl/n2 - to the link module defined by means of the n2-number. Thanks to the separate link Lb,nl/n2 the outgoing call signals do not need to contain the nl-number being associated with the transmitting link module.
, . . .
'
It is known to use time division multiplex switching ~17~
, , .
systems whlch, for example, are indicated as "time-space-time"-- or "time-space-space-time"- or "space--time-space"- systems, the indication showing in which turn information coming in to the switching system in time division multiplex form is transferred between time stages to carry out time interchanges and between space stages to carry out space interchanges.
A known module switch for time division multiplex digital information, which is described in "Colloque International de Commutation Electroni~ue, Paris 1966, pages 513-520", mainly contains similar modules each switching between a number of input llnks and a number of output links, the time division multiplex format, i.e. the number of time slots per frame, being different for different types of links, and the space interchanges within a module being obtained by means o~ an inter-nal multiplex format having at least as many time slots as there are information channels coming to the module. Time division multiplex links arranged between the modules have the same function as the mentioned connection link groups, one group being constituted by one single link connection having a time division multiplex format which guarantees that connections are established without congestion.
In Canadian ~atent No. l,068,80~, issued December 25, 1979 ~Braugenhardt et al, a "time-time"-switching system is described which makes use of input modules which through a single common time division multiplex connection are connected to output modules. Thanks to said common time division multiplex ` connection a space stage is avoided and compared to the first mentioned known module switch, improved handling possibilities are obtained. When a module defect occurs the faulty module is replaced by a faultless module without affecting the switching capacity of the other modules. During an expansion of the system, further input- and output modules are connected to the ~1~L7Z~
-' mentioned common time division multiplex connection, if required during operation.
.
- 2a -Besides the above mentioned points concerning the modules forming the switching sys-tem,the way in which the paths through the switch are established, i.e. the control of the switch, plays an impoxtant part in the reliability and the ; profitability of a tele-communication system. It is known, for example fr~m the above mentioned publications, to control a digital time division multiplex switch by means of a central computer, which receives from subscribers' lines or from remote concentrators control signals defining an order for establishment of a connection. The computer finds, owing to the mentioned control signals the addresses, indeces, time slots, connection link numbers and so on which, depending on the chosen switching system, have to be transferred to the time- and space stages and the modules of the switch in order to establish the in-structed connection. In the oldest time division multiplex ~
systems an extra control communication system was arranged Eor ~;
the connection of the computer. In modern and improved -time multiplex systems, for example the digital "time-space-time"-system being described in the Canadian patent No. 1,001,27~
issued Dec. 7, 1976 (Edstrom et al), a relief of the computer is aimed at, at the same time as the mentioned control cummunica-tion system as far as possible is included in the time division multiplex information transferring system.
The purpose of the present invention is to achieve an easily handled and an easily expandable IST (Integrated Switchin and Transmission)-network whose congestion free -~ "space-time"-switching system comprises identically designed switch modules which are controlled in a decentralized manner without an extra control communication system and completely without a centrally arranged control unit or computer.
Accordingly the present invention provides in an integrated switching and transmission network comprising ~r-~ ~
~ 3 ~
117Z~L
a plurality of line yroups connected to a congestion free digi-tal switching system comprsing identical switch. modules, through respective link modules each containing a transmi-tter and a receiver and through respective link connections each containing a first link and at least a second link for transferring in time division multiplex form digital communication information and ~ signal information from the transmi.tter to the switching system : and from the switching system to the receiver respectively, ~ said switching system carrying out space interchanges and time 10 interchanges to switch between arbitrary time division multiplex channels for digital information which is transferred by means of said link connections, wherein the improvement comprises that each of a first group of said switch modules is associated with a respective pair of said link modules and has, . ~
through said link conenctions its input connected to the :~ transmitter of one of said associated pair of link modules and ` its output connected to the receiver of the other of said associated pair of link modules, that each module of said first ~ group of switch modules comprises a -time stage means for 20 carrying out time interchanges of the communication information being switched between the associated transmitter and the associated receiver, that each module of sai.d first group of switch modules further comprises a signalliny logic means for converting signals received from the associated transmitter ; to operation signals which control the associated time stage, as ` well as to signals intended for the associated receiver, that ~ the switching system lacks a connection between the input of one and the output of another of said switch modules, that said signalling logic means of the switch modules lac~ connections to any central control unit included in the switchin~ system, and that each link module comprises a control means for establish-; ing communication paths within the line group associated with ~ 4 _ .. .
7Z~4 ; that link module and, in cooperation with the control units of other line groups, for controlling the switching sys-tem upon , establishing connections between that line group and said other line groups.
The invention will now be described in more detail ; by -i I
:`' . - 4a -~L7Z~L
way of e~ample only, in which:
Fig. 1 is a block diagram of an IST-network, Fig. 2 shows a synchronizing clock for use with the IST
network;
Fig. 3 shows a time stage of a switch module;
Fig. 4 shows three signal receiving units which are included the signalling logic circuit of a switch module; and - Figs. 5 and 6 each show a signal converting unit.
Fig. 1 showsn linegroups LGl-LGn between which telecom-munication connections are achieved by means of n link modules ; LMl-LMn and a digital switching system comprising at least n~-n switch modules S~ ach link group, for example LGl, is associated J~
with a link module LMl comprising a transmitter Tl and a receiver r Rl which through time division multiplex links Lal and Lbl are respectively connected to switch modules SMl/2 - SMl/n, which are shown in rows in Fig. 1, and switch modules SM2/1 - S~ln/l which ` are shown in columns. The time division multiplex links transfer in time division multiplex form digital communication- and signal information from the link modules to the digital switch and vice versa.
; The IST network which is shown in Fig. is simplified in order to clarify the description and, only those network components which are needed to explain the present invention are shown. The ~ time division multiplex synchronization of the IST network, for ; instance, is indicated by means of only one clock CL which is connected to all switch modules so that the receiver Rl-Rn receive ~ the information coming from the switching system during synchronous ; frames. Within each link module a frame synchronization is performed ~-~
so that also the lnformation being transferred from the transmitters 3Q Tl-Tn to the switch is synchronous. In practice the synchronization conditions are not so ideal but phase displacements and so cal~ed plesiochronous information transmissions to the switch occur owing ~ .7;~
. ,, to the fact that in larger networks the link modules are allocated one clock each. It is, however, known to synchronize the informa-- tion coming to the switch for example by -taking the fastest clock and arranging phase compensation circuits in the link modules or by making use of so called "pulse stuf~ing" arrangements to avoid information losses. For convenience it will be assumed that the link modules, link connections and switch modules form an ideally synchronized system.
A time division multiplex format is, as known, mainly defined by its frame frequency, which is, for example 8 k~z, and I -by the number of time slots per frame period; for example, there may be m groups of 32 time slots in each frame. In each time slot an information unit is transferred, which in a digital system con-sists of a digital word consisting of a number of bits, for example 8. Most time slots in a frame period are allotted to the communica-; tion information but a few time slots, for example 2 within a 32-time slot group, are reserved for the purpose of synchronization ! ~.
and signalling. It is assumed in the proposed IST-network that the synchronization does not demand a time slot in each frame period but that so called idle signals indicating that there is no need for signalling within a given time slot group are used as synchroni-zation signals so that the few time slots which would normally be ; required for synchronization can be used for digital signals and signal messages as will be described in more detail in relation to the communication channels of a 32-time slot group, which channels may partly be intended for pulse code modulatedspeech transmissions and partly for data communication.
It is known in an IST-network to use both parallel and serial transmission and to vary between time division multiplex formats having different multiples of 32-time slots. It is assumed for the network shown in Fig. 1 that the same format and transmission principle is used for the links La, ~b. Known parallel serial or ~17Z~
serial parallel converters, if any, are included in the link- and switch modules of the network and are not shown in ~ig. 1. Addi-tionally analog/digital- and digital/analog converters can be arranged either in the subscri~ers' equipment or in the link ~odules, but these are not shown as they do not form part of the present invention. Also, concentrators (not shown) may be included in the link modules if a line group comprises a greater number of f~
subscribers' lines than there are time slots in the time division fff multiplex format being chosen for the link connections.
In Fig. 1, each link module comprises at least one control unit CU which is allotted to a line subgroup. Each control unit controls the allotting of a number of time slots to the respective link pair ~ax/Lbx; for example one of the mentioned m 32-time slot groups, to transfer the communication information of the subgroup and associated signal information to and from the switch. In Fig. 1 a system is shown which is so extended that only one control unit is arranged in each link module except in the link module LM2 which comprises m control units CU2,1 - CU2,m, and so that the line group LG2 consequently comprises m subgroups LSG2,1 - LSG2,m. The men-tioned m control units have the use o~ a 32-time slot 3roup each, i.e., altogether they have the use of all of the time slots of the link pair La2/Lb2. The link module LM2 comprises a concentrator not shown in Fig. 1 if one of the mentioned line subgroups comprises > 30 subscribers' lines, because by means of the associated control unit 30 lines a~ most can be connected at the same time in time ~ division multiplex ~orm for example to the link connection La2.
A control unit included in a link module is designed in such a way that it controls the establishment of connections within its own line subgroup. If the link module only comprises one con-3Q trol unit the switch does not necessarily need to comprise a switch module switching between the time slots on the link pair connected to this link module but the link module can contain, in this case, : ~h~7;~
, ~
an internal switch to achieve in-ternal subgroup connections.
Furthermore,if thesubscribers~lines of this subgroup each have a separate connection to the link module, the internal switch con-stitutes a space stage. The advantage of having an internal switch is that the subgroup internal communication connections on the associated link pair do not make use of time slots intended for communication information nor time slots intended for signal infor-mation. Thus an increased switching capacity is obtained. As, on the other hand, the communication information of the subgroup is nonetheless converted into time division multiplex digital infor-mation which is switched through the switching system to other link modules, and as the internal switch required in the link module mostly cannot be designed simpler than a switch module, the greatest 9 possible uniformity of the IST-network is obtained if the switching system comprises n2 equal switch modules. Switch modules, for example SM2/2, connected through a link pair La2/Lb2 to the assoc-iated link module LM2 each must, however, always be provided if the link modules comprises > 1 control units because connections between subgroups belonging to the same line group, ~or example between ~SG2,1 and LSG2,m, can be connected only through the switching system. In the switch shown in Fig. 1 the modules S~l/l, S~ln-l/n - 1 and SM/n have been ommitted and it is assumed that the link modules LlIl, LMn - 1 and LMn contain internal switches which are not shown.
A control unit included in a link module is furthermore designed in such a way that it, together with contro] units of other subgroups, controls the swltch when establishing external connec-tions between its own subgroup and the other subgroups of the same line group whereby the time slots intended for signal information are used. This means in other words that the control intelligence of the whole IST-network is distributed over the decentralized control units. Each of the modules of the switch comprises a time stage TS and a signalling logic S~ stage, which are completely %~
passive and without intelligence of their own. Each module, besides -the clock CL/ in order to achieve synchronism, is connected exclu-sively on the input side to one of the transmitters Tl - Tn and on the output side to one of the receivers R Rn. Thus the switch is not provided with any intelligent central control unit. The decen-tralized control units of the link modules obtain their intelligence for example by means of programs stored in memories. The stored program controlled control units do not need to be described in detail in relation to the present invention. When establishing the external connectionsthe mostimportant functionsof thecontrol unitsof ~he proposedIST network thatis thesignalling eitherbetween control units or between a control unit and a switch, are obtained by means o~ computers known per se, such as Motorola's micro computer M6800~ r programmed in a suitable manner.
. ! -The signalling between two control units aims at inter-changing messages which are coded for example according to a signal system having the CCITT-designation X-25. The structure of the signal system does not need to be described in detail in order to understand the present invention but it is sufficient to mention ~0 that each message unit is coded in such a way that the receiving control unit knows when all of the message unit, consisting of an ; individual number of digital words, has been received. Furthermore the structure of the signal system is such that an interchange of message units in both traffic directions results in both control units knowing whether a communication connection is not to be .-established through the switching system is to be established or is to be released by means of addresses and time slots, which have been obtained due to signalling between two control units. In the proposed IST-network the messages of the signal system are trans-mitted during one of the time slots intended for signal information,below called time slot 1~. In order to transmit a message unit for example from -the control unit CU2,m to the control unit CUl, the _ g _ 1~7Z~
,_ , .
switch module SM2/1 must perform a time in-terchange from time slot 16 within the 32-time slot group allotted to the control unit CU2,m to the time slot 16 within the 32-time slot group allotted to the control unit CUl, a so called 16-16 interchange. The operation of the switch module will be described below. Before the control unit CU2,m starts transmitting the mentioned message unit, it has to know that neither the switch module SM2/1 being ordered by for example the control unit CU2,1 nor one of the switch modules SM >
2/1 being ordered by one of the control units CU > 2 is carrying out any 16-16 time interchange to transfer another message to the ; control unit CUl.
In order to achieve a reliable message communication, the control unit CU2,m transmits first during the second of its time slots intended for signal information, below called time slot 0, a call signal addressed to the control unit CU1. The address to the control unit CUl also defines the only switch module SM2/1 through which the call signal has to be transferred. A control unit trans-mits the call signals one at a time, indicating that the transfer of the intended message uni-t has to be finished before this control unit transmits a new call signal.
Owing to call signals which a control unit has received during its allotted time slot 0, this control unit transmits answer signals one at a time during its time slot 0, indicating that the transfer of the intended message unit by means of the respective call signal has to be completed before this control unit transmits a new answer signal concerning another call signal. In the assumed signalling example the control unit CUl transmits, according to the mentioned "one at a time"-rule, an answer signal addressed to the control unit CU2,m. The address to the control unit CU2,m also defines the only switch module SMl/2, through which the answer signal has to be transferred.
The mentioned "one at a time"-rule concerning calls and ... .. .
z~
answers renders the following acknowledgemen-t operations possible:
A call signal is continuously repeated until the associated answer signal has been received. When the received call signal ceases the called control unit knows that its answer signal has arrived at the calling control unit. Also an answer signal is repeated at least until the first word of the message unit has been received. When the answer signal ceases the calling control unit knows that the -mentioned 16-16 connection works reliably. There are, however, maximum times to how long the call- and the answer signals are transmitted. If no answer signal or no message work has been re- ;
ceived after the maximum time the waiting control unit yenerates an alarm signal.
` When the called control unit, the control unit CUl 9 according to the example, has received the whole message unit during its time slot 16, it transmits to the calling control unit, the control unit CU2,m according to the example, during its time slot 0 a signal the contents of which indicate that the message unit either is correctly received or has to be retransmitted. The ; mentioned "correctly received"- and "retransmission"-signals are modified answer signals having the property in common that they do not have to contain the address of the called control unit/ because due to the "one at a time"-rule the calling control unit knows that such answer signals have to come from the called control unit. The mentioned acknowledgement principle is also used to complete the transfer of the message unit in a reliable manner. The called control unit continuously repeats the mentioned "correctly received"-signal The calling control unit answers hy continuously trans- !
mitting a "correctly received"-signal to the called control unit.
When the called control unit receives the "correctly received"-signal it completes its "correctly received"-transmission. When the calling control uni-t no longer receives "correctly received"-signals also the calling control unit completes its transmission.
~7Z~
The mentioned signalling process results in a single message unit being reliably transferred in one traffic direction.
In order to achieve a message interchange an equivalent process is repeated for the other traffic direction, whereby the two con- ~
trol units change their roles.
Besides the mentioned "one at a time"-rule there is a first priority rule according to which a control unit has to answer received call signals before it as the calling control unit starts or continues a message interchange. The mentioned first priority rule prevents too large an accumulation of unanswered call signals.
The mentioned maximum time valid for call signals is determined with reference to the fact that a contrQl unit can be called by all the other control units of the IST-network during the same frame period.
~ Queuing problems are obtained not only in the called control unit but also in the concerned switch modules and the concerned link connection in order to transfer the call signals from the switch to the called control unit. Furthermore the mentioned types of answer signals share in the queuing of signals addressed to a control unit J
but due to the "one at a time"-rule there is maximum one signal of answer type together with a number of call signals. The solution af the mentioned queuing problem will be described below.
During frame periods, which are neither occupied to trans-fer the hitherto explained signals of call- or answer type nor establish signals or release signals being explained as Eollows, the time slots 0 on the link connections of the IST-network are used to transfer the above mentioned idle signals.
~ The signalling between the control units and the switch aims at establishing or releasing the mentioned 16-16-connections between the control units, as well as ml,tl - m2,t2 connections which are included in communication connections between the sub-scribers' lines. Thus, the switch performs time interchanges from the time slot 16, being allotted a transmitting control unit, to 1~7 , ~, the time slot 16, being allotted a receiving control unit, as well ; - as from the time slot tl associated with the 32-time slot group ml in question, during which the communication information in question .... .
; is received by the switch, to the time slot t2 associated with the 32-tlme slot group mZ in question, during which the switch transmits the mentioned communication information.
As will appear from the explanation of the passive func-tions of the switch the above mentioned call signals are used to establish the mentioned 16-16-connections. In order -to establish an ml,tl - ml,t2-connection, a control unit, for example CU2,1, the nl-number of which is 2, transmits an establish signal during its allotted time slot 0 which at the same time defines the 32-time slot group ml=l of the control unit. The establish signal contains an establish code as well as an n2-number, for example n2=2, to address the only switch module 1n question, the switch moduie SM2/2 according to the example. The establish signal contains furthermore the mentioned time slots tl and t2 as well as an m2-number, for example m2=2, to indica~e the receiving subgroup of the subscribers' lines and its 32-time slot group including the mentioned time slot t2.
According to the example the establish signal indicates a one-way communication connection from a subscriber's line of the subgroup LGS2,1 (nl=2, ml=l) to a subscriber's line of the subgroup LGS2,2 ~ ;
(n2=2, m2=2). The signalling logic of the receiving switch module SM2/2 converts the establish signal into operation signals by means of which the time stage of this switch module establishes the ~i .
intended connection. The establish signal, owing to its n2-number, r does not influence any other time s~age in another switch module.
~n this elegant manner the space in-terchanges of the switch are carried out without conventional space stages and without special space interchange signals.
In order to release an ml,tl - m2,t2-connection a control unit transmits during its allotted time slot 0 a release signal .7;Z~
. .
defined by means of a release code, the mentioned release signal ; differing from an establish signal only by the fact that an infor-~. mation of a tl-time slot is unnecessary. A release of a 16-16-- connection is signalled to the switch either by means of the above mentioned "correctly received"-acknowledgement signal or by means of a release signal containing t2=16.
The mentioned signals generated by the control units each comprise, as the message units of the signal system, a code and r~ variables in question such as the mentioned nl,n2- and ml, m2-number addresses and tl, t2-time slots. In a larger system having for example ~ link modules each comprising 32 control units, in order to switch in a congestionless manner and without need for concentra-tors between about 8000 subscribers' lines, the signals cannot be each defined by means of only one digital word comprising 8 bits.
In IST-time division multiplex systems, so called multi frames are introduced to transfer such signals comprising several words, .~
whereby multi frames having a constant or a varying number of frame periods exist. In connection with the explanation of the working manner ofthe switchthe mentionedknown multi frame technique will to the necessary extent be referred to.
; Below, principles are described concerning the passive operation of a signalling logic circuit in one of the switch modules ~ of the proposed IST-network. The signalling logic circuit comprises - receiving units only reacting to the associated n2-number address and respective signal code, and comprises converting units which convert signals coming to the switch module to the mentioned opera-. ., ,, ._ ~_ tion signals and to signals going out from the switch module. The converting units for treating the call signals decide, according to a cimple second priorit~ rule, which of the call signals coming at 3Q the same time and addressed to the same receiving control unit is converted into an operation signal to establish respective 16-16-connection to this control unit, and into a call signal going out to this control unit. The converting units for treating signals of "~ the above mentioned answer types have a simpler design than the call converting units. Due to the above mentioned "one at a time"-rule it is sufficient if the receiving control unit receives the answer code while a converted call signal has -to give information from which control unit of which link module the call comes. The treatment of the answer signals does not demand any priority rule.
- A receiving control unit, for example C~2,2, receiving signals from switch modules SMl/2-SMn/2 shown in column in Fig. 1, at the same time can be called through all switch modules of respec-tive column (n2=2) and can receive an answer through one of the switch modules of the column. If the receiving control unit is connected to the mentioned column of switch modules by means of a common time division multiplex link, according to the example and Fig. 1 link Lb,2 a multi frame hasto be decided concerning the time slot O of the receiving control unit. Within this multi frame, for example the switch modules of the column and consequently the calling link modules are associated with an nl-frame period each to transfer call signals, and with a frame period com~on to all of the switch 2Q modules in a column to transfer signals of answer type. The men-tioned common frame period is not needed if the mentioned call- and answer converting units are modified so that an answer signal inhibits a call signal. Each switch module then transmits during a time slot O only one signal, eitl~er an answer type signal or a call signal. If, furthermore, a separate time division multiplex link is arranged for each of the switch modules, in order to trans-fer information to respective link module, one avoids the mentioned multi ~rame forming concerning signals going from the switch. In an IST-network modified by means of the mentioned separate links, 3Q which will be explained in connection with Fig. 6, one obtains a quicker signalling process having shorter maximum times than the system shown in Fig. 1 having the mentioned common links Lb.
72~
. . .
Fig. 2shows thecommon clock CL ofthe switchingsystem, men~
tioned at the beginning,in orderto generatea time divisionmultiplex format comprising 32 time slot groups each having 32 time slots.
A frame period lasting f=125 ~s comprises 32 x 32 time slots so that the duration of each time slot, p is approximately 122 ~s.
The time slots are designated by means of two numbers 0 < m ~ 31 -0 < t < 31. The time slot 0-0 starts a frame period, precedes the frame period 0-1 and follows the last time slot 31-31 of the previous frame. The clock defines the time slots by means of pulse series shown in Fig. 2, whicll are generated in a known manner, for example by means of a shift register. It is assumed that the IST-network uses the parallel transfer principle, therefore there is no dividing bit within the time slots. The clock is provided with an output 0 which according to Fig. 2 transmits a pulse series which within each time slot comprises a pulse and an interval. The 0-pulses are needed in order to avoid, in a known manner, coincidence in the writing- and reading operations described below in connection with the time interchanges. The clock is driven by an oscillator OS, the basic frequency of which is 23 5 5 1 kHz ~16 MHz.
Fig. 3 shows a time stage known per se to perform time interchanges within the mentioned 32 x 32 time division multiplex format. The time stage mainly comprises an information memory IM
and an address memory AM. The writing inputs of the information memory are through an AND-gate Gl and through 32 x 31 AND-gates G2 connected to the link La,nl for incoming information. During the ~-pulses of a frame, communication- and message information arriving during the time slots m 1 to m-31 is written in associated locations of the information memory, while signals arriving during the time slots m-0 are not registered in the information memory. Thus, the ' 30 communication information and the message information transferred on the link La,nl is registered in all of the switch modules con- ~
nected to the link, the mentioned switch modules forming a row in - 16 ~
Fig. 1. The address memory AM has its reading outputs connected to a time interchange decoder TDEC through 32 x 31 AND-gates G3, the mentioned decoder addressing the information memory during the 0-intervals for reading to the link Eb,nl/n2 going out from the switch module. The nl- and n2-designation defines respectively, according to Fig. 1, the transmi-tter Tnl and the receiver Rn2 assoc-iated with the time stage.
In Fig. 3 it is assumed that the time interchange decoder receives the addresses 31-1 and 0-16 respectively during the time slots 0-31 and 31-16, while during the other time slots the addresses m 0 are transferred, which do not occur in the information memory.
The communication information ki registered in the information memory during the time slot 31-1 is transferred during the time r~
slot 0-31 to the link Lb,nl/n2, and the message information mi registered during the time slot 0-16 is switched to the time slot 31-16, but the remaining information registered in the information memory i5 not transferred to the outgoing link. The address memor~
AM has its writing inputs connected, through an opera-tion decoder - ODEC and through AND-gates G4 activated during the 0~pulses, to the operation inputs 01 and 02 of the time stage.
Fig. 4 shows signal receiving units SRU-C, SRU-A and SRU-E, which are included in the signalling logic of a switch - --module SMnl~n2 and which receive call- answer- and establish signals ` registered in a signal register SREG. For the above mentioned ; release signals and signals of answer type the signalling logic comprises further receiving units corresponding to the mentioned receiving units SRU-E and SRU-A and therefore not shown in Fig. 4.
The mentioned signal register SREG registers by means of an OR-gate G5 and an A~JD-gate G6 during the time slots m-0 idle-, - 30 call, answer-, and establish- or release signals coming from the link La,nl. Each call- or answer signal consists of two digital words, the first of which contains besides respective code C or A, ~1~L7Z~
.
-~an n2-number in order to address the switch module SMnl/n2, and of which words the second contains an m2-number to address one of the receiving control units connected to this switch module. An esta-blish signal consists of four digital words, the first of which contains besides the establish code E, an n2-number to address the switch module SMnl/n2, and of which words the second, third and the fourth contain the above explained m2-, t2- and tl- establish -information respectively.
The signal receiving units each comprises a code register CREGr AREG and EREG to constantly store the mentioned C-n2-, A-n2-and En2- information respectively. ~urthermore the signal receiving units each contain a comparator CC, AC and ED, the one input of ~hich is connected to the respective mentioned code register CREG, ~ ¦~
AREG and EREG and the second input of which is connected to the mentioned signal register SREG. Each of the mentioned comparators has its output connected to 32 AND-gates G7, which are each activated during a test pulse, according to Fig. 4 the time slot 0-20, 1-20 ... 31-20, and whose outputs are each connected to a first shift stage of shift registers S~l which are clocked by means of the clock 2a pulses 0-0, 1-0 .... 31-0. In correspondence to the number of words o~ the signals the mentioned shift registers contain two or four ; shift stages. Thus, for example, the other shift stages are acti-vated between the second and the third 0-pulse after that test pulse during which the connected gate G7 is activated. The second, third and fourth shift stages of the mentioned shift registers SH are each connected to a first input of an AND-gate G8 whose second input is connected to the signal register SREG and whose third input is activated coincidently with that gate G7 which is connected to the respective shift register. The outputs of the mentioned gates G8 constitute the outputs CM2, ~2, EM2, ET2 and ETl of the signal receiving units, from wllich the above mentioned m2-, t2- and tl-numbers aretransmitted. The receiving unit SRU-A for answer signals 13L~L7;Z~
:
; is provided with a common output A~12 while the receiving units SRU-C and SRU-E Eor call- and establish signals are provided with separate outputs CM2 and EM2, ~T2, ETl, which each are alloted to a transmitting control unit defined by means of an ml-number. The receiving unit SRU-E for establish signals is furthermore provided with outputs M which are activated by means of AND-gates G9 during a ~irst operation pulse occurring after a respective -test pulse and, -according to Fig. 4, constituted by that m-30-pulse which coincides with the activation of the fourth shift stage of the respective shift register.
Fig. 5 shows a converting unit for establish signals comprising first operation registers OREGl and AND-gates GlO. The mentioned first operation registers are connected to the mentioned outputs EM2, ET2 and ETl of the receiving unit SRU-E but also com- -prise register parts to constantly store the ml-number of the respective transmitting control unit. The mentioned gates G10 associated with the respective ml-number have their inputs connected to the mentioned output M of the receiving unit SRU-E and to the mentioned first operation registers OREGl and have their outputs connected to the mentioned operation inputs Ol and 02 of the time stage in such a manner that the ml-tl-operation information is written during the 0-pulse of the rnentioned first operation pulse in memory locations of ~he address memory A~`1 of the time stage, the location addresses being defined by means of the m2-t2-operation information.
Fig. 6 shows a combined converting unit ~or call- and ànswer signals. The m2-numbers obtained from the receiving unit SRU-A for answer signals through the mentioned output A~12 are decoded by means of an answer decoder ADEC and "l"-set bistable flip-flops FF. An "l"-set flip-flop indicates that the associated m2-control unit shall receive an answer signal and activates the first input of an AND-gate Gll associated with the same m2-number, ~7;~
the second input of which is activated during the time slot 0 of the same m2-number and the third input of which is connected to an answer register REG-A which constantly stores an answer code A.
The "0"-setting oE the flip-flops is achieved by means of reset pulses associated with respective m2-number, 10-pulses according to Fig. 6. The outputs of the mentioned gates Gll are connected to the link Lb,nltn2 going out from the switch module.
The m2-numbers obtained from the receiving unit SRU-C
for call signals through the mentioned outputs C~12 are decoded by means of call decoders CDEC, which are associated each with an ml-number for transmitting control units. The mentioned call decoders have -their outputs connected to priority devices PC-0 to PD-31 each associated with an m2-number for receiving control units. Each priority device selects, according to the above mentioned second priority rule, one of the control units which, during a frame, calls the associated receiving control unit. Each priority device is provided with outputs CMl associated with an ml-number each and of which outputs a maximum of one is activated between two successive priority pulses occurring after the test pulse of the time slot 2Q group m=31 and whlch priorit~ pulses, according to Fig. 6, constitue 31-30-pulses. The mentioned outputs CMl are each connected to an AI~D-gate G12 and an AND-gate G13. The mentioned gates G12 transfer in an activated state outgoing call signals through ~ND-gates G14 to the link Lb,nl/n2 going out from the switch module SMnl/n2. The mentioned outgoing call signals containing besides`a call code C, the m-l number of the calling control unit are constantly stored -- -- .
in call registers R~G-C. The mentioned gates G13 transfer in an activa-ted state ml-16-operation information through AND-gates G15 to the operation input 01 of the time stage. Each priority device PD associated with an m2-number, furthexmore, has all of its outputs connected to an OR-gate G16 the output of which is connected to the 7Z~9L
,. . ~.
first input of an AND-gate G17 which in an activated state trans~ers m2-16-operation information to the operation input 02 of the time stage. The mentioned operation information ml-16 and m2-16 being constantly stored in second operation registers OREG2 is u~ed to establish 16-16-message connections. ~oth inputs of a-gate G12 or of a gate G13 are associated with the same m-number. Furthermore, the mentioned gates G17 each have a second input connected to that - register of the mentioned second operation registers OREG2 which stores an m-number corresponding to the m-number of respective priority device.
The mentioned gates G14 are opened during the time slot 0 of the respective receiving control unit provided that a call but no answer is to be transferred to the receiving control unit. If an outgoing call signal is transferred to the receiving control unit, the gates G15 and G17 associated with the respective m2-number are opened during a second operation pulse associated with the respec-tive time slot group, the m2-5 pulse according to Fig. 6.
The mentioned gates Gll and G24 are controlled without the above mentioned multi frame ~orming as it is assumed that the men-2~ tioned link Lb,nl/n2 separately connects the switch module S~nl/n2 - to the link module defined by means of the n2-number. Thanks to the separate link Lb,nl/n2 the outgoing call signals do not need to contain the nl-number being associated with the transmitting link module.
, . . .
'
Claims (2)
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. In an integrated switching and transmission net-work comprising a plurality of line groups connected to a con-gestion free digital switching system comprising identical switch modules, through respective link modules each containing a transmitter and a receiver and through respective link con-nections each containing a first link and at least a second link for transferring in time division multiplex form digital communication information and signal information from the transmitter to the switching system and from the switching system to the receiver respectively, said switching system carrying out space interchanges and time interchanges to switch between arbitrary time division multiplex channels for digital information which is transferred by means of said link connec-tions, wherein the improvement comprises that each of a first group of said switch modules is associated with a respective pair of said link modules and has, through said link connections its input connected to the transmitter of one of said associated pair of link modules and its output connected to the receiver of the other of said associated pair of link modules, that each module of said first group of switch modules comprises a time stage means for carrying out time interchanges of the communication information being switched between the associated transmitter and the associated receiver, that each module of said first group of switch modules further comprises a signalling logic means for converting signals received from the associated transmitter to operation signals which control the associated time stage, as well as to signals intended for the associated receiver, that the switching system lacks a connection between the input of one and the output of another of said switch modules, that said signalling logic means of the switch modules lack connections to any central control unit included in the switching system, and that each link module comprises a control means for establishing communication paths within the line group associated with that link module and, in cooperation with the control units of other line groups, for controlling the switching system upon establishing con-nections between that line group and said other line groups.
2. The integrated switching and transmission net-work according to claim 1, wherein each of a second group of said switch modules is associated with one of said link modules and has its input and its output connected respectively to the transmitter and the receiver through that link connection which is associated with this link module, that each module of said second group of switch modules comprises a time stage means and a signalling logic means which are identical with said time stage means and signalling logic means arranged in each module of said first group of switch modules, and that the line group connected to this link module comprises at least one line sub-group which is connected to a control means included in this link module to establish communication paths within the associated subgroup and, in cooperation with the control means of other subgroups, to control the switching system upon establishing connections between the associated subgroup and said other subgroups.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| SE7710116A SE424498B (en) | 1977-09-09 | 1977-09-09 | DIGITAL SELECTED |
| SE7710116-0 | 1977-09-09 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1117204A true CA1117204A (en) | 1982-01-26 |
Family
ID=20332216
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000310754A Expired CA1117204A (en) | 1977-09-09 | 1978-09-06 | Integrated switching and transmission network |
Country Status (23)
| Country | Link |
|---|---|
| JP (1) | JPS5451304A (en) |
| AR (1) | AR218081A1 (en) |
| AU (1) | AU519944B2 (en) |
| BE (1) | BE870252A (en) |
| BR (1) | BR7808744A (en) |
| CA (1) | CA1117204A (en) |
| CH (1) | CH649665A5 (en) |
| DE (1) | DE2857028C1 (en) |
| DK (1) | DK155268C (en) |
| EG (1) | EG13352A (en) |
| ES (1) | ES473203A1 (en) |
| FI (1) | FI65694C (en) |
| FR (1) | FR2402991A1 (en) |
| GB (1) | GB2036506B (en) |
| HU (1) | HU177611B (en) |
| IT (1) | IT1098818B (en) |
| MX (1) | MX145178A (en) |
| NL (1) | NL189277C (en) |
| NO (1) | NO149755C (en) |
| PL (1) | PL209489A1 (en) |
| SE (1) | SE424498B (en) |
| WO (1) | WO1979000138A1 (en) |
| YU (1) | YU212078A (en) |
Families Citing this family (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4201889A (en) * | 1978-03-17 | 1980-05-06 | International Telephone And Telegraph | Distributed control digital switching system |
| US4201890A (en) * | 1978-03-17 | 1980-05-06 | International Telephone And Telegraph | Multiport digital switching element |
| DE2826113C2 (en) * | 1978-06-14 | 1986-11-06 | Siemens AG, 1000 Berlin und 8000 München | Indirectly controlled switching system with time channel connection paths routed via time channel couplers, in particular telephone switching system |
| DE2849348A1 (en) * | 1978-11-14 | 1980-05-29 | Siemens Ag | Indirectly-controlled TDM telephone exchange - has speech information preceded by routing and signal information bytes followed by parity byte |
| US4322843A (en) * | 1979-12-26 | 1982-03-30 | Bell Telephone Laboratories, Incorporated | Control information communication arrangement for a time division switching system |
| US4280217A (en) * | 1979-12-26 | 1981-07-21 | Bell Telephone Laboratories, Incorporated | Time division switching system control arrangement |
| DE3106868C2 (en) * | 1981-02-24 | 1984-08-09 | Siemens AG, 1000 Berlin und 8000 München | Circuit arrangement for time division multiplex telecommunications switching systems, in particular PCM telephone switching systems, with data paths between a central control unit and decentralized control devices |
| FR2503513A1 (en) * | 1981-04-03 | 1982-10-08 | Cit Alcatel | TEMPORAL SELF-TIMER WITH DISTRIBUTED CONTROL |
| JPS5829286A (en) * | 1981-08-14 | 1983-02-21 | Nippon Telegr & Teleph Corp <Ntt> | Switching system |
| DE3301966A1 (en) * | 1983-01-21 | 1984-07-26 | Siemens AG, 1000 Berlin und 8000 München | Circuit arrangement for a telecommunications system, in particular a telephone PABX system, with subscriber and line transmission groups and interface modules |
| FR2562368B1 (en) * | 1984-04-02 | 1989-07-28 | Cit Alcatel | SPATIAL CONNECTION NETWORK FOR HIGH SPEED DIGITAL SIGNALS |
| JPH0787626B2 (en) * | 1986-09-30 | 1995-09-20 | 日本電気株式会社 | Frame phase synchronization method in time division exchange |
| EP2960051A1 (en) | 2014-06-27 | 2015-12-30 | Kowalewski Sp. z o. o. | Method of preparing multilayer material for commerical stands production, multilayer material for commerical stands production and joint made of this material |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3446917A (en) * | 1964-12-29 | 1969-05-27 | Bell Telephone Labor Inc | Time division switching system |
| DE1299338B (en) * | 1967-04-06 | 1969-07-17 | Western Electric Co | Circuit arrangement for the connection of connection devices in a time division multiplex message switching system |
| US3573381A (en) * | 1969-03-26 | 1971-04-06 | Bell Telephone Labor Inc | Time division switching system |
| BE795167A (en) * | 1972-02-08 | 1973-05-29 | Ericsson Telefon Ab L M | SWITCHING ORDERS INFORMATION PRODUCTION DEVICE FOR THE TRANSMISSION OF MODULATION WORDS BY CODE PULSES |
| DE2602561C3 (en) * | 1976-01-23 | 1978-11-02 | Siemens Ag, 1000 Berlin Und 8000 Muenchen | Time division switching network |
-
1977
- 1977-09-09 SE SE7710116A patent/SE424498B/en not_active IP Right Cessation
-
1978
- 1978-08-16 BR BR7808744A patent/BR7808744A/en unknown
- 1978-08-16 WO PCT/SE1978/000033 patent/WO1979000138A1/en unknown
- 1978-08-16 DE DE2857028A patent/DE2857028C1/en not_active Expired
- 1978-08-16 CH CH5114/79A patent/CH649665A5/en not_active IP Right Cessation
- 1978-08-16 GB GB7933704A patent/GB2036506B/en not_active Expired
- 1978-09-01 AU AU39477/78A patent/AU519944B2/en not_active Expired
- 1978-09-06 BE BE190294A patent/BE870252A/en not_active IP Right Cessation
- 1978-09-06 YU YU02120/78A patent/YU212078A/en unknown
- 1978-09-06 CA CA000310754A patent/CA1117204A/en not_active Expired
- 1978-09-07 IT IT27415/78A patent/IT1098818B/en active
- 1978-09-08 FI FI782754A patent/FI65694C/en not_active IP Right Cessation
- 1978-09-08 DK DK397878A patent/DK155268C/en not_active IP Right Cessation
- 1978-09-08 AR AR273633A patent/AR218081A1/en active
- 1978-09-08 NL NLAANVRAGE7809216,A patent/NL189277C/en not_active IP Right Cessation
- 1978-09-08 PL PL20948978A patent/PL209489A1/en unknown
- 1978-09-08 FR FR7825934A patent/FR2402991A1/en active Granted
- 1978-09-08 JP JP11059678A patent/JPS5451304A/en active Granted
- 1978-09-08 MX MX174817A patent/MX145178A/en unknown
- 1978-09-08 HU HU78EI811A patent/HU177611B/en unknown
- 1978-09-08 NO NO783057A patent/NO149755C/en unknown
- 1978-09-08 ES ES473203A patent/ES473203A1/en not_active Expired
- 1978-09-09 EG EG544/78A patent/EG13352A/en active
Also Published As
| Publication number | Publication date |
|---|---|
| NO149755C (en) | 1984-06-20 |
| NL189277B (en) | 1992-09-16 |
| GB2036506A (en) | 1980-06-25 |
| SE7710116L (en) | 1979-03-10 |
| AU3947778A (en) | 1980-03-06 |
| BE870252A (en) | 1979-01-02 |
| BR7808744A (en) | 1979-12-11 |
| DK155268C (en) | 1989-07-24 |
| YU212078A (en) | 1982-06-30 |
| CH649665A5 (en) | 1985-05-31 |
| NL189277C (en) | 1993-02-16 |
| GB2036506B (en) | 1982-04-28 |
| NO149755B (en) | 1984-03-05 |
| EG13352A (en) | 1981-03-31 |
| NO783057L (en) | 1979-03-12 |
| DK397878A (en) | 1979-03-10 |
| SE424498B (en) | 1982-07-19 |
| FI65694C (en) | 1984-06-11 |
| HU177611B (en) | 1981-11-28 |
| FR2402991B1 (en) | 1983-02-11 |
| ES473203A1 (en) | 1979-10-01 |
| IT7827415A0 (en) | 1978-09-07 |
| WO1979000138A1 (en) | 1979-03-22 |
| JPS5451304A (en) | 1979-04-23 |
| JPS6329477B2 (en) | 1988-06-14 |
| FR2402991A1 (en) | 1979-04-06 |
| FI782754A (en) | 1979-03-10 |
| MX145178A (en) | 1982-01-12 |
| AU519944B2 (en) | 1982-01-07 |
| FI65694B (en) | 1984-02-29 |
| PL209489A1 (en) | 1979-06-18 |
| DK155268B (en) | 1989-03-13 |
| NL7809216A (en) | 1979-03-13 |
| AR218081A1 (en) | 1980-05-15 |
| DE2857028C1 (en) | 1982-06-09 |
| IT1098818B (en) | 1985-09-18 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4569043A (en) | Arrangement for interfacing the space stage to the time stages of a T-S-T digital switching system | |
| CA1075798A (en) | Multiprocessor control of a partitioned switching network by control communication through the network | |
| US4460994A (en) | Loop communication system | |
| CA1281801C (en) | Time division multiplex (tdm) switching system especially for pulse code modulated (pcm) telephony signals | |
| US4782478A (en) | Time division circuit switch | |
| CA1117204A (en) | Integrated switching and transmission network | |
| US3492435A (en) | Four-wire concentrator without separate control path | |
| GB2186762A (en) | Communications switching system | |
| US4287590A (en) | Time division multiplex communication system | |
| US4254496A (en) | Digital communication bus system | |
| US3925621A (en) | Digital circuit switched time-space-time switch equipped time division transmission loop system | |
| US4484323A (en) | Communication arrangements for distributed control systems | |
| US4484324A (en) | Control information communication arrangement for a time division switching system | |
| CA1238968A (en) | Communication switching system | |
| US5590129A (en) | Single stage telecommunications switch with partitioned processors | |
| US4261052A (en) | Integrated switching and transmission network | |
| CA1089963A (en) | Digital time division switching arrangement | |
| GB2127651A (en) | Tdm concentrator system | |
| US3641272A (en) | Time division automatic telephone switching equipment | |
| CA1114933A (en) | Digital communication bus system | |
| US4524442A (en) | Modularly expandable space stage for a T-S-T digital switching system | |
| US3872256A (en) | PCM time-division multiplex switching procedure | |
| US4520478A (en) | Space stage arrangement for a T-S-T digital switching system | |
| NZ243988A (en) | Communication between point to point connected circuit mode supports |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MKEX | Expiry |