CA1110775A - Drive circuits for a high resolution cathode ray tube display - Google Patents

Abstract

ABSTRACT OF THE DISCLOSURE
This invention discloses a high frequency two way scan circuit for causing trace and retrace scans on a cathode ray tube having a yoke. A sweep means is connected to the yoke for causing the trace to sweep across the tube and a receiving means is provided to receive a trace sync signal. A first circuit turns off the sweep means during the retrace and a second circuit is provided for turning on the retrace means.
The cathode ray tube having this circuit permits an extremely high resolution cathode ray tube display which has unparalled clarity and resolution when compared to the prior art devices.

Description

~, 1 This is a divisional applicakion of Canadian patent application serial number 325,771 filed on April 17, 1979 and assigned to CPT Corporation.
13ACKGROU~l~ OF THE INVENTION
This invention relates to display circuits for cathode ray tubes. Because of current circuit designs being utilized, conventional television monitors are operated at a horizontal drive frequency of about fifteen kilocycles. Conventional high speed monitors are operated with a video drive frequency of about twenty megacycles. It has been recognized repeatedly in the past that achievement of higher frequency operation would and could produce improved resolution.
This realization has produced some specific develop-ments such as described in United States Patent No. 3,878,532, which discloses a high frequency analog to digital conversion apparatus, to ~e used with a cathode ray tube having an apertured target member. Other attempts which have been made to vary the fre~uency response and thus improve resolution include patents such as Unites States Patent No. 3,750,133 which teaches a method of rotating the de1ection yoke of a cathode ray tube ninety degrees to provide fast vertical rather than fast hori-zontal sweeps.
While such incremental increases in frequency may provide incremental improvements in resolution, the total inter-action of frequency response in the entire display circuitry has not been approached with an integrated design and selected improvements to indi~idual circuit parameters have not produced a substantial improvement in overall resolution of cathode ray tube displays.

3 SU~lMARY OF THE :[NVENTION
The present invention is a design or the display tj~ :

1 circuitry for a cathode ray tube which permits the operatiny frequency of the horizoIltal drlve to be increased by a factor of four and the operating frequency of the video drive to be increased by a factor of ten. Using the circuits disclosed horizontal drive can be operated at a frequency of about fifty kilocycles and video drive can be operated at a frequency of two hundred megacycles. Complementary design changes are also disclosed for vertical drive circuitry.
The high frequency video drive signal is achieved using emitter coupled logic (ECL) coupled with discrete com-ponents in a circuit design which yields the high frequency response desired. An ECL differential amplifier driver is used as a hiyh frequency receiver for the raster scan video input siynal. The high frequency input signal is then converted to a high speed current signal with two ECL drivers connected in parallel and each connected to a two transistor current mode switch. ~ high frequency voltage output signal is created with a third transistor connected in a cascode arrangement with one of the transistors in the current mode switch. The output signal ~ is critically damped and diode clamped to protect the outpu-t transistor. Means are also provided for dissipating power created within the circuit.
The hiyh Erequency horizontal drive circuit also uses high speed components to create a two-way scan circuit. Two transistors are connected to the horizontal yoke of the tube to cause sweep and retrace to occur. During normal operation the sweep transistor is on. Timing components are provided to receive, time and control the duration of retrace after receipt of a re~race sync pulse. First timing means establish a first timing interval. The first timing means are connected to an 1 electronic switching circuit which controls the sweep transistor and turns it off during retrace.
The retracP sync pulse also turns the retrace transis-tor on causing a retrace scan to occur. This is accomplished with a second circuit means having a retrace timer which gener~
ates a time interval for retrace which is smaller in duration than -the time interval during which the sweep transistor is off and which is initiated a finite time after the first time interval and terminated prior to the termination of the first time interval. An electronic switching circuit is also connected to the retrace timer to control the retrace transistor.
Voltage generated by the horizontal drive circuit is also used with a vol-tage multiplier to provide a 1.1 kilovolt acceleration potential for the first anode of the tube. Voltage generated, with appropriate controls, is also used as a variable voltage supply to the brightness grid of the tube.
The vertical drive circuit disclosed also utilizes solid state design. A voltage ramp generator is utilized for the vertical trace wave form with a solid state shaplng circuit ~ for compensating for nonlinearities due to the surface of the tube. The shaped wave form and the voltage ramp are connected to the summing node of an operational amplifier to produce the output signal for the vertical yoke. Circuitry is also disclosed for vertical retrace which is an integral part of the vertical drive circuit. A zero crossover network is also disclosed as well as a dynamic focus circuit which is connected from the vertical drive circuit to the ocus grid of the tube because the vertical axis is the long axis in a preferred embodiment of the invention.
Protection circuitry is also disclosed which removes 7~

1 the sign~l from the brightness grid i~ loss of horizontal or vertical signal is detec-ted.
To this end, in one of its aspects, the invention p.rovides a high frequency two way scan clrcult for causing -trace and retrace scans on a cathode ra~ tube havi.ng a yoke comprising:
sweep means conneclied to the yoke of the cathode ray tube for causing the trace to sweep from a first side of the tube to the other; receiving means for receiving a retrace sync signal; first circuit means connected to the sweep means for turning the sweep means off during retrace comprising: first timing means con-nected to the receiving means for generating a first timing :: :
interval during which the sweep means will ~e off; electronic switching means connected to the first timing means and the sweep means ~or switching the sweep means off during the first timing interval and on after the timing interval esta~lished by the first timing means; retrace means connected to the yoke of ~he tube for causing the trace to return to the first side of the tube; and second circuit means connected to the retrace means for turning the retrace means on comprising: second ~ timing means connected to the receiving means for generating asecond time interval smaller in duration than the first time interval and which is initiated a finite time after the ~irst time .interval and which terminates prior to the termination of the first time interval; and a second elec~ronic switching cir-cuit connected to the second timing means and the retrace means for switching the retrace means on during the second timing interval and off after the second timing interval.

DESCRIPTION OF THE DR~WINGS
___._ _ Figure l, comprising Fi~ures la through ]d, discloses-.

i.n schematic diagram form a preferred embodiment of the ~ 3 ~

1 invention. As shown in the drawing, the invention comprises horizontal drive circuitry shown primarily in Figures la and lb, vertical drive circuitry shown primarily in Figures lc and ld, and video drive circuitry shown in Figure ld~
DESCRIPTION OF THE PREFERRED EMBODIMENT
Extremely high operating frequencies are achieved utilizing emitter coupled logic (ECL) in an integrated design -with high speed solid state components. This permits operation o~ the video drive circuitry at approximately two hundred mega-cycles and produces pulse rise and fall times in that circuitry in the range o two to five nanoseconds. Similarly, the hori-.,.
zontal drive circuitry disclosed utilizes high speed components -in a two way scan design that permits operation o~ the horizontal drive circuitry at a frequency of fifty kilocycles. While improvements are disclosed to each oE the circuits shown, the ~-preferred embodiment utilizes, in combination, all improvements to create a high resolution display.
-~
Instead of a conventional MOS character generator, the ~ ~
, input to the video drive disclosed requires a higher speéd character generator (not shown). High speed PROMs, manufactuxers designation 74S741, could be utili2ed. Specially manufactured high speed TTTL ROMS suf~icient to generate a seven by nine dot matrix have also be0n found satisfactory. The output of the high speed character generator should be converted with an ECL
shift register (not shown) to a raster scan video input signal of the desired operating fre~uency.

The circuits described in detail below are preferably utilized with a high resolution tube. The circuit designs shown and described can be satisfactorily utilized with a high resol-ution, one hundred ten degree, ifteen inch tube manufacturedby Clinton Electronics in Chlcago, Illinois.

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1 V ~ o~Drlve Circuitr~
As shown in Figure ld, video il~put from the ECI, shif-t register is applied to video input pins 5 and 6. Each input line 1~, 20 is terminated with a resistor 22, 23 to a negative voltage source gencrated with a zener diode 26, having a small bypass capacitor 2~3 to gro~nd. The resistance is chosen -to match the impedance of the wires leading to the input as is conven-tional in high speed logic circuits to eliminate reflections in the line.
The input lines 18, 20 are connected to an ECL ampli-fier 31, operating as a receiver, for common mode rejection of any noise or re~lections which the terminating resistors ~2, 23 do not shunt out. The outputs 33, 34 of the ECL amplifier 31 are terminated by resistors 35, 36 and connected to a pair of ECL differential drivers 37, 38 connected in parallel. Two drivers 37, 38 are used to achieve sufficient current for operation of the circuit and to achieve higher speed of operation of the circuit.
The outputs 42, 43 and 45, 46 of the differential ~O drivers 37, 38 are connected to two transistors 51, 53 connected as a differential amplifier to form a non-saturating high speed current mode switch. The transistors 51 and 53 are selec-ted to have a high band width at the operating current level. The emitters of the transistors 51, 53 are connected together and connected through two resistors 58, 59 to voltage source to form a current source. The collector 61 of one 51 of the two tran-sistors 51, 53`forming the differential amplifier is connected to ground. The second transistor 53 is connected in a cascode arrangement to a transistor 63 to form a single ended voltage drive to provide a relatively low operating voltage for the first ' ~ .

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transis-tor 53 and a relatively high operatinq current which is converted to high variable voltage by the other translstor 63.
In the collector-emitter circuit 66 between the tran-sistors 53, 63, a resistor 68 is provided connected to a posi-tive bias that guarantees that when khe Eirst transistor 53 is off that the second transistor 63 is reverse biased so that there will be no leakage. Two high voltage, fast recovery clamp diodes 68, 69 are connected to the collector of the transistor 63 to keep the transistor 63 out of saturation. The diodes 68 69 which prefera~ly have a recovery time in the neighborhood of one to three nanoseconds, are capable of withstandiny voltages in the neighborhood of forty volts and can handle surge currents up to two hundred milliamps. A commercially available diode clamp of this type is manufactured by Motorola under Part No. MSD 7000.
To obtain sufficient power to operate the video beam at the desired high frequencies, the output of transistor 63, from the collector, is connected to a regulated voltage source by a high power low resistance bank of resistors 78-82. It is important that these resistors be high power carbon composition resistors rather than wire wound to negate effects of inductance and capacitance.
A small inductor 86 is also provided to compensate for residual capacitance in the video drive, including capacitance attributable to the tube and other circuit parameters including the transistor 63 and diodes 68, 69. A resistor 88 is provided across the inductor 86 to damp any oscillations caused by interaction between the inductor 86 and capacitance of the circuit and the network is grounded through a capacitor 92 to provide a tuned circuit which is critically damped and diode .

1 clamped so that the video drive signal is sufficiently attenuatecl to prevent overshoot during operation.
Horizontal Drive ~ixcu;try To opera-te at the desired high f:requency the horizontal drive is nok operated with the conventional flyback technique.
Instead, the trace is driven in both directions. ~lso, rather than using a tuned oscillator which is conventional in raster displays, an inherently linear circuit has been devised which eliminates the correc-tion devices common to conventional displays.
1~ The horizontal drive circuit, which in its normal state is in the sweep mode, responds to a horizontal syne pulse for retrace which is applied to pin 1. Pin 2 is connected to ground. As in the video circuit a pair of terminating resistors 103, 104 is connected to the input. The pulse is applied a short period of time before retrace is desired, the time interval ~eing in the neighborhood of one to two microseconds.
The pulse is applied to a one-shot timer 106 which can be adjusted with a potentiometer llO to provide precise timing for the operation of the circuit~ The one-shot preferably has a nominal value of one-half microsecond which can be varied over a range of five to one with the use of a potentiometer 110 to compensate for the various storage times or delays of the circuit components. The output, when the one-shot times out, ~rom pin 4 is connected through various components describe~
more fully below to transistor 112 to control the sweep trace and is also connected to transistor 113 to control the retrace.
To turn the sweep transistor 112 off to allow retrace to occur the output of the timer 106 from pin 4 is connected to pin 10 of a retrace one-shot timer 120 having a nominal time period of eight to twelve microseconds. The time period should 7~

1 be suf~icient to allow retrace to occur. The output Erom the retrace timer 120, pin 12, is inverted by three inverters 123-125 in parallel. The :inverters 123-125 are of the open collector type to interface b~tween the TTL logic and discrete components.
The output of the inverters 123-125 is connected to two tran sistors 130, 131 connected as a clifferential ampliier which operates as a differential switch. The differential switch operates to, in one state, turn the sweep transistor 112 on, and ~
in the other state, to turn the sweep transistor 112 off. ~^-To operate properly, the sweep transistor 112 must be driven on hard and driven off hard. Consequently, the output of the three inverters 123-1~5 is connected to a voltage divider made up o~ two resistors 133, 134. The output, from the middle of the voltage divider 133, 134, is applied to transistor 130 which is one slde of the differential switch. The voltage applied to the second transistor 131 of the differential switch obtained from the voltage divider formed from resistors 135, 136, is higher than the voltage applied to transistor 131 but is less than full potential so that a transistor 138 controlled by 20 transistor 131 and directly connected to the base of the s~eep ;~
transistor 112, can be driven on in the opposite state. Con-nected to the emitters of transistors 130, 131 are three bias resistors 140-142 in parallel, although one properly selected resistor could be used if available.
Transistor 138 is provided to aid in deenergizing the sweep transistor 112. The base of transistor 138 is connected to the output of transist~r 131 by resistor 144 and when it is driven into sat~ration by transistor 131 it guarantees that the sweep transistor 112 will be turned off. It is connected to a 3~ negative voltage supplied b~ a conventional regulator 1~0 to _ g 7`~

1 avoid uneven turn-off tlme or ripp:Le in the voltage. Conse-quently, during retxace, the first transistor 130 of the dif~ernetial switch is of~ and current ~lows through 131 from the negati~e power supply through resistor 152 and the base emitter juncti.on of 138. The collector o 138 is directly .
connected to.the base of sweep transistor 112. Therefore, the negative pulse on the base of 112 -turns the sweep transistor off and assures that there is no leakage during the entire retrace cycle. The direct coupling of the collector of tr.an-sistor 138 to the base of the sweep transistor 112 produces a turn-off time of under one hundred nanoseconds.
A high speed diode 156 is connected across the sweep transistor -to protect it by bypassi.ng excess energy from the yoke.
After about nine microseconds, at which time the timer 120 times out and returns to its normal state, the low output o~
the timer 120, which is connected through the drivers 123-125 turns transistor 130 on and transistor 131 off thereby turning transistor 138 off and transistor 112 on to cause another sweep trace.
This condition continues during the sweep trace and remains until another horizontal sync signal is received to cause another retrace sweep.
The same pulse that turns the sweep transistor 112 o~f is utilized to turn the retrace transistor 113 on to cause retxace. However, it is important that the sweep transistor 112 be fully off before the retrace transistor 113 is turned on since there is virtually no impedance between them~ To achieve the time delay, a timer 155 is utilized to create a nominal 30 delay of approximately one to three microseconds. The nominal -~

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1 time delay is achieved with components 158, 159 which can be varied to give sufficient timing.
After the nominal time delay the Q output from pin 12 is connected to a third timer 162 to produce an adjustable turn-on pulse with a nominal width of approximately -two microseconds.
Timing components 163, 165 and variable resistor 167 are provided to adjust the turn-on pulse with a range of three to one. The function of the timer 162 is to control the duration of the retrace pulse. It can also function to compensate for anomali-ties in previous circuit elements.
The output of timer 162 is also connected to three inverters 171-173 to interface the TT~ logic levels with discrete ; .;.~
logic levels for transistor operation. Three inverters 171-173 are used to produce higher current for a transistor 176 which operates as a current switch. When the retrace pulse occurs a voltage is produced across resistor 180 which produces a current i :
through it which i5 run through common base transis~or 176 and `
182 which are selected for their high voltage, mediu~ power characteristics. Tha two transistors 176 and 182 are connected in series in a cascode arrangement to convert the current to voltage. The base of transistor 176 is connected directly to a positive power supply which determines the current through resistor 180. Resistor 184 is connected between the base and emitter of transistor 176 to guarantee that the transistor 175 has no leakage when it is in its off state. Any leakage current which occurs is shunted through resistor 184 to the base of transistor 176 where it is dissipated.
The base of transistor 185 is maintained at half the horizontal yoke retrace voltage by resistors 188, 189. Capaci-3~ tors 191 and 193 are connected across a voltage divider made up t of resistors 188 and 189 to bypass any noise. The collector oftransistor 182 is connected to the base of transistor 195 to turn transistor 195 on for the entire retrace pulse. The collector oE transistor 195 is connected through diode 198, a DC blocking diode in the off state, to transistor 113, the retrace transistor, which i5 then turned on and supplies the horizontal yoke with energy through diode 201 connected to the emitter of the retrace transistor 113.
During the entire retrace sweep inductor 203 is charqed through resistor 20S. After the retrace network shuts off, detected at transistor 185, the inductor 203 has sufficient energy to apply a negative pulse to the base of transistor ]95 to guarantee that the transistor 195 has good turn-off characer~
istics. That circuit is clamped by diode 207 to assure that the negative pulse from the inductor 203 doe~ not put a reverse , r bias on the base of the transistor 195 which would damage it.
, A damping resistor 309 is also connected across the inductor 203 to keep the circuit from ringing due to parasitic capacitance '~
in the inductor 203.
~ An inductor 212 is provided which is connected to the base of the retrace transistor 113 which is the power-driver transistor for the horizontal yoke. The inductor is charged, ~, through resistor 214 and is damped by resistor 216. The output - of the inductor 212 is amplified by transistor 218 to turn the - ' ~' retrace transistor 113 off quickly.
Capacitor 221 connected to the emitter of the retrace transistor 113 and across diode 201 assures negative bias of the transistor 113 to prevent leakage current. In the sweep mode it keeps'the emitter of transistor 113 at a higher potential than, the ~uiescent point of -the base. Capacitor 221 is selected for its hîgh speed characteristics.

1 ~lso connected to the yoke drive is diode 223 which protects transistor 113 from reverse bias and shunts energy lnto capacitors 228 and 229 during the first half of the retrace period~ In the absence of such a diode 223 the voltage on the yoke would go sufficiently high to burn O~lt the transistor 113.
The diode 223 is selected for its high voltage, high speed characteriStiCS and is an extremely fast recovery diode. Diode 156 connected across the sweep transistor 112 is the equivalent of diode 223 and similarly protects the bottom driver 112 by bypassing excess retrace energy during the first half of trace.
The two capacitors 228 and 229 are especially selected to provide electrical characteristics suitable for the circuit.
Capacitor 228 is preferably a low capacitance non-polar mylar or polystyrene capacitor designed -to take high current for a very short period of time to handle the switching edge or load.
However, it does not have sufficient capacity to provide sufLi-ciently low ripple so capacitor 229 is connected across capacitor 228 which is a high capacitance aluminum electrolytic capacitor to handle the drive current which itself could not be used alone because it does not have satisfactory high frequency characteri~tics.
Also connected to the horizontal yoke is a dampex consisting of capacitor 232 and resistors 234 and 235 which are connected to ground. These components 232, 234, 235 comprise a yoke damping circuii sufficient to damp extremely high frequency oscillations, in the range of one megahurtz, which may occur~ The components 232, 234 and 235 must be selected according to the inductive characteristics of the yoke utiliæed with the circuit and the capacitor 232 selected should have a negative temperature coefficient to provide stable operation at - 13 ~

: : . . : , 1 increasing currents. In addition, the resistors 234, 235 should be carbon composition to avoid inductance and must provide su~ficient power dissipation for the circuit.
To assure linearity, the yo]ce is preferably not con-nected fro~ the trace and retrace transistors 112, 113 to ground but is connected from the switching pair 112, 113 to a shapiny circuit comprised of a high frequency polystyrene or Mylar capacitor 238 plcked in value to match the inductance of the yoke.
The horizontal drive circuitry is also connected to protection circuitry 240 as di.scussed more fully below.
- Rather than dissipating all of the energy accumulated by the inductance of the yoke it is utilized to provide a well regulated high voltage power supply for the first anode. This :; .
is accomplished through a high voltage multiplier 242 consisting of resistor 246 which is connected to a capacitive diode multi~
~' plier of the typi.cal cascade type which consists of diodes 2~0 . ~
through 256 and capacitors 260 through 267. The diodes 250-256 , , ~.
must be of a high recovery type and the capacitors 260-267 must ~ :
20 be high frequency with a high voltage ratlng and should be as ~:
large as physically feasible. Preferably the high voltage ,-~
multiplier 242,is designed to provide 1.1 kilovolt for the ~-~
first anode.
The energy from the yoke drive is also utilized to provide a negative voltage to the brightness grid. This voltage is supplied to capacitor 282 through capacitor 284 and resis-tor :
286 and is,maintained with diodes 290 and 291. The actual voltage supplied to the brightness grid is highly adjustable .
through the use of adjustable resistors 293, 294 and 296.
Vertical Dr ve Circuitr~
As discussed in detai]. below, the vertical drive .

1 circuit utilizes semiconductor design for all ~unctions ;ncluding shaping which permits direct coupling of componell-ts.
The vertical retrace pulse is applied to the vertical drive circuit shown in Figures lc and ld at input pins 3 and 4.
The vertical retrace pulse is a positive going pulse of short duration. Pln A provides the ground return. As in -the case of the horizontal drive circuit, a TTL signal is provided, which is terminaied b~ resistors 302 and 306. The input is connected to a one-shot timer 310 which functions to provide a precise 10 retrace pulse regardless of the input pulse received. The timer ~;
310 triggers on the positive edge of the pulse and employs an internal Schmitt trigger for noise rejection. The timing of the timer 310 is nominally set for one hundred microseconds with components 312 and 314. The timing period must be sufficient to discharge the vertical sweep capacitor 320 which should be selected for its dielectric absorption. The output of the timer 310 is connected to a diode 312 to interface with the sweep :
generator~ the output of which is connected to a current source ~ consisting of resistor 314 connected to the positive voltage supPlY.
When pin 1 of the timer 310 is in the low state, the diode 312 conducts and discharges the capacitor 320. When the timer 310 is in the normal state and the circuit is not retracing, pLn 1, the Q output of timer 310 is high and the diode 312 is ~cut off which produces no appreciable effect on the current ramp or voltage ramp produced by the circuit. The resistor 32A is provided to limit the surge current into the capacitor 320 ~- during the retrace pulse from the timer 310.
The foregoing circuitry will produce a linear ramp at 3~ the capacitor 320 which is linear up to the desired voltage. Its _ 15 ~

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1 repetition rate is at the fre~uency of operation which is sixt~
hertz in the United States and about fifty hertz in Europe. The linear ramp is supplied to an operation ampl:ifier 330 which functions as an impedance buffer having a low output impedance.
The output of the operational amplifier 330 is connected through a DC blocking capacitor 33~, to the summing node input, pin 6, of a second operational amplifier 334 through resistor 33~ and through resistor 339 to a lineari-ty correction or shaping circuitry 3~2. .
The gain or amplitude of the shaping circuit 342 is governed by variable resistor 344.
.
The shaping circuit which consists of transistors 347 and 348 and associated components 352~356 produces the shaping function due to the exponential characteristics of the collector current versus base emitter resistance of the transistors 347, ~
348. Svmmetric operation is assured by the differential arrange- ~ ;
ment of parts. The differential transistors 347, 348 and tran-sistor 350 are preferably chosen in a quad pack rather than ~ -utilizing matched transistors or matched pairs. Transistor 3~0 ~0 is used for impedance matching of the operational amplifier 334.
The output of the shaping circuit 342 is connected to the operational amplifier 334 at pin 6, the output of whichj from pin 7, is used to dri~e the verticai yoke. Pin 5 of the summing amplifier 334 is grounded while pin 6 is bypassed with a capaci-tor 372 to ground to critically damp the circuit. The output from the amplifier 334, on pin 7, functions during the vertical sweeP trace to drive a variable current source 380, shown in Figure ld.

The current source is made up of a pair of matched diodes, 386, 388, each connected to regulated voltages b~

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1 resistors 392, 394. The output from each diode 386, 388 is connected to the base of a pair of transistor 398 and 394, respectively, creating an inverted output on the collectors of the transistors. ;
When the output of the operational amplifier 334, pin 7, goes positive the base of transistor 398 goes slightly posi~
tive increasing the current through the transistor 398. At the same time, the base of the second transistor 399 goes positive decreasing the current through the second transistor 399 creating an amplified analog output. This design is utilized so that the transistors 398, 399 do not switch states which prevents zero cross-over.
The collector outputs of the transistors 398 and 399 are connected to power transistors 406 and 408 which drive the vertical yoke. Resistor 411 is connected across the collectors of transistors 398 and 399 to assure satisfactory quiescent current of transistors 406 and 408 and resistors 414 and 416 are also provided to shun-t current across the base emitter circuit of transistors 406 and 408 to improve the quiescent performance o~ the transistors~
The output from the collectors of transistor 406 and 408 is connected to the yoke through an inductor 420 which is designed to decouple noise picked up by the vertical yoke from the horizontal drive signal. The return from the yoke is connected through a power resistor 424 to ground. The voltage signal present on the ungrounded side of resistor 424~ repre-senting the current going through the vertical yoke is connected back to the summing node, pin 6, of the operational amplifier 334 through resistors 430 and 434 closing the loop. In this manner gain is increased automatically when the yoke current and , ~7~

1 temperature increase creating a larger voltage to drive the yoke to assure that current througll the yoke remains essen-t:i~].ly constant.
The linear amplifier circuitry previously d.iscussed drives the yoke during normal sweeping, that is, ~rom the top o~ the scrPen down to the bottom. An additional circuit is provided consisting of transistors 448 and 449 and associated components 452, 453 and 454, also controlled by operational amplifier 334 to return the beam to the top of the screen. It 10 is supplied from the energy source supplying the video drive ..
since the video drive is always off during vertical retrace in ~-normal operation. .
The retrace signal to the hase of transistor 448 is produced when, at the bottom of the sweep, the sweep capacitor .
, .
320 has dlscharged. The operational amplifier 334 has positive :~
drlve on both ends of the current source into pin 6 so the summing node is highly negative. Consequently the ou-tput, on .
pin 7, goes positive until transistor 448 clamps the voltage. . ~
Since~the output is directly coupled to transistor 448, the ;

2~ transistor 448 is driven into saturation. Transistor 448 is : connected to the base of transistor 449 by resistor 452. This produces a sufficient signal to saturate transistor 449. When transistor 449 is in saturation sufficient energy to accomplish ..
retrace is provided to the yoke through resistor 456.
Resistor 453 is provided to keep transistor 449 in the o~f state during the vertical sweep and capacitor 454 is con-nected across resistor 453 to bypass noise which may be generated from the video circuit.

A dynamic focus circuit 461 is also provided which is ~ .

connected to the yoke. The yoke current is connected to pass 1 through a differential amplifier made up of transistors 466 and 467. The differential current is amplified and rectified by r ~ransistors 472 and 474 producing a variable current through resistor 477 which is proportional to the absolute value of the vertical position of the trace from center. In other words, a high current from the yoke is produced when the ~race is at the center, and a low current is produced at the top and bottom of the trace. Voltage is applied to transistor 481 from the vol*age source through resistor 483 to the collector of the transistor.
10 The output, from the dynamic focus circuit 461, is connected to the base of transistor 481 which produces a sawtooth trace varying between substantially zero volts when the trace is in the center vertically and higher voltages when the trace is at the top and bottom of the screen with a linear ramp in between.
The signal is coupled through capacitor 488 to the focus grid of the tube as a focus correction to the standard Eocus re~uired by the screen. The focus correction is required because of the longer path that the electron beam must follow when it is at the edges of the screen. Since the vertical 20 axis is the long axis for the preferred embodiment of the display this focus correction is adequate when applied to only the long axis.
Protection Circuitry Protection circuitry 240 is also provided to remove - the signal from the brightness grid. This will occur any time that a horizontal sync signal or vertical sync signal is lost for any reason. Elimination of the brightness signal will prevent burning or otherwise damaging the screen. The protection circuitry utilizes a dual retriggerable one-æhot timer 491, 30 which is connected to the signal from the horizontal yoke~ The 1 timer is set for a nominal timi.ny of fift~ microseconds wi1:h the use of components 494 and 495 under normal operatlon w:ill be triggered every twenty microseconds.
The protection circuitry 240 is also connected to the vertical drive at input pin 2 of a second retriggerable timer 497 which is designed to time out at approximately fifty milliseconds with components 503 and 504. Vertical retrace should occur every sixteen to twenty milliseconds depending on use in the United States or in Europe. If a vertical retrace pulse is not received, timer 497 times out and the Q output on pin 13 is connec.ted to the clear input of timer 491. Conse- ; .
quently, if a vertical retrace sync is no-t received, the timer .~ . .
4~1 will be cleared and the video wi.ll be shut down. Shut down is accomplished with the utilization of a switchable current source through transistor 508. The current source is produced by a fixed voltage across resistor 511 producing voltages on -~
resistors 293, 294 and 296 which are connected directly to the brightness terminal of the displ.ay.
In general, while a specific embodiment of the ~ :
invention has been described, it is to be understood that this is for the purpose of illustration only and that various modi-fications can be made within the scope of the invention and that all such modifications are within the intendment of the invention.

Claims (13)

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. A high frequency two way scan circuit for causing trace and retrace scans on a cathode ray tube having a yoke comprising:
sweep means connected to the yoke of the cathode ray tuba for causing the trace to sweep from a first side of the tube to the other;
receiving means for receiving a retrace sync signal;
first circuit means connected to the sweep means for turning the sweep means off during retrace comprising:
first timing means connected to the receiving means for generating a first timing interval during which the sweep means will be off;
electronic switching means connected to the first timing means and the sweep means for switching the sweep means off during the first timing interval and on after the timing interval established by the first timing means;
retrace means connected to the yoke of the tube for causing the trace to return to the first side of the tube; and second circuit means connected to the retrace means for turning the retrace means on comprising:
second timing means connected to the receiving means for generating a second time interval smaller in duration than the first time interval and which is initiated a finite time after the first time interval and which terminates prior to the termination of the first time interval; and a second electronic switching circuit connected to the second timing means and the retrace means for switching the retrace means on during the second timing interval and off after the second timing interval.

2. A scan circuit as claimed in claim 1 wherein the first timing interval is less than 10 microseconds.

3. A scan circuit as claimed in claim 1 wherein the second timing interval is on the order of two microseconds.

4. A scan circuit as claimed in claim 1 wherein the scan circuit operates at a frequency of approximately 50 kilocycles.

5. A scan circuit as claimed in claim 1 wherein the retrace means comprises a retrace transistor and wherein the circuit further comprises means for improving the turn off characteristic of the retrace transistor comprising:
an energy storage device connected to the base of the retrace transistor for accumulating energy during the second time interval and for applying a negative pulse to the transistor after termination of the second timing interval.

6. A scan circuit as claimed in claim 1 wherein the second circuit means comprises an electronic current switching device connected to the second timing means; and means for converting the current signal through the electronic current switching device to a voltage signal.

7. A scan circuit as claimed in claim 1 further comprising:
bypass means connected across the sweep means for by-passing excess energy produced during the first time interval;
and energy storage means connected to the bypass means for accumulating excess energy produced during the first time interval.
8. A scan circuit as claimed in claim 1 further comprising:
bypass means connected across the retrace means for bypassing excess energy produced during the second time interval;
and

Claim 8 continued:
energy storage means connected to the bypass means for accumulating excess energy produced during the second timing interval.

9. A scan circuit as claimed in claim 1 wherein the cathode ray tube has a first anode connection and wherein the scan circuit further comprises a voltage multiplier for generating a high voltage for the first anode connection of the tube.

10. A scan circuit as claimed in claim 9 wherein the voltage multiplier generates a 1.1 kilovolt acceleration voltage to be supplied to the first anode of the tube.

11. A scan circuit as claimed in claim 1 wherein the cathode ray tube has a brightness grid and wherein the scan circuit further comprises means for generating a voltage to be supplied to the brightness grid of the tube.

12. A cathode ray tube display circuit as claimed in claim 1 wherein the cathode ray tube has a brightness grid and the display circuit produces an output signal to the brightness grid further comprising protection circuitry for cutting off the output signal to the brightness grid when loss of a signal is detected.

13. A scan circuit as claimed in claim 1 wherein the cathode ray tube has a horizontal yoke and wherein the scan circuit is connected to the horizontal yoke to produce a horizontal drive signal with a frequency in excess of 40 kilo-cycles.