CA1109137A - Acoustic encoding apparatus - Google Patents

Abstract

ACOUSTIC ENCODING APPARATUS
ABSTRACT OF THE DISCLOSURE
Encoding apparatus for a business machine includes a resilient striker for inducing diverging sound waves with-in a rod by impact with it at a given location. Transducers positioned along the rod on each side of the striker and at unequal distances from it, convert the sound wave fronts into a first and a second output signal having a pre-determined time interval between them which is dependent upon the location of impact with the rod. The transducers are connected to a logic unit which includes an oscillator-driven binary counter. The first output signal starts the counter and subsequent arrival of the second output signal determines the elapsed time, the counter output at that instant being a binary code value usable for any desired purpose: control, display, etc. The encoding apparatus may be incorporated in a keyboard having a number of keys and a corresponding number of strikers differentially positioned along the rod such that each key produces output signals with a predetermined time interval between them and accordingly a unique binary code may be obtained upon actuation of each key.

Description

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BACKGROUND OF THE INVENTICN ~ _ 1. Field of the Invention !
The present invention relates to encoding apparatus for business machines such as typewriters, tele~ypewriters, cal-culators, adding machines, cash registers, etc. and periph-.~._.... eral equipmen~ such as computer terminals, keyboard modules, and the llke. More particularly it relates to encoding appa-ratus for keyboards having sound generating keys coupled with . .' `'''"
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¦ electronics for determining the key depressed by the keybosrd ¦ operator.
¦ 2. Description of the Prior Art.

S ¦ To satisfy the increasing demands and requirements of ¦ modern business machines, the trend of manufacturers has ~een ¦ to reduce or eliminate mechanical arrangements for control and data input by introduction of equiYalent electronic components ¦ and circuitry. The electronic keyboard, in particular, is an 10 ¦ approach which is desirable because of the simplicity and re-¦ liability of the few moving parts required and elimination of ¦ adjustments due to wear. For these reasons, electronic key-¦ boards are more economical because of the significantly reduced l manufacturing cost. Another advantage of electronic controls 15 ¦ and keyboards in particular is that the space formerly occupied ¦ by bulky mechanisms is no longer needed, the great reduction in space requirements thus allowing foria more compact and lighter machine. Also, electronic keyboards easil~ increase the versa-tility of business machines because use of large scale inte-grated circuits permits increasing functional capabilities atlittle added cost.
~ lany prior art business machines employ mechanical switch-es for sensing mechanical actions, e.g. key depressions in electrical keyboards. This arrangement is undesirable because 2S the switches are subject to wear during use, to atmospheric attack on the contact material and to dirt build up on the contact faces -- all of which affect`the electrical resistance.
To overcome the problem of contact wear and susceptibility to atmospheric attack, manufacturers have had to employ contacts ~0 made of a noble metal such as gold at substantial increase in . -`

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l manufàcturing expense. The problem of dirt and dust can only 1 ¦ be avoided by enclosing the contacts which again adds to the cost.
I Bounce is another major problem encountered with the use 5 ¦ of switch contacts, it being difficult to eliminate entirely ¦ ~n conventional switches by mechanical desi~n alone. Antl-¦ bounce circuitry has been introduced as one way to eliminatebounce, but this adds to the complexity of the design with ¦ corresponding increase in cost.

10 ¦ The above problems have inspired designs of more elaborate keyboard circuitry employin~ arrays of devices such as Hall ¦ Effec~ switches, miniature transformers, piezoelectric ele-¦ ments and variable capacitors -- many of which eliminate bounce and have a long life. The disadvantages of such circuitry are substantial. The arrays all require¦many individual trans-ducers mounted on a printed circuit board, one transducer being needed at each key station. Further, these prior art key-boardsrequire many interoconnectionslas well as many repetitive sensing circuits. For these reasons such keyboarq designs have proved complex and expensive.
Another approach in keyboard design is the photo-electric keyboard. Such keyboards typically comprise a matrix of channels and orthogonal grooves with a light source at one end of each channel and a photocell at the other end. Shutters are provided in the grooves for selectively intercepting light beam~ in the individual channels. Interception of the llght beams de-ener-gizes the photocells and, through appropriate circuitry, conveys an information signal. A disadvantage of this keyboard apparatus is that the matr~x of channels and grooves is complex and difficult ~o manufacture. Another disadvantage is that the light sources and photocells must be accurately aligned, which . .

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1 ¦ results in costly assembly time.
Accordingly, there is still a need for a low-cost encoding ~ apparatus, one particulaFly suitable for use with keyboards.

5 ¦ Sl~MMARY OF THE INVENTION
¦ The present invention sets forth a method and encoding ¦ apparatus in which vibratory energy (which may be acoustic ~
¦ or sound energy) is induced for generating an output represen-¦ tative of a mechanical motion. The apparatus includejs a member 10 ¦ for transmitting vibratory energy, means operable in response ¦ to the mechanical motion and efective to induce vibratory ¦ energy within the member in the form of separate wave fronts ¦ travelling in diverging directions, means operatively connected f ¦ to the member for transducing the wave fronts into signals 15 ¦ with an elapsed time between arrival of these signals, and ¦ means connected to the transducing means and operable to ¦ generate from the elapsed time an output representative of ; ¦ the mechanical motion.
¦ In a particular form, the encoding apparatus includes 20 ¦ a rod for providing different distances for the wave fronts to ¦ travel in the diverging directions, a striker for impacting the ¦ rod at a particular point, and transducers connected to the ¦ rod and positioned appropriately on either side of the point at ¦ which the striker impacts the rod such that induced sound 25 ¦ waves are sensed by the transducers at different times. The transducers each convert the sound waves into a corresponding electrical output signal, the sound wave transmitted over the ¦ shorter distance being transduced into a first signal (i.e.
¦ the "leading" signal). After a predetermined elapsed time, ~0 ¦ the other sound wave - that transmitted over the longer distance-is transduced into a second signal (i.e. the "following"
¦ signal). Circuitry ~ . . . _ _ ~ r~

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1 ¦ connected to the transducers measures the elapsed time between ¦ these two signals and a code is then generated from the elapsed ¦ time. Uore particularly, the encoding apparatus may be associ-¦ ated with one or more depressible keys, in which case the code S ¦ generated is representative of depression of the one key, or a ¦ selected one of many keys.
Accordingly, an obJect of $he present invention is to pro-~ ¦ vide an encoding method and apparatus that utilizes acoustic I energy.
10 ¦ Another object ot the present invention is to provide en-¦ coding apparatus that is easily adaptable to the many kinds of ¦ machines using a keyboard.
¦ A further object o~ the present invention is to provide an ¦ encoding keyboard that is of simple construction, having few 15 ¦ ~oving parts. /
¦ A further object of the present invention is to provide an ¦ encoding keyboard that is efficient, reliable, rapid in response, l ; low in manufacturing cost and extremely easy to assemble.
¦ Other objects, features and advantages will become more 20 ¦ apparent from the following description, including appended l claims and accompanyi~g drawing.
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_ ¦ B~I~F DESCRIPTIO~ OF THE DRA~YINGS

¦ Figure 1 is a perspective view of the encoding apparatus 25 ¦ associated with a keyboard mechanism having electronic and logic circuitry connected thereto as an embodiment of the present i~-¦ vention.

¦ Figure 2 is a sectional right side elevation along section ¦ A-A of Fig. 1 with solid lines showing the Xey mechanism and its 30 ¦ relation to a sound-inducing striI<er at rest position and dotted I ', , 01 lines showing the relation of the same parts just before release 02 of the striker after it has been engaged by the key mechanism 03 during a key depression.
04 Figure 3 is an enlarged perspective view of the key 05 mechanism associated with a portion of the apparatus.
06 Figure 4 is a front elevation view of the acoustic rod 07 portion of the apparatus with a single striker located at a given 08 position and showing the sound waves induced by striker impact.
09 Figure 5 is a front elevation view of a portion of the apparatus, illustrating different embodiments of multiple striker 11 positions along a rod.
12 Figure 6 is a block diagram of the logic portion of the 13 apparatus.
14 Figure 7 is a detailed schematic of the electronic portion of the apparatus including the logic elements of Fig. 6 16 and signal conditioning circuitry.
17 Figures 8a-8O present individual portions of a timing 18 diagram illustrating the generation of various signals and 19 related codes by the elements of Figures 6 and 7. Figs. 8d and 8h to 81 are on an expanded time scale for greater clarity.

22 Referring to the drawings and more particularly to 23 Fig. 1, it is shown that, in general, a code generating or 24 "encoding" apparatus 10, according to the present invention, includes an actuator 16, a sound wave or "acoustic" wave inducer 26 18, an acoustic member 20 in which diverging sound waves may be 27 propagated by the inducer 18 in response to the actuator 16;
28 transducing means 22A, 22B for converting the sound waves into a 29 pair `i~, 1 ¦ of electrical signals, the transducing means being so located with respect to the diver~ing vaves that each electrical signal of the pair ls produced at a different time; and a lo~ic unit 24 I for producin~ a code representative o~ the ti~e difference. / --~
5 ¦ ~'ihile the acoustic system is shown in Fig. 1 as a resilient ~ striker 18 for delivering an impact to an elon~ated me~ber 20 : adjacent to it, other i~plementations are possible, e.~., a ' ¦ pulsed electroma~net could be used to induce co~pression waves ¦ in a magnetostrictive ele~ent closely coupled to it. ~esilient 10 ¦ striker 18 may be in the for~ of a cantilevered spring fixed at one end in a frame and deflectable at the other end by the actuator 1~, ~hich may be associated for example with a key-button 2~ of a keyboard 12. The elon~ated acoustical member 20 may be a long rod (as it will be termed hereafter for convenience) extendin~ perpendicular to the striker 18 for optimu~ performance.
Striker 18 is normally at a rest positioll a~ainst rod 20, but is enga~eable with actuator 16 ~hen l~eybutton 2~ is depressed by an operator. Through the action o4 a key mechanism 14, depression o~ the keybutton 2~ only flicks the striT.cer 18 -- that is, momentarily deflects striker 18 and then releases it. After striker 18 has been released, stored flexural ener~y returns it to the normal position, giving rod 20 a sharp blow in so doin~.
The impact with rod ~0 induces sound energy within it in the form of diver~ing sound w~ves. Transducer devices 22A, ~B are operatively connected to rod 20, one on each side of striker 18, for convertin~ the sound ~vaves into electrical output si~nals.
The transducer devices 22A, 22B are positioned alon~ rod 20 at unequal distances from striker 18. Therefore, sound ~vaves ori~inated by a sinOle i~pact or blou~ from stri~er 18 are trans-~0 duced into output si~nals by -transducers 22A and 22B at different !

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1 ti,nes. The sound wave traveling over the shorter distance is transduced lnto a first output si~nal hereinafter referred to as the "leading signal", and the sound wave traveling over the longer distance is transduced into a second output signal, here-S inafter referred to as the "following si-Jnal". For a ~iven location of the strilcer, the~e is a known time interval between the two outputs since the velocity of sound is a constant for a given material so lon~ as temperature re.nains substantially unchan~ed. The elapsed time between the leadin~ and followin~
si~nals is measured by circuitry including the lo~ic unit 2 connected to the transducing means ~2A, 22B by their output lines 108A, 108~. Arrival of the leadin~ si~nal at the logic unit 24 starts the time measuring and arrival of the follo-in~
signal at logic unit 24 causes the elapsed ti~e between signals lS to be determined, a correspondin~ code then bein nade availa~le on lines 25 for display or recording in a utilization device or for control of such device. The code generated in correspond-ence ~ith the measured time interval is ~roadly airepresentation of occurrence of a mechanical motion. Nore narrowly, the code produced by the time measurin~ circuitry may be representative of a selected key of the above-~entioned keyboard 1~. For _ e~ample, as sho~n in Fig. 1, each key 26 of keyboard 12 is associated with an individual striT~er 18 which is differentially positioned along the elonOJated rod 20 in a way such that each stri~er 18 has a uni~ue differential distance relation with the transducin~ means (with use of appropriate discrininatin7 means under conditions of symmetry, as will be seen). 'rherefore, the time interval for ge.leratin~ a representative code can be made unique for each key.
As seen in Fi~ the electronic arran~ements include ,7 / ~ ,, ~L10~ 7 1 signal conditioninc~ circuitry ll~A, llGB, connected betu~een a respective one of the transducer outputs 108~ and 108~ and the lo~ic unit 24 provided for measurin~ the elapsed time and pro-ducin~ a corresponding code. ~he si~nal conditioning circuitry 5~ ll~A, 116B is necessary to ensure coi~patibility r~ith the type of integrated circ~its chose~ for imple~entation of lo~ic unit 24, as more fully explained subsequently. 'rhe path of the signal from the transducer output 108A to the logic Ullit input line 118A which lncl~des signal conditionin~ circuitry ll~A is herein defined as Channel A for convenience. Similarly, the path of the signal from the output 10~ to the lo,ic unit input line 118B
which includes conditionin~ circuitry 116B is herein defined as Channel B.
Referring IIOW to Ficgs. 2 and 3, there is shown one form of the key mechanism 14 for use in the keyboard 12 associated with the encoding~ apparatus 10 according to the present invention.
It should be understood that other ~echanisms could equally well be used. The l;ey mechanism 14 includes a fin~ger-engagable, keybutton 26 mounted on a TceyleYer 28, which keylever has one end 30 pivotally supported and ~guided within a slotted frame 32.
The other end 34 of keylever 28 has a right angle extensicn 36 projectin~ down-~ard throu~h a guide fra~e 38 for stabili3ina keylever 28 durin~ key depression. Extension 36 is ter~inated at its lower end by an upstop arm 39 ~hich abuts against an upstop 46 when ~eylever 28 is in a normal rest position (solid lines in Fi~. 2j. A leaf sprin~ 40 has one end 42 secured to frame 32, and the other end 44 extends beneath ~;eylever 28 to en~age it and urge it to the rest position. Similarly, a down-_ stop arm 48 extends foru~ard (this term bein~ used in the context of the keyboard 12 being at the front of the machine as is ~6~

1 usual) from extension~36 at a point beneath keybutton 26 forabutment with a downstop 50 when '~eylever ~8 is depressed.
~ctuator 16 is provided on extension 36 of keylever ~8 for operative movement of striker 18 and comprises one arm 16 ~as 5~ it will be ter~ed hereinafter) of a bellcrank 52 pivotally 'mounted at 54 on extension 3G, the other arm 58 of bellcrank 52 projectinJ downward and'terminating in a form 60 normally rest-ing a~ainst an edge 67 of extension 3~. A tension sprinr~ G2 has one end G~ hooked on the arm 1~ of bellcrank 52 and the other end 6~ hooked Oll keylever "3. Spring G~ thus urges bell-crank ~ in a clocl~ise direction (as vie-~ed in Fig. '~) such that ~orm ~0 is in its normal position.
Resilient striJ~er 18 is sup~orted in cantilever fashion, as mentioned earlier, with one end ~8 rigldly clamped in a frame 70, the other end 72 bein~ free. Free end 7~ extends under rod 20 toward arm 1~ of bellcranl~ 5~, ter~inating substantially'~e--low an ear 57'formed on arm 16. Deprcssion of kcybutton .6 causes the ear 57 of ar~ 16 to engage with the free end 72 of striker 18. ~.esilience of stri.cer 18 allows deflection from a irst, or rest position (solid lines in Fi~. 2) uhen a^tuated by arm 16 and restoration to that first position when released from arm 1~ at a flex~d position (dotted llnes in Fir. 2).
Resilient striler 18 may be ar elongated wire and is preferably constructed from a spring steel material or an e~uivalent.
A guide member in the form of a comb 74 has slots 7G through each of which e~tends the free end 7'7 of a striter 18, there being preferably more than one striker when ihe acoustic encod-ing apparatus is associated with a ~ceyboard. 'i'he purpose of co~b 74 is the lateral alignment of the free end 72 of stri~;er 18 with respect to car 57 of ar~ lG and the Ouidance of stri~;er ~ /f-/,7-,7,7 i' - - ~
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1 ¦ 18 during its vertical deflection. The guidance is necessary ¦ not only to prevent premature disenra~rement fro~ arm 16 which might otherwise result upon sideways displacement, but to main-tain orthoronality of the striker and rod at impact and precision of the impact position. Ortho~ronality of impact has been found to reduce any tendency to~ard asyL~metry and unequal intensity of the induced ~vave front u~ilich could cause si~rnificant errors in time measure.~ents, if uncontrolled. Yariations in the impact position lil~e~ise affect the time measurer,lents as is clear fron the fore~oing discussion.
As mentioned earlier, the acoustic member 20 is preferably an elon~ated rod arranged substantially perpendicular (orthoro-nal) relative to striker 18, restinr near the free end 72 there-of so as to form a contact point 78 to the rear of ar~ 16. Be-cause of this contact with rod 20, s~riker 18 is under a slightbending load which tends to reduce undesired bounce of striker 18 when impactin~ rod 20. The material and configuration of rod 20 are not critical, in ~reneral. The ~aterial selection fior rod ~0 is not restricted as lon~ as the follo-win~ characteristics are present. Rod 20 must be capable of propa~atin~ sound enerry when induced, for ccam.ple, upon i~pact by striT~er 1~. r.od 20 _ rlust further be capable of sustainin-r sound energy in the form of sound waves u~ithin itself and transmittinr these in diver~ent directions at a predetermillable, substantially constant velocity uithout excessive attenuation. ~or the embodiments of this invention, rod 20 may be, for e.ample, a round metal rod havia~r a dia~eter o~ 1/16 inch and preferably made of steel. Other metal alloys, crlass or plastic viould satisfy the material re-quirements, houeYer, as is Xnown from delay line art. Ilollo-v, 3~ elon~ated members containin~ gases and liquids ~uld also . ~
1 ¦ s,at;isfy the material requireMents. As to confi~uration, rod 20 ¦ ~ay be any desired shape, although shown in the figures as a ¦ ri~ht circular cylinder. The circular form shown is ~erely one exa.-lple of a suitable elongated r,lember. Other for~s of elon,ated 5 ¦ m2~bers, such as a tube or a square bar, could e~ually well be ¦ used.
Referrin~ baok to Fi~. 1, rod 20 is seen to be supported at each end such that it is acoustically isolated fro~ eY~ternal ¦ effects such as motor vibra~ion or environmental shocXs. '~he supporting structures at each end of rod 20 are identical, there-fore only one need be described. ~od 20 rests on two pads 80 located near the eV~tremities of rod 20, each pad S0 bein-~ con-structed from a dampenin~ material such as corT; or plastic foaD.
The da~pening rnaterial has little effect on the sound ~enerated by the apparatus 10 since the sound ~:aves are bein~ transmitted w~ithin rod 20. Each pad 80 is affixed -- as by an adhesive --to an upper surface 82 of a support brachet 8~. A pin 8~ is ri1idly mounted to a lower arm 88 of the support bracl-~et 8~, extending outwardly therefro.~ and passing throu~h a rubber grommet 90 secured within a frame plate 92, thus givin~ proper support to rod ~0 when combined ~ith the upward force e,:erted by the strikers 18 i~ their rest position. For ~reater stabi-lity for use with a sin~le striIcer 18, the lo.ver arm 88 can be provided with a spaced secolld pin enC~agin~ fra.lle plate 92 in fashion similar to pin SG.
Operation of Iiey mechanis3 1~ to induce sound energy within rod 20 will no~!~ be deacribed in connection wlith Fio. 2. 3epr~s-sion of keybutton 2~ causes keylever ~8 to pivot counterclocX-wise. The ear 57 at the rearward tip of arm lG of bellcranT 52 30 ¦ t ensa~es ~he free end 7~ ~f resilie~t s~riker lB ~:hich it ~ /7-~7 01 overlies and deflects it from the first or rest position shown in 02 solid lines. When keylever 28 comes to the position shown in 03 dotted lines, the free end 72 slips out of engagement with ear 04 57. Deflection of striker 18 as compared with the travel of 05 keylever 26 is, of course, such that release occurs prior to 06 abutment of keylever 28's arm 48 against downstop 50. Upon 07 disengagement from ear 57, resilient striker 18 springs back to 08 its first position (solid lines) where it strikes rod 20.
09 Restoration of keylever 28 is accomplished under the urging of leaf spring 40. As keylever 28 is restored, the top surface of 11 ear 57 of arm 16 engages the free end 72 of striker 18 (now 12 stationary against rod 20 as shown in the solid line position in 13 Fig. 21. Bellcrank 52 is yieldably mounted on extension 36, 14 rotating clockwise on pivot 54 to allow keylever 28 to bypass free end 72. Subsequently, spring 62 restores bellcrank 52 16 toward its initial location, return motion ceasing when form 60 17 abuts the edge 67 of extension 36. Meanwhile, having bypassed 18 the end 72 of striker 28, keylever 28 comes to rest with arm 39 19 against the upstop 46 under the urging of leaf spring 40.
The sharp blow from striker 18 which rod 20 receives as 21 a result of the above-described flicking action by arm 16, 22 induces sound energy in the form of sound waves within rod 20. A
23 distinct blow occurs, bounce being minimized because of the 24 contact load between striker 18 and rod 20 when the former is at rest. Though slight, the sound generated within the rod 20 is of 26 an intensity sufficient to be audible to the operator. This is a 27 desirable characteristic of apparatus 10 since it provides the 28 operator with an indication that depression of the selected key 29 has initiated the encoding action.
As shown in Fig. 4, divergent sound waves 94A and 94B
31 arise .

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1 ¦ upon the striking of rod ~0 and propagate to the left and the right, respectively, alon~ the axis of rod 20 at a substantially ¦ constant velocity. The sound waves 94A and 94B each include a ¦ respective compression wave front 9CA and 96B, followed by a 5 ¦ series of expansion/compression wave cycles. Since striker 18 ¦ is initially at approxi~ately a ri~ht angle to rod 20 and is ¦ guided by a slot 7~ of comb 74 throu~hout its motion, as ex-¦ plained above, it will be at approximately a right angle to rod ¦ 20 at lmpact. As ~entioned earlier, if the blow is substan- --tially orthog~onal, the sound ~Yaves 9~, 9~ are sy~metrical and of approximately equal intensity at least in the first few cycles. ~ach sound ~Yave 94A and 94~ is a co~plex composite of multiple cycles when vie~ed over the entire duration of the sound wave. The flrst half-cycle of Wa~efront 9~A, 96~ is the clearest and least distorted, ho~ever, and this portion alone is all that is actually necessary to sense for proper operation of tne present invention, as wi~l be seen. ~ecause of the nature of acoustlc ~vaves, rod 20 ~vill 'ring" (i.e., reflected waves will be present) for a certain period of tine after it is struck, but intensity ~ill generally taper off as energy is dissipated, though interference phenomena, and vibratory interaction ~vith striker 18 (~vhich also rings) may have reinforcing or canceling effects at intervals as indicated in Fi~. 8a. Such occurrences only affect the repetition rate of the inputs to the encodin~
apparatus 10 since they are of no concern in the initial alterna-tions of the signal and circumvented by addition of circuitry ~o prevent input of ne~v data while there is the possibility that the apparatus is still exhi~iting effects of the preceding impact.
r.eferring now to Fig. 1 and also to Fig. 3 (for greater ~0 clarity), it is seen that the first transducer 22~ is located .

~/~ J/-/7 7 ~L$~7 01 at one end 98 (at right in the figures) of rod 20 and the second 02 transducer 22B is located at the other end 100. Such transducers 03 are electromechanical devices for converting sound energy in rod 04 20 into electrical energy transmitted along the previously 05 mentioned lines 108A and 108B. For purposes of this application, 06 the term sound energy is interpreted to include the 07 characteristics of sound waves 94A and 94B (see Fig. 4). The 08 transducers 22A, 22B are constructed from a durable material such 09 as a piezoelectric crystalline substance (for example, lead zirconate or barium titanate) and are commercially available in a 11 wide variety of sizes and shapes. One supplier of a satisfactory 12 transducer for this application is the Ferroxcube Corporation of 13 Saugerties, ~ew York, publisher of a booklet entitled 14 Piezoelectric Ceramics fully describing such a transducer.
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Transducers 22A, 22B are each preferably an "X" cut piezoelectric 16 disc used in the 33 mode of operation, the first mode number 17 identifying the direction of the displacement and the second mode 18 number identifying the direction of the mechanical stress or 19 strain. In particular, the numeral 3 refers to the Z direction of a right hand orthogonal crystallographic axial set X, Y, Z, as 21 more fully described in the above-mentioned Piezoelectric 22 Ceramics booklet. For later reference, it may be noted at this 23 point that transducers 22A, 22B are high impedance devices.
24 Proper functioning of associted electrical circuitry in the preferred embodimer.ts requires that the first compressions --26 that is, sound wave fronts 96A and 96B -- each be transduced into 27 a positive voltage excursion. Accordingly, each transducer 22A, 28 22B is a piezoelectric disc, metal plated on both sides for ease 29 of making solder connections, and polarized as will be described shortly. Transducer 22A has one plated side 102 ~.

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adjaeent end 98 or rod 20, and affixed to it with a strong adhesive such as ~astman 910, a 7round lead 104A bein~ solder ¦ conneeted to side 102~ The side 106 opposite to 102 is solder ~ ¦ eonnected to the output line 108~. Transducer 2~B is similarly 5 ¦ plated on both sides, with one plated side 110 of transducer 2~B
¦ adjaeent end 100 of rod 20 and a~ain afficed to it by adhesive.
Side 110 has a ground lead 104~ soldered to it. Cpposite to side 110 is slde 112 ~hich has an output line 108B soldered to ¦ it. Transducers 22A, 22B are polarized sueh that their sides 102, 110 adjacent rod 20 are ne,ative, while the respective opposite sides 106, 112 are positive. Polarization thus oriented is such that the electrical ener~ry output on line 108A or 108B
is a positive volta~e when the related transducer is compressed.
~eferring now to Fig. 4, striker 1-8 must be positioned along rod 20 sueh that con~ct point 78 is located at une~ual distances fro~ each of the transducers 2~, 22B, in order that a measurable difference may exist in the time of arrival of the sound wave 94A, ~4B sensed by the respective transducer 22A, 22B.
In the example of Fig. 4, the distance from contaet point 78 ,to~; transdueer 22B is elearly shorter than that from contact point 78 to transducer 22A (or it could be vice versa). It should be understood, therefore, that any combination of unequal distances from either transducer will satisfy the require~ents for the specifie embodiments of the present invention, discussed subsequently, the only change needed as the stri'~cer 18 approaches closer to the midpoint 114 of rod 20 being an inerease in the resolution of the aasociated time ~easurln~ deviee in lo~ie unit 24 because of decrease in elapsed time.
~pon arrival of sound ~.ave ~4B at transducer 22~ (~Yhich ~0 is closer in Fi~. 4), that sound u~ave is converted into a , IL ~3 ~
~ ~ 7 l 1 ¦ periodic electrical signal termed the "leading" signal, as ¦ previously indicated, which is fed alon~ line 108B to the electrical circuitry of lo~ic unit 24 (described subsequently), _ ¦~
the wave front 9~B in particular giving rise to an initial positive half-cycle of the electrical si~nal in view of the polarization of transducer 22B. Some time later, sound wave 94A
arrives at transducer 22A and is similarly converted into a periodic electrical si~nal termed the "following" signal, which is fed along line 108~, the wave front 9GA of sound ~ave 94~
again ~iving rise to an initial positive half-cycle of the elec-trical signal in view of the polarization of transducer 22A.
T'ecause of the unequal distances traveled-and the constant velocity of the sound waves, it is evident that a predetermined time interval exists between the first positive half-cycles of each of the two perlodic electrical signals for a given location oi impact along rod 20.
As a nu~erical example, in ~ig. 4 the distance between transduccrs 22A, 22~ may '~e postulated to be eight ilches and the contact point 7~ of strilcer 18 postulated to be located 2.1 20 inches from trancducer 22A and 5.9 inches from transducer 22B.
Further, let it be postulated that rod 20 is made of steel, in which sound travels with a velocity of approximately 0.2 inch (0.51 cm) per microsecond. Accordin~ly, 10.5 microseconds after any impact of rod ~0 by striTcer 18 at the above-specified loca-tion, the wave front 9~B of sound wave 94~ which diverges left-;ardly, is converted by transducer 22~ into a leading electricalsignal fed alon~ line 108B. 29.5 ~icroseconds after that same impact, the wave front 9~A of sound wave 94A diverging right-wardly is converted into a follo~in~ si~nal fed alon~ line lOSA.
~0 Thus, the time interval between the initial half-cycles of the ,~ V~

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1 leadin~ and follo~in~ si~nals is predetermined by the physical characteristics of the ap~aratus as 19 microseconds as lon~ as there is no chan-e in the position at uhich rod 20 is struck.
Those skilled in the art ~ill recognize that the time interval S or elapsed time (T) bet~cen the two wave ronts generated by a ~iven stril~r 18 (or 18a, of course) can be determined directly fro~ the relation T = 2 d/v where d is the distance from the striker to the ~idpoint 11~ of the rod 20 and v is the velocity of sound along the axis of rod 20. Conversely, of course, the distance d can be co~puted if the time interval is known.
Refer next to Fi~. 5, showin~ two embodiments of a multi-striker encoding apparatus, each havin~ a slightly different arran~ement of the strikers 18 alon-S rod 20. In a first embodi-ment (open circles), evenly-spaced stri~ers 18 are positioned lS symmetrically about the .midpoint 114 of rod 20. In a second embodiment where solid dots represent the strikers l~a, thcre is an almost identical sequence of equally-spaced stril;ers 18a, the exception beins that these are now positioned asymmetrically about the midpoint 114 of rod ~0.
In the first e~bodi~ent of the present invention (open circles)~ the sym~etry of the arran~ement causes the elapsed time bet~veen the first half-cycle of each si~nal to be the same for two different locations of striker 18 (mirror i~.a~es about the midpoint 114), the only difference beina the side of mid-point 114 from u~hich the rod 2~ is struck. It then becomes necessary to distin7uish bet~Yeen the t~o locations by arbitrar-ily addin~ an extra bit to one or the other of the sets of other-wise identical data (the left or Channel B half of l;eyboard 12 has been chosen herein to ha~e a 1 bit in the hi~hest order ~0 when it carries the leading si~nal) and then deterl~inin~ whether ~ .

- ~ .

01 the leading signal originated from transducer 22A or from 22B.
02 Circuitry (later described) for determining precedence as to the 03 signals from transducers 22A, 22B is provided in this first 04 embodiment. In the asymmetric arrangement of the second 05 embodiment (solid dots for strikers 18a in Fig. 5), each striker 06 18a upon impacting rod 20 produces diverging sound waves therein 07 which yield a unique time interval between the leading and 08 following output signals since no other striker 18a is at the 09 same relative location. As is evident from Fig. 5, for a given spacing between strikers 18, the use of that same spacing in the 11 asymmetric arrangement of the strikers 18a of the second 12 embodiment requires that one of the strikers 18a be closer to the 13 midpoint (or "center-line") 114 of rod 20 than either of the 14 innermost two strikers 18' located next to midpoint 114 in the symmetric arrangement of the first embodiment. As a result, 16 though the time intervals between signal~ are totally unique in 17 the second case, the resolution requirements for the time 18 measuring device increase because the magnitude of the shortest 19 time interval is decreased, as previously mentioned.
It will be recalled that the primary purpose of logic 21 unit 24 is to measure -the elapsed time between the leading and 22 following signals and then provide a code indicative thereof.
23 Another function of logic unit 24 is to determine whether the 24 input signals are valid and, if not, to eliminate the erroneous signal inputs so as to provide a code output only for signals 26 originated by depression of a keybutton 26. For the first 27 embodiment of the present invention -- that is, the one with 28 symmetric arrangement of the strikers 18 -- still another 29 function is to determine whether the leading signal was sensed by transducer 22A or by transducer 22B, i.e., whether it appeared on 31 Channel A or : .

~, , - .

.

~ ll 1 Channel B, and generate an extra bit to distinguish between otherwise identical codes. Furthermore, since the encoding apparatus must accommodate a succession of characters, loric unit 24 must be cyclical in operation. Therefore, upon arrival of the leading si~nal, the unit must be ~activated~' or put in an "GN" condition and ~ust remain in the "ON" condit~oll until after the last si~nal has ended, to indicate a "busy" state.
It should be understood as to activation of the lo~ic unit 24, that the followin~ signal may arrive and, because of the physical characteristics, in fact almost always arrires at lo~ic unit 24 during the occurrence of the leading signal. It should also be pointed out that because the duration of the followin~ si~rnal can be less than that of the leading si~nal, the followin~ signal may not always be the last to disappear. Therefore, the cycle in logic unit 24 may terminate with the disappearance of either the leadin~ or the followinc~ si~nal depending upon the dura~ion of each. The disappearance may only be a temporary fadins, as there may well be a recurrence of the si~rnals as shown in Fi~.
8a. In the preferred embodiments, a delay has therefore been provided in the logic circuitry such that when the longer lastina of the two sirnals has ended, a fixed period of quiescence will ensue before lo~ic unit 24 is returned to an "Off" condition in preparation for receivin~ additional inputs.
i~lectronic circuitry for measurin~ the elapsed time between the leadin~ and follo~vinr slgnals to renerate a code indicative thereof and for providin~r the other functions mentioned above is shown in block form in Fi~rs. 1 and 6 and schematically in Fi~. 7, with timin r dia~ra~s bein~ criven in Fi~s. 8a to 80. The structure shown is only one exa~ple of many which satisfy the ~0 requirements of each e~bodiment of the present invention. This ~ f~

1 ¦ structure ~vill next be described in reference to the just-¦ mentioned fi~ures.
~ i~. 8a illustrates the characteristics of the transduced signals presented at the outputs 108A and 10~2 of transducers S ~2A and ~ hese si~nals are not al~ays consistent in inten sity, because of the hi~h impedance nature of transducers in general. The a~plitude of the si~nal voltage depends on a number of factors which include the force with which rod 20 i ~

struck, the distance the sound waves 94A and 9~B must trave ~ and the material used for rod 20. In the embodiments of the present invention, a typical si~nal on the first positive excursion peaI~s at a minimum of 0.25 volt. The duration of th2 signals is typically of the order of two ~illiseconds, but can be ~reater than tllat ~Yhen the previously-melltioned rin~in~ ~Yi tllin the system is talcen into consideration. This duration of the si~nals is quite large relative to the time difference (rou~hly ~4 ~icro-seconds at maximum for the embodi~ent disclosed herein) in arrival of the wave fronts 96A, 96~. ~t is thus evident that the characteristics of the si~nals at outputs 1O8A~ 10~B (~ a) may not al~ays be conducive to proper functioning of the lo~ic unit 24. The signals must be such that when enterin~ the lo~ic unit ~4, each si~nal lies within a discrete ran~e of volta~e values of a desired-polarity for compatibility with the elec-tronic elements. ~ccordin~ly, the si~nal condi,ionin~ circuitry llGA, llGB has been introduced in the Channel ~ and Channel B
paths, respectively. _ In ~eneral, the si~nal conditionin~ circuitry 116A of Channel A includes a co~parator 115A provided ~ith a reference volta~e as one input and an P.C circuit as a second input. The ~0 ~C circuit shifts t}le level of the transducer output si~nals and 1/~ //7',7-~7 1 filters out possible low frequency signals from drive units such as the stepping motors now coming into such frequent use in ~
print-out devices. Signal diodes 125A, 125B to limit voltage , excursions may also be included at the second input, if 1, S necessary, but my otherwise be omitted. The output of comparator 115A in circuitry 116A connects directly to logic -____ unit 24 via a line 118A as shown in Figs. 1 and 7. The signal conditioning circuitry 116B of Channel B contains identical elements and is similarly connected via a line 118B.

Consider next, the details of modification of the output signals 94A, 94B, from transducers 22A, 22B (typical signals for , each stage being shown in Figs. 4 and 8a, 8b) in reference to the section of the circuits shown at the left in Fig. 7, and, generally identified by the heading "116A, 116B" and correspond-ing to the signal conditionin~ circuitry for Channels A and B.

As shown in Fig. 7, the positive output side of transducer 22A --that is, lead 108A -- is connected ~o the junction lL7A of a pair of series-connected, voltage-dividing resistors 120A, 121A via an isolation capacitor 122A (capacitance 250 picofarads). The resistors 120A, 121A are high precision devices (1%) of equal magnitude (lOOY ohms, say) pLaced between a source of voLtage V
and ground. Because of require~,ents of the preferred TTL, (transistor-transistor loOic) integrated circuits used in, Logic unit 24, the voLtage of source V is preferably +5 volts D.C.
Accordingly the voltage at junction L17A is substantiaLly 2.5 volts. The high precision resistors are necessary in order to ensure that differences in attenuation of the sound waves and resuLtant decr~ase in the ampLitude of the alternating output ~0 signaLs on line 108A will not be compounded by differences in the voltage offset or bias applied to the output signals. In _ ~ / ~ //~/ 7- 7 '`I ' ~ ~
-~ 7 l such cases, equal voltage for the modified signals might be . attained at significantly different portions of the wavefronts.-thus introducing undesired timing errors.
The junction 117A is connected by a lead 123i~ as an input S to the "plus" terminal of comparator 115A, while the "minus"
terminal is connected by leads 124, 12~a to a source of re~er-ence voltage, na~ely;the junc~ion 126 of series-connected, voltage-dividing resistors 127, 12~, likew;se placed between the voltage source, V, and ground. Resistors 127, 128 are also ' hi~h-precision (lCi~) resistors, but are not equal in value, the fo m er being about 10~-,'.lower than the latter (90.9Kohms vs . lO0 I~ohr"s, respectively, say) such that the voltage at junction .. 126 is approximately 5% higher than the quiescent voltage of junction 117A. The 3.C, reference voltage at junction 126 may be further stabilized by addition of a filter capacitor 129 (capacitance 0.1 microfarad, say). ~'hen the audible frequency alternating electrical signal is generated by transducer 22~ in response to sensing, ;sound wave 94A, that signal is superposed on the D.C. level existing at junction 117A and because of the comparator 115A only positive cycles having an excursion greater than 0.1 volt cause a positive pulse to appear at line 118A.
As comparators ll5A, 115B, one ~.ay use readily available commercial integrated circuit devices, such as the dual high speed comparator package supplied by ~ational Semiconductor

2~ Corp. af Sunnyvale, California and identified by the nu~.ber ~l 319. The L~l 31~ serves the purpose exceedingly well because it has two comparators in a sin~le pacXage and an uncom~itted collector in each ou~put stage allows it to be readily made compatible with TTL circuit components by the addition of a / pull up resistor (500 ohms, say' 129A connected between the . ' ' ' .

.",. .

~ -¦ output line llEA (from co~parator 115A) and the 5 volt supply source V. The adjacent capacitor 130 located between the -~ supply source V and ground is the usual -by-pass unit added to ¦ protect the package from sudden surges in supply voltage.
5 ¦ The line 118A completes Channel A by connecting the output ¦ of comparator 115A with the logic unit 24 as previously stated ¦ (see Fig. 1 or Fig. 7). The output of comparator 115A when supplied with alternating signals similar to those shown in Fi~. ~a is therefore a series of unipolar (positive) pulses, the leading edge of the first of the pulses being synchronous with the wave front 96A and having a peak value compatible with ; the components of logic uni~ 24. Identical conditioning circuitry 116~ for ChanneL B has its components identified by the same numbers except that they bear the suffix "B'l in place lS of "A". Eein~ identical they will therefore not be described -____ further herein. Typical output signals issuing from co~parator 115A (and its cou~terpart 115B) are sho~n in Fig. ~b.
~ efore considerin~ the individual ele~ents of logic unit 24 in detail, a broad overview of these will be given in reference to the blocX diagram of Fio. 6. As seen in that figure, the modified siOnals appearinO on lines ll~A, 118~ are supplied to the Channel latches 137 where they cause the setting of a related latch, the pulsating input signals thus being converted to logic levels. Simultaneously, through lines 119A, ll9B
25 tapped fro~, lines 118A, 11~ and connecting to a Cycle Ti~,e Out unit 136, the signals inhibit operation of this unit 136 until a later ti~.e. The logic levels fro~ the Channel Latches 137 appear on a respective oneof the output lines 141A, 141~, the first to appear (elther line) initiating a c~-cle of the logic ~0 unit 24 by activating aCycle Time Control unit 144, causing it ola,.~ - 24 ~ // ~ ~ 7 1 o emit signals on its output lines 145 and 148. Line 145 is connected to a Counter 147 which begins counting when it re-ceives the signal on line 145. Counting occurs at a rate de-¦ termined by pulses on a line 133, the pulses being obtained 5 ¦ from a free running source 134 of clock pulses. Line 148 ¦ from Cycle Time Control Unit 144 leads, on the other hand, to a ¦ Window Generator 153, the appearance of a signal on line 148 re-¦ sulting in the emission of a slightly delayed signal of pre-¦ determined duration on line 154 at the output of Window Gener-ator 153, the delay being sufficient to exclude the effects ofshocks or electrical interference which might give rise to substantially simultaneous signals. On the other hand the duration of this signal is sufficient to encompass time intervals corresponding to actuation of a striker 18 which is furthest from one of the transducers 22A, 22B, or, expressed another way, furthest from midpoint 114 of rod 20. Signals with a greater time separation are excluded, however.
Line 154 proceeds to Coincidence Circuitry 155 and to the "Most Significant Bit" Latch 146 (referred to herein-after as "MSB" Latch 146 for convenience). When a signal ap-pears on line 154, it enables the Coincidence Circuitry 155 and clocks Latch 146, the output being dependent on the input, as will be seen. The significance of these two events is that, in the first instance, only signals on lines 118A and 118B which have a time separation consistent with that for depression of a keybutton can cause generation of a code. In the second instance, or.ly if the leading signal is on Channel B can Latch 146 be set to indicate that a "one" bit should be included in the most significant position of the code generated. As seen ~0 in Fig. 6, the Coincidence Circuitry 155 responds to signals on lines 142A, 142B tapped into the output llnes 141A, 141B from , . ,,.

~ O - 25 - ~ ~ ~

-~ 37 1 the ~hannel latches 137 and when both are latched, i.e. defining the elapsed time up to appearance of signals.on both channels.
a level appears on line 156 to transfer the status of counter 147 at that instant into the 0utput Control 158 via counter out-S put lines 149. The status of the ~ost Significant Bit latch146 is also determined at the sa~e time, that inform.ation being like~ise transferred into Gutput Control 158 via the output line 150 from latch 146. Transfer of information into the 0ut-put Control l58 is accompanied by setting of a flaæ in 158 to 1~ alert utilization device 151 of the availability of data or "Data Good" by issuance of a signal on line 184 from 0utput Con-trol 158. The binary co~e output correspondin~ to the elapsed time is stored in 0utput Control 158 until called for by Utilization Device 151 b~ a "Read-Out" signal sent to 0utput Control 158 via a control line 185 connected to 0utput Control 158. After latchinæ of the elapsed time code, Counter 147 continues to count without further effect until it reaches a predetermined value su~ficient to allow for the full range of . norr.al elapsed ti~es for the ~iven acoustic encoding apparatus.
- 20 At that instant, it provides a signal on line 159 to serve two purposes: first,to trigger generation of 2 delay prolonging the cycLe(as a margin of safety), ~y Cycle Time-0ut Generator .
136 (with no effect so long as there is still a signal on either lines 119A or 113 inhibiting its action), second ---and more important at this point --.the purpose of the signal on line 159 is to reset the Window Generator 153. Such re--____ setting removes the enablinæ signal on line 154 leading to the Coincidence Circuitry 155, blocking any possibility of later emitting a signal on output l~ne 156 to cause transfer of a ~0 spurious binary value into the storage part of Port 158. Thus, . -., ~ .. 0 - 26 - ~ ~

:

1 nly signals on lin~s IlP.i~ and 118B which have a maximulr, time ¦ separation consistent with that for location of the striker 18 ¦ furthest from midpoint 114 of rod 20 can cause generation of ¦ a code. Line 154 also leads to the MSB latch 146, but resetting S ¦ of Window Generator 153 has no real significance with respect to ¦ that unit, since transfer of the o~tput from latch 146 this late ¦ in the c~cle is not possible in view of the just-mentioned dis-¦ abling of the Coincidence Circuitry 155. Thereafter, Counter ¦ 147 counts on as before, periodically reaching the above-10 ¦ ~ientioned predetermined value and giving another signal on line ¦ 159 to again trigger the Cycle Time-Out Generator 136, and again with no effect if a pulse originating from rod 20 is still present on either line llgA or 11,B. Finally, when pulses have disappeared from both these lines, the tri~gering signal on line lS 159 takes effect. After a predetermined miniF.um time delay subsequent to signal disappearance, a sign~l is e~itted by Cycle Time-Out Generator 136 on output line 163 connected to Reset Generator 162. The si~nal on line 1~0 triggers the Reset Generator 162, causing it to issue a "clear" pulse on its output line 164 connected as a resetting input to the Channel Latches 137 and the ~.S~ latch 146. This pulse marks the end of the c~cle. The duration of the "clear" or "~eset" pulse on line 164 is determined by the appearance of the next clock pulse on line 133A tapped to line 133 and connected as a reset input to Reset Generator 162. It maj7 be noted that Cutput Control 158 is cleared of its contents not by the above-described l'Reset"
pulse, but by another control signal from the Utilization Device 151 transmitted along the interconnection 1~5.

~laving given a broad view of the various elements of lo~ic ~-unit 24, a detailed description will now be given in reference - 27 ~ ~ // j ~ 7 1 ¦ to Fig. 7 and the timing diaOra~.s of Figs. 8a-8O. ~s drawn, ¦ the schematic of Fig. 7 is strictly applicable only to the / first embodiment of the encoding apparatus of the invention, i.e. one with a multiplicity of equally spaced strikers 18 ~disposed s~-~metrically (mirror image) about the mid-point 114 of rod 20. ~ig. 7 is actually applicable also to the second e~bodiment -- that with the equally-spaced stri~ers 18 disposed as~metrically or "offset'l with respect to the mi~point 114 of _ rod 20 -- upon mere removal of the MSB latch 146 and provision of a double frequency clock souce 134, recognizing that the -time scale would be hal~ that shown in Figs. ~i and 8k, so the count would not stop at 31, but go on to 64; and that the codes for most of the keys would be different. Because of the slightly more complex structure of the symmetrical approach, thltone will _ be described, the other being substantially identical except for the a~ove-mentioned changes which would not alter the overall description in major respect, the basic principle bein~ unchanged.
The circuitry of logic unit 24, herein described, in-cludes many well-known TT~ (transistor-transistor loOic) inte-grated circuit components which are commercially available froma number of sources, the sources of the preferred units being named in each instance. Other types of circuitry components having the same capabilities and limitations could be used. As previously described in reference to Fig. 6, Lo~ic Unit 24 in-2S cludes Channel latches 137 for storing information as to thearrival of signals on lines 118A, 118B; a Cycle Tim.e Control 144;
a Counter 147; a Source of cloc'.~ pulses 134; a Window Generator 153; a Coinci~ence Circuit lS5; a Time Out &enerator 136; a Reset Generator 162 and -- for the first embodiment only -- a "Most ~O Significant Bit" (MSB? latch 146. Unused inp~ts of the components may be assumed to be connected to appropriate voltage levels, in well-known fashion.

- 28 - ~ ~ /~ 7~7 - ` ~ ~
;~

~ ~
~ !

I '.'~ I

1 ¦ The Channel latches 137 comprise a pair of identical "set/
¦ reset" latches 138A, 138B. These latches being identicaL, only ¦ the first (138A) will be described. Latch 138A consists of a ¦ two-input OR-gatè 139A and a two-input AND-gate 140A with the S ¦ output (-3, the ~h indic~t~ng it is a suffix to the gate number o~:itte~ -for brev~ity) of each gate cross-connected with an input I of the other gate by lines 166A, 167A in a known fashion to form ;a ~emory device. Output line 118A of Channel A forms the other ¦ input (-2) of OR-gate 139A. Accordingly, when a signal appears 1-on Channel A -- thzt is, appears on line 118A -- the first positive pulse of the signal will pass thro~gh O~-gate 139A and because of the cross connection 166A it will be supplied, as above indicated, to one inpu~ (-2) of AND-gate 140A~ The other i~

input (-1) of gate 140 is connected to a line 164b and is normal-lS ly enabled since there is a high level on line 164b, it being connected to the Q output of the reset generator flip-flop 163 via the tapped connections to lines 164 and 164a. The Q output of flip-flop 163 is normally high, since the reset generator 1~2 i, is activated (flip-flop 163 put into its set state where Q is l~
low) only at the end of the c~cle, as will be seen. Thus, im-mediately upon appearance of a si~n~l on line ll~A at the first-mentioned (-1) input to OR~gate 13A, the cross-connectionjl66A
between the output of OR~gate 139A ~nd the enabled A~D-gate 140A

results in the passage of that signal through Ai~-gate 140A witn 2S a slight delay. Then, via the cross connection 167A to the other input (-2) of ~R-gate 139~, the delayed signal passes through the C~-gate 139A to repeat the circulation and esta~lish a continuous output on line l~lA regardless of the pulsating nature of the signal on line 118~.. This "Latching" of the out-~0 put of GR-gate 139A to a constant high state indicates that . ' ' '' ... - 29 - ~ //- ~ ~7~

I ~

1 ¦ logic 24 is "0.~" -- that a cycle has begun -- and is shown in ¦ Fig. 8c, The Channel L~tches 137 may be implemented by ap-¦ propriate interconnection of A~-gates and OR-gates from the ¦ sets of four in the respective integrated circuit packages of 5 ¦ the 74 series ~anufactured by Texas Instruments Inc., Dallas, ¦ Texas, and identified as 7408 and 7~32. ` -The outpu~ (-3) of CR-gate 139A goes to the Cycle~ Tire ¦ Control 144 via line 141A and to the Coincidence Circuitry 155 ¦ via line 142A tapped ~o line 141A. As seen in Fig. 7, line 142A is, however, just one input (-1) to a two-input AND-gate 160~ having its output (-3) connected to the cLock input C of a flip-flop 170 via line 171. At this time, assuming that the signal on Channel A is the leadinO signal, no signal should be :
/ present on the other input ~-2) of gate 168 which is connected lS to a similar line 142B fro~. Channel B. In such case, there is no effect on the Coincidence Circuitr~ 155. As to the Cycle Ti~e Control 144, it is seen to contain a two-input OR-gate 172 having line 141A as one input (-1). .Accordingly, when the out-put (-3) from latch 13~; goes high, that level passes through O~-gate 172 and appears on a li-ne 173 between the output (-3) of OR-gate 172 and an inverter 174 connected in turn to the out-` _ put line 145 of Cycle Time Control 14~. Line 173 is also con-nected to the l~indow Generator 153, discussed ne~t, by a line 1~8. . _ ~s previously mentioned, th_ function of the "windows"

~enerated by circuit 153 is to deter~,ine whether a "following::
signal appearing at logic unit 24 is valid -- that is, "follow-inO" signals ~hich are too early or too late in terms of the window are invalid and must be prevented from erroneously ~0 generating a code output. The ~Jir.dow Circu}t 153 co~.prises a _ 30 - ~ ~ // / ~37 I ~

~~~~~ 1 ¦ flip-flop (or "latch") 157. ~.11 flip-flops shown herein are ¦ TTL circuits of the D type which have preset, data and clear ¦ (or "reset") inputs, while the outpu~ Q and Q (the latter in-¦ versely of course) reflect the status of the Data input D
S ¦ upon tri~gering of the clock input C by the positive-going ¦ edge of a pulse or a change to a high level, With one exception ¦ discussed subsequently, the preset is not used. Referrin~ still ¦ again to Fig. 7, it is seen that the line 148 tapped to the line ¦ 173 at the output (-33 of C~-gate 172 is connected to the input C of flip-flop 157. ~ccordingly, when the first positive pulse of the leading signal appears on line 118~ (or line 11i9A, as the case may be) and passes through OR-gates 139A and 172, the positive-goin~ ed~e of the resultant step to a hi~h level at the OUtp-lt (-3) of OR-~ate 172 causes triggering of the clock input of flip-flop 157 via line 148, the status of the input D

then being transferred to the output Q of that flip-flop. As seen in Fig. 7, the input D of flip-flop 157 is clamped at a , high level by being connected to the source of voltage V. Ac-cordingly, whenever its clocX input C is triggered, flip-flop 157 will be "set" and the level at the output Q will go high.

This high l~vel, which appears subsequent to the c~-cle initi-ation ti~e because of several ~ate dela~s as shown in Fig. 8 d , is presented via lead 154 to the input D of flip-flop 170 and to the clock input C of I~E latch 146 discussed subsequently.
Returning now to consideration of the high level through OR-gate 1J2 to inverter 174 and line 145, the effect of the change of state on line 141.~ is that the level on line 145, previously hi,h because of the inversion of the low on line 173, ~0 conversely now ~oes fro~ hi~h to low. Line 145 -- it will be recalled -- is connected to the Counter 147. This counter is an 8 stage binary counter of which the first two stages are used

3~ >o~///7-~7 I ~

l ¦ for purposes of resolution. Counter 147 is preferably imple-mented with a dual 4-bit binary counter, an integrated circuit package of the 74 series identified as S~ 74393 and manufactured l by TeYas Instruments Inc. 7 Dallas, Te~as. This integrated 5 ¦ circuit uses positive logic and has individual clear inputs for ¦ each of the 4-bit binary counters to~ether with individual clock inputs trig~ering when the cloc~ pulse goes low. As seen in Flg.
7, line 145 is connected to pins 1~7-2 and 1~+7-12 (dash numbers ¦ bein~ the above-na~ed manufacturer's pin numbers) which are the "clear" inputs in the SN 74393 package. Accordingly, when the level on line 145 goes low at the time when latch 138A is set, clamping of the Counter 147 to zero output is released. As a result, the clock pulses on line 133 from the clock source 134 (implemen~ed as a well-known free runnin~ crystal oscillator having a square wave output at a 2.0 megaherz frequency) take effect in view of the connection of line 133 to pin 147-li the clock input to the low order 4-bit counter in the SN 74393 package. The size of the counter and the clock rate are inter-related and are determined, in the embodiments disclosed herein, by the fact that the encoding apparatus 10 is intended for use wi~h a t~-pewriter ke~!board 12 having at least 56 keys 26 in / staggered rows and operating stri~ers 18 spaced abcut 0.2 inch (0.51cm) apart. Consequentl~, the innermost strikers 18 of the syr,metrical embodirents are located at 0.1 inch (0.25 cm) 2S to each side of midpoint 11~. In an asyrmetric arran~er,ent, with the same spacin~ between strikers 18a, the closest to the midpoint 114 would be located at half ~hat distance from it -namely, 0.05 inch (0.13 cm). Eased on information ~iven earlier for the steel rod of the embodîments,the 0.2 inch spacin~ corre-sponds to elapsed times separated by 2 microseconds, the short-est elapsed time - i.e. the earliest arrival time for the - 32 ~

I ~ ,r~
I .
1 ¦ following signal being at 1 microsecond for the symmetrical ____ ¦ embodiment and at 1/2 microsecond for the asymmetric arrange-ment. For proper resolution, the clock period should be at least half the shortest elapsed time, or 1/2 microsecond for the symmetrical embodiment and 1/4 microsecond for the asymmetric embodiment. Accordingly, the fre~uency of the clock pulses should be 2.0 Megaherz for the symmetric embodiment as shown in Figs. 7 and 8h, 8i. It should be noted that the values given for spacing, frequency, sound velocity, etc. are rounded numbers for simplifying the discussion and thus differing some-what from the values to be used in actual design. It may benoted from Figs. 5 and 8j that the spacing of the strikers 18 in relation to the counting activity of counter 14i -i- including the preliminary stages not shown -- is such that the transitions of the counts appearing on the latter are offset from the arrival times of the following signals to avoid potential race conditions here.
As mentioned above and as is more evident from the timing diagram, Figs. 8h-8i, it is only at the time of the fourth pulse frorn clock source 134 that there will be appearance of an output .-on the least significant bit output line 149-1, which is connec-ted to pin 147-5, actually the third stage of the low order binary counter. Further, the output of the fourth stage of that internal counter is used as the clock source for the high order binary counter, as evidenced by connection of the pin 147-6 to pin 147-13 via line 175, the last mentioned pin of the SN 74393 package being the clock input to the four higher orders of the combined 8 bit counter. Accordingly, the counter will ~0 change state every two microseconds as shown in Fig. 8i, there being appropriate changes on the output lines 149-1, 14 9-2 r . . .

. .. ~ ~ Z7,7 1 49-16, the dashed suffixes indicating the binary weight of the ¦ particular data line 14~. The bits of information on the lines are continuously available to the Output Control 158 for cap~ure, ¦ though intermittently varying as the counter operation progresses.
S ¦ In the meantime, the following signal should arrive on the other channel -- t;lat is, on line ll~B if the leading signal appeared on line ll~A, and vice versa. For purposes of the ¦ present discussion, which began with the appearance of a signal on line 118A, then the following signal must appear on line 118B, the first positive pulse thereof setting the latch 13~A and thus causing the presence o a high level on line 141B and also on line 142B t~pped therefrom. This high level too passes through O~-gate 172 of the CycLe Timer Control 144, but produces no change as it merely duplicates the conditions established earlier on line 141A at the other input (-1) of OR-gate 172. Presence of the high level on line 142B, however, causes a corresponding high level output on line 171 of previously-mentioned A~lD-gate 168 of Coincidence Circuit 155, because there is now a high level on both inputs (-1 and -2) of that A.lD-gate~ The appearance of a high level on line 171 clocks flip-flop 170 of Coincidence Circuit 155 and transfers'the state of the D input thereof to its output (-3). It will be recalled that the leading signal / set the output of Window Generator 153 to a high level such 2S that via line 154 the D input of flip flop 170 is high, then the high level appearing on line 171 (which interconnects the output of Ar~ gate 16~ with the clock or C input of flip flop 170) upon arrival of the first positive pulse of the following signal, _ causes the immediate setting of flip flop 170. As a result, the level on the Q output of flip flo~ 170 which is connected to a ~0 . .
. -.

-3~ 7~7 , ~ ?7 , ' 1 line 156, goes low. Line 156 serves as one input (-2) of a ~wo-input AND-gate 178, which forms part of the Output Control 158.
AND-gate 178 is connected to a strobe input of a 6-bit data ~tch or preferably an Input/Cutput Port 180. This last is 5 preferably i~,plemented by the int-egrated circuit package identi-fied by model number 8212 and manufactured by the Intel Corp. of Santa Clara, Calif. which is an 8-bit latch with tri-state output buffers along with control and device selection logic as well as a service request flip-flop for the generation and control of ' interrupts to the utilizat~on device 151. A ~ gate 178 has its output connected via a line 182 to pin 1~0-11 of the Input/Output Port 180. Pin 180-11 is the strobe input of the Input/Output Port 1~0. The known operation of this Input/Output Port 180 is such that placing a low level on the pin 180-11 clocks the infor-mation on the input lines 149-1 to 14~-16 into internal data latches (not shown in Fig. 7), thus capturing the value then existing in Counter 147. The output of the ,`~SB (most significant ., bit) latch 146 of the first e~.bQdiment is also captured at the same ti~e. Thè~internall~ atched data are not available on lines,25-1 to 25-32 at this time because of the high impedance state of the buffers. Latching of the information is accompa-nied by the setting of the above-mentioned service request flip-flop (not shown in Fig. 7) as a flag to indicate that data are now available. An inverted signal fro~ the output of that flip-flop on line 184 is sent to the utilization device 151 as an indi-cation that data are available or "good". Then, when the utili- .
ation device is ready for the da~a,it sends a readout instruc-tion via a line 185 which selects the Input/Output Port 180 for trznsfer of the information from its internal latches to the six ~0 ~Y~ _35_ 9/~ //-/ 7_,7 7 1 ~ 7 I . : ' 1 ¦ buss lines 25-1 to 25-32, the signal on line 185 gating inter-nal buffers of the Input/Output Port 180 to a high Gr a low as required (the buffers also not heing shown in Fig. 7).
¦ The readout instruction also clears the flag in the service re-5 ¦ quest flip-flop tagain not shown). It may be noted that the lines 184, 185 form part of the inter-communication path between _ I Utilization Device 151 and Output Control 158, as was shown in ¦ Fig- 6-¦ An interactive communication path is not a necessary ele-10 ment of the invention because if the utilization device were a display unit, for instance, the data from lines 149-1 to 149-16 and line 150 would merely need to be latched and output directly to the display device from that instant on. That is to say, there would be no need for any buffering, nor for intercommuni-15 cation of control information.
The time interval between the leading and following signals having been determined and the appropriate count transmitted either directly to the utilization device or to a storage unit ;
to be held until requested by the utilization device, the basic 20 function of the encoding apparatus will have been achieved. It r is however necessary to perform several other functions--namely, / to determine the end of the cycle and to reset the various memory elements in preparation for reception of the next input signal. As mentioned earlier, the elapsed time varies consider-25 ably depending upon the location of the particular striker 18 actuated in response to depression of a related keybutton 26.
Accordingly, the duration of the signal from Window Generator 153 must be such as to accomodate time intervals corresponding to strikers 18 which are at the greatest distance from the ~
~0 midpoint 114 of rod 20~ In the embodiment shown, the maximum elapsed time as seen from Fig. 8k is somewhat less than 64 microseconds allowing for _ 3 6 ~

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:

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1 ¦ tolerance in the system. Accordingly when the signal appears on pin 147-8 of the 8-bit binary counter 147 (an output on this pin having true binary weight of 128) it occurs 64 microseconds after the start of counting by Counter 147 remembering that the S clock rate is 2 megaherz (0.5 microsecond period). Then via lines 159, 159A it proceeds to the Window Gen~rator 153. There, line 159A connects through an inverter 186 to the reset input o~
flip-flop 157, forming part of the Window Generator 153. The reset input of this flip-flop ~ecomes active upon a low input as stated previously and as indicated by the small circle implying inversion, in customary fashion for the 7474 type of flip-flop.
Accordingly, the presence of a high level on line 159A causes a low level at the output of inverter 186, which resets flip-flop 157 via line 187. The resetting of flip-flop 157 puts a low .
15 level on its output Q and therefore via lines 154 and 154a to the clock input C of flip-flop 146 and the data input D of flip-flop 170. There is no effect with respect to flip-flop 146 because the clock action is not sensitive to a negative-going signal i.e.
the return from-a high level ~o a low level does nothing. As to the flip-flop 170, however, closing of the window from generator 153 means that if that flip-flop were now clocked, the low level on line 154A connected to the input D would transfer a zero to the Q output (not shown) and conversely place the output Q at a "1", causing it to remain at a high level. Thus it would 2S no longer be possible to pass a signal via line 156, gate 178 and line 182 to the strobe lnput (-11) of the Input/Output Port 180. In other words, any signal on line 171 indicating that there was now a high level on both inputs to AND-gate 168 could not cause the latching of the current counter output on ~0 .

... - 37 - ~

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1 ¦ lines 149-1 to 14g-16 and line 150 in the Input/Output Port 180, ¦ the coincidence of the signals having come too late to be a valid, ¦ key-originated signal. The closin~ of the window does nothing else to the system, Counter 147 continuing to respond to the clock pulses on line 133. It should be noted, however, that the output on line 147-8 which was applied to lines 159 and l59A also went via line L5g to a counter 190, hereinafter referred to as _ the "Time-Out Counter", which is part of the Time-Out Generator 136. Counter 1~0 is an 8-bit binary counter identical to Counter 147, l.e. preferably an integrated circuit device equivalent to _ S~ 74393. Line 159 is connected to pin lg0-1 which is the clock input to the low order 4-bit counter of the combined -bit unit. , The clock will attempt to increase the count in Time-Out Counter _ 1~0 by one. However, it will be noted that the pins 1~0-2 and lS 190-12 (which are the reset inputs of counter 190) are connected via a line 191 to the output (-3) of a two-input OR-~ate 192 which has the lines ll9A and ll9B connected to a respective one of the two inputs. As rientioned earlier, the two lines 119A and 119B are tapped to the Channel A and Channel B input lines 118A, 118B to logic unit 24. Accordingly, as long as there is a pulse on either of these lines, that pulse will pass through O~-gate 1~2 and via line 191 will put a clear signal on pins 190-2 and 190-12 (the reset inputs of Counter 190) and thus pre-vent any countin~ b~ Time-Out Counter 190. Eventually, however, as seen in ~igs. 8a and Sb there will no longer be any output from transducers 22A, 22E to give rise to pulses on line 118A or 118B with the result that the next time that counter 147 achieves an output on lines 147-8, that output will again be transmitted via line 159 to the clock input 159-1 wi~ the result that Time-Out Counter 190 will then increase its count by 1. This output .. ~ -38~

~ . '-':
1 on line 147-8 will recur periodically as counter 147 continues its cycling. Eventually, clocking of signals into the Time-Out Counter 190 will cause an output to appear on its pin 190-10 corresponding to a binary 16. This differs from the weight as-S ~signed to that pin in Counter 147, because the substages of Time-Out Counter 190 are given full weight in calculating the value of the stage having its output at pln l90-10. The binary value :
of 16 for the signal appearing on line 160 corresponds to that many complete cyclings of Counter 147 after disappearance of , the last pulse on either of the two lines ll9A, ll9B. Thus, the signal on line 160, which is the reset signal, as explained .x below, has been delayed about 2 milliseconds in view of the fact that each cycle of Counter 147 takes about 128 microseconds r when clocked by a 2 Megaherz pulse train such as that from clock lS source 134. The 2 milliseconds of delay after disappearance of the last pulse on either the two lines ll9A, ll9B, is an arbi-trary value and can be adjusted to suit the requirements of a particular system by connection of thç line 160 to an output pin of Counter 190 having the necessary binary value (other output pins not shown, but identical to the pins shown for Counter 147~.

Reset Generator 162 is provided to generate a "clear"
pulse, shown in Fig. 8O, for ending the cycle of logic unit 24.
The primary function of the clear pulse is to reset the channel latches 138A and 138B to put logic unit 24 in the ready condition ~or the next key depression. Reset Generator 162 comprises a D
type flip-flop 163 of the kind previously described - namely, a 7474 manufactured by the Texas Instruments Company. The line 160 from the pin 190-11 of the Time-Out Counter 190 connects with the clock input C of flip-flop 163 which has an output Q feeding ~0 back via line 164 to the data input D of flip-flop 163. Because . . .
.

. - 39 - ~ ~7/
. ~

? 0 1 there is a norrnally high level on line 164, as previously ~r.en- -tioned in connection with the enablin~, of the Channel Latches 137, the step change in level on line 160 from low to high will trig-ger transfer of the hi~h level present on the input D of flip- ` _ 5 flop 163, causing the setting of this flip-flop which is accorn-. panied by a change of the Q output to a low level as a ne~ative- , logic reset signal. _ The duration of the reset signal is controlled by the clock source 134 inasmuch as line L33 has a line 133A tapped to it which connects through an inverter 132 to a line 135 leading to neg~tive-logic reset input R of ~lip-flop 163. Accordingly, after the flip-flop L63 has ~een set by the signal on the line 160, it will be reset by the positive-coing edge of the next .
cloc'~c pulse to appear on line 133A, the inverter 132 changing the .;
15 reset logic from negative to positive as is evident. Because the Counter 147 is ti~red by a negative-Ooing portion of the clock pulses on line 133 and there are propagation delays in transr~,itting the count inforTnation from Counter 147 to counter 190, the duration of the output pulse is of the order of less 20 than one-half of a clock period, i.e. less than one-~uarter microsecond, but.this has been found sufficient to assure effec-tiveness of che clear pulse fed along lines 164a and 164b to AND-gates 140A and 140B of the Channel latches 138A and 138B.
The low level applied at inputs 140A-1 and 140B-l of the Ai~D-2S gates disables the A~ ;ates, interrupting the recircuiating siOnals from the 02-gates 139~. and L3B thro;lOh the respective .
cross-connections 166A and 166B. The interruption.places a low level on lines 141A and 141~. an indication that the Channel latches are reset and that the logic CJ C1e of unit 24 is com-. .

A J .~O~ ~ 77 ~ 7 ~

1 ¦plete. The low level on lines 141A and 141B in turn puts a low ¦ level on line 173 at the output of OR-gate 172, this low level ¦being changed by inverter 174 to a high level which resets ¦Counter 147 through line 145 to pins 147-2 and 147-12. The S clear pulse on line 164a resets the MSB latch 146 via its nega-ti~e-logic reset input R. Time-Out Counter 190 is not reset at 1 this time but maintains its count, it may be noted from Fig. 8n, 1~ ~
until the appearance of the next signals on lines ll9A and ll9B , ~ ;
which will pass through OR-gate 192 and, via line 191 to pins ,, 1~ 190-2 and 190-12, will then reset the Time-Out Counter 190 and continue to do so periodically, as previously described, as long as the signal trains are present. The Coincidence Circuit latch 170 is not reset ~y the clear pulse, but rather by the readout signal appearing on line 185 from the Utilization Device 151.
The readout signal is a negative-logic signal fed to negative-logic reset input R of flip-flop 170 via line 185a which is tapped to line 185. The reason for this late resetting of flip-flop 170 is that premature resetting would remove the low level on line 156 at the input 178-2 to AND-gate 178 which caused the latching of the elapsed time data in the Input/Output Port 180 and thus might permit garbling of that information prior to receipt of the readout signal on line 185. Furthermore, because of this resetting action by the readout signal, a line 185b tapped to line 185a is provided as a second input to AND-gate 178 such that during the presence of the readout signal on line 185, the output of AND-gate 178 on line 182 is held low even though flip-flop 170 has been reset and the signal on line 156 has gone high as a result of the low level on line 185A connected to _ the reset input R of flip-flop 170. The signal on readout line ~0 . ',' 1.
. ,, .

1 - 41 - V ~ //~/~ ~ ~
.

-~ `~7 l ¦ 185 will simiLarl~ reset the internal latch in the Input/
¦ Output Port 1~0 which has been transmitting a negative-logic ¦ "data good" (DG) signal on line lQ4 to the Utilization Device ¦ 151. Las~ly,it will be seen that a negative_logic signal RS on S ¦ line 1~ is provided to the reset input R of the Input/Output .
¦ Port 1~0 and to a present input P of fLip-flop 163 via a line ¦ 18~A ta~ped to line 1~. These inputs along lines 1~, 188a ¦ are used for initializing the system condition when power is turned on. ~fter all the flip-flops have been reset, the ap-paratus 10 is ready for ti~ing .~,he next inputs received alongchannels P~ an& B. .
. The ..SB latch l~i~ provides a data bit for the final data to distinguish whe~her the leading signal arrived on channel A or channel B. r~eferring to Fig. 4, strikers 18 are positioned sy~.~ .
:. lS metrically about the midpoint 114 of rod 20 and are equally : spaced. Therefore, the two signal trains generated by a striker 18 positioned on one side OL midpoint 114 will have the same ; elapsed time interval between their first ~ositive half-cycles . as will the two si~nal trains generated by the striX.er 1~ at an eq~al distance from ~idpoint ll~ ut located on the opposite side.
It beco~es necessary in the first em~odiment to assign the sixth binary bit arbitrarily to one side or the other of the keyboard 12. For purposes of this disclosure, as ~.entioned previously, the left side or Channel ~ has been chosen. It is now necessary to deterr..ine whether the leading signal originated on the right or the left side of the rod 20. ~eferring to Fig. 7, it is seen that l~;SE latch 146 is a D type flip-flop with a data input D, a cloc~l.input C, a negative-logic reset input R and an output Q.

'~0 . . .

D~ - ~ 2~ //./7 ~

-~ 3~
1 Flip-flop L46 is a TTL circuit of the D type which triggers on ¦ the positi~e-going edge of the clock pulse to transfer the ¦ data from input D to the output Q. Because of a potential race ¦ condition, the unit sui~able here is a higher speed version of S the flip-flop previousl~- described, manufactured by Te~2s Instru-ments and identified as a ~lodel 74~1,74, the first digit pair in-dicating that the device is also a member of the 7~ series and the letter H indicating that it is a :-.igh-speed unit. The re-sponse time for this flip-flop is onl~ 15 nanoseconds as com-pared to the 20 ~Janoseconds of response ti~e for the units suit-able for the other l~tches. The higher speed unit is necessary for ~ reason which will beco~.e evident. The data input D of flip-flop 146 is connected to the output line 141~ from the Channel B latch 143B through a line 143~ tapped to line 1412.
lS The clock input C of flip-flop 146 is tied to the line 15~ con-necting with the output Q of the Window Generator flip-fLop 157.
The output Q is initialLy at a low level, but ~oes high when active;, i.e. ~hen flip-flop 157 is "set". The setting occurs whenever an input fnom either channel A or channel ~ has ini-tiated a cycle of the lo~ic unit and therefore the l!i..dow Ger.-erator flip-flop 157 has becn set through line 1~,~ from C~ ate 17~, as previousl~ ~escribed. T~e change to a high le~el on -____ line 154 connected to the clock input C of flip-flop L45 trig-2~ gers the transfer of the status of its dat~ input D to output Q.
As seen in Fig. 8d. the window signal 154 goes high a little bit later than the original signal on line 141B shown in Figure 8c because of gate delays. Even so, because the same signaL gives rise to both the data input e.nd the clock inpu~ to flip-flop 146, even with the ga~e delays the response of the data input is ~ar-~0 .

_43~ 77 `7 01 ginal when the circumstances favor the high end of the tolerance 02 range. Accordingly, it is desirable to use a faster device for 03 flip-flop 146 than is used for flip-flop 157. If then, the 04 leading signal appears along channel B, it sets the latch 138B, 05 placing a high level on line 141B. That high level passes 06 through OR-ga~e 172 and line 148 to set flip-flop 157 and, in 07 view of the fast response, assuredly places a high level on the 08 data input D of flip-flop 146 via line 143B such that the setting 09 of flip-flop 157 clocks a high level to the output Q of flip-flop 146 and to the Input-Output Port 180 via line 150. There it is 11 latched when the subsequent arrival of the signal on line 118A
12 causes setting of the Coincidence Circuit flip-flop 170, with 13 resultant transfer of the counter outputs on lines 149-1 to 14 149-16 and the value on line 150 to the data latches of Input/Output Port 180. A high level on line 150 indicates that 16 the leading signal appeared on channel B--that is, the striker 18 17 triggered from keyboard 12 was one situated to the left of the 18 midpoint 114 of rod 20. Conversely, if the leading signal is on 19 channel A, the low level on the data input D of flip-flop 146 when line 154 goes high to clock the transer of the D input 21 status, places a low level on the output Q but this does not 22 signify a change since flip-flop 146 is initially in the reset 23 state. The output Q of flip-flop 146 then remains at a low level 24 as shown in Fig. 8f to indicate that the leading signal was along channel A and that the sixth bit should be a zero, the count thus 26 being 31 or less.
27 The foregoing description of an encoding apparatus 28 comprises a rod 20, one or more strikers 18 (or 18a) arranged 29 symmetrically (or asymmetrically) about the midpoint 114 of rod 20, piezoelec-, .

, . -- . -:
.

.

,~

. l,,, I 1.
1 ¦ tric transducers 22A, 22B affixed to respective ends 98, 100 of ¦ rod 20 and effective to convert into electrical signals any ¦ sound waves propogated in rod 20 upon impact by striker 18 (or ¦ 18a). The electrical signals are separated into a leading and S ¦ a following signal and fed to a logic unit 24 which includes a ¦ binary Counter 147 driven by a free-running clock source 134.
The leading signal starts Counter 147, the counter output appearing in binary code form on five (or six) lines 149-1 to 149-16 (or 149-32 in the asymmetric case), and the output on a further line 150 supplying a higher order bit of binary weight 32 (as required in the symmetric case). The code on these lines is transferred into the temporary storage of an Output Control 158 upon arrival of the following signals. The stored code in Output Control 158 may be supplied io a Utilization 15 Device 151 immediately or upon demand. The strikers 18 may be operatively connected to the key mechanisms 14 of a keyboard 12.
The present invention may be embodied in other specific;

forms without departing from the spirit or essential character-istics thereof. In particular, as will be evident to those skilled in the art, the single striker shown in Fig. 4 could be movable to any of the positions shown in Fig. 5 (either embodi-ment) and actuated there to achieve the desired code output.

Likewise, the one overall "window" signal of Fig. 8d could be 2S replaced with a series of short windows, each encompassing a predetermined elapsed time. Furthermore, while Fig. 4 implies the use of longitudinal waves, it will be clear to those skilled in the art that torsional waves,transverse (or shear~ waves, surface wavesj etc., solely or in combination could also be used.
~0 ~ ' ~, ' ... - 45 - ~ ~ 7 -~

1 ¦ Moreover, it will also be clear that just one transducer 22 ¦ located at one end of the rod 20 and forming the leading ¦ and following signals by picking up direct and reflected waves could be used but would require a more sophisticated and S ¦ expensive system. Also, while the bit added to distinguish ¦ between the two sets of identical codes for the symmetrical arrangement has been shown as a "most significant" bit, it will likewise be clear that the distinguishing information could be located in any order of the output including the least significant and could even comprise more than one bit, if desirable.
The presently disclosed embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended lS claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.

'! ' - ~ .

- 46 - ~ /~/7~~
o~

Claims (27)

WHAT IS CLAIMED IS:

1. An apparatus for generating a code representative of a mechanical motion comprising:
a member for transmitting vibratory energy;
means for inducing vibratory energy within said member in response to said mechanical motion, the vibratory energy forming separate wave fronts travelling in diverging directions;
means operatively connected to said member for transducing said wave fronts into signals with an elapsed time therebetween; and means connected to said transducing means to generate from said elapsed time an output representative of the mechanical motion.

2. The apparatus as defined in claim 1 wherein said signals are a leading signal transduced from a first arriving wave front and a following signal transduced from a second arriving wave front.

3. The apparatus as defined in claim 2 wherein said member is an elongated member.

4. The apparatus as defined in claim 3 wherein said elongated member is a cylindrical rod.

5. The apparatus as defined in claim 4 wherein said cylindrical rod is made of metal.

6. The apparatus as defined in claim 3, wherein said inducing means is operable at a plurality of positions along said elongated member, there being a discrete elapsed time for each position.

7. The apparatus as defined in claim 6, wherein said elongated member has a midpoint, and said plurality of positions are spaced in lateral symmetry about the midpoint.

8. The apparatus as defined in claim 7 further including a pair of transducers equally spaced from said midpoint.

9. The apparatus as defined in claim 7 wherein said output is in code form and said transducers are at the ends of said elongated member and further including means responsive to one of said pair of transducers and effective to provide different codes for symmetrical positions which give rise to identical elapsed times.

10. The apparatus as defined in claim 1 wherein said transducing means includes a pair of transducers operatively connected to said member at unequal distances from said inducing means.

11. The apparatus as defined in claim 10 wherein said transducers are of a piezoelectric material.

12. The apparatus as defined in claim 1 wherein said means to generate an output includes an electronic timing device.

13. The apparatus of claim 12, wherein said electronic timing device comprises a counter with code-form output, a clock source for operating the counter at a predetermined rate, means initiating counting by the counter at the predetermined rate in response to a leading signal transduced from the first arriving wave front and means operatively connected to the counter and effective to capture the then existing code-form output of said counter in response to the following signal transduced from the second arriving wave front.

14. The apparatus as defined in claim 1 together with a depressible key, said mechanical motion arising upon a depression of the key and the said output being a code representative of said depression of the key.

15. The apparatus as defined in claim 3 wherein said inducing means includes a striker for impacting said elongated member.

16. The apparatus as defined in claim 15, wherein said striker impacting said elongated member produces an audible vibration within said member.

17. The apparatus as defined in claim 15, wherein said striker includes a resilient elongated wire rigidly supported at one end and having a free end striking said elongated member in response to deflection and release of said free end.

18. The apparatus as defined in claim 14 wherein said inducing means is a flexible steel spring mounted for move-ment from a relaxed first position to a flexed second position and return toward said first position for striking said elongated member in response to said key depression.

19. The apparatus as defined in claim 18 wherein said inducing means includes means for guiding said movement of the steel spring.

20. In a keyboard having at least two keybuttons, a device for providing a signal representative of the keybutton which is activated, which device comprises:
a member for transmitting vibratory energy;
means activated by said keybuttons for imparting vibratory energy to said member at a different location for each keybutton;
means for detecting said transmitted energy at two spaced apart locations and having the outputs thereof coupled to means for providing a signal representative of the difference in time of arrival of said transmitted vibratory energy at said detection means, whereby a unique signal is obtained for each keybutton activated.

21. An apparatus for a keyboard having at least two depressible keys, the apparatus operable to generate a unique code representative of each key, comprising:
an elongated member for transmitting acoustic energy;
a striker corresponding to each said key and spaced along said elongated member for impacting said member and inducing acoustic energy therein, each said striker being operable in response to depression of the corresponding key and the induced acoustic energy forming separate wave fronts travelling in diverging directions;
means operatively connected to said elongated member for transducing said wave fronts into a leading and following signal with an elapsed time therebetween; and means connected to said transducing means to generate therefrom said unique code representative of each key.

22. The apparatus as defined in claim 21 wherein said transducing means includes a pair of transducers operatively connected to said elongated member at spaced apart locations and said striker corresponding to each key having a different location along said elongated member with unequal distances from said pair of transducers.

23. The apparatus as defined in claim 22 wherein said strikers are spaced about a midpoint of said elongated member.

24. The apparatus as defined in claim 23 wherein said strikers are paired symmetrically about said midpoint whereby equal elapsed times occur for each symmetric pair, and further including means responsive to production of said leading signal by a discrete one of said pair of transducers and effective to provide a unique code.

25. A method for generating a code representative of mechanical motion which comprises the steps of:
providing a mechanical motion;
inducing vibratory energy within a member in response to the mechanical motion, said vibratory energy forming separate wave fronts travelling in diverging directions;
transducing said wave fronts into a leading and following signal with an elapsed time therebetween; and generating said representative code from said elapsed time.

26. The method of claim 25, further including the steps of:
providing a depressible key, and generating said mechanical motion upon depression of the key.

27. The method of claim 25, further including the steps of:
providing a counter with a code-form output, initiating counting in response to the leading signal, and capturing the count in said counter output in response to the following signal.