CA1108241A - Heart beat rate monitor - Google Patents

Abstract

HEART BEAT RATE MONITOR

ABSTRACT OF THE DISCLOSURE
A heart beat rate monitor is provided with memory means for storing upper and lower limits of a range of heart beat rates. The limits are transmitted to and stored in the memory means from an external source. The monitor wearer's heart beat is sensed and whenever the sensed beat rate is outside the range defined by the limits an out-of-range indica-tion is provided to the wearer. The memory means are powered so as not to be affected by the depletion or the main battery which is the primary source of power for the monitor circuitry.
In some embodiments, the limits received from the external unit are transmitted thereto for verification purposes. In some embodiments the actual sensed heart beat rate and/or the stored limits are displayable to the wearer upon request.

Description

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BAC:~CGROU~D OF T~IE INVEN'rION
1. Field of the Invention:
The present invention generally relates to a pulse rate monitor and, more particularly, l:o a device for monitoring the rate of human heart beating and for providing an indication when the heart beats at a rate which is outside a rate range, defined by limits, which are programmable into the device from an external source.

2. Description of the Prior Art:
As is appreciated, during each systolic heart beat the heart contracts, forcing blood through the arteries, in the course of which the arteries expandO q~is expansion can be sensed either manually or by means o~ sensing devices at various points in the body. Typically~ it is sensea at the wrist, or at the carotid artery at the nec~ Various devices have been proposed in the prior art to measure or monitor ~le human body heart beat rate, which is gen~rall~ expressed in terms of beats ox pulses per minute.
In the devices, proposed to measure the heart beat xate~ various means have been proposed to au~omatically sense the heart beats by sensing the expanding arteries. These mean~
include pressure transducers, photoelectric devices, mechanical diaphragms and the like. The sensed heart ~eats are typically converted into corresponding electrical pulses whose rate is monitored. Some presently known heart beat monitors provide an indication whenever ~he heart beat rate is outsi~e a rate ~efined by high and low rate limits, which are manually set in the : monitor.
The use o a heart beat monitor, capable of providing 30 an indication when the heart beat rate exceeds and/or falls below sele~ted rate limits is particularly important for a f~ :~

patient having questionable cardiac conditions, e.g., a patient with a cardiac stimulator~ By presetting the heart beat monitor with high and low rate limits, chosen to be above and below the patien~'s pacemakex pulse rate, or ~he patient'~ normal pulse rate, the heart bea-t monitor can be ~sed to indicate pace-maker failure or excessive pulse rate above a normal rate.
The heart beat monitor, particularly one with a preset upper limit can be used very effectively or post hea~
at~ack patients. ~enerallv, doctors advise such patients to exercise in order to strengthen their heart muscles. However, when exercising i~ is most important -that the weaken~d heart muscles not ~e overtaxed. This can be achi~ved by first se~ti~g the high or upper limit in the heart beat monitor to a selected relatively lcw level, and permit the patient to firs~
exercise until his heart beat rate reaches the set limit. Then y as the patient's condition improves the upper limit may be raised. Since practically all post heart attack patients are under a doctor's care, it is of primary importance to enable the doctor, rather than the patient, to establish the limits 20 in the heart beat monitor, based on the meaical diagno~is of ~he patient's conditions.
In the prior art, heart bsat monitor~ have been described which are in the form of a wrist~atch intend~d to be worn by the patient, Some of ~hese monitors include means which enable the patient to set and vary the uppar and ~ower limits by manipulating dials or other means in the monitor.
That is, the limits are subject to change by the patient rather than the doctor, and t~erefore may be set at unsafe levels for the particular patient conditîon. A need therefore exists for a heart beat monito.r in which the limits are program-mable or storeable into the moni~or rom an external source under the control of a doctor or the llke. OnOB the limits . .

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are stored they shoul~ not be subject to variati.on by the monitor-wearing patient, except by a subsequent programming operation, from the external source. ~uch a monitor would prevent the patient from setting improper limits in the monitor.
In such an externally programmable monitor it is highly desirable to s~ore the limits so that they rema.in unaf~
fected by the monitor ' s main power source, e.g.~ a primary battery, which may be depleted by energization o ~he various monitor circuits including an audible ala~m and/or a visual rate display.
OBJECTS ~ND SUr~M~RY OF TilE I~VENTION
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It is a primary object o the inYsntion to provide a new heart beat monitor.
~nother object of the invention is to provide a new heaxt beat monitor, into which upper andfor lower rate limits are programmed and stored from a source ex~ernal to the monitor, so that the limits cannot be varied except by a subsequent programming and storing operation.
~ further object of the pr~ent invention is to provide a new lightweight heart beat monitor designed to receive and store only preselected rate lim~5 which are tran~-mitted thereto from an external source, an~ to provide one or more indications whenever the heart beat rate is outside a range defined by said limits~
These and other objects of ~he invention are achiev~d b~ providing a heart beat monitor which includes means or sellsing the heaxt beat~ and comparing their rate with rate-defining limits~ stored in a memor~ section thereof~ The monitor further inclu~es means for providing one or more indica-tions whenev~r the rate of the sensed hear~ beats i5 in a range outside one defined by the rate limits stored in the . . . .

( 75/325 memory. The novel monitor includes telemetry receiver and decoder means, designed to receive rate-limit indicating signaLs;
which are transmitted ~hereto from an extexnal source. These rate-limit-indicating signal~ are used to stor~ rate limits corresponding thereto in the memory means. It is these rate limits which define a heart beat rate range, 50 that when ~he sensed rate of the hear~ beat is outside their limits an indica-tion is provided to the patient.
To immunize the system from noise and from undesired sources of signals which may be mistaken for rate~limit-indicating signals, ~he transmission of appropriate rate-limit indicating signals takes place only after the ~ransmission of a preselected code, hereinafter referred to a~ a sync pattern. Only when the latter i5 recei~ed and ~ec~ded are ths ~ubsequently received rate-limit-indicating signa~s used to store the limits~indicated thereby in the memory means. T~
further inc~ease system reliability it is important to protect the memory means from being affected by the depletion of the main power source which is used to energize the re~t o the monitor circuitry, including the means used to provide the indication(s) when the heart beat rate is ~utsidc the }imits defining range~ This may be achieved by powering the memory means with a power source, e.g., a battery which is separate from the main power source. Alternately, a single power source may be used and a voltage sensor may be incorporated to disable all ~he circuitry~ except the memory means, rom the single power source when the sensed voltage drops bel~w a safe level. Limits in the memory means can only be changed by the rece~tion of a different set of rate-limit-indicating signais which follow the preselected code. In some embodiments means are included to displa~ the monitor wearer his actual heart beat rate. Also, ; ~

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in some embodiments means are provided to retransmit signals to the external source, indicating the limits received from the latter for verification purposes. Furthermore, in some embodiments means are provided within the monitor to display, upon the request the limits stored therein.
According to a broad aspect of the present invention, there is provided a system for monitoring heart beats of a subject, comprising: a heart beat monitor including heart beat sensing means for sensing the subject heart beat and for providing pulses corresponding thereto, first means including receiver means for receiving signals transmitted to said monitor ~
from a source external thereto, said signals including signals defining at ~r least a selected upper limit of heart beat rate, and memory means for storing ;~
said upper rate limit defining signals, received by said received means, circuit mearls responsive to said pulses for comparing their rate with said rate upper limit, stored in said memory means, and for providing an indication to said subject when the rate of said pulses exceeds the rate upper limit~
; and a power source means for powering at least said circuit means; and means external to said monitor for transmitting signals to said receiver means in said monitor, said signals including signals defining at least said selected rate upper limit, said external means including controllable variable means for controlling the rate upper limit defined by said signals.
The invention will now be described in greater detail with refer-ence to the accompanying drawings in which:
Figure 1 is a block diagram of one embodiment of the monitor of the present invention;
Figure la is a waveform diagram of a binary modulated RF carrier use~ul in explaining one aspect of the invention;
Figure 2 is a multiwaveform diagram useful in explaining the operation of the circuitry shown in Figure l;
Figure 3 is a diagram of a portion of the monitor circuitry;

Fi~ure ~ is a diagram of monitor circuitry for selectively display-ing sensed heart rate, a stored rate low limit or a rate high limit;

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Figure 5 is a diagram of a receiver-decoder unit 22, shown in Figure 1 and means for retransmitting rate-limit-indicating signals which were received from an external unit to the latter;
Figure 6 is a multiline waveform diagram useful in explaining the operation of circuitry shown in Figure 5;
Figure 7J appearing on the same drawing sheet as Figure ~, is a ~:
diagram of one embodiment of an external unit 20;
Figure 8 is a partial diagram of another embodiment of monitor clrcuitry; , Figure 9 is a diagram indicating an arrangement for recharging ' ~ -the battery; and :;' ' , , ', , ' ' .
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2~ 75/325 Figure 10 represents a diagrarn of the monitors positioned on a wrist.

DE:SCRIPTION OF THE PREFERRED EMBODIMENTS
~ttention is ncw directed to Figure 1 in connection with which an embodiment, useful in explainin~ the basic pxinciples and advantages of the present inventiotl 9 will be described. Therea~ter, different embodiments wi~1 be de~ribedO
As previously pointed out, in accordance with the present inven-tion rate limits are stored in ~he memory means of the monitor~
These rates limits define a heart beat range, so that when the sensed heart beat rate is outside the range an indication is provided to the monitor wearer. These limits are transmit~ed to the monitor for storage therein from an external transmitter unit in the form of rate-limit-indicating signals. In order to insure that the rate limits correspond only to appropriately transmitted rate-limit-indicating signals and are not affected by noise or o~her spuriou~ signal sources, a selected cod~, hereinafter referred to as a sync pattern, i8 trans~itted ahead of the rate-limit-indicating signals. Thus, only when the sync pattern is received ~Id ident~ied are the subse-quently received rate-limut-indicating signals used to store the rate limits. Otherwise, the pxeviously stored rate limits remain unaffected.
- Preferably, the memory means are powered by a 2S power source, e.g., a battery which is separate from the main battery, ~hich is used to power the rest of the monitor circuitry.
In such an arrangement the long term, low current drain of the main battery by the memory means is eliminated. Also, when the main battery runs down and has to be replacedt the memor~ ~on-30 tent is not lost. In a pr~ferred embodiment, me~ls are incor~porated to tran~mit signals to the external unit t:o Yeri~y that 3291:~L

the previously transmitted signals from the ~x~ernal ~nit resulted in the storage of proper rate limits. Also, to reduce drainage of the battery or batteries of the ~onitor, i~
desired, the power received during the reception of the sync pattern and the ~ollowing rate-limlt-indicating signals may be used to provide power for ~he circuitry which is used to decode and identify ~he sync pattern and feed the following :.
~ignals to the memory means.
In Figure 1, numeral 10 designates a heàrt beat moni tor which is assumed to be ~f the wrist type, i.e.~ one to be ~` worn on the wrist, like a watch. It includes heart beAt sensor 12 which senses the heart beats. Any of the presently kn~wn devices capable of sensing heart beats may be used. For example, sensox 12 may be in the form of an electrode, such as i~ used in recording EKGs, or a strain gauge or mechanical diaphragm, designed to sense ex$ernal s~in motion which varies due to the blood flow rate. Also, it may be a ultrasonic doppler type sensor. In general, sensor 12 may be any known device capable of ~ensing heart beats. As shown in Figure 1, the output of sensor 12 is connected to a beat-to-pulse converter 14 whose output is a sequence of beat pulses 15, each pulse corresponding to one heart beat. It is the rate of these pulses that the monitor 10 is designed to monit:or and indicat~
when ~heir rate i5 outside a selected range.
The limi~s of the range are supplied to the monitor 10 from an external unit 200 The latter i~ assumed to include circuitry, such as knobs, or dials, by means of which an opera-tor, e.g., a physician, can set the desired lim~ts to be trans-mitted. Atex selecting the range limit a transmit switch is activated. ~s a result, a preselected fixed sync pattern is generatea and is followed by a first sequence cE pulse~ which ~8--represents one of the range limits, e.g., the lower or low limit and a second sequence of pulses representing the upper or high limit. Binary techniques are employed so that the sync pattern is a selected pattern of a fixed numb~r of ~itsO For explana~
tory purposes le~ it be assumed ~hat ~he sync patt~rn is an eight-bit pattern such as OOlGllOl as viewed from right to left. It is further assumed that is followed by a number of 0's which define the selected low limit and by a number of l's which define the high limit. A zero (0) following khe last 1 indicates the end of the complete sequence. The number of 0~s defining the low limit and the number of l's defining the high limit, depend on the limits selected by the operator.
Generally, the sequence with the sync pattern viewed from righ~ to left may be represented by 01..... 10..... 0~101101 end ~ J ~ J~
bit high low ~ync llmit limit p~ttern This bit sequence is used in the external unit 20 to modulate an RF carrier signal, ~rhose modulated output, e.g., amplitude modulated is transmitted via a transmitter coil to a receiver and demodulator unit 22 of monitor 10.
In unit 22 the received RF carrier i5 demodulated and decoded t~ retrieve the original modulating binary sequence.

The unit ~2 includes an 8-bit sync pattern ~ecoder~ Upon sensing the proper 8-bit sync pattern of 00101101 it enables the following sequence of 0's representing the 3elected low limit, to be ~tored in a l~w limit counter 23. Then~ the foll~wing sequences of 1 ' s representing th~ high limit, are stored in a high limit counter 24~ Once the 0 end bit is sensed it effecitvely disables the unit 22 from supplying additional 2~

limit-indicating signals to the counters. Thus, the proper limits are stored in the counters 23 and 24 and they remain stored therein, without being altered, until it is desired to change the limits. Thi~ is achieva`ble by transmi~tin~ another bit sequence which includes ~he proper sync pattern as the front or leadin~ portion of the sequence.
~ he RP carrier power is chosen to be high enough to enable unit 22 which may be located at a selected dist~nce~
e.g., several inches,. frvm the external unit 20 to receive the transmitted signal. In unit 22 the transmitted waveform is received by appropriate means, e.g., a pickup c~ and is demod ulated to extract the waveform-modulating bin~ry se~uence~ It should be appreciated that the various circuit arrangements and technique~, well known by those familiar with the art, may be used for this end. The transmitted power should be sufficien~ly law so as not to provide RF interference which would re~ire FCC certification. It should be apparent that di~ferent frequen-cies and techniques may be used to transmit a binary ~equence as hereinbefore described to the monitor. For example, the caxrier frequenc~ may be above the audio ran~e, e~g., 22KHzo with 30-50% amplitude modulation. The ~e~uence may be trans-mitted at any desired bit r~nge, e.g., 200 bits per second.
Defining each bit period as T, a logical 1 may be in the for~
of 3/4T On and 1/4T Off, while a logical 0 may be 1/4T On and

3/4T Of. An example of such a modulated waveform i~ shown in Figure la, for the first 5 bits 10110 of ~he sync pattern, as viewed from left to right. "On" reers to a high level and "Qff" to a low level.
In order not to d.isturb the li~its wh.ich are stored in the counters 23 and 24, wllich together represent memory means, as previously pointed out, it is preferably to power these . . .

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, .. .

. 75/325 counters with a baktery 26, which is separate from a main battery 27, used to power the rest of the monitor's circuitry.
Thus, the depletion of the main battery 27 does not affect the ; contents of the counters 23 and 24. In ~igure 1, numeral 28 represents a manually operable On-Off switch tshown in ~he Off position) which the wearer may turn On only when wearing the monitor and thereby minimize the drainage of main battery 27 when the monitor is not in use, 5witch 28 is pre~erably of - the type which is switched On when the moni~or is worn by the wearer and is switched Off when the mon~tor is removed. For example, it may be a very small pushbutton t~pe switch on the back of the monitor which is automaticall~ pushed to be in the On position when the wrist monitor is placsa on the wrist.
In the embodiment, diagrammed in Figure ~ ~ the moni-tor is shown including a one shot 31 ~Ihich is used to control input And gates 33 and 34 of counters 23 and 24, respectively~
Also, shown is an And gate 35, having one i~put which receives the beat pulses 15 from converter 14 and anvther input, connected to one shot 31 through an inverter 35. A150 included is a ~ control flip flop ~F~) 3~ with its set (S) inpu~ controlled by gate 35 and its reset (R) lnput connected to a line 39 at which a contx~l level,assumed to be high, is applied only when the sync pattern is first recognized by unit 220 The Q outp~t of FF 38 is connected to o~e input of an And gate 41, whose other input is connected to a clock 40.
The output of gate 41 clocks a pulse interval counter 42, whose output is supplied to each o~ comparators 43 ~nd 44~ Counter 42 is resettable by the output of an Or gate 46. The latter is supplied with ~he ~ output of FF 38~ and wi-th the output of gate 75/3~5 35 through a delay un.it 47. The output of gate 35 is also applied directly to one input of each of And gates 51 and 52.
The former is also supplied with the output of co~parator 43 while gate 52 is supplied with the out:put vf comparator 44.
The outputs of gates 51 and 52 are respectively connected to the set (S) inputs of flip flops 55 an~ 56, whose reset (R) inputs are connected through a reset switch 57 to the battery 27, when switch 28 15 closed ~On)~ The Q
outputs of FFs 55 and 56 are connected to an Or gate 58 whos~
1~ output is connected to an alarm 60~ The alarm is activated only when enabled by gate 58 which occurs whenever either 55 or FF 56 is set.
The operation of the monitor 10 may best b~ describ~d in co~nection with a specific example and the multi-line wave-form diagram shown in Figure 2. For explanatory purposes let it be assumed that clock 40 provides 100 pulses per sacond (pp5~
and that the desired heart beat range to be monitored i5 between 60 beats per minute (bpm~ and 120 bpm, which correspond to 1 beat per second ~bp~) and 2bps. For this particular ex~tple, the ~it ~equence may include 100 0's to de~ine ~h~ lcw limlt of 1 bps, and 50 l's to deine the hiyh limit. In Fiqure 2, lines a-d are used to diagram the waveforms of bea~
pulses 15, the level on line 39, the output of one shot 31 and the state o FF 38, respectively.
Let it be assumed that at time t~ unit 22 detects the sync pattern. Thus, line 39 goes high, as represented by pulse 65 (line b) r for the bit duxation ~etween the last sync pattern bit and the first 0 of the sequance defining the low limit. When line 39 goes high, it resets FF 38 (line d).
Consequently, gate 41 is disabled to prevent the pulses fxom clock ~0 to be clocked into counter 42. The latter is reset through Or gate 46 since khe Q output of FF 38 is highO Also, hen line 39 goes high it resets counters 23 and 24 to an all zero count. In addition, it activates one shot 31 who~e output goes high (line c) thereby ena~ling gates 33 and 34. The 0 i s defining the low limit, from unit 22 are invexted into l's by an inverter 61 and are clocked into counter 23 through enabled gate 33. In the particular example lûO pulses are clocked in~o counter 2 3 . The subsequent sequence of 1 ' s defining the h.igh limit, passes from the unit 22 through gate 34 ana are clocked or counted in counter 24~ For the specifi~
example SO pulses are counted.
The period P, during whi~h the output o one ~hot 31 : is high, is chosen to be long enough to ~nsure that both th~
O and 1 sequences, whlch define the limits are clocked into the two counters 23 and 24. With modern binary signal trans-- 15 mlssion techniques, transmission rates of ~hou~ands o bits . per secor~d is easily achievableO Thus, the lilNt-defining O's and 1's can be loaded into their respective counters in a fraction of a second. Therefore, the period P:can be less ; than one secondO However, in any case it has to be long enough 20 to maintain gates 33 and 34 open until the two limit-defining se~uences are u~ed to store the limits in the two.counters.
It should be noted that as long as the output of one shot 31 is high the output of inverter 36 is low. Therefore, gate 35 is disabled and consequently beat pulses 15 ~o not:
~5 pass beyond gate 35. At the end of the period P, at time t the output of one shot 31 goes low, thereby disabliny gates 33 and 34, and the output of inverter 36 goes high. Following tl when the next beat pulse 15 is received, such as at t2 the output of gate 35 goes high, setting FF 38 (line d~.
~herefore, its Q output goes high a~d thereby enables gate 41, to enable the pulses from clock 40 to be clockeci or counted in .. . . .. . . .

counter 42. These pulses are assumed to be at a rate of 100 pps. Once FF 38 is set it remains set until a subsequent sync pattexn is recognized and line 39 goss high.
Until the next beat pulse lS is received such as at time t3 the counter 42 is clocked by the pulses from clock 40 at the rate o~ 100 pps~ Also, comparator ~3 compares the count in counter 42 with the count of 100 ~for 1 bps), stored 1n low limit counter 23. Similarly, comparator 44 compares the coun~
of 50 (for 2 bps) in counter 24 with the count in counter 420 Comparator 43 operates to provide a high output only when the count in counter 42 is greater than that in counter 23. Other-wise, the output of comparator 43 is low. On the other hand comparator 44 operates to provi-le a higll o~put only when the count in counter 42 is less than that in counter 24~ Other-wise, the output of comparator 44 is low.
As shown in Figure 1 the outputs of comparators 43and 44 are applied to And gates 51 and 52 respectively. Now~erO
these gates are only enahled when a beat pulse 15 is received~
which also resets the counter 42 throug~ Or gate 46 after a delay proviaed by 47. The delay is required to permit gate~
51 and 52 to become enabled and possibly s~t one of FFs 55 and 56, depending on the outputs of the comparator~, before the counter 42 is reset. ~his delay can be extremely sho~t, on the order of 1 ms or less.
In operation the first heart pulse 15 at time t2~
following the On or high period P of one shot 31, ~ets FF 38~s Therefore, gate 41 is enabled and counter 42 co~ts the pulses at 100 pps from cl~ck 40. When the next beat pulse 15 is received at time t3 gate 35 is again enabled and provides a high ~utput, thereby enabling gates 51 and ~2. If while gates 51 and 52 are enabled the heart beat rate is between 1 bps ~60 bpm) and 2 bps (120 bpm) i.e., 0.5 second _ ~t3 - t2) . . .. . - , , . : , ... .. .. ..
. , , ~

1.0 second, the count in counter 42 is not less than 50 or more than 100. Since counter 23 stored a count of 1~0 the output of com~arator 43 is low. Therefore~ one of inputs to gate 51 is low and consequentl~ i~ does not provide a high output which S ~ould have set FF 55. Similarly, since counter 24 stores a count o 50 and the count in coun~er 42 is not less than 50 the output of comparator 44 is low and therefore gate 52 does not set FF 56. With neither FF 55 nor 56 ~et, Or gate S8 is not enabled and therefore the alarm 60 is not activated. After a short dela~ provided by delay unit 47, the counter 42 is reset and starts counting pulses from clock 40 t~ efectively measure the time interval between the beat pulse 1~ sensed at.
time t3 and the next beat pulse assumed to be sen~ed at time ~4' If, however, the heart beat rake is one outsiae the range of 60 bpm and 120 bpm one of the flip flops 55 or 56 will be set and cause the alarm 60 to be activated. For example~
if the heart beat rate is 40bpm the interval between beat pulses is 1.5 seconds. Thus, the count in counter 42 between pul9es reache~ 150. Consequentl~, the output o~ comparator 43 goes high and there~ore when gate 51 i~ enabl~d by a beat pulse 15 its output goes high and ~herefore FF 55 i9 set. A~
a result, the output of Or gate 58 goes high and activates the alarm 60 to indicate an out of range condition. On ~he other hand if the heart beat is higher than the high limi~ 120 bpm e.g., 150 bpm the interval between beat pulses is only 0.4 second. Thu~, the count in counter 42 will reach only a count of 40 when the gake 52 is enabled. Since the count in counter 24 is 50, i.e., higher than 40 in counter 4Z, the output oE
3~ comparator 44 will ~e high a~d thereore gate 52 will set FF 56, which will cause Or gate 58 to ac~ivate the alarm 60. A5 long ,, . . . ~ ~ , . . . ...

as either FF 55 or FF 56 is set -the alarm 60 remains activated ~ne wearer may rese-t the se-t flip flop by momentarily depressing reset switch 57. It should be pointed out tha-t the out~ut o~ Or gate 58 may be used to activate any device whicn would provide the S wearer wi-th an out-of-range indicat~on. For example, a light may be energized by the output of Or gate 58, to~ether with or instead of activating alarm 60. Thus, numeral 60 should be regarded as representing one or more energizable devices to provide an out of-range indication.
As previously pointed out, the switch 28 is used to contro~
the supply or power from the battery 27 to the monitor's circuitry, excep-t for the memory mec~ns 3 i.e., counters 23 and 24 in which the limits are stored and which are powered continuously by separate battery 26. Thus, whenever the monitor ;s not in use the switch 28 should be open (Off), as shown. When in use the switch is closed tOn). As previously indicated, it may be of the type which closes automatically when the monitor is worn. For example 9 it may be a pushbutton type~switch which closes upon pla~ing the monitor on the wearer's wrist, as shown in Figure 10 wherein the wearer's wrist is shown in cross section and designated by ~J~ and the monitor 10 is shown secured to the wrist by wrist bands WBl and r,~B2.
When the monitor is firs-t placed in position and switch 28 is closed, either au-tomatically or manually, FFs 55 and 56 Yhould be in the reset state, to prevent unintentional act;vation of the alarm 60. If desired a one shot ~not shown) of very short time duration may be incorporated. The latter may ~e used to provide a resetting pulse to the fl~p flops whene~er s~itch 28 closes.
During use the flip flops are resettable by switch 570 After switch 2~ is closed, it is desirable to insure tha-t the alarm 60 is not activated, except due to beat pulses which co~respond to hear~ beats~ sensed by sensor 12, at a rate outside the range, defined by the s-tored ~ . 75/325 2~

limits. This may be achieved by incorporating in the monitor an additional one shot 62 and an ~nd gate 63, as shown in Figure 3.
Basically, the one shot 6~ is o~ the reset~ble type and responds to each beat pulse 15, from converter 14, whieh drives the output of the one shot high as representea by 62a for a selected period, which is not less ~han the period batween any two pulses 15 at the lowest expected heart beat rate. Thus, as long as heart beats are sensed, at a rate not 10 less than the minimum expected rate, the first pulse 15 will activate the one shot 62 to provide a high output and each subsequent pulse 15 will re~et the one shot 62 to maintain the ,output high. The high output of one ~hot 62 will enable gate 63 to activate alarm 60 when the output o Or gate 58 goes high. ~lowever, if heart beats axe not sensed ~or some rea~on~
such as due to improper alignment of the heart ~ensor 12, the output of one shot 62 is low, ~hereby disabling gate 63, so that even if switch 28 is closed and the output of Or gate 58 is high the alarm 60 is not activated. Assuming that the minimum expected heart beat rate is 3~ bpmt whic~ corxesponds to a period of ~ seconds between heart beats, the period o~ one shot 62 may be chosen to be slightly greater than 2 seconds, e~g., 2.1 seconds. Such an arrangement would prevent the alarm 60 from being activated, unless heart beats at a rate of at least 30 bpm are ~ensed.
In the foregoing described embodiment the wearex is provided only with an indication that the heart beat rate is outside the ~hosen range when the alarm 60 is activated.
However, the wearer is not provi~ed with an indieation of his actual heart beat rate. Also, the wearex is not provided with . -17-Z~

an indication of the limits stored in counters 23 and 24.
If desired, the wearer ma~ be provided with an indication in the form of a vi6ual display of his actual heart beat rate or either of the stored limits by the addition of some circuitryv which will be described in connection with Figure 4.
Therein, numeral 65 represents a four-position - display contxol switch, with positions de~ignated OFF, LOW
LIMIT, HIGH LIMIT, and SENSED ~ATE. Numeral 66 de~ignates a multibit xegister, while numeral 67 designates a display calculator. And gates 68 and register 66 are energi~ed only when the switch 65 is in the SENSED R~TE position. Gates 68 axe enabled on1y when each pul~e lS from converter 14 is ~produced. Thus, as each beat pulse is xeceived prior to reset-ting the counter 42 its content is transferred to registex 6 and remains stored therein until a subsequent pulse 15 is received. The outputs of register 66 when the latter is energized when switch 65 is in ~he SENSED RATE position are connected to a display calculator 67 through Or gates 6~, When the switch 65 is in the LOW LIMIT position And gate~ 66a are ener-gized to supply the count in counter 23 to calculator 67 throughOr gates 69, while when switch 65 is in the HIGEt LIMIT position And gates &6b are energized to supply the high limit count in counter 24 to calcula~or 67 througn gates 69. The function ; ~ of calculator 67 is to convert the count supplied thereto into a number in beats per desired unit of time~ e.g.~ bpm, and display said nu~ber.
As should be apparent from ~le foregoing description, in counter 42, which is assumed to be a multibit counter, before it is reset by a delayed beat pulse 15, the count in it is re lated to the kime interval since the preceding beat pulse~ If desired the sta~es of counter 42 may be eonnected to corresponding stages of a register 6~ through control gates 68. These gates are assumed to be enabled by the leading edges of the beat pulses 15. Thus, as each beat pulse is received, prior to resetting the counter 42 its content i5 transferred to register 66 and remains stored therein until a su~sequent pulse 15 is received. The register 66 is shown connected to a display calculator 67 whose function is to convert the count in register 6~ and display it as a number in beats pex desired unit time, e.g., bpm.
For the foregoing description, in which the clock 40 is assumed to provide 100 pps, the required calculation .is D - (60 x 100)/R where R is the supplied count in re~ister 66, or counter 23, or counter 24 and D is the displayed number in.

beats par minute. Clearly, known caiculator circuitry and displa~s, such as tho~e employed in small pocket calculators~
can be used in implementing the di~play calculator 670 In general, the required calculation can be expres~ed as D =
(T x C)/R, where D is the dispLayed heart beat rate Por a peri~d of T seconds, C represents the number of pulses per second from clock ~0 and R is the supplied count.
In the particular ~xample, when the sensed rate is selected for display, the display will be updated for every heart beat. If this update rate is fOuna to be too high the 25 control gates 68 may be enabled by every nth beat pulse, where n is an integer. In order to minimize the depletion of the main battery 27, the circuitry shown in ~igure 4 should be connected so that regist~r 66 and gates 68 are energized only when switch 65 is i.n the SENSED R~TE position, gate~ 66a an~ 66b are energized only when switch 65 is in th~ L0~ L~MIT
and HIGH LXMIT position respectively, and display calculator _~9_ ~ 75/325 ~ ~8~

67 and Or gates 69 are energiæed whenever swit~h 65 is other than in the OFF position.
From the foregoing it should be appr~ciated that several unique advantages are realiæed with the monitor o~ the present invention. In the novel monitor the limits, which define the rate range, are transmittea into the monitor fr~m an external unit. Thus, the wearer cannot change the~ unless he has access to the external unit. This is particularly significant when the potential wearer is a pa~ient under a physicianqs super-10 vi~ion and only the physician desires to have control over thelimits, depending on the patient ' s meclical condition. Also, in the monitor of the present invention a multibit 3ync pattern is transmitted, ahead of the rate-limit-inaicating signals, such as the O's and l's, hereinbefore describ~d. Also, the transmitted 0's and l's in the sequence are controlled ~o have appropriate shapes. Such an arrangement insures that only the pxoper transmitted binary signals, following ~he sync pattern rather than noise or other signals are used to de~ine the limits, which are stored in the monitor7 s memory mean~, such a~ the ~0 counter~ 23 and 24~ Furthermore, by powering the lattex with a battery, such as battery 26, which i~ separate from the main battery 27, used to power the rest of the mor~itor's circuitry, , ~he depletion of the main battery 27 does not a~fect the .
limlts' storing counte~-s. mus~ the monitor's reliability i5 Z~ grea~ly enhanced~
In addition, in the described embodimant after the storing of the limits~ the time intexval between evexy pair o~
successive beat ~ulses 15, such as those sensed at ti~es t2 and t3, t3 and t4, etc., is measured, to provide an indication whether the sensed heart beat rate between any of t:hese pairs of ~ 75/325 32~.

pulses is within or outside the selected range. This is beliPved to be quite si~nificant for cases in which it is important to produce an out-of-range indicakion, preferably as soon a~ the heart beat rate is outside the ~nge, particu-larly when it exceeds the high ~imit. Thi~ may be quite impor-tant to prevent possible permanent injuxy to the wearer, which may result if the out-of-range indication w~re produ~ed only after a relatively long period, e~g., lS seconds during which a large number of potentially damaging high rate heart beats may occur. In another embodiment of the invention to be described hereinafter several heart beats may occur before an out-of-range indication is produced. However, therein the maximum number of heart beats which may occur be~ore the out-of-range indication i~ produced is very small generally less ~han 10.
Thus, for all practical purposes the o~t-o~-range indication is produced practically as soon as the sensad heart beat rate .
; is outside the range.
~t should be appreciated by those familiar with ; circuit designs that various circuik means ~ay be used to implemenk the circuitry, hexeinbeore described. Therefore, the following description should be regarded as only specific examples of circuitry whish may be used, rather than to limit the invention thexeto. As pr~viously explained the sync ` pattern ~nd the xate-limit-indicating ~ignals may be transmitted : 25 to the monitor by amplitude modulatin~ a RF carrier. Attention is nGw directed to Figure 5 in which one possible embodiment o~
circuitry, represented in Figure 1 by unit 22, one shot 31, And gates 33 and 34 and inverters 36 and 61. : .
Briefly, in Figure 5, numeral 70 represents a re¢eiver and decodëx uniti:~hown including a pickup coil 72, which picks up the amplitude-modulated RF carrier ~see Fi~ure la) which is transmitked from the external unit 20. The ~eceiver and decoder _zi_ 75 ~ 32 5 !

unit 70 is shown to include a rectifying circuit~ consisting of a diode Dl ~Id a capaci-tor Cl, resistors Rl-RI~, a transistor Ql, a Zener diode Zl, another diode D2 and two capacitors C2 and C3, connected as shown. The rece;ved RF carrier is rectified so that the demodulated signal or ripple is present at point 75. That is, thereat a voltage, e.g., ~6 volts is present which is rnodulated above and below its average level by the binary sequence. The output on line 76 ;s the original binary sequence, with the lower amplitude of each bit being at ground and its upper amplitude at a selected voltage, e.g., +5 vol-ts, as diagrammed in line a of Figure 6. The voltage at point 77 9 designated ~Vp, represents the average received voltage. It may be used to power the various circuits in the monitor which are used-to detect the sync pa-ttern and receive and store the limits in the counters 23 and 24, and thereby reduce -the drainage of the main battery 27. Furthermore, if desired, the voltage ~p9 when present at point 77, may be used to recharge the ~ain battery 27~ assuming the latter is of the ~echargeable t~pe. In Figure 9 a recharging circuit RC, which receives the v~ltage +Vp, is shown connected across battery 2 7 to recharge the latterl Such recharge 20 circuits are well known in the art. They are typical~y used to re-charge ba~teries of the type used in portable devices, e.g.g casset~ recorders and the like.
As shown in Figure 5 the circuitry includes a one shot 80 and an eiKht-stage (Sl~S8) shift register 82 to which the binary output of unit 70 on line 76 is applied as an input. The outpu~ of unit 70 ;s also used to clock a one shot 80~ whose outputs 01 and 2 are applied to lines 83 and 84 respectivelyO The output 2 is the complement of l which is used to clock the register 82~
Defining each bit period as T, as shown in Figure 6, the one shot 80 is clocked by each low to high transition of the unit 70 output. The time oonstant of the one shot is 1~2T, so -that l i5 high for the first half of each period T~ as shown in Figure 6, line b, and 2 is high for the second half of each period T, as shown in line c. The shift register 82 is clocked by the high to low tr~nsition of l~ such as at `

times tl, t2, t3, etc. If at the time oE clocking the register the input to it, i.er, the output af unit 70 on line 76 is high, a binar~ 1 is clocked into Sl of the register, Howevery if the input is low, a bin ar~ 0 is cl.ocked into Slo From 5 ~igure 6, lines a and b it should be apvarent that at times t~, t~, t3, etc., bits 1, 0, 1 etc., are clocked into Sl o register 82. At time t8 the last bit of the 8-bit sync pa~tern is clocked into the register. Thus, register ~ta~es S1-S8 contain the sync pattern 00101101, respectively~
As shown in Figure 5, the outputs of stages S3~ S5 and S6 and S8 are connected directly to inputs of an 8-input And gate 8S while the outpu~s of stages Sl, S2, S4 and S7 are connected to the gate 85 throu~h inverter~ 86-89 xespectively.
Thus, at time tg, the sync pattern of 00100101, viewed from left to right is present in stages Sl-S8, respectively.
Consequently, all the inputs of And gate 85 are high ~nd : therefore its output on line 91 is high, thereby indicating the identification of the sync pattern. It is used to reset counters 23 and 24 ~Figure 1) to all zero counts, and to begin 20 the memory programming or s~oring operation.
As shown, the circuitry also includes a JK flip flop ~FF~ 92 whose K input is connected to line 91 and its clock input to line ~4, on which the output 2 f one shot 82 is applied~ Assuming ~hat FF 92 is clocked by ~he positive to ~egative transition of each output pulse of O~ ~see Figure ~, line c~ at time tg, following t8, FF 92, which is assumed to have been previously set so that its Q ou-tput is hi~h, îs reset , driving its ~ output high~ Once FF 92 i~ :reset , i . e ., its Q output goes high on line 93, one input to each of Nand gates 94 and 95 is high.

~23-75/3~5 The other input o gate 94 is applied from the output of inverter 86. trhus, each time a 0 is clocked into stage S1 the output of inverter 86 is high and therefore the output of gate 94, which is applied to one input of Nor gate 98, goes S low, thereb~ enabling the latter. Nor gate 98 is also supplied with 2' merefore, whenever 2 undergoes a high to low transition both inputs to Nor gate 9 8 ar~ low or û ' s and therefore its output goes high, or is a 1, which is clocked into low limit counter 23.
10For example, after ~le sync pattern is recognized at t8~ and the output of ~nd gate 85 goes hi~h, at time tg~
FF 92 is reset so that line 93 goes hiyh, enabling gate 94 '(and gate 95)~ Then, at time tlo, the first 0 of the sequence, which represents the low limit, is clocked into Sl. Si~ce it is a 0 bit the output of inverter 86 is high and therefore the output of Nand gate ~4 is low (0)O Consequently, at time tll .
. both inputs to Nor ga~e ~8 are low, and a 1 is clocked into counter ~3 for the first 0~ Similarl~, every 0 in the sequence which defines the low limit i~ clocked into the low li~it coun~er 23.
It should be pointed out that when the low limit is clocked into counter 23, Nand gate 95 is effectively disabled, in turn disabling Nor gate 999 Each 0, clocked into 51, is directly applied to Nand gate 95~ Thus, its output is high, thereby disablin~ Nor gate 99 since the latter's output will remain law (O) xegardles~ of 2 which is applied to its other input~ Thus, the output of Nor gate 99 does not clock the high limit counter 2 4 .
After all ~he O's in the se~uence, representing the low limit are clocked into as l's into counter 23, the following sequence of l's representing ~he high limit is received, bit - -24~

~&~2~

by bit and clocked into Sl, Due to each 1 b-t the input to gate 95 from Sl is high~ Thus, the o~tput of gate g5 remains low and therefore enables NOL gate 99. Consequently, when 2 goes from high to low Nor gate 99 pxovides a hi~h output which clocks high limit counter 24 . After all the l~s repre-senting the high limit, are clocked into counter 24 the 0, representing the end-of-se~uence bit is receivedO Therefore~
the states of stages S1 and SZ are 0 and 1~ respecti~ely, Consequently~ both inputs to Nor gate 101 are low ~Q~ and there~ore its output goes high setting FF 92. Corlseq~ently, its ~ output goes high and its Q output goes low. When Q
goes low it disables both gates ~4 and g5 and, therefore ,. no additional clocking of the limit-storing counters 23 and 24 take~ place. That is, their counts remain unalterea~ The 1~ Q output of FF 92 is applied to vne input of And gate 3~ ~se~
Figure 1). Thus, each beat pulse 15 set~ e., enables the gate 35 to provide a high outputt as herein~efoxe described.
From the foregving it is thus se~n that the circuitry, shown in Figure 5, is clearl~ ade~uate and reliable to receive 20 the transm1tted binary sequence which includes a ~quence portion, such as the 0 ' 5 representing the 1GW limit, a ~equence poxtion, such as 1'~ representing the high lim~t, a sync pattern, such as the 8-bit pattern, preceding both limit~ ~
indicating signals and an end bit. Only after the sync pattern 25 is received and recognized , i .e., decoded , resulting in a hi~h output by gate 85 on line 91, does the loading of the counters 23 and 24 with the lirnit5 start~ The use of the beat pulses 15 is temporarily suspended, since gate 35 is aisabled.. After both limits are stored in the counters and the end bit is ~25--~ z ~ ~ ~ 75/325 received, e.g., the 0 bit following the last 1 of the high-limit-sequence portion, is FF 92 set~ Consequently, all additional clocking of the counters 23 and 24 is terminated, gate 35 is enabled and the regular pulse monitoring is resumedO
It should be pointed out that the limlts are stor~d in the counters only after the sync pattern is recognized, and limit storing is terminated whe~ the 0 sequence-end bit is detected, thus setting FF 92, which disables the gates 94 an~ 95 and in turn disables countex input gates 98 and 99.
Thus, the stored limits are practically iT~nune ~rom being affec~ed by any noise pulses. By pcwering the counters with a separate battery 26, once the limits are stored, they are unaf~
fected by drainage of the main battery 27. Once a set of 1 imits is stored in the counters it remains unaltexed until a new bit sequence is receiv~d by u~it 70 from the external unit 20. The new sequence is of course recognized w~en the sy~c pattern i5 received and ~ecoded, i.e., is stored in khe ; register 82, causing And gate 85 to provide a high output, which results in subsequent limit-loading-operating ~eps, ~0 as hereinbeore de~cribed.
If desired, the monitor may include means to trans-mit the limits, stored therein, to the external unit 20 in order to verify ~lat the chosen limits were actually loaded ~stored), in the counters. This may be achieved in different ways. For example, the outputs of two oscillators at differ ent frequencies may be amplitude modulatea by the se~uence of bits, supplied to the two counters during limit loading. The modulated outputs of the two oscillators may then b~ ~ransmitted from the monitor to the external unik 20. Since the retrans-mission of the limits to the external unit 20 occurs while ' the latter transmits the limits for storage in the monitor, the power from the received power, e.g., ~Vp (at point 77, Fi~ure 5) may be used to power the oscillators in the monitor to minimiæe battery drainage.
Alternatively, if desired, at any point durin~
actual pulse monitoring, i.e., other than when limits are stored, signals, indicative of the stored limits may be trans~
mitted to the external unit. Using ~he foregoing example in which it was assumed that counters 23 and 24 store counts of 100 and 50 respectively, the counts of 100 and 50 may be converted into two voltages V100 and V50 which correspond to counts o~ 100 and 50 respectively, and be transmitted to the external unit 20 wherein these voltages, i.e., V100 and V50 may be used to activate appropriate displays, e.g~, displa~
counters~
- For explanatory purposes an arrangement for feeding back the limits being stored to the external unit 20 during limit loading, is shown in Figure 5. Therein, an oscillator A, assumed to provide an RF carrier at one frequen~y ~1 is shown connected to a modulator-transmitter 105, which is modulated by each o ~he 100 pulses as they are clocked into low limit counter 23~ The modulator-transmitter 105 includes a transmitting coil 106 which couples the RF carrier at fl, modulated by ~he 100 pulses, to a pic~up coil 107 in external unit 20. The coil 107 feeds a receivar-demodulator 108 tuned to fl. The output of the latter would be 100 pulses which may be used to clock a low limit display 110.
Oscillator B assumed to provide ~n RF carrier at f2, where 1 ~ f2 ~ is shown connected to another modulator-transmitt~r 112 which is fed with the 50 pulses ac; they are -~7-. 75~325 being clocked into hi~h limit counter 24. Th~ modulated carrier at f~ is fed to a txansmitting coil 113, which couples energy to a pic~up coil 114 in unit 23. Coil 114 feeds a receiver-demodulator llS, tuned to f2, whose output would be a sequence of 50 pulses which may be displayed in the external unit 20, for verfication as they are loaded in the monitor`s counter 24.
Clearly, oscillators A and B ~nd units lQS and 112 may be powered by the received power ~Vp~ Furthermore, if desired a single oscillatox and modulator-transmitter may be used. The pulses fed to one of the counters such as 23 may be used to modulate ~he RF carrier to one level of modulation, . e.g., 50~ while those fed to the other counter ~ shown in 24) used to modulate the RF c.arrier to another level, e.~., 30~
Then in the external unit 20 these diferent levels o~ modulation may be sensed to feed the ~wo groups o pulses, representing the two differenk limits, to the two displays 110 and 120.
Attention is now directed to Figure 7, which is an example o~ one embodiment of circuitry in external unit 20 ~or generating and transmitting the limit-indicatin~ signals and the sync pattern to the monitor, as repxesented by the waveform in ~igure la. As previously explained, the sync pattern is represented by a ixed preselected bit pattern, for example the 8-bit sequence 10110100, as viewed from left to right. It is ollowed ~y a number of 0's defining ~ne sele~ted limit, e.g., the lower limit, which axe oll~wed by a number of - 1's, defining the other limit. The bit sequence terminates : with a 0 end bit. The number of 0's and/or l's can be varied to vary the lower and upper limits, xespectively~ Each bit ; 30 period is the same, hereinbefore designated as T. A binary , - ` 75/325 1 is represented by a high level during the first 3/4T, followed by a low level during ~he last 1~4T. ~ binary 0 is represented by a high level during the first 1/4~ foll~ed by a low level during the remainder 3/4T.
As shown in Figure 7 the external unit 20 is assumed to include a clock ox pulse oscillator 125 which is activated when a transmit switch 126 is closed. Once a~tivatQd the clock 125 provides pulses 128 to a 2-stage bina~ counter 130. The interval between pulses 128 is 1~4T. Thus, the counter 130 is clocked at 4 times the bit rate T. The outputs of khe two stages of counter 130, are designated Cx and Cyo The our combinations of the two stages of counter 130 dur ng each T period are represented by the truth table next to counter 130 ~he circuitry includ~s an ~-s~age shift register 135, which is ini~iall~ set to store the sync patte~n 10110100~ -as viewed from left to right, in stages Sl-S8, respectively.
Then as the register 135 is clocked, as will be explained hereinafter, the bits in the stages shift ~xom left to right.
The output of stage S8 lS applied to two inputs T2 and I3 o~
a four-position multiplexer 136, whose other two inputs I
and I4 are connected to high ~V) and l~w ~ground) levels, xespectively. The output o the multiplexer o~ line 137 to a modulated power oscillator 140 depends on the states of Cx and C~ which control which of the four inputs Il - I4 is appl~ed to line 137, as rep~esented in the truth table.
As shown a Nand gate 142 is connected directly to Cx and C~. Thus, only when Cx and Cy are both 00 the output of gate 142 goes high~ The low to high transition of the output of gate 142 clocks register 135.
In operation the countcr 130 i5 assumed to be initially reset to 00 count. ~en clock 125 is activated by closing switch 126 each pulse 128 adv~nces the count ln counter 130.

-~9_ The first pulse 128 drives Cx to a 1. m us, input Il, which is high, is supplied by 136, via line 137 to oscillator 140.
The next pulse 128 drives Cx ana cy to a 01 state, in which the output of 136 is its input I2. SinGe the first sync pattern bit in S8 is a 1, i.e., high, the output o 136 is high.
Simllarly, the next pulse 128 drives Cx and Cy to state 11 in which the output of 136 is I3. It is high since $8 stores a 1. Then, when the ~ourth pulse 128 i5 received Cx and Cy are in the state 00 in which 136 outputs ~4 which is low. Also D
Nand gate 142 clocks the register 135 to shift the bits orward by one ~tage.
From the foregoing it should thus be apparent that . with the above described arrangement during each bit period T during the ~irst 1/4T the output of multiplexer 136 is high, while during the last 1/4T it i5 low, irrespective of ~he bit . in stage :S8. However~ during the center hal.f of each T period the multiplexer output is high if the bit in S8 i5 a 1, and is low if the bit is a 0. The output level of multiplexer 136 on line 137 modulates power oscillator 14~ whose output is the m~dulated ~F carrier, as shown in Figure la, which is applied to a transmitting coil 14~ for tran~mission to the monitor.
As shown the circuitr~ furthex includes two variable o~e shots 146 and 147. It is with these one shots ~hat an operator controls to select the limits to be tra~smitted.
25 ~ One shot 146 is used to set the lc~w limit by controllin~ the number of 0's which will be transm1tted following the sync pattern, while one shot 147 controls the upper limit by controlling the number of l's which will be txansmLtted.
In operation, when switch 126 is closed it activates ~ne sh~t 146 so that its output on line 149, which is applied to one shot 147, goes high. Line 149 remains higll for a variable .. . . . . . ... ..

2~

period~ chosen by the operator. As long as line 149 is hi.gh ~he output of one shot 147 on line 150, which is the input line to stage Sl of register 135, is low. Thus, every time register 135 is clocked and line 150 is low a 0 is clocked.
into Sl. Defining the time constant of one shot 146 as TL, during which its output is high, 50 that the output of one shot 147 is low, it i~ clear that the number of n 's, clocked into the register 135 is ~ /T. Clearly, b~ changing the number of OIs which define the lower limit can be varied.
At the end of TL the outpu~ one shot 146.goes lo~, triggerin~ one shot 147, ko provide a high ou~put on line 15~
for a period controlled by its vaxiable time constant, dei~able as TH. As lon~ as line lS0 is high, 1'~ are clocked into the register 135. Clearly, the number of 1'~ which are transmitted to define the upper limit is TH/T. At the end of period TH
line 150 goes low so that during the next period T a 0, repreW
senting the end of the .se~uence or the end bit is clockea into Sl. If desired, the high to low transition on line 150 may be used to activate a delay uni~ 152 ~o open ~wi~ch 126 and 20 thereby terminate the transmission operation after a delay of xT, where x is a number suficiently large to insure that during . xT all the proper bits are transmitted. Generally, x should not be less than 9 to enable the ei~ht bLts in the register an~
the 0 end bit to be clocked into the re~ister after line 150 goes l~w, to be shifted out of the register and be transmitted out of the external unit 20.
It ~hould thus be apparen~ that the circuitry, shown in Figure 7, is capable of generating and transmitting to the monitor the kit sequence, including the 8-bit sync pattern, the Q J s def.ining th~ lower limit, the l's de~ining the upper limit and the 0 end bit. Clearly, by varying either TL ~ one shot ~ .

4~

1~6 and/or TH f one shot 147 the number of O's and/or the number of ~'s which define the l~er and upper lim1ts respec-ti~ely may be varied in a simple and most convenient way. Each one shot may be connected to a separate dial, calibra~ed in beats per minute, to facil.itate the control o~ the time constant o~ the one shot.
~ In oxder to reduce the size of ~he monitor preferably ; large scale integrated (LSI) circuits should be employed. To facilitate such implementation all counters and other circuits ~hould be of t~e bina~y type ~ where possible. In the embodiment, shown in Figure 1, limit countexs 23 and 24 and the pulse interval counter 42 are assumed to be o~ the bina~y type. The number o bits or stages o each o these counters clearly depends on the outside range limits to be monitored and the 15 clock rate of clock 40.
Assuming the latter ' s rate to be lOOpps and assuming ~hat the monitor is designed to de~ine a low rate, down to 30 beats per munute which corresponds to 1 beat per 2 seconds~
counter 42 should be one capable of counting up to 200 pulses which is achievable with an 8-bit counterl which can count up to 256. Each of counters 23 and 24 may 'al50 be an 8-bit counter. It should be appreciated that since ~he count in counter 42 is compared with the co~ts in counters 23 in comparators 43 and 44, each of the comparators should be an 8~bit comparator.
; If desired, the various circuit arrangements, herein~
beore described, may be modifiea considerabl~ without departing from the spirit of the invention~ For example, the 1~ and high limits, once stored in counters 23 and 24, may be used to determine whether the beat pulses 15 ~Figure 1) are recei~ed :

I . 75/325 at a rate ~ithin the rate range, defined by these limits, or are outs.ide such range, by oth~r than performing the comparisons, as hereinbefore described in connection with Figure 1. Atten-tion is now directed to Figure 8 wllerein another possible par-tial embodiment of the monitor is diagrammed. With such anarrangement the need for two multistage comparators t such as comparators 43 and 44 is eliminated, at the price of some additional circuit components. In Figure 8, elem~nts like those previously described, ~ld performing similar functions~ are designated by like numeralsO
The circuitry in Figure 8 will ~e described in connec tion with a monitor in which the lowest low limit which may be set is one corresponding to a time interval between beat pulses 15 of 2.04g seconds, which in terms o~ beats per second is 60/2.049 = 29.2 bpm. For explanatory purposes the lawest low limi~ will be assumed to ~e 30 bpm corresponding to 1 beat per 2 seconds. Each of the limit counters 23 and 24 is assumed to be an ll-stage binary counter, capable of counting up to 2048, (0-2047) pulses. When this count i5 exceeded its last ~tage underyoes a high to low transition. In Figure 8 output line 161 of counter 23 is shown connected to the clock input of a ~-type flip flop 162 through an inverter 1630 WhPn the count in count~r 23 exceed3 2048 line 161 goes from high to low and consequently, the output of inverter 163 goes from low to high, clocking FF 162. Since FF 162 is a D-type FF with its D input at ground ~low or 0), when clocke~ its Q output on line 162a is high.
Similarly, output ~ine 1~4 o~ counter 24 goes from high to low when the count in counter 24 exceeds 2048 9 causing the output of inverter 165 to go from 1~J to hlgh and thereby clock D-type FF 166 so that its Q output on lin~ 166a is low, ! . 75/325 Z~

since its D input is low lground)~ The Q and Q outputs of FFs 166 and 162 respectively are connected to a Nox gate 167, whose output is applied to the D input o~ D-type FF 168. The Q
output of the latter on line 169 is connected to the alarm 60 The circuitry further includes an input JK-type FF
170 which is clocked by the beat pulses 15 from converter 14 ~Figure 1). The Q output of FF 170 on line }71 is applied t~
the clock input of FF 168 and to the set (S) input o each of FFs 162 and 166. FFs 162 and 166 are set and FF 168 is clocked by the low to high transition on line 171 a~ indicated by arrow 172 on waveform 173. Each of these flip flop9 i~ assumed to provide a high (1) Q output when set. ~hus, when ~'F 162 is ~e~
its Q output is high 11) and its Q output i5 low ~0)-As will be pointed out hereinafter, the counters ~3 and 24 which are loaded with lim~ts ~co-mts), and are clocked when line 171 first goes 1~7, SO that if the heart beat rat~-is within the range defined by the limits, FF 166 ls clocked and FF 162 is not clocked before line 171 goe~ high. Therefore, lines 166a and 162a are both low and the output o Nor gat~
167 i~ therefore high, fiO that when F~ 168 is clocked line 169 is high and the alarm 60 is not activated. I, howe~er, the heart beat rate is highex than the upper limit, set in counter 24, FF 166 is not clocked before line 171 ~oe~ high. T.here fore, line 166a is high and therefore the o~tpu~ o~ Nor gate 167 is low when FF 167 is clocked. Con~equently, line 169 goes lo~ and ~he alarm 60 is activated. On the o~her hand, if the heart beat rate is below the lower limit, set in counter i 23, FF 162 is clocked before line 171 goes high. There~ore, ; line 162a goes high, so ~hat when E'F 168 is clocked the output ; 30 of Nor gate 167 is low and as a re~ult line 169 goes low, acti~
vating alarm 60.

. -3~-.

' 75/325 ~-t~

As shown .in Figure 8 the Q output o ~F 170 on line 175 is converted to the reset (R) input of a D-type FF 176, whose Q output on line 178 is applied to the X input o~ FF 170 The set (S) input o~ each o:E FFs 170 and 176 is connected to the Q outpu~ of FF 92 via line 93 ~se,e Figure 5) . Thus ~ during limit loading or progr~nming, since line 9 3 is high, both FF i70 and FF 176 are set (lines 171 and 178 are high~ and ar held in that state until limit loading is completed.
The circuitry further includes a multibit counter 180 which is clocked by pulses from an oscillator 182. For explanatory purposes the latter is assumed to provide pulses at a rate of 2 KHz, so that the rate of output pulses Exom the ' first stage o counter 180 on line 183 is 1 KIIz. The counter 180 is assumed to count up to 4096 and when excee~ing this : 15 count is reset so that the ou~put o its last stage u~dergoes a high to low transition, produced on line 185, which is connected through inverter 187 to the cloc~ input of FF 1760 When the latter is clocked since its D intput is connected to ~V its Q output is high. ~owever, when FF 176 is reset its Q output on line 178 undergoes a high to low txansition. ~ine 17B is connected to the reset input o~ counter l80. When line 178 undergoes a 1~ to high transition the counter 180 is reset and prsvented from counting the pulses from oscillator 182 until line 178 undergoes a high to low transition~ ~n addition, a 2-position switch 190, sho~n for explanatory purposes as a me~hanical switch, is included. Durin~ programming when line ~3 is high switch 190 is in the position as shown. Thus, the limit-indicating pulses are clocked inko the counters 23 and 24, as previously explained. However, after programming when FF 92 is set and line 93 is low switch 190 connects line 183 to gates 98 and 9g 80 that the pulses from the first stage of counter 180 at 1 KIIz are cloeked into the counters 23 and ~4, ~ 2~ 75~325 The operation o ~he circuitry may best be explained with a specific example. Let it be assumed that the low limit is chosen to be 30 bpm, which corresponds to a 2 second int~r-val between pulses. Since the maximum count in counter 23 is 2048 and is clockable by pulses on line 183 at 1 KHz during programming the counter 23 is clocke~ to a count of 2048 -2(1000) = 48. Le~ the selected upper or high li~it ~e assumed to be 150 bpm, corresponding to an interval between beat pulses vf O.4 second. Duriny programming counter 24 is clocked to a count of 2048 - 0.4(1000) = 2048 - 400 = 1648. As previously explained during programming both FF 170 and FF 1~6 are held in a set state and therefore lines 171 and }78 are h~gh. FF
, 170 does not change state during pro~ramming irrespe~tive o~
the clocking beat pulses lS. Also~ since line 178 is high ..
counter 180 is an all 0 or reset state.
After programming is completed, i.e., line 93 goes low~ The first beat pulse 15 following programmin~, such as tx ~see waveform 173) clocks FF 170 which toggles ~since both J and K are high), i.e., switches to its reset state so that line 171 goes low and line 175 goes high~ When line 175 goes higher it resets FF 176. Consequently, line 178 goes lowO
The high to low transition on line 178 enables counter 180 to count the 2 RH2 pulses from oscillator 182. ~owever, the pulse~
on line 183, whieh are fea to counters 23 and 24 through switch 190 an~ ga~es 38 and 99, are at-a 1 XH~ rate. Thu~, the count in counter 23 which was programmed to 48 inc~ements is at a 1 KHz rate. Similarly, the count in counter 24, programmed to : 1648, increments at the same rate.
When the second pulse 15 arrives such as at time tx it clocks FF 170 so that line 171 ~oes high thereby settin~ F~
162 and F~ 1~6 and clocking FF 168. ~Iowever, when FF 168 i~

, ~ 75~3~5 clocked, whether or not alann 60 is activated depends on ~he time which elapsed between the irst pulse 15 ~at tx~ which reset F~ 170 so that line 171 went low, and ~he second pulse lS (at timc ty~ which sets FF :L70 causing li.ne 171 to go high, and thereby clock FF 168.
For the particular example Eor a range of 30 bpm to 150 bpm counters 23 and 24 were programmed ~o contain counts of 48 and 1648 respectively. If the interval bet~reen the first and second pulses 15, i.e~, ty ~ tx is not less than 0.400 second, corresponding to a rate not greate~ than 150 bpm, and is not greater than 2.000 seconds, corresponding to a rate of not le~s than 30 bpm, then before the secona pulse 15 is . received at time ty, FF 166 is clocke~, while FF 162 is no-t c3Ocked, so thak it remains set. Therefore5 when FF 168 is clocXed, since both inputs to Nor gate 167 are l~w, it~ outpu~
i5 high and therefore line 169 is hiqh, res~lting în the alarm 60 not being activated. However, if the heart beat rate is greater than the upper limlt of 150 bpm, e.g., 180 bpm so that the interval (~ - tx) between the first an~ second pulses 15 is only 0.333 sacond, only 333 pulses are clocked into counter 2~ which was set to a count o 164~. Consequently, its co~nt reache~ 1648 ~ 333 a 1981 when the second pulse 15 is received at time ty and therefore F~ 166 is not clocked. Consequently, line 166a is high,and the outpu~ o~ Nor gate 167 is low when FF 168 is clocked. As a result, alarm 60 i5 activated to ~ndicate an out-of-range condition.
On the other hand, if the heart beat rate i5 below the set 1~ limit of 30 bpm (represented by the count o~ 48 ~et in counter 23~, e.~., 20 bpm, the time interval t~ - tx between th~ irst and second pulses 15 is 3 second~. Consequen~ly, beore the second pulse 15 is received at time t~ more than -37~

! 75/325 2000 pulses have been clocked into counter 24, and it in turn causes FF 162 to ke clocked, so that line 162a goes high.
Consequently, when the second pulse 15 is received at time t~, the output of Nor gate 167 is low~ so that when F~ L68 is clocked line 169 is low activating alarm 60 to indicate the out-of-range conditionO
As shown in Figure 8 and a5 previously explained when counter 180 reaches a count of 4096 ~such as at time tz), which corresponds to 2048 pulses from its first stage on line 183 FF 176 is clocked so that its Q output on line 178 goes high~
resetting the count in counter 180 and stopping the counting of the pulses from oscillator 182, until line 178 goes low once more. Since each of counter~ 23 and 24 axe capabla o counting up to 2048, the original limits stored therein, eOg. ~ 48 and : 15 1648 respectively, are xe-established ~herein It should be pointed out khat after the first pulse 15 following limits' loading or programming, when ~ine 171 goes low ~such as at tx~ the J input to FF 170 is high and the K input is low. ~ine 171 remains hi~h irrespective of the appearance of additional pulses 15 at the clock input of FF 170, as long as the K lnput ls low. However, once line 178 goes high, such ag at time tz, the K input of FF 170 is high so that when ~he next pulse 15 is received it clocks FF 170, resetting it, which initiates a second compare cycle.
For the particular example in which counter 180 is clocked by 4096 pulses until it clocks FF 176, which corres-ponds to clocking sounters 23 and 24 with 2048 pulses, the number of heart beats or pulses 15 between updates ~compare cycles~
is as sho~m in the following table:

~3~-8Z~ 75/325 R~TE INTE~VAL BETWEEN HEART TI~E BETWEEN NO. OF ~IE~RT BEATS
~bpm) BEATS (PULSES 15 ) UPl:~TES ~PULSES 15 ) BETWEE~J
UPDATES
2p00 ms 4 sec~ 2

5 60 1000 3 3 100 600 2,,4 ~
120 500 2,~5 5 200 300 2.1 7 From the foregoing i~ ~hould thus be appreciated that in the arrangement, shown in Figure 8, the FFs 162 and 166 efectively replace the multistage or ~ultibit comparators 43 and 44~ respeatively9 ~hown in Figure lv However~ the saving in the number of stages, needed to determi~e whether the heart beat rate is within or outsi.de ~he ran~e, de~ined ~y the limits, i5 paxtially reduced by the need of FFs 170 and 1760 It should be appreciated by ~hos~ familiar with the art that, if desired, the limits, stored i~ ~he counters 23 and 24 in the arrangemen~ shown in Figure 8, may be retrans-mitted to the external unit 20, for verification, in a manner.
similar to the arrangement shown in Fi~ure 5. For example, during one compare cycle modulator transmitter ios ~see Figure 5) may be enabled rom the start of the c~mpare cycle tx until CQUn~er 23 reache~ a full count and line 161 goes hight thereby j enabling the modulator transmitter 105 to transmit to ~he external unit 20 a number of pulses corresponding to the difference between the maximum count which can be ~tored in counter 23, l2048) and the previously set low limit ~herein, such as or example 48, i.e., 200.0 pulses~ which wou~d indicate in the external unit 20 that the proper limit, namely 48 pulses, were stored in the counter 25~ Than, during a sub~equent compare cycle modulator tran~mitter 112 may be enabled to .: ' ~, , 75/325 transm:i t the pulses ~eing sul~plied ~o the high limit counter 24 until ~he latter reaches a full count, namely its output line 164 goes high~ In the par-ticular example in which it was assumed that ~he counter 24 ~as prestored with a count of 1648 pulses, 4~0 pulses would be transmitted to the external ~nit 20 which when displayed would indicate that the proper high limit, repres~nted by 1648 pulses, previously programmed into counter 24, have been properly stored therein. Clearly, other arran~ements ma~ be employed to transmit to the e~ternal unit 20 the limits stored in the counters 23 and 24, for v~rification purposes ~
Althouyh particular embodiments o the in~ention have .been described and illustrated herein, ît is recognized thak m~difications and variations may .~eadil~ occur to ~hose skilled ln the art and consequently, it is intended ~hat the claims be interpreted to cover such modifications and ~quivalents.

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Claims (29)

1. The embodiments of the invention in which an exclu-sive property or privilege is claimed are defined as follows:
   
   l. A system for monitoring heart beats of a subject, comprising:
   a heart beat monitor including heart beat sensing means for sensing the subject heart beat and for providing pulses corresponding thereto, first means including receiver means for receiving signals transmitted to said monitor from a source external thereto, said signals including signals defining at least a selected upper limit of heart beat rate, and memory means for storing said upper rate limit defining signals, received by said received means, circuit means responsive to said pulses for comparing their rate with said rate upper limit, stored in said memory means, and for providing an indication to said subject when the rate of said pulses exceeds the rate upper limit, and a power source means for powering at least said circuit means; and means external to said monitor for transmitting signals to said receiver means in said monitor, said signals including signals defining at least said selected rate upper limit, said external means including controllable variable means for controlling the rate upper limit defined by said signals.
2. 2. The system as described in Claim 1 wherein said external means include means for transmitting a preselected sequence of signals, defining a sync pattern, prior to trans-mitting signals defining at least said selected rate upper limit, and said receiver means in said monitor include means for identifying said sync pattern and for enabling said memory means to store the signals defining said rate upper limit only after said sync pattern is identified.
3. 3. The system as described in Claim 2 wherein said external means include means for transmitting following each sync pattern two sets of signals, one of which defines said selected rate upper limit and a one set defining a selected rate lower limit, the two rate limits defining a heart beat range, said memory means in said monitor include separate means for storing said rate upper and lower limits received from said receive means after the identification of said sync pattern, and said monitor's circuit means include means for providing said indication to said subject when the heart beat range thereof is outside said heart beat rate range.
4. 4. The system as described in Claim 1 wherein said power source means includes a first power source for powering at least said circuit means and a second separate power source for powering only said memory means.
5. 5. The system as described in Claim 4 wherein said external means include means for transmitting a preselected sequence of signals defining a sync pattern prior to trans-mitting signals defining at least said selected upper rate limit, and said receiver means in said monitor includes means for identifying said sync pattern and for enabling said memory means to store the signals defining said upper rate limit only after said sync pattern was identified.
   6. The system as described in Claim 5 wherein said external means includes means for transmitting following each sync pattern two sets of signals one of which defines said selected upper limit and a one set defining a selected lower rate limit, the two limits defining a heart beat rate range, said memory means in said monitor include separate means for storing said upper and lower rate limits received from said
6. CLAIM 6 ----continued receiver means after the identification of said sync pattern, and said monitor's circuit means include means for providing said indication to said subject when the heart beat rate thereof is outside said heart beat rate range.
7. 7. The system as described in Claim 1 wherein said monitor includes second means for producing a visual display of the rate per a selected unit of time at which pulses were sensed by said sensing means.
8. 8. The system as described in Claim 7 wherein said second means are powerable by said power source and include subject-controlled switch means for controlling the powering of said second means by said power source means,
9. 9. The system as described in Claim 8 wherein said power source means includes a first power source for powering at least said circuit means and a second separate power source for powering only said memory means.
10. 10. The system as described in Claim 9 wherein at least said first power source is a battery rechargeable by power received by said receiver means when signals are transmitted thereto from said external source.
11. 11. The system as described in Claim 1 wherein said system further includes means in said monitor for trans-mitting to said external means signals representing at least the limit stored in said memory means, and means in the external means for receiving the signals transmitted thereto and for providing an indication of the limit represented by said received signals.
12. 12. The system as described in Claim 1 wherein said monitor further includes selectively energizable means for providing an indication of the limit stored in said memory means.
13. 13. A system for monitoring heart beats of a subject comprising:
    a heart beat monitor including, heart beat sensing means for sensing the subject heart beats and for producing a pulse corresponding to each sensed heart beat, receiver means adapted to receive signals transmitted thereto from external means and for identifying in said received signals a first set of signals defining a rate high limit and a second set of signals defining a rate low limit, memory means coupled to said receiver means for separately storing therein the high and low limits, said limits defining a heart beat rate range and circuit means responsive to the pulses corresponding to the sensed heart beats and including indication means for providing an indication when the rate of the sensed heart beats is outside the rate range defined by said stored limits, and power means for powering at least said circuit means; and external means for transmitting to said receiver means signals including said first and second sets of signals defining said limits, said external means including means for separately selectively varying the signals in each set to vary the rate limit defined thereby.
14. 14. The system as described in Claim 13 wherein said monitor further includes selectively energizable means for displaying the sensed heart beat rate of the subject.
15. 15. The system as described in Claim 13 wherein said system further includes means in said monitor for trans-mitting to said external means signals corresponding to the high and low limits stored in said memory means, and means in said external means for receiving and utilizing the limits' indicating signals, transmitted thereto, to provide indications corresponding to the limits stored in the memory means of said monitor.
16. 16. The system as described in Claim 13 wherein said monitor's power means comprises a rechargeable battery, rechargeable by power from said receiver means when signals are transmitted thereto from said external means.
17. 17. The system as described in Claim 13 wherein said power means includes a separate power source for powering said memory means.
18. 18. The system as described in Claim 13 wherein said monitor includes selectively energizable means fox providing at least one rate indication corresponding to at least one of.
    the limits stored in said memory means.
19. 19. The system as described in Claim 13 wherein said external means include means for generating and trans-mitting a preselected sequence of signals defining a sync pattern prior to transmitting said first and second sets of signals, and said receiver means include means for identifying said sync pattern and fox enabling said memory means to store said high and low limits only after said sync pattern is identified.
20. 20. The system as described in Claim 19 wherein said monitor further includes selectively energizable means for displaying the sensed heart beat rate of said subject.
21. 21. The system as described in Claim 20 wherein said system further includes means in said monitor for trans-mitting to said external means signals corresponding to the high and low limits stored in said memory means, and means in said external means for receiving and utilizing the limits' indicating signals transmitted thereto to provide indications corresponding to the limits stored in the memory means of said monitor.
22. 22. The system as described in Claim 21 wherein said power means includes a separate power source for powering said memory means.
23. 23. The system as described in Claim 21 wherein said monitor includes selectively energizable means for providing at least one rate indication corresponding to at least one of the limits stored in said memory means.
24. 24. The system as described in Claim 21 wherein said power means includes first power means for powering said memory means and second power means for powering at least said circuit means exclusive of said memory means, and said monitor includes selectively controllable means for providing a visual indication to said subject of the limits in said memory means.
25. 25. The system as described in Claim 13 further including means for inhibiting said indication means from providing said indication when the rate of the heart beat sensed by said sensing means is below a preselected rate, which is lower than the rate defined by said low limit.
26. 26. The system as described in Claim 13 wherein said monitor is of the wrist type, and includes switch means for connecting said power means to said circuit means only when said monitor is placed on the subject's wrist.
27. 27. The system as described in Claim 24 further including means for inhibiting said indication means from providing said indication when the rate of the heart beat sensed by said sensing means is below a preselected rate, which is lower than the rate defined by said low limit.
28. 28. A system for monitoring heart beats of a subject comprising:
    heart beat sensing means for sensing the subject heart beats and for producing a pulse corresponding to each sensed heart beat, memory means for staring variably selected high and low limits which define a rate range;
    circuit means coupled to said memory means and to said sensing means for providing first and second signals when the sensed heart beats are at rates outside and within said range, respectively;
    power means for powering at least said circuit means;
    output means coupled to said circuit means for provid-ing an out-of-range indication when said circuit means provides said first signal;
    
    display means for controllably displaying an indication represent-ing any of the rate of the sensed heart beats or one of said stored limits;
    and external means for transmitting signals representing said high and low limits, and further including receiver means, coupled to said memory means, for receiving said transmitted signals and for storing the high and low limits, represented by the received signals, in said memory means.
29. 29. The system as described in Claim 28 wherein said system further includes means for transmitting to said external means signals indicative of the limits stored in said memory means.