CA1104264A - Data processing system with improved bit field handling - Google Patents

Abstract

DATA PROCESSING SYSTEM WITH IMPROVED
BIT FIELD HANDLING
Abstract of the Disclosure Hardware facilities are described whereby the handling of data represented by variable length fields of bits may be made faster, use less storage and be less prone to errors in programming. The bit fields are handled independently of the natural storage addressing elements and boundaries. Data may be packed into main storage with the highest efficiency, and manipulated with a fast and efficient hardware instruc-tion set.

Description

- INTRODUCTION
: This invention relates to the handling of bit fields : independently of natural storage addressing elements and boundaries.
A preferred embodiment of the invention is embodied within an electronic data processing system, various aspects of which are described in detail in the following patents.
..: U.S. Patent 4,047,161, issued September 6, 1977, and assigned to.the assignee of the present invention, describes a data processing system.
U.S. Patent 4,038,642, issued July 26, 1977, and assigned to the assignee of the present invention, describes the preferred form of the controls associated with the present processor, I/O devices, channel and I/O interface for transferring data to and from the I/O.devices.

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, .,: ~ . ~, , : -' " . " ' ~ , 110~264 1 U.S. Patent 4,037,214, issued July 19, 1977, and assigned to the assignee of the present invention, describes the preferred form of the addressing controls associated with the present processor and main storage.
The following patents, each of which is assigned to International Business Machines Corporation, describe various aspects of an exemplary system in which the present invention may be embodied:

1 U.S. Paten_ Number Date of Issue 4,042,913 August 16, 1977 4,037,215 July l9, 1977 4,042,911 August 16, 1977 4,050,060 September 20, 1977 4,038,645 July 26, 1977 4,035,779 July 12, 1977 4,037,207 July 19, 1977 4,041,062 August 9, 1977 4,038,641 July 26, 1977 4,053,950 October 11, 1977 4,050,094 September 20, 1977 ~4 In typical data processing systems, as exemplified by the above references, the contents of the main storage are divided into small groups of bits for addressing purposes.
These groups (or "elements of addressability") may be, for example, bytes, as in the IBM* System/360 or words (of two bytes each) as in the IBM 1130 System. It is important to note that all storage addressing means can only reference information located at the boundary of an element of address-ability and that data are fetched or stored from main storage as single or multiple elements of addressability.
Users and programmers of prior art data processing systems must thus operate under considerable difficulty when attempting to deal with main storage operands which are not aligned with the boundaries of elements of addressability or which are not the same size as one element, or some integral number of elements of addressability.

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*Registered Trade Mark 11~)4264 1 Historically, interrogation (that is, reading) of a

2 general bit field implied loading the word(s) or byte(s)

3 containing the information, and then two shifts (or the

4 equivalent) to isolate and align the field of interest.
Emulation and interpretation techniques make heavy usage of 6 such techniques.
7 The inverse operation (storing a general bit field) 8 historically required such extensive manipulation that data g was often not packed (with inherent storage inefficiency) if it would subsequently require random updating.
11 The prior art describes partial solutions to this problem 12 in that it does describe means whereby the leading edge of an 13 unaligned operand may be accessed. However, the prior art 14 handles situations in which the operand does not overlap the boundary of the next element of addressability. This means 16 that all directly accessable unaligned operands must lie -17 totally within a single unit of addressability. It should be 18 evident that, although this lessens the user burden (by 19 reducing the frequency with which a programmer has to recompute addressability) it does not eliminate the problem. The prior 21 art, in contrast to the present invention, does not permit 22 the general accessing of unaligned bit fields of variable 23 length without regard for boundaries of elements of address-24 ability in the ~ystem.
This invention overcomes the above difficulty by enabling 26 one to easily handle unaligned bit fields of varying lengths 27 with a single machine instruction. It provides storage 28 optimization for information represented as bit fields of 29 arbitrary length (up to a predetermined maximum length) with-out cor,cern for byte or word boundaries.

11~4z~;~

2 In accordance with one preferred embodiment of this 3 invention, apparatus is provided for recognizing and executing 4 four new instructions. Three of the instructions are "load"
instructions which will cause a particular bit field to be 6 loaded into a specified register from memory. The fourth 7 instruction is a "store" instruction which will cause a bit 8 field that is contained in a specified register to be stored 9 into memory. In the preferred embodiment, each of the instructions contains, in addition to the operation code, 11 (1) a specification of a machine register that is the source 12 or destination of the bit field, (2) a specification of a 13 register which contains a memory byte base address and (3) 14 a specification of the length of the bit field (particularly, in this preferred embodiment, a value that is one less than 16 the actual length of the bit field). The specific bit loca-17 tion in memory of the beginning of the bit field is attained 18 by summing the contents of the byte base address register with l9 the contents of a particular predetermined machine register which specifies the amount by which the bit field is offset 21 from the base address in memory. In the preferred implemen-22 tation of this apparatus, means are provided for appropriately 23 updating the contents of the displacement register when load-24 ing or storing successive variable length bit fields.

BRIEF DESCRIPTION OF DRAWINGS
26 In the drawings:
27 FIG. 1 is a block diagram of a data processing system in 28 which the present improvement may be advantageously incorpor-29 ated;

~1~42~i~

l FIG. 2 shows the organization of FIGS. 2A - 2H which 2 latter figures illustrate the major components and data flow 3 of the preferred form of the processor of FIG. l;
4 FIG. 3 is a diagramatic illustration of the primary components of the processor task management system;
6 FIG. 4 is a map of the preferred form of the stack 7 registers;
8 FIG. 5 is a schematic diagram showing the interconnection 9 of various level registers and an interrupt mechanism utilized in the processor;
11 FIG. 6 is a schematic diagram of the read only storage 12 (ROS) controls of the processor illustrated in FIGS. 2A - 2H;
13 FIG. 7 shows the preferred format of the microprogram 14 instructions;
FIG. 8 shows the basic timing signals for the micro-16 program execution;
17 FIG. 9 is a map of the various areas in the read only 18 storage of the present processor;
19 FIGS. 10 and 11, respectively, illustrate the micro-program routine which is executed to perform an exemplary 21 machine level instruction "add immediate" and the basic 22 timing cycles for the add immediate routine;
23 FIG. 12 illustrates the timing of storage cycles;
24 FIGS. 13 and 14 are timing diagrams which illustrate the execution of the last microprogram word in each machine 26 level execution routine;
27 FIG. 15 illustrates certain of the conditional branch-28 ing logic which is utilized in the preferred embodiment of 29 the present improvement;

11~42~;4 1 FIG. 16 illustrates the format of the four new instruc-. .
2 tions realized with this invention;
3 FIG. 17 shows an example of the use of the "load field 4 and increment" instruction to access variable length bit fields within packed data; and 6 FIG. 18 describes the microcode which may be used to 7 implement a preferred embodiment of the invention in the 8 exemplary data processing system.

t4~

GENEIU\L Dl~SCRIPTION OF THE SYSTEM
2 ` .
3 ~'igure 1 is an o~erview block diagram of a preferred 4 system within which the present.improvement is incorporated.
The central proccssing unit (CPU), or processor 1, 6 is the primary element of the system and is shown in more 7 detail in Figure 2A-2~]. It executes instructions and controls 8 activity on the two primary in~eraces of the system, the 9 input/output ~I/o) Interface 2 and the storage/translator 10 interface 3.
11 A plurality of input/output (I/0) devices 4-1 to 4-n 12 are coupled to the I/0 interface 2 by way of respec~ive device .
13 attachments 5-1 to 5-n. The device attachments 5-1 to 5-n, 14 together with.the CPU 1, control the transfer of data.between .. _.
.the CPU l and the I/0 devices, 4-1 to 4-n.
16 The storage translator interface 3 couples the CPU 1 17 to u main storage 8 and to a relo~ation translator 9. An 18 interPace 11 couples the relocation txanslator 9 to an 19 asynchronous storage 10. The main storage 8 inclu~es an inner ~ .
storage section 14 and an outer stoxage sectio~ 15. An inter-21 face 12 couples the CPU 1 to the main storage 8 for.controllins .
22 the transfer of data between the CPU and the inner storage 14.
23 An outer storage interface 13 couples the.main storage 8 ~o 2.4 the relocation translator 9 for controlling the transfer of data between the CPU 1 and the outer storage 15.
26 An operator console 6 is coupled to the CPU 1 by way o~
2~ an interface ?.
28 The inter~ace 2 includes an I/0 address bus, an I/0 29 data bus, and I/0 interface control signals which will be described in ~reater detail with respect to Figure 2. The Docket BC9-?6-022 -9-6~ -1 interface 3 includes a main storage bus and CPU/translator 2 control signal busses. The interfaces 12 and 13, respec-3 tively, provide a path for inner storage control signals and 4 outer storage control signals during data transfers. The interface 11 includes a data bus out and a data bus in, 6 together with interface control signal lines. These inter-7 faces are briefly described below.
8 CPU Data Flow (FIGS. 2A - 2H) g The CPU 1 includes an arithmetic and logic unit (ALU) 51 (FIG. 2E) of conventional construction. A pair of input 11 registers are provided for the ALU 51, i.e. the WA register 12 52 and the Y register 53, which registers are coupled to the 13 ALU 51 by way of buses 54 and 55, respectively. The ALU 51 14 includes an output bus 56 which is coupled to the processor bus 57 by way of an AND gate 58. The processor bus 57 is coupled 16 to the registers 52 and 53 by way of AND gates 60 and 61 to 17 provide input data to the ALU 51.
18 The processor bus 57 acts as the main data bus for both 19 source and destination data. Therefore, each of the function-al components of the processor, which acts as the source, is 21 coupled to the processor bus 57 by way of an AND gate; and 22 each functional component of the CPU 1, which acts as a 23 destination, i8 coupled to the processor bus by way of a 24 respective AND gate. Most of the functional components of the system act as both a source and a destination for data;
26 and, therefore, are coupled to the processor bus 57 by both 27 source AND gates and destination AND gates.
28 Thus, the processor bus 57 is coupled to a Z register 29 65 by way of a destination AND gate 66 and a source gate 67, 2~
1 , , to a processor storage data register 70 by way o~ a destination 2 ~ND gate 71 and a source AND gate 72, to a counter 75 by way 3 of a destination AND gate 76 and s'ource'AND gate 77, to a 4 register stack 80 by way of a destination AND gat,e 81 and

5 ' a ~ource AND gate 82, to an address key register 85 by way

6 of a destination AND gate 86 and a sourcé AND gate 87 tQ a

7 hardware level status register 90 by way o~ a destination

8 AND gate 91 and a so~rce AND gate 92, and to a processor

9, storage address registex'95 by way of,a destination AND gate 96 ;~nd a source AND gate'97.
11 ~he processor bus 57 is coupled to the console 6 ~Fig. 2A) 12 b~ way of a source ,AND gate 100 and interface bus 7a. ,Data is 13 directed from the processor bus 57 ~o the cohsole 6 way way of 14 the AND gate 66, the Z register 65, and the interface bus 76.
An operation ~O) register 101 (F~g~ 2F~ is c~upled to the 16 processor bus 57 by way of a sou~ce AND gat~ 102. Operation 17 codes are stored into the OP Reg. 101 from the processor 18 storage data register 70 by way o~ an AND gate,103. A'stack 19 addre,ss register 105 (Fig. 2G) is coupled to the processor bus 57 by way of a destination AND gate 106. A current 21 instruction address register 107 is coupled to the processor 22 bus 57 by way of a source AND gate 109. The input of the 23 register 107 is coupled to the output of the stack registers 24 80 ~y way of a bus 108. A stora'ge protect array 110 (~ig. 2H) ' is coupled to the'processor bus'57 by destination and source 26 ~ND gates lll;and 112.
27' A program status word (PSW) register 115 has its output 116 28 coupl~d to the processor stDrage ~us 57 by a source AND gate 29 117. Inputs to the'register 115 are provided from various system check input lines 120, from a key compare register 121 Docket BC9-7G-022 . ~~ ~' `I

lit~426~ . ' i and ~rom a storage check condition bus 13~. ' 2 Inputs to the key compar~ register 121 are provided by the 3 storage protect array register 110 by way,of the output bus 125 4 of array 110 and from a key select iogic circuit 126 by way of a bus 127. The output 128 from the register 85 is coupled to 6 one input of the circuit I26. The second input 129 to the 7 circuit 126 is provided by cycle steal protect latches 130 8 (Fig. 2D). The input bus 129 fro~ the latches 130 is also g coupled to the register 90. The output'l27 of the key select logic circuit 126 is also coupled to the main storage 8 and 11 relocation translator 9 by way of the output bus 127 which 12 forms a part of the storage/translator interface 3.
13 The interface 3 also includes a synchronization bus 135 14 (Fig. 2H), the check condition bus,13'6, an address bus 137, and I5 ' input and output buses 138 and 139. The output 140 of the 16 processor storage address register 95 ,is coupled to' the address , 17 ' 'bus 137 by way of an AND gate 141. The cycle steal storage I8 address register 142 has its output 143 coupled to the address 19 bus 137 by way of an AND gate 144. , A zero detect,circuit 150 (Fig. 2C) has its input coupled 21 to the processor bus 57 and its output 151 coupled to a 22 conditional branching logic circuit 152 (Fig. 2A). The output 23 151 of the zero detect circuit 150 is ,also coupled to the input 24 of a result indicator'circuit 153 (Fig. 2G). A second input 154 25 to the result indicator circuit 153 is derived from the output 26 Of the ALU 51.
27 The processor bus 57 also forms an input to the conditional 28 branching logic circuit 152.
29 The output 160 of the counter 75 (Fig. 2F) provides inputs 30, to a Halt I/O dec,~oder 161 and to the cycle steal storage addresses Docket ~C9-76-022 -12-11~4~
.

1 register 142. The ouput 162 of the decoder 161 1s coupled to 2 an inter,face gate control circuit 239 ~ig. 2D). The input 3 data bus 138 from maïn storage is coupled to the processor'storage 4 data register 70 (Fig. 2E) by way of an AND gate 165 and to a cycle steai storage data register 166 by way of an AND gate 167.
6 The output 168 from the processor storage data register 70 is 7 coupled to the output data bus 139 to main store by way of an AND
8 gate 169. The register 166 is co~pled to the bus 139 by way 9 of an AND gate 170. The outputs of register 70 ~nd 166 are also coupled to a storage parity check 171 ,(Fig. 2F). The 11 circuit 171 provides parity bits to the output data bus 13~ when 12 no parity error exists and provide,s an output signal on ;;ne 173 13 when a storage parity error is detected. ' . , 1~ A mask register 175 (Fig. 2A) is coupled to the processor bus 57, bits 12~, 13, by way of input and output gates 176, 16 177. The output 178 of the mask register 175 is also coupled 17 to a current level register by way of driver circuits 180 18 . an2 a bus 182a. ' ' , ' 19 A selected level register 185 is coupled to the processor bus 57, bits 14, 15, by way of an input. An output 185a 21 of register 185 is coupled to the stack SAR 105 (Fig. 2G) by ,i2 way of a gate 185b. The output 185a is also coupled to the 23 current level register 181 by way,of decoder circuits 190 24 and the output 191 of the decoder circuits 190. The output 192 of the current level register 181 is coupled to the Read 26 Only Storage Address Register (ROSAR) 193 (Fig. 2B) of a micro-27 progxam control mechanism 200 of the CPU 1. The output 181a 28 of the register 181 is coupled to the stack SAR 105 by way 29 of gate 181b after being encoded from four to two bitg by ~0 encoder 181c.
Docket BC9-76-0 2~ ~3~

i4 1 The microprogram control mechanism 2Q0 includes a Read Only .
2 Storage (ROS) 201, which is coupled to the pracessor bus~ 57 by 3 way of the ROS output da~a register 202 and source AND gate 203.
4 A second output 204 of the ~OS output data register 202 is coupled to a'source decoder logic circuit 205, a destination 6 decoder logic circuit 206,' a storage control decoder logic 7 circuit 207,'an ALU function decoder logic circuit 208, other 8 control decoder logic circuits 209, and the ROSAR 193.
9 ' Address selection for the ROS 201 is provided from the ROSAR 193 via bus 212 and an address.decoder logic circuit 213.
11 ' A link register 1 210 and a link register 2 211 have t~eir ' 12 inputs coupled to ROS,193 via bùs 212 and have their outputs 13 214, 215'. The propessor storage data register 70 (Fig. 2E) 14 provides another input to'ROSAR 193 via bus 73. The con~.itional branching logic 152 provides an inpuL to ROSA~ lg3 via DUS 216.
.
16 The source decoder circuits 205 includes output source 17 control lines 231, which are utilized to'control the ~arious 18 source AND gates ~such as gate 102) to access source data. The 19 destination decoders 206 include output destination control lines 232, whicn control various destination AND gates ~such as gate 76) 21 to direct destination data to'the proper registers or other com-. . .
22 ponents. The ALU'function decode,r circuits 208 include ou,put 23 ' ALU function control lines 233, which are utilized to control a4 the various functions of the ALU ~uring processor cycles. These 25' destination controls, source controls and ALU function controls 26 will be described in greater detail below, insofar as they are 27 related to the improvement of the present appiication.
28 The storage control decoder logic circuits 207 have an 29 output 235 coupled to a storage control circuit 236. The circuit 236 includcs a second input 237 derived from tllc decodcr Docket ~cg~6-0'2a -14-110~4~

1 circuits 209 and a third input 238 ~rom the channel interfacc gate 2 , control circuits 239 ~Fig. 2D). This bus 238 is bidirectional 3 ~ and is utilized during data transfers between the I/O devices 4 ~ ~ 4-1 to 4-10 and the CPU 1. The interface bus 12 and the synchronization bus 135 are both coupled to the storage controls 6 logic circuit 236.
7 The decoder circuits 209 have a state control output 240, `8 a sample interrupt request output 241, and a check condition g output 242. In addition an output 243 from the decoder circuits io 209 is coupled to a clock controls circuit 245 ~Fig. 2C). A
11 crystal oscillator 246 provides signals to a frequency divider 12 247 which in turn is coupled to the input of the clock controls 13 circuit 245 to provide the timing pulses for the data flow and 14 controls of the CPU 1. These timing pulses to the CPU data flow ~5 ~nd controls are provided by way of output lir,~s 248-1 - 248-N
16 of the clock con$rols circuit 245. The synchronization bus 17 135 is coupled to the clock control circuit 245 and is a two-way 18 communications bus for this purpose.
1~ ~he channel hardware 250 (Figs. 2A, 2D) will now be d~scr~bed in detail. The channel hardware 250 includes a ~ uFality of driver and receiver circuits 251 to 256, inclusive, 22 ~hich are coupled to the ~arious lines and buses of the I~O
~3 lnte~face 2. Thus, the receiver 251 is coupled to a request 24 iP bus 261, bits 0^3. The receiver 252 is connected to a ~ ~equest in bus 262, bit 16. A group of receiver and driver 26 circuits 253 are connected to the poli line 263, the poll return 27 line 264 and the burst return line 265; The driver circuit 254 28 is coupled to the pol. identifier bus 266, bits 0-4. The 29 driver and receiver circuits 255 are coupled to lines 267-1 to 267-lO, inclusive, which are the service gate line, the D~ckct BC9-76-022 -15-1 service gate return line, address gate line, address gate return 2 line, data strobe line, ho,ld or m~ch~ne check line, system 3 reset line, word/byte indicator line, input/output indicator 4 line, and,cycle steal status bus, bits 0-3, respectively. The receivers 256 are connected to a condition code input'bus 268, 6 bits 0-2. The interface 2 also includes a,data bus 269, a~
7 address bus 270, bits 0-15, an addre~s'bus bit 16 line 272 and a 8 power on reset line 271.
g . The data bus 269 is coupled to ~he input of an I/O
interface parity checker and generator circuit 275. The circuit l 275 includes a first output 276 which provides parity bits ~2 . to the I/O interface data bus 269 when no error exists in data transmitted from an I/O device into the CPU l'. The circuit 14 275 includes a second output 277'which provides a signal when a.pari*y error,occurs on the data bus 269. Thë data bus 269 is 16 aleo coupled to the processor bus 57 by way of a source AND .
17 ' gate 278. The data bus 269 i$ coupled to the input of the.cycle 18 steal s~orage data reglster.166 by way'of an AND gate 280 and is :19 co~pled to the output of the cycle steal storage data register 166 by way of an AND gate 279. The data bus 269 is coupled to 21 the output 55 of the Y register 53 by,way of an AND gate 281.
2i The address bus 270 is,coupled to the, input of the cycle 23 steal storage address register 142. The address bus 270 is 24 , also coupled,to the output 160 of the counter.75 by way of a 25 ' gate 273.
26 The output 182~ of receiver circuits 251 is coupled to 27 an input of the current level register 181 via AND gate ~8 187c, the other input of which is the mask dr.iver output 182a.
29 ' The driver and receiver circuits 252, 253, 254 are coupled to a poll sequence control circuit 285. Thç current level Docket BC9-76-022 -16-~lV~

. .
,1 ~egister 181 prouides another input to the circuit 285 via 2 output 181a. A request acknowledge line 286 provides a 3 further input to the poll sequence control circuit 285. The 4 poll sequence control circuit 28S is also coupled to the interface gate control circuit 239 by way of a, line 289. An 6 interface sequence ad t~meout check control circuit 288 is ,~ 7 coupled to the poli sequence control circuit 285 by way of a ~8 line 287. The power on reset line 271 provides an additional g input to the circuit 285.
Lines 290-1 to 290-10 couple the driver and receiver 11 circuits'255 to the in,terface gate control circuit 239.
12 The processor bus 57 is a 16 bit wide bus for conveying 13 information between source and destination elements in the CPU
14 data flow as selected by the,microprogram controls.
The operation register ~OP REG) 101 is a 16 bit register 16 which contains the first word of the instruction, including 17 reg~ster address arguments for the registe~ stack 80, during .
18 instruction decode. It i8 also used'as a temporary data register , 19 when not'holding the fi~st word of the instruction. Its output i8 a source element to the processor bus $7,. It receives its 21 ,input from'the storage data register 70.
22 The ALU 51 is a 16 bit element which performs arithmetic 23 and logical functions as specified by the instructions. Its 24 output 5.6 is a source element to the processor bus 57. It receives its input from the WA and the Y registers 52, 53.
26 , The WA register 52 is a 16 bit register which is the primary 27 in~ut'to the ALU 51 for arithmetic and logic operations. It 28 receives input as a des~ination eiement from the processor bus 57.
29 The Y register 53 is a 16 bit register which is the secondary input to the ~LU 51 fox arithnietic and logic operations.
Docket ~C9-76-0 22 -17-2t~4 1 In conjunction with the ~7~ xegister 52, it performs shifting on 2 double word shift operations. It receives input as a 3 destination element from the processor bus 57. This register 53 4 also provides the data'path'for out~ound data to the I/O data bus 269 for direct program control I/O operations.
,6 . The processor stoxage data register (PROC SDR1 70 is a 7 ' 16 bit register through which all data to or from main storage, 8 except cycle stealing data, is gated. The first word of every g instruction that is fetched from main'storage 8 i~ gated through the PROC SDR register 70 to the OP register 101. This 11 reg,ister 70 is also used as a temporary data register during 12 other processor operations. Theref~re; it can receive input 13 as a destination element from the processor bus 57 and outputs .
14 as a source element to the processor bus 57.
I5 ;The cycle steal storage,data register ~CS SDRj 166 is a 16 16 bit register through which all data is gated to'and from 17 main storage 8 v~a the I/O,~ta bus 269 and either the in or out 18 storage bus i38 or 139 during cycle steal operations.
''19 The low order 8 bits of the 16 bit counter (CTR) 75 are used as a counter for keeping track of various processor '21 . operations. It is also used as a temporary register for other 22 processor operations. Therefore!;it is a source and destination 23 element for the processor bus 57. It is also used to hold the 24 device,address for device selection and the I/O command is gated via gate 273 to the I~O address bus 270 during direct ': 26, program,control operations.
27 ~ The processor storage address register ~PROC SAR) 95 is a 28 16 bit register used primarily to hold a main storage address.
29 Its contents axe ga,ted via gate 141 to the storage address , bus 137 for storage~accesses during normal proccssing and Docket BC9-76- 022 -18-4Z~
, .
1 direct program control operation,s. It is also used as a 2 té,mporary data register when not needed for addressing main 3 storage. , ' , 4 The cycle steal storage address register (CS SAR) 142 is a 16 bit register used to hold a main ,stroage address transferred 6 v~a the I/O address bus 270 from the I/O device during cycle 7 steal data transfer operations. It is gated via gate 144 8 to the storage address bus 137 for cycle steal storage accesses g only.
The primary purpose of the 16 bit Z register 65 is to '~
~,11 hold the data for the operator data display indicators (not 12 shown) of the console 6. It is also used as a temporary 13 register for other processor operations~ It is a source and 14 des~ina~ion element for the processor bus 57.
~he register array (stack) 80 (Fig,. 3) is an arrav of mono-16 lithic latches used to hold the registers, level status, 17 address keys and instruction address for each of the four 18 ' interrupt levels. It also contains certai'n working registers '-19 used by the microprogram, i.e., the TEMP, TEMPl-3, DBUF, SOAl, SOA2, current }evel save and AXR save, organized as shown in ~21 , Fig. 3.
, 22 The TEMP and TEMPl-3 registers contain temporary data used 23 by the microprogram during normal'processing. SOAl contains 24 the man,ually entered address to be used for stop-on-address operations and SOA2 contains the console storage key in the low 26 three bits, the remaining bits are zero. The DBUF register 2~ ~s the console data buffer. The contents of this buffer drives 28 the data display indiGators (not shown) on the console 6. The 29 currçnt level register contains the level that was active when stop state was entcred. The AYR save register contains a copy of Doc~et ucg-76-n22 -19-llV~

1 the current level AKR.
2 The data in the LSR, AXR and IAR registers of the stack 80 3 or the current level are alsPo held in the corresponding hard-4 ware registers 90, 85, 107 for performance reasons, i.e., to reduce the number of stack accesses. ~he stack 80 of the 6 preferred embodiment is comprised of two 64X9 arrays connected 7 in parallel to form a 64X18 array.
8 The stack address register 105 1s a six bit register 9 ~or address~ng the stack 80. Inputs to register 105 are provided from an incrementer 320 via a stack iink register ~
il 321 and a destination gate 322, the selected level register 12 185 via bus 185a and gate 185b, the current level register 13 181 via bus 181a and gate 181b, from the OP register lOL~
14 vla bus lOla ~nu ~dte lOlb, and the processor ~us 57. The ~tack address register 105 is loaded from the processor bus 16 57 ~ia gate 106.
~7 The hardware level status register ~LSR) 90 is a 16 bit 18 hardware register used to hold the current level status.
19 During prscessing on a specific level, the contents of the 2D hardware register LSR 90 change as the result of arithmetic 21 ~ and logical operations. The current level LS~ in the reglster 22 stack 80 remains unchanged until a le~el exit occurs, ~t 23 this time, the hardware LSR register 90 contents are placed 24 $nto the LSR register in the register stack 80 of the level being exited; and the new level status ~rom the register 26 ~tack 80 is placed into the hardware LSR register 90.
..
.

Docket ~C9-76-0 22 -20-.. . .. . . .

11~)4.2S~ ; .

1 , Certain of the contents of the LSR register 90 are as 2 follows:
3 TABLE~
4 Level Status Register Bit Neaning 6 0 Even Indicator 7 1 Carry Indicator ~
8 2 Overflow Indicator Result Indicators g ~ Negative Result indica.~or 4 Zero Result Indicator 11 8 Supervisor State . .
12. 9 In Process- ; State Controls 13 10 Trace 14 11 Summary Mask The result indicators are used by software for decision- -16 making.
17 The even, carry, and overflow indicators are also used 18 by I/O operations to hold the condition codes sent to the 19 processor 1 by the I/O devices 4-1 to 4-n.
During an I/O instruction execution the even, carry and 2~ over~low indicators are assigned the following condition code 22 alu~:

', ' ' ' '~' . ' .

; - .

Docket ~C9-76-022 -2i-.

~1~J4~6~ .

1 ' TABLE 2 2 Condition Code Even Carr~ Over~low Meaning 3 . 0,' . 0 0 0 .Device.N~t Attached 4 l , 0 0 1 Busy 2 0 l , 0 Busy ~fter Reset 6 3 0 1 1 Command Reject 7 4 l 0 . 0 Intervention.
8 ~ Required - 9 ' 5 l 0 ' 1 Interface ,Data Check 6 l l 0 Controller Busy 11 7 l l l Satisfactory , 12 During interr_~ acceptance all condition codes are " 13 reported by the device. The even, carry and ov,erflow indicators..are assigned the following condition code val~es:

16 Condition Code Even Carry Overflow Me&:~ing . , 17 0 0 0 Controller End 18 l 0 0 , . . l . ,PCI
19 2 . 0 . l .. 0 Exception 20 ' '' 3 0 l , - . 1 ' Device End ,.21 l 0 . 0 Attention : 22 5 .l . . 0 , l. Attention and 23. . - . , . . .PC.I
24 6 , , ` l 0 Attention and ' .' ' , Exception ' ' 26 ' 7 l . l l . Attention and - 27 . . Device End , 28 where PCI is a program controlled intcrrupt.
: . ...
' Docl;'e~ ncs - 76-~.22 -22-, .

4~6~ .
1 ' TABLE
2 Level Status Register Bit De-finitions 3 Bit 4 0 Even Indicator----- Set to one if the low order bit of the ,result is zero; otherwise 6 set to zero.
7 1 Carry Indicator--- Set to one if thc result of add or 8 ' subtract operations cannot be 9 ' - repre-.ented as an unsigncd number;
otherwise sët to zero.
11 2 Overflow Indicator- Set to one if the result o~ an 12 ' arithmetic operation cannot he 13 represented as a signed number, 14 otherwise set to zero;
3 Negative Indicator- Set to one if bit 0 of the result is - -' 16 one; otherwise set to zerc.
17 4 Zero Indicator---- Set to one if the result i all zeros;
18 otherwise set to zero.
19 8 Supervisor State-- Set to one whenever the processor 1 enters supervisor state. Supervisor 21 ' state is entered when: ' 22 . - A supervisor call instruction 23 is executed.
24 ~ ' - A class interrupt occurs.
_ An I/O interrupt is accepted.
26 9 In Process-~ - T,his bit is set or reset by the 27- corresponding bit in the LSR o~ the 28 ' storage ~evel status block (LSB) when-29 ever the load level status block ~LLSB) instruction is executed. The LLSB
Dockct BC9-76~022 -23--42~4 8it 2 loads an LSB from storage 8 into 3 ` , the designated level L5B in the 4 ' stack 80.

10 Trace~ ---- This bit is set or reset by the 6 ~ corresponding bit in the LSR7 , register of the storage LSB,when-8 ever the,local level status block g instruction is executed. The LLSB
loads an LSB from storage 8 into

11 ,' the designated level LSB in the

12 stack 80.

13 11 Summary Mask---------- When the summary mask = 0, all 1Y . priority nterrupts on all leve7s i5 , are disabled. When the summary 16 , mask = 1, all priority ir.terrupts 17 ' on all levels àre enabled. The 18 .. ~ummary mask is set to one (enabled) ~9 ' by the following:
, , - Execution of the enable 21 ' instruction with bit 15 = 1.
22 -'- . - System Reset, Power-On Reset, 23 IPL.' 24 - Execution of an LLSB instruction 'with bit 11 of the storage LSR -26 1- , ! ' 27 , ~ - Acceptance of a priority 28 , interrupt on the interrupted to 29 level.

D~c~et LC9-76- 022 -2~-1 , The summary mask is set to zero (dis-2 abled) by the following:
3 - Execution of the supervisor call 4 ' (SVC) instruction.
. , ' , - Execution of the disable instruction 6 with bit 15 = 1.
7 . - Any clas,s interrupt:
8 Machine Check Program Check ~10 . Soft Exception Trap 11 P,ower Thermal Warning 12 ' Supervisor Call 13 Trace

14 Console - Execution of.the LLSB instruction 16 wi~h bit 11 of the storage LSR = 0.
17 The processor 1 does not regard numbers'as either signed or 18 unsigned, but performs the designated operation on the values 19 presented.~ All indicators reflect the result of the operation.
. This allows the programmer to test results for the type of 21 operation performed.
22 The processor stat~s word (PSW) register 115 is a 16 bit 23 registe,r which contains error and exception information that 24 causes a program check, machine check, soft exception trap, or power thermal warning class interrupt to occur. Three 26 status flags are also contained in the PSW register 115. The 27 PSW register 115 is set by hardware and microprogram-detected 28 conditions.
- . ~ .

Dockct BC9-76-022 - -25-~1~4Z6~ .

1 ~ABLE 5 2 . Processor Status Word 3 Bi.t Meaning - 0 Specification Check . 1 Inbalid Storage Address 6 Program Check 2 Privilege Violate 7 3 Protect Check . 8 4 Invalid Function teither program g chec'~ or soft exception) .
Floating Point Exception 11Soft Exception Trap 6 Stac~ Exception 12 7 Reserved - : ~
13 8 Storage Parity Check .
I4Machine Chee~ 9 ~eserved .:
~PU Control Check ..
16 - 11 I!o Check 17 12 Sequence Indicator 18Status Flags 13 Auto IPL
19 4 Translator Enabled 20: Power/Thermal 15 Power/Thermal Warning 21 The address key register (AKR) 85 (Fig. 2G) is a sixteen 22 bit hardware register used to contain the contents of the 23 c~urrent leveI AKR during processing on that particular level.
24 The AKR register .85 provides the address key which is compared in circuit i21 against the protect key in the stQrage 26 protect array 110. This is done for each storage access 27 except for cycle steal operations~ The instruction space key - -28 (ISK) field of the AKR is also used as the console address key 29 for any manual storage accesses from the console 6.

Docket BC9-76-022 -26-2~

.

2 Address Key Register 3 Bit Meaning *
4 0 . ; Eguate Operand Spaces Operand 1 Key bit 0 6 6 Operand 1 Key,bit 1 7 7 Operand 1 Key bit 2 8 9 Operand 2 Key bit 0 9 10 Operand 2 Key bir 1 `10 11 Operand 2 Key bit 2 11 13 Instruc,tion Space Key bit 0 12 14 Instruction Space Key bit 1 13 15 Instruction Space Key bit 2 14 The current lnstruction aadress register (iCIAR) 107 (Fig. 2G) contains the address of the instruction being 16 executed. The CIAR register 107 ~s loaded at the beginning of 17 each instruction. During the execution of the instruction, 18 the leyel IAR in stack 80 is updated to the next instruction 19 address. Should a class interrupt stop the current instruction from being fully executed, the class interrupt is handled, 21 then the CIAR register 107 is used to readdress the interrupted 22 instruction which is executed again.
23 The st~ protect array 110 ~Fig. 2G) consists of the 24 ' thirty-two storage key registers (not shown). The array is enabled whenever the storage protect feature is installed 26 and enabled. Each register contains the protect key and the 27 read only bit for controlling a two thousand forty-eight byte 28 block of storage 8. The set storage key instruction sets the 29 key and read only bit into a specific storage key register.
~ The copy storage key instruction reads out a specific storage Docket BC9-76-022 -27- ~

"

~1~4Z~4 1 'key registcr.
2 The current level registcr 185 (Fig. 2A) consists 3 of a 2 bit register which is used to hold the current level indicator that is presently in effect.' The register 185 is set whenever the level is changed. The 6 register 185 is used in addressing thc proper level 7 status block in the local storage,stack 80 and is also used to determine if an interrupt may bc accepted. For g 'this latter purpose, a two to ~our b~t level decoder 190 is used. The register 185 is a source and destination 11 element for the processor bus 57.
12 The mask register 175 (Fig. 2A) is a four bit 13 register which is used to enable to disable priority 14 interruptions on the four interrupt levels, as follows:
TABLE ~ , 16 Bit 0 = 0 Level 0 Interruptions disabled 17 Bit 1 = 0 Level 1 Interruptions disabled 18 Bit 2 = 0 Level 2 Interruptions disabled 19 Bit 3 - 0 Level 3 Interruptions disabled 21 ' Bit 0 = 1 Level 0 Interruptions enabled ' 22 Bit 1 = 1 Level 1 Interruptions enabled 23 Bit 2 = 1 Level 2 Interruptions enabled 24 Bit 3 = 1 Level 3 Interruptions enabled The mask register 175 is set by the load mask instruc-26 tion. It is a source and d,estination element for the 27 processor bus 57.
28 The mask registcr outputs 178 are also connected 29 to the maslt unloadcd driver's 180 which permits the ANDing of the four bits of mask register 175 with the Docket ~C9-76-022 -28-1 ~ppropriate priority intcrrupt request bits from the 2 I/O interface receivers 251 and bus 261 for use in 3 establishing interrupt acceptance ac~ion.

.~ , Docket DC9-76-022 -29-1 A crystal oscillator 246 generates the basic clock 2 frequency for the CPU l. A ~requency divider 247 generates 3 the free-running clock pulses A, B, C and D as shown in 4 Fig. 8. The up level indicates logical l. Each pulse is active for 55 nanosecond-s once every 220 nanoseconds.
6 The clock controls 245 control the stopping and 7 starting of the gate clock pulses, distribute the clock 8 pulses to the data flow and controlg, and generate certain g speci;l clock pulses, for main storage timing. The gated clock pulses are of the same form as the A, B, C and D
~ pulses described above, but may be stopped and started by 12 conditions arising in the microprogram as hardware.
13 The Bus Zero Detect logic l~0 lS a group of combinatorial 14 logic elements which are capable of determining ~hether lS the value on the processor bus is zero. Its output is 16 used by the microprogram in decision-making.
17 The parity generator and checker circuit 171 checks 18 for odd parity on all bytes received from main storage 8 by l9 the CPU l. It generates parity on all bytes sent to main storage 8 by the CPU l. Detection of a processor cycle 21 storage parity error sets the storage parity bit in the PSW
22 register lIS and causes a machine check class interrupt.
23 Detection of a cycle steal cycle storage parity error 2~ . causes the error condition to be signalled to the active I/O device.
26 ~he I/O Interface Parity Generator and Chec~er 275 27 checks for odd parity in all bytes received over the I/O
28 interface data bus 2. It generates odd parity on all bytes 29 transmitted over the I~O interface data bus 2. Detection of a parity error on inbound data causes the error conditlon Dockct ~C9-7~-022 -30-. 11~4~164 '. ...

1 to be signalled to the active I/O device.
2 The llalt I/O decoder 161 decodes the Halt I/O command 3 which is executed by the channel 250 rather than by an I/O
4 device. It causes a reset of all I/O devies 4-1 to 4-n attached to the system.
6 The key selection logic 12B is used to select one of 7 the threc ~KR keys in register 85 or the cycle steal key 8 via ~us 129 for main storage reference. During cycle 9 steals, the I/O cycle steal key is transmitted to the CPU 1 on the Condition Code In Bus 268 of the I/O interface 2.
11 .T~e output 127 of this logic 128 is sent to the translator 9 12 and to the key compare logic 121.
13 The key compare logic 121 is used to compare the -~:
14 ~elected key wi~n the storage prot~ct key fram the storage protect array 110. ~ violation causes the protect check bit 16 in the PSW to be set and an interrupt occurs.

;' . ' ' . - ' , . , ,: ' ' ' ' ' .' , ' r .
Docket BC9-~G-022 -31-.

1 ~ The poll sequence controi 285 skews and generates 2 the poll tag on line 213 and poll identifier on bus 266, 3 provides signalling to the interface gate controls 239 4 for service gate operation, and is the interface device and line out controls 288 for error checking. The poll 6 sequence is to resolve contention between multiple 7 re~uesting devices for the same'CPU resource.
8 The interace auto control 239 skews and generates' 9 the address and service gates for the interface, and provides contention resolution between same, registers 11 cycle'steal storage access errors for presentation to 12 the device, provides line signalling to and from the 13 storage controls, and deskews the interface buses and 14 ' controls the condition code in latches 130.

15 - The interface sequence and time out controls 2~8

16 provide the time out controls for sequcnce e~ror checking

17 on the interface 2, detects invalid combinations of

18 interface tags and reports detection of ma,chine check

19 cond;tions on the interface to the processor 1.
The I/O interface 2 connects the CPU channel 250 21 to device attachments 5-1 to 5-n. It consists of the 22 element~ described beiow.
23 . The I/O data bus 269 is a bidirectional bus of 16 24 data and two parity lines. It ~s used to transfer data to and from the I/O devies 4-1 to 4-n during direct 26 program control operations and cycle stealing operations, '' 27 and to transfer dev,ice address and interrupt status byte 28 to the CPU 1 during interrupt acceptance.

Dockct Dc9-7G- 022 -32-1 . The I~O address bus 270 is a bidirectional bus of 2 16 lines used to pass éach device address for device 3 selection and I/O commands to I/O devices 4-1 to 4-n 4 during direct program controlled operations. It is also used to transfer main storage addresses from the 6 active I/O device to the CPU 1 during cycle steal 7 operation.
8 TIJe I/O interface control sign;als on lines 267-1 9 to 267-10 are a group of signals used to pass condition .10 codes to the CPU 1, to post status to I/O devices 11 . 4-1 to 4-n, to select and control IPO operations, to 12 transfer interrupt and cycle steal requests to the 13 CPU 1, to poll and control acceptance sequences for 14 interrupt and cycie steal, ~o controi L~ets,'and LO
provide proper sequencing of direct pxo~ram control and 16 cycle steal operations.
17 The device attachments 5-1 to 5-n control and attach 18 I~O devices 4-1 to 4-n to the I/O Interface 2. An atta¢h-19 ment such as 5-1 may control more than one I/O device . such as 4-1.
21 The storage~translator interface 3 includes a 22 main storage bus consisting of address bus 137 for 23 .addressing main storage 8, and to transfer logical and 24 physical storage addresses between the CPU 1 and relo-cation translator 9, and busses 138 and 139 to transfer 26 data between main storage 8 and the CPU 1 and between the 27 relocation translator 9 and the CPU 1.
28 The interface 3 alæo includes the CPU/~ranslator 29 Control Si~nal buses 127, 136 and 135 to transfer active address keys, check Conditiolls, and synchronization Dockct ~C9-76-o22 -33-1 signals between the CPU 1 and relocation translator 9.
2 The inner storage control signal bus 12 provides ~ ph~sical.selection of the inner storage area 14, partial 4 array selection in the selected area, and read/write S control signals properly sequenced for accessing the zero 6 to ~ixty-four kilobyte range of inner main storage area 14.
7 ~he console 6 provides both operator and. programmer 8 with comprehcnsive access to CPU 1 data flow elements 9 and to main storage 8. It attaches to the CPU 1 by a micro-program controlled interface integrated into the data 1OW
11. of the CPU 1.

.

:, ' . ,' . ' - ~.:

.
- . . ~. ~
~ , , ' '~

.

Docket BC9-76-022. -34-.

}42~;4 1 Micro-Program Control (Figs. 6-9) , 2 Figs. 6 and 7 show the data flow and format of the 3 processor 1 of the ROS controls; Fig. 8, the cycle 4 timing; and Fig. 9 is a map of the ROS 201. The micxo-program control works on the principle that each machine 6 level instruction uses only as many microcycles as necessary.
7 During each microcycle one "source" may be gated to the bi-8 directional processor bus 57 and one or more "destinations"
g may be loaded from this bus 57. In the preferred embodiment, .
it will be assumed that the processor 1 uses a 32 bit ROS 201.
11 Twenty-two of the bits are used to control the data flow of i2 processor 1 via bus 204b. The next address (NA) field (bits 2Z-31) of each ROS word supplies via bus 204a the ten low ~4 order bits to the ROSAR 193 (Fig. 6S. The one high or~r 1~ ~it ~f ~he ~osAr~ . ~3 is sup~lied by hardware or microcode 16 via a set ROSAR latch 302 and AND gate 303. The buses 204a 17 and 204b together comprise bus 204 of Fig. 2B.
18 Initiat;on of Instruction Execution 19 There are five hardware force entry locations in the . .
~OS as illustrated in Fig. 2B. Each of these entries has one 21 or~more hardware conditions (vs instructions) to force 22 the entry, 23 If no hardware force entry occurs, the first five 24 bits of the instruction forces a ROS entry as shown in the upper right portion of Fig. 9. Note that on instruction 26 force entries, the Set ROSAR latch 302 Fig. 6 is set.
27 From this point until th~ end of the instruction, the 28 Set ROS~R 0 latch 302 along with either the l0 bit Next 29 Address (NA) field from the ROS Data Register (ROSDR) 202 or the contents of one of the 10 bit link registers Dock~t ~C9-76-022 -35-11~4Z64 . .

1 (ROSLR) 210 or 211 specifies the next ROS word to be 2 executed.
3 Terminating and Instruction Execution 4 Selected hex NA values are decoded by the hardware 205 to select a last microcyclc to terminate the 6 - instruction being executed, reset the SRI and SR2 latches 7 305 and 306 and initiate a new instruction via an initial 8 entry. A reset load or a class interrupt will also g terminate the instruction, reset the SRl and SR2 latches 305 and 306 and force a branch to the start of the microcode.
11 ROS Link Registers and Timings 12 Every time C clocks the ROS Address Register (ROSAR) 13 193. Every time A clocks the ROSDR 202. Every time A, 14 except when the Subroutine 1 (SRll latch 305 is on, clocks ROSAR bits 1-8 into ROS Link PQgister 1 (ROSLRl) 210 bit 1-8, while ROSAR bits 9-10 go through a two bit 17 incrementer 307, into ROSLRl 210, bits 9-10. The effect of 18 this is to set the ROSLRl 210 to the value of the ROSAR~
19 except in the case where the last two bits of the ROSAR 183 are both on, in which case the ROSLRl 210 is set to the value 21 of the ROSAR-3. This is the return address from the first 22 level subroutine back to main].ine code.
23 Every time A, except when the SR2 latch 306 is on, 24 c.locks exactly the same value into ROSLR2 211 as described above for ROSLRl 210. This is the second level return 26 address. The SRl and SR2 latches 305 and 306 (which 27 frecze ROSLRl 210 and ROSLR2 211, respectivcly) are 28 clocked at Timc C.
29 Docket ~C9-76-022 -36-~ i 1 First Level Subroutine Call 2 ' A subroutine call consists of a branch to a particular 3 area (group of ROS addresses)., If a,branch is made from 4 the low mainline to subroutine area 1, (Fig. 9) the subroutine return address will be in ROSLR1 210 a the end of Time A.
6 During Time C, the SRl latch 305 is set, thus freezing 7 this value in ROSLRl 210. The first level subroutine 8 can use any of the ROS addresses except those in subroutine 9 . 'area 2. If a branch is made from the high mainline area ,10 to the area above the ROS 201, i.e., llX XXXX XXXX, the ,11 AND circuit 303 between the 5et ROSAR 0 latch and ROSA~
12 ~it O iS clockea, resulting in a,brancn tQ O~X XXXX ~XXX
13 which is exactly the same subroutine call ~s from the low 14 mainline.
1~ , ' First Level Subroutine Exit 16 The first level subroutine returns.to mainline code 17 , by a NA hex value o 03F which is decoded as a di'screte lB ' function by the hardware 209. At Time C, the SRl latch i9 305 is reset and the ROSAR 193 is loaded from the ~OSLRl 210, thus resuming mainline code at the previously 21 , frozen subroutine return'address. Note that if the 22 calling location was in the high mainline area, the 23 return will be back to the high ~ainline area since the Set , 24 ROSAR 0 latch 302 is still on and the set to ROSAR bit 1 will be off. The~last microcycle decode also 26 forces a subroutine exit.
27 Second l,evel Subroutine Call .
28 If a branch is made to Subroutine'Area~ 2, the subrou-29 tine return address is frozen in ROSLR2 211 via the S~2 latch 30G in the same manner as described above for the ~ocket ~C~-7G-022 _37_ ~U~6~
, '. . .
1 first level call. ~he second lcvel subroutine can use any 2 of the ROS addresses.
3 Second Level Subroutine Exit 4 Thc second level subroutine returns to the first level subroutine'by a NA hex value of 03E. At Time C, the SR2 6 latch 306 is reset and the ROSAR 193 is loaded from the . 7 ROSLR2 211, thus resuming first level subroutine code at 8 the previously frozen subroutine return address. The last 9 microcys~le decode also forces a subroutine exit.
A second level subroutine can return directly to main-11 line by using a 03F next address. At Time C, the ROSAR
12 193 is loaded from R~SLR1 210, thus resumin~ mainline at the 13 previously frozen subroutine return address. 'At the 14 same Time C, both the SRl and SR2 latches 305 and 305 are rese~, thus allowing a new subroutine call af~er only '6 one word of mainline code.
17 First Level Subroutine in Subroutine Area 2 18 ' I a bra~ch is made from mai'n,line code directly to -.
' '19 Subro~tine Area 2 (NA,bits 1, 2 = 1, 1), the SR2 latch 306 is'set and ROSLR 2 2il is frozen exactly as for 21 a second level call. The exit back to mainline is next 22 address 03E, exactly as for a second level exit. This 23 allows a subroutine in Area 2 to be used either as a first , 24 level sub,routine or a second level routine.
The returns are summarized below:

28 ,.
29 , . . . . .

Dock~t ~C9-76-o22 -38-.i . ..
- ..
.
- : :

3 NA Loaded From SRl 305-SR2 306 Return To From ID
4 03F ROSLRl On OffMainline 1st Level Area 1 03F ROSLRl On OnMainline 2nd Level Area 2 6 03E RO-SJ.R2 On On-lst Level 2nd Level Area 2 7 03~ ROSLR2 Off On.Mainline .lst Leve]. Area 2 9 03F resets both the SRl and SR2 latche~
03E resets only the SR2 latch.
11 . Conditional ROS Branching Logic 152 12 The processor has 4-way, 8-way and 16-way conditional 13 ROS branches. If a conditional branch is seieted and the 14 condition is met, the appropriate NA bit is forced on.
If one of the NA bits is already on, that con~ition is a 16 don't care, hence ail 4-way branches can be subdivided into 17 2-way branches, 16-way branches can become 12-way branches, 18 etc.
19 The NA bits which participate in conditional ROS
branches are bits 5-8. Since the NA bits used for returns 21 are bits 9-10, these can be used with conditional ROS
22 branches to do conditional subroutine returns.
23 For example, if location 00011000010 did a first 24 level subroutine call and the subroutine did a 4-way conditional ROS Branch return, the four return addresses 26 are:

28 00011010011 .

Docket BC9-76-022 . -39-1 ROS ~it Decodes 2 The control decodes control various operations in the 3 CP~ 1. The conditional nos branches a~low the micro-4 code to branch diffcrent places depending on machine conditions. The source field specifies what source is 6 to be ~ated onto thc processor bus 57. The destination 7 ficld specifies one or more destinations to be loaded 8 from the processor bus 57. The next address field specifies 9 the next ROS word to be executed.
-Emit Field -11 There are four destination decodes that not only 12 .specify the destination but also to emit ROS bits 0-15 13 to the processor bus 57 as a source. There are twelve 14 destination decodes that specify to emit ROS bits 8-1-5~ -1~ tc the processor bus 57. This allows the use~of the 16 control/conditional branch field in the same ROS word as 17 the 8 bit Emit.

19 .

Docket BC9-76-022 .-40-4~64 1 Main Storage Control Decodes - ROS Bits 13-'15 (Not Emit) 2 ' Value Function 3 0 No storage cycle 4 1 SR - Change the next LW or SW to Load or Store Segmentation Reyister if translator is installed.
6 If translator is not installed, set invalid 7 function program check.
8 2 BR - Block the next LW or SW. The'next LIW, LUW, 9 LW or SW can be executed in the second, micro-cycle after the blocked LW or SW,.
,11 3 SBY - Change the next LW or SW into a byte request 12 instead of a word request. Change the next 13 clock result,indicator into a clock byte 1~ recult indicator and inhibit changing byte 0 in the same word.
16 4 LIW - Load instruction word into ~D~,using ISK.
17 5 LUW - Load unconditional word into SDR using OPK.
18 6 LW - Load data word (two bytes) into SDR.
19 7 SW - Store data word from SDR'into storage.
Operation 21 The normal storage requests are LIW, LW, and SW. All 22 the others modify these. The four modifying storage control 23 decodes are used to modify common subroutines. The SR, BR, 24 and SBY ,decodes are executed before a common subroutine containing the LW or SW they are to modify. These three 26 have no effect on LIW. The BTR decode is executed 27 immediately following a LI~, LW, or SW in the l'ast word 28 of a common subroutine.

Dockct BC9-7fi-~22 -41-:

llU4~1~4 1 The SBY decode not only modifi.~s later storage control decodes (LW and SW), but also modi~ies later clocking of 3 result indicators to o~erate only on 8 bits instead of 16 4 bits.
S Priority of Modifying Requests 6 BR is top priority and resets SR and SBY
7 SR is second priority and re~ets SBY
8 SBY is lowest priority 9 , ,.

. .

Docket BC9-76-o22 -42- .

426~ .
1 , ~ig~. 10 - 14 have b~en sllown to illustrate various 2 cycle timings in the preferred processor within which 3 implementation of the,i~provement is intend,ed.
4 Fig. 10 illustrates the five microinst,ructions wllich arç executed to perform a machine level Add 6 Immediate instruct~on and Fig. 11 illustrates the 7 timing of the source; destination and storage accessing 8 during the execution of the five microinstructions.
9 Fig. 12 illustrates the cycle timings of the main storage controls.
11 Figs. 13 and 14 illustrate the cycle timings 12 of the microinstruc,tion type which is executed as the 13 last microinstruction of each routi~e for executing I4 machine level instructions. Depending upon the detection o~ (or $ailure to detect),a s~mpled condition, 16 either the timing o$ Fig. 13 or Fig. 14 is effected.

18 ,, 19 , . .. ..

21 ' ' ' 22 ' , ' 23 ~ -27 ' 28 , ~ ,, ' - ' , Docket BC9-76-022 -43-" ~

1 Interruptions 2 Efficient operation of a central processor such as 1 3 depends on prompt response to I/O device service requests.
4 This is accomplished by an interruption scheme that stops the current processor operation, branches to a device service 6 routine, handles device service, then returns to continue 7 the interrupted operation. One processor 1 can control many 8 I/O devices 4-1 to 4-17; therefore, an interruption priority 9 is established to handle the more important operations before those of lesser importance. Certain error or exception 11 conditions (such as a machine check) also cause interruptionq.
12 These are called class interruptions and are processed in a 13 manner similar to I/O interruptions.
14 Interruption priority is established by four priority levels of processing. These levels, listed in priority 16 sequence, are numbered 0, 1, 2 and 3 with level 0 having 17 highest priority. Interruption levels are assigned to I/O
18 devices 4-1 to 4-n via program control. This provides 19 flexibility for reassigning device priority as the application changes.
21 Each of the four priority levels has its own set of 22 registers LSB level 0 to LSB level 3 in a stack 80 as shown 23 in FIG. 4. These consist of an address key register (AKR), 24 a level status register (LSR), eight general registers (R0-R7), and an instruction address register (IAR). Information 26 pertaining to a level is automatically preserved in these 27 stack hardware registers when an interruption occurs.

1 ~ X/O and class interrupti.onS include automatic branching 2 to a service routine. Fixed locations in main storage 8 3 aræ reserved for branch addresses or points ~lhich are 4 ~eferenced during interruption processing. Hardware pro-cessing of an interruption includes automatic branching 6 to a service routine. The processor 1 uses a reserved storage 7 area in main storage 8 for branch information. The xeserved 8 area begins at main storage address 0030. The total size of 9 the area depends on the number of interrupting devices 4-1 to 4-n attached. One word (two bytes) is reserved for eàch 11 interrUpting device.
~2 The. storage locations used for a class interruption each 13 include a level status block (LSB) pointer which points to 14 ~he first address of an are~ ~n main st^-^ w~exe a level status block is stored, and a s~art instruction address 16 (SIA) which points to the first instruc~ion of the service 17 routine.
18 Each storage word used for an I/O interruption con-19 tains a device data block (DDB) pointer which is the address of the first word of a device data block. This word is used 21 to obtain the start instruction address for the service 22 routine.
23 Interruption masking facilities provide additional 24 program control over the four priority levels. System and level masking are controlled by a summary mask and the 26 interrupt level mask register l75. Device masking is con-27 trolled by a device mask in thc information transmitted by 28 the Prepare I/O command.~ Manipulation of the mask bits can 29 enable or disablc intcrruptions on all levels, a spccific leve1, or for a specific device.
Dockct ~C9-76--022 -4s-11~4269~
1 As previously stated, four priority interruption 2 levels exist. Each I/0 device 4-1 to 4-n is assigned to 3 a level dynamlcally, dependent on the application. When 4 an interruption on a ~iven level is accepted, that level remains active until a level exit (LEX) instruction is executed 6 or a highcr priority in~erruption is accepted. In 7 the latter case, the processor 1 switches to the higher 8 level, completes execution (including a LEX instruction), g then automatically returns to the interrupted-from level. -This automatic return can be delayed by other higher 11 priority interruptions.
i2 ` Ii an interruption request is pending on the currently 13 active level, it will not be accepted until after execution 14 o a LEX instruction by the current program. If no other level of interruption is pending when ~ level exit instruc-16 tion is executed, the processor 1 enters the wait state.
In the wait state no processing is per~ormed, but the 18 process~r can accept interruptions that are exp~cted to 19 occur.
Supervisor state is entered upon acceptance of all ` 21 priority interruptions. The priority interruption algorithm 22 is:
23 . 1 The summary mask must be on (enabled).
24 2. ~he mask bit ~interrupt level mask register 175) for the interrupting level must be on (enabled).
26 3. For I/O interruptions the device must have its 27 device mask bit on (enabled).

Dockct ~C9-76-022 -46-~1~34~

1 4. The interruption request must be the highest priority of the outstanding requests and higher than the current level of the processor.
5. The processor must not be in the stop state.
Class interruptions do not change priority levels. They are processed at the currently active level. If the pro-cessor is in the wait state when a class interruption occurs, priority level 0 is used to process the interruption.
In addition to the above-described interrupt condition, program-controlled interrupt switching is provided using the LLSB and STLSB instructions as described in aforementioned U.S. Patent 4,047,161. This mechanism provides efficient software task management.
Bit Field Instruction In order to attain the capability of storing variable length bit fields into memory and of loading such fields into a register from memory, independently of the boundaries of addressable elements, this invention provides means for recognizing and executing four new instructions. The format of the new instructions is illustrated in FIG. 16. As shown in FIG. 16, each of the instructions in the preferred embodi-ment contains sixteen bits. The first five bits (bits 0 through 4) are the operation code. These four instructions all have the same operation code (10110). The next three bits (bits 5 through 7) specify a machine register R which is the source (when executing a store instruction) or the destination (when executing one of the three load instruc-tions) of a bit fieId. The next two bits (bits 8 and 9) specify a register RB which contains the address of an element of addressability 1 (e.g., a byte, or a word) within the memory. The address will 2 be utilized as a base address. The next two bits (FN) in the 3 instruction (bits 10 and 11) will be decoded by the system to 4 indicate which particular one of these four new instructions is to be executed. The final four bits L (bits 12 through 15) 6 contain a binary number which is one less than the length of 7 ~the bit field. Thus, bit fields that are as long as sixteen 8 ~bits in length may be accommodated. Besides the machine ~ ~
9 registers that are explicitly specified by the instruction illustrated in FIG. 16, one other machine register is of 11 ~ primary significance. In this preferred embodiment, one 12 particular general register, general register 7 (R7), is 13 always utilized to hold a signed displacement from the 14 boundary addressed by the contents of the register specified by RB. This signed displacement in R7 consists of a signed 16 byte displacement in the upper thirteen bits of the register 17 and a bit displacement (from the byte boundary) in the lower 18 three bits of the register.
19 In executing one of these instructions, the effective bit address of the first bit in the bit field is calculated by 21 first determining the storage byte in which the bit field 22 begins. This is done by adding the contents of the register 23 specified by RB to the signed byte displacement (the thirteen 24 high-order bits) of R7. In performing this addition, the byte displacement bits of R7 must be right-justified. The 26 original three low-order bits of R7 determine the bit within 27 this byte that is the beginning of the desired bit field.
28 The four instructions that are included within the 29 preferred embodiment of this invention are three load 6~

1 instructions, each of which may be utilized to load a bit 2 field into a specified register from storage, and one store 3 instruction which is used to put into storage a bit field 4 contained in a specified register. The four instructions function as described below.
6 Load Field (LF): FN = 00. The specified bit field is 7 loaded into register R from storage. The field is right-8 justified in register R with zeros filling out the high-order g bits. The system result indicators are changed to reflect the final value loaded into register R.
ll Load Field and Increment (LF+): FN = 01. The specified 12 bit field is loaded into register R. The field is right-13 justified within register R with zeros filling out the 14 high-order bits. A value equal to L + l is added to R7 and replaces the contents of R7, thus updating it to point 16 to the beginning of the next bit field. The system result 17 indicators are changed to reflect the final value loaded 18 into register R.
19 Decrement and Load Field (LF-): FN = 10. A value of L + 1 is subtracted from R7 and replaces the contents of 21 R7. The specified bit field is then loaded into register R
22 and is right-justified in register R with zeros filling out 23 the high-order bits, This enables a string of bit fields to be 24 processed from right to left. The system result indicators are changed to reflect the final value loaded into register R.
26 Store Field (STF): FN = 11. The low-order L + 1 bits 27 of register R are stored into the specified storage field 28 without disturbing any other bits.

1 An example of the use of the Load Field and Increment 2 (LF+) instruction will now be given. FIG. 17 illustrates a 3 portion of memory which contains five bit fields A, B, C, D
4 and E containing seven bits, eleven bits, eight bits, five bits and seven bits, respectively. As shown in FIG. 17, it 6 is assumed that the first bit in field A is offset by two 7 bits from the starting boundary of byte location 1000 (that 8 i9, the first bit in field A is the third bit in the thousandth 9 byte in memory). Assume it is desired that fields A, B, C, D
and E be loaded into the five machine registers Rl, R2, R3, 11 R4 and R5, respectively. A computer program for accomplishing 12 this would need first to initialize a base register RB and 13 register R7. Assuming that register R0 is to be used as the 14 base register, initialization could consist of an instruction which loads RO with 1000 and an instruction which loads R7 16 with 2. (The high-order thirteen bits of R7 would, in this 17 example, indicate a byte displacement of 0.) After initial-18 ization, the loading of the five registers Rl through R5 can 19 be easily accomplished by the following five instructions.
LF+ R = Rl, RB = R0, L = 6 21 LF+ R = R2, RB = R0, L = 10 22 LF+ R = R3, RB = R0, L = 7 23 LF+ R = R4, RB = R0, L = 4 24 LF+ R = R5, RB = R0, L = 6 After executing these five instructions, registers Rl 26 through R5 Will have been loaded with bit fields A through 27 E, respectively, and each of the bit fields would have been 28 right-justified in its register, with zeros filling the 29 high-order register positions. R7 will have been incremented ~l~g;264 1 to contain the binary number 101000 tequal to the decimal 2 number 40) and the system will be ready to load the next field 3 F if it should be of interest. (If field F is of no interest, 4 the fifth instruction above could have been an LF instead of the LF+). As was described above, the contents of R7 represent 6 a byte displacement (in the high-order thirteen bits) and a bit 7 displacement (in the low-order three bits). In this example, 8 the binary number 101000 in R7 represents a byte displacement 9 of 101 (equal to decimal 5) and a bit displacement of 000. This correctly points to the beginning of bit field F which is dis-11 placed five bytes from the address indicated in the base register 12 R0. Of course, the example would have worked just as well if 13 R0 had been initialized with some other number such as, for 14 example, 456 and the high-order (byte displacement) portion of lS R7 had been initialized with a number equal to 1000 minus the 16 contents of R0, in this case 544.
17 Those skilled in the art will recognize that this 18 invention could be implemented on a given processor with 19 sequential logic, or microprogramming or a combination of both. The specific manner of implementation will largely 21 depend upon constraints imposed by the environmental system.
22 Therefore, the best way to describe a preferred implementation 23 of the invention is to present the following description of 24 the elemental steps utilized in executing the above instruc-tions in the exemplary environmental system described herein.
26 The description provides a clear definition of sequential 27 logic that could be used to implement the invention. It 28 also provides a clear definition of microinstructions that 29 could be used.

1 Initial Conditions: Assume that one of the above 2 instructions is in the OP register; its address is in the work 3 area (WA) register; the base byte address is in a register RB;
4 the displacement is in general register R7 and the target register is R. Referring to FIG. 18, the controls are 6 described as follows.
7 The instruction address is incremented by 2 and stored 8 into the storage address register and into the instruction 9 address register for use in fetching the next sequential instruction following the end of this one (see Block 1). (As 11 will become evident later, the storage address register will 12 in fact get overwritten during the course of execution of the 13 instruction. However, the destination control is common between 14 the storage address register and the instruction address register, so it was convenient to put the updated instruction 16 address in both.) A value of "3" is also emitted to the work 17 area and to a counter. (In this description all numerical 18 values are expressed in decimal notation unless otherwise 19 stated.) The function of the next ten blocks is to form a mask of right-justified one-bits equal in length to a value 21 that is one greater than the length specified in the L field 22 of the instruction. To this end a test is made (Block 2) of 23 the most significant bits of the L field (that is, bits 12 24 and 13) and a ones complement value is emitted to the Y
register (Blocks 3, 4, 5 and 6 expressed as hexadecimal 26 numbers). As shown in Block 7, the two less significant bits 27 (14 and 15) are tested and the value in the Y register is 28 shifted left or right (Blocks 8, 9 and 10) the appropriate 29 amounts to form the ones complement mask. The mask is then 11~4Z6~

1 inverted and stored in a location known as TEMP in the stack 2 (Block 11). The contents of the OP register (that is, the 3 instruction) are moved to the work area (Block 12) and 4 immediately following this, an emit field of OOOF (hexadecimal) is moved to the Y register (Block 13). Then (Block 14) WA
6 and Y are ANDed together and the result placed in the storage 7 data register. The effect of the operations shown in Blocks 8 12, 13 and 14 is to copy just the length field from the 9 instruction into the storage data register where it is retained for later use. Then register 7, which contains the signed bit 11 displacement, is fetched and moved to the work area (Block 15).
12 In the same cycle the Y register is shifted right one position 13 so that the value in it at the end of the microcycle is 0007.
14 Then these two values (that is, work area and register) are ANDed together and again placed in the local storage stack 16 in the location known as TEMP 1 (Block 16). At the end of 17 this, TEMP 1 contains the low-order three bits of the bit 18 displacement and is subse~uently used to indicate the starting 19 bit number for the selected bit field. As shown in Block 17, a test is made of the OP register bits 10 and 11. A value 21 of 00 in this field corresponds to "Load Field". 01 corresponds 22 to "Load Field and Increment". 10 and 11 correspond respectively 23 to "Decrement and Load Field" and to "Store Field".
24 Taking the 01 leg out of Block 17 (Load Field and Incre-ment) the system retrieves (Block 18) the length of the bit 26 field which was previously stored in the storage data register 27 (see Block 14) then adds the original value of the signed bit 28 displacement (which is in WA) to the length of the current bit 29 field operation (which is in Y) and an additional "1" so that ll~J~

1 the result points directly to the next bit field to be handled 2 via the subsequent field instruction (Block 19). The result 3 of this is placed into the register stack in the position for 4 register 7 for the current level. The apparatus defined by Blocks 18 and 19 has caused the value of the signed bit 6 displacement to be incremented by the length plus 1 to effect 7 an automatic update of the bit pointer. The apparatus described 8 below is common to both Load Field and Load Field and Increment.
9 The system then sets up the byte address of the location containing the first bit of the field. The work area which 11 contained the bit displacement is shifted right 3 (Block 20) 12 to strip off the bit identifiers and leave a byte address. In 13 the same cycle, the base address from RB is fetched from the 14 register stack and moved to the Y register. As shown in Block 21, WA and Y are then added and the result is placed in the 16 storage address register which then contains the effective 17 byte address of the byte holding the first bit of the selected 18 field. Then (Block 22) the storage data register is copied 19 into the work area. (The storage data register held the length of the bit field but must now be considered volatile since a 21 storage cycle i8 about to take place. On all storage cycles 22 the storage data register is set to storage data, so we must 23 first copy it into the work area). A read of main storage is 24 also called in this cycle to get the first byte. The bit number is retrieved from TEMP 1 in the register stack and 26 moved to the Y register (Block 23). (Note that references to 27 the register stack refer to that part of the hardware in the 28 exemplary environmental system which contains the general 29 purpose registers, the level status registers, the address z64 1 key registers, and also contains buried internal registers 2 such as TEMP and TEMP 1 which are used as internal work areas 3 and are not directly accessible to a programmer.) The bit 4 number is now back in the Y register. We add it to the length (Block 24) and then (Blocks 25 and 26) subtract a constant of 6 "8" from the sum of the length plus the starting bit number.
7 The purpose of this operation is to determine whether or not 8 the starting bit position and the length of the bit field are 9 such that overflow into the next byte of main storage will occur. This test is indicated in Block 27.
11 If the result of the subtraction indicated in Block 26 is 12 negative, it implies that the bit field does not stretch into 13 the next byte position, and so the contents of the storage 14 data register will be moved to the Y register (Block 28j. The byte moved from the storage data register to the Y register will 16 in fact contain the beginning and end of the bit field in this 17 case, since it has been determined that the bit field does not 18 overflow the boundaries of this byte. Then the W and Y
19 registers are ~hifted right and a counter is decremented with each shift until the counter is zero. (The counter was set up 21 with the appropriate value as shown in 27.) When the counter 22 has gone to zero, the byte will have been shifted as far to 23 the right as is appropriate and will be in the righthand byte 24 position of the Y register. The instruction address register content~ is then transferred to the storage address register 26 to set up the accessing of the next sequential instruction 27 (Block 30). As shown in Block 31 the value TEMP which contains 28 the mask established as shown in Blocks 2 through 11 is loaded 29 into the`work area and a read of main storage to fetch the 11~4~

1 next sequential instruction, preferably overlapped (for 2 optimum performance) with the end of the execution of this 3 instruction, is performed. Then the work area and Y are ANDed 4 together and placed in the target register in the register stack (Block 32). The effect of this is to place the appropriate 6 bits of the byte in the Y register, as specified by the bit 7 field parameters, into the register specified by the R field.
8 The clocking of the result indicators to indicate the 9 characteristics of the value just stored into the register then completes the instruction execution.
11 If the test shown in Block 27 was not negative, then the 12 bit field certainly overlaps into the next byte, and may in 13 fact overlap into a third byte. In this cycle, the constant of 14 value "8" which was in the Y register is again subtracted from the sum length plus bit number (Block 34) to determine whether 16 or not the bit field length laps into only one more byte or 17 two more bytes. The result of the subtraction is inverted and 18 a test for negative is performed (Block 35).
19 If the result is negative (i.e., the bit field occupies two bytes) the storage address used for the first byte is moved to 21 the work area (Block 36). As shown in Block 37 the storage 22 data register (which contains the first byte fetched due to 23 the request shown in Block 22) is loaded into the Y register.
24 Then the previous storage address for the first byte is incremented by one and restored to the storage address register 26 and a further request to main storage is made (Block 38).
27 The Y register is shifted left eight positions (Block 39) 28 to allow subsequent merging of the previous byte and the current 29 byte. By this time the byte has been read into the low-order 1 byte position of the storage data register and it is copied 2 into the work area (Block 40). The work area is then ORed 3 with the Y register and the result placed in the Y register 4 (Block 41). This has the effect of merging the two appropriate bytes together into the Y register with the most significant 6 one occupying bit positions 0-7 and the least significant one 7 occupying bit positions 8-15. The main line execution apparatus 8 is now rejoined at Block 29 where right justification of the 9 bit field, loading of the target register R, clocking of the result indicators and next instruction fetch continues.
11 When the bit field extends over three bytes, the test for 12 negative (Block 35) will be followed by subtraction of yet 13 another value of 8 from the work area (Block 42) and placement 14 into the counter of the appropriate number of bit positions to be shifted (Block 43). The storage address register is copied 16 into the work area (Block 44), the operand address in main 17 storage is again incremented by 1 (Block 45) and main storage 18 is read. The storage data register contents is saved in 19 TEMP 1 (Block 46) which already contains the first byte fetched from main storage. The contents of the storage data register 21 (which had been set by the storage request shown in Block 45) 22 are moved into the Y register (Block 47). This register then 23 contains the second byte associated with the bit fiald. The 24 work area (which contained the storage address of that byte) is incremented by "1" and replaced in the storage address 26 register to address the third byte (Block 48). Main storage 27 is called in this cycle. Then the Y register is shifted left 28 "8" (Block 49) to accommodate the least significant byte which 29 is about to arrive from main storage and which, after its -2~ .

1 arrival, is moved to the work area (Block 50). The second 2 and third bytes are ORed together and thus concatenated 3 (Block 51). Then the most significant byte is retrieved 4 from TEMP 1 in the stack and placed in the work area (Block 52). We then return to Block cycle 29 for the common ending 6 execution where the whole value of work area and Y is shifted 7 right until the counter is 0, and termination of the instruction 8 proceeds as before.
9 The preceding detailed description of specific implementa-tions of "Load Field" and of "Load Field and Increment" are 11 sufficient to teach those skilled in the art exactly how to 12 implement other instructions that might be included as part 13 of this instruction. Therefore, there is no need to present 14 similar detailed descriptions of "Decrement and Load Field"
or of "Store Field".

1 Those skilled in the art will recognize that many 2 variations to the preferred embodiment described above could 3 be made in implementing this invention. The variations will 4 depend primarily upon two factors, (1) constraints imposed by a system in which this invention is embodied, and (2) the 6 particular requirements of desired applications.
7 For example, the maximum allowable length of a bit 8 rield could be something other than 16. If five bits in the 9 instruction are available for specification of L, fields of up to 32 bits could be handled. If only three instruction 11 bits were available to specify L, then eight bits would be the 12 maximum field length.
13 Also, it will not always be essential that the displace-14 ment register (R7 in the preferred embodiment) be prespecified.
If the architecture of the environmental system permits it, 16 the programmer could specify the displacement register.
17 Alternatively, the destination register R and/or the base 18 register RB could be prespecified instead of being selectable 19 by the programmer. However, in the vast majority of applications a significant amount of flexibility would be lost if the 21 programmer were not given the option to specify at least the - -22 destination (source) register R.
23 In the preferred embodiment, each of the four instructions 24 was shown to have the same operation code, with further definition provided by the field FN. Whether the invention 26 is implemented in this particular manner, or whether two or 27 more totally distinct operation codes are used for the 28 instructions will generally be determined by the architecture 29 of the environmental system.

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1 It also is not essential that there be exactly three 2 different load instructions and only a single store instruction.
3 There could be more than three, or fewer than three load 4 instructions and there could be a similar variety of store instructions. A determination of which types of load and 6 store instructions should be implemented will depend primarily 7 upon the intended usage of the system.
8 While the invention has been particularly shown and 9 described with reference to a preferred embodiment thereof, it will be understood by those skilled in the art that the 11 above and other changes in form and details made by made 12 therein without departing from the spirit and scope of the 13 invention.

ESG:ehc

Claims (4)

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. A method of operating an electronic data process-ing system so as to permit a single bit-field instruction to cause access of variable length bit fields in a storage of said system without requiring any special relation between the boundaries of addressable elements within said storage and the beginning and end of the bit fields, comprising the steps of:
initializing a base register of said system to contain a base address of an addressable element;
initializing a displacement register to contain (1) the element displacement, from said base address, of the address-able element containing the first bit of a desired bit field, and (2) the bit displacement, from a boundary of the last recited addressable element, of said first bit; reading into an instruction register of said system a bit-field instruction which contains (1) an operation code identifying it as a load instruction or a store instruction for causing access of a bit field, (2) an identification of which regis-ter in said system shall be used as said base register, (3) an identification of another register R in said system which is to be used as the destination of a bit field to be loaded into R from storage or the source of a bit field to be stored from R into storage and (4) a number L indicating the number of bits in said particular bit field;
adding said element displacement to the contents of said base register;
concatenating said bit displacement to the result of said addition, thereby providing an indication of the loca-tion in storage of said first bit; and beginning with said first bit, either loading said number of bits into R from storage or storing said number of bits from R into storage depending upon whether said bit-field instruction is a load instruction or a store instruc-tion, respectively.

2. The method of claim 1 including the additional step of combining a number equal to said number of bits with the portion of said displacement register containing said bit displacement in order to initialize said displacement register with respect to a bit field immediately adjacent in storage to said particular bit field.

3. In an electronic data processing system, apparatus responsive to a single bit-field instruction to cause access of variable length bit fields in a storage of said system without requiring any special relation between the bound-aries of addressable elements within said storage and the beginning and end of the bit fields, comprising:
a plurality of registers, each usable as a base regis-ter;
means for initializing a base register of said system to contain a base address of an addressable element;
a displacement register;
means for initializing said displacement register to contain (1) the element displacement, from said base address, of the addressable element containing the first bit of a desired bit field, and (2) the bit displacement, from a boundary of the last-recited addressable element, of said first bit;
an instruction register;
means for reading into said instruction register of said system a bit-field instruction which contains (1) an operation code identifying it as a load instruction or a store instruction for causing access of a bit field, (2) an identification of which register in said system shall be used as said base register, (3) an identification of another register R in said system which is to be used as the desti-nation of a bit field to be loaded into R from storage or the source of a bit field to be stored from R into storage and (4) a number L indicating the number of bits in said particular bit field;
means for adding said element displacement to the con-tents of said base register;
means for concatenating said bit displacement to the result of said addition, thereby providing an indication of the location in storage of said first bit; and means for beginning with said first bit, either loading said number of bits into R from storage or storing said number of bits from R into storage depending upon whether said bit-field instruction is a load instruction or a store instruction, respectively.

4. The apparatus of claim 3 further including means for combining a number equal to said number of bits with the portion of said displacement register containing said bit displacement in order to initialize said displacement regis-ter with respect to a bit field immediately adjacent in storage to said particular bit field.