CA1098216A - Loop decoder for josephson memory arrays - Google Patents
Loop decoder for josephson memory arraysInfo
- Publication number
- CA1098216A CA1098216A CA298,267A CA298267A CA1098216A CA 1098216 A CA1098216 A CA 1098216A CA 298267 A CA298267 A CA 298267A CA 1098216 A CA1098216 A CA 1098216A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
- H03M7/001—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits characterised by the elements used
- H03M7/002—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits characterised by the elements used using thin film devices
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/44—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using super-conductive elements, e.g. cryotron
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- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Superconductor Devices And Manufacturing Methods Thereof (AREA)
Abstract
LOOP DECODER FOR JOSEPHSON MEMORY ARRAYS
Abstract of the Disclosure Decoder circuit arrangements for use with Josephson memory device arrays are disclosed. In one circuit of N
stages, an input circuit consists of a Josephson junction and a shunting impedance connected across the junction by means of a matched transmission line. The transmission line has two output portions each of which controls the actuation or nonactuation of a pair of devices of circuits similar to the above-described circuit which are disposed in series in a pair of branches of a serially disposed superconducting loop of a first stage. Each branch has a serially disposed address gate to which true and complement address signals are applied. Each succeeding stage is similar to the first stage except that each branch of each succeeding stage contains twice as many circuits similar to the above-mentioned first stage circuit. Each stage provides a pair of output portions from each circuit in each branch and these outputs are connected so that the outputs of one circuit are connected to an actuable device in each branch of a succeeding stage.
Abstract of the Disclosure Decoder circuit arrangements for use with Josephson memory device arrays are disclosed. In one circuit of N
stages, an input circuit consists of a Josephson junction and a shunting impedance connected across the junction by means of a matched transmission line. The transmission line has two output portions each of which controls the actuation or nonactuation of a pair of devices of circuits similar to the above-described circuit which are disposed in series in a pair of branches of a serially disposed superconducting loop of a first stage. Each branch has a serially disposed address gate to which true and complement address signals are applied. Each succeeding stage is similar to the first stage except that each branch of each succeeding stage contains twice as many circuits similar to the above-mentioned first stage circuit. Each stage provides a pair of output portions from each circuit in each branch and these outputs are connected so that the outputs of one circuit are connected to an actuable device in each branch of a succeeding stage.
Description
1 Backg ound of_the Invention Field of the Invention _ __ This in~ention relates generally to decoder circuits ~ -for the selection of storage devices in memory arrays. More specifically, it relates to loop decoder circuits which utiliæe Josephson junctions and superconducting loops which can be utiliæed in conjunction with bit oriented memory arrays which incorporate Josephson junction memory cells.
Still more spe~ifically, it relates to decoder circuits which utili~e serially disposed address devices which, in turn, control` current flow in a plurality of supercondueting loops each of which contains current steering circuits, the outputs cf which control the actuation of 2N similar cir~
cuits associated with a pair of loops of a succeeding ~N~l) stage. Still more specifically, it relates to a deeoder circuit which utilizes a plurality of serially disposed loops each branch of which contains 2 ~2 circuits similar to a serially disposed first stage eircuit which includes an ,~
1 actuable device shunted by an impedance connected across the device by a transmission line. The transmission line contains a pair of output portions one of which controls an actuable device of a similar circuit in each branch of a succeeding .
serially d sposed loop~ Each branch of each loop contains a serially disposed address device. Thus, each loop provides
Still more spe~ifically, it relates to decoder circuits which utili~e serially disposed address devices which, in turn, control` current flow in a plurality of supercondueting loops each of which contains current steering circuits, the outputs cf which control the actuation of 2N similar cir~
cuits associated with a pair of loops of a succeeding ~N~l) stage. Still more specifically, it relates to a deeoder circuit which utilizes a plurality of serially disposed loops each branch of which contains 2 ~2 circuits similar to a serially disposed first stage eircuit which includes an ,~
1 actuable device shunted by an impedance connected across the device by a transmission line. The transmission line contains a pair of output portions one of which controls an actuable device of a similar circuit in each branch of a succeeding .
serially d sposed loop~ Each branch of each loop contains a serially disposed address device. Thus, each loop provides
2 outputs which actuate 2 actua~le devices in 2 circuits of a succeeding stage. The resulting decoder circuits provide advantages which include improved decoding time, improved density and improved margins over known decoders. --. ~ A
''~' ~ ' B~.~6 1 Description of the Prior Art 2 Tree decoders are well-known in the prior art. One such
''~' ~ ' B~.~6 1 Description of the Prior Art 2 Tree decoders are well-known in the prior art. One such
3 decoder is shown in FIG. 6 of U.S. patent 3,626,391, filed July 15,
4 1968 in the name of W. Anacker and assigned to the same assignee as the ass~gnee of the present invention. These arrangements incorporate 6 current steering and serially disposed actuable devices controlled by 7 address lines block varisus paths so that a path is establlshed to only 8 one of a plurality of outputs to which current is directed.
9 Another decoder arrangement is shown in IB~I Technical Disclosure Bulletin, Vol. 17, No. l, June 1974, p. 280 in an article entitled 11 "Matrix Decoder" by W. Anacker et al. In this arrangement J one out of a ~ --12 plurality of array lines is selected by simultaneously providing gate 13 current to one group out of a pluralit~J of groups of devices simultaneously 14 wi~h control lines each of which connects to a different actuable device in each of tne plurality of groups. The application of a gate current ~;
selects one of the plurality of groups while the simultaneous application 17 of a control current selects one device out of the selected group.
18 Current then flows in the array line associated with the device that was 19 actuat~d by the simultaneous application of gate and control currents.
Summary of the In~ention 21 In accordance with the broadest aspect of the present invention, 22 a multistage decoder circuit is disclosed comprising an input stage ~`
23 circuit which includes an actuable device and a shunting impedance. The 24 ~mpedance and the actuable device are connected by an interconnection line which has at least two output portions. Also included is address 26 loop means associated with each decoder stage. The circuit has at 27 least a pair of address devices connected with each loop means.
1 The actuation of one or the other of the address devices accesses 2 /2 circuits like the input circuit. The output portions of the circuits 3 like the input circuit of the first stage to the ~th-l stage being 4 arranged so that 2N outputs are available per stage; each output portion controlling an actuable device of a circuit like said input circuit.
6 The output portions of the Nth stage are each electrically connected to7 2r3 circuits different from said input clrcuit and N has a value equal to 8 ~ 2, 3, 4 9 In accordance with the broadest aspects of the present invention, a multistage decoder circuit is disclosed which further includes means 11 connected to each of the pair of the address devices for actuating one 12 of said pair per stage to provide for the actuation of one of the circuits 13 different ~rom said input circuit at a time.
14 In accordance with the broader aspects of the present invention, a multistage decoder is provided wherein the actuable device and at 16 least one of the pair of address devices per stage is subjected to the 17 sa~e current.
18 In accordance with the broader aspects of the present invention, 19 a multistage decoder circuit is provided wherein said impedance is a resistor or an actuable device capable of carrying Josephson current.
21 In accordance with the broader aspects of the present invention, 22 a multistage decoder circuit is provided wherein said actuable device 23 and said address devices are devices capable of carrying Josephson 24 current.
In accordance with the broader aspects of the present invention, 26 a multistage decoder circuit is provided wherein said address means is a 27 closed conductive loop having first and second branches each of which is 28 connected to 2~/2 circuits, 2~;
1 In accordance with more particular aspects of the present 2 invention, a multistage decoder circuit is provided wherein said address 3 loop means is a pair of closed conductive loops each of which is connected 4 to 2N/2 circuits.
In accordance with still more particular aspects of the present 6 invention, a multistage decoder circuit is provided wherein the resistor 7 has values of resistance sufficient to render the associated actuable 8 device latching or self-resetting.
9 In accordance with still more particular aspects of the present invention, a multistage decoder circuit is provided further including 11 resetting means connected to said address loop means for suppressing 12 circulating currents in said loop means.
13 It is, therefore, an object of this invention to provide a 14 multistage decoder circuit which has reduced address and resetting times which, in turn, provides reduced memory cycle times.
16 Another object is to provide a loop decoder wherein the address 17 loops instead of being independent of the decoders are integral parts of 18 the decoder.
19 Still another object is to provide a loop decoder wherein the address loops do not cross any actuable device such as an interferometer 21 thereby providing reduced loop inductances. :
22 Still another object is to provide a loop decoder whereby ~he ;
23 providing of address loops eliminates memory address registers thereby 24 enhancing both circuit density and speed.
Yet another object is to provide a loop decoder which has 26 improved operating margins over known tree decoders.
27 Still another object is to provide a loop decoder which is ~
28 less sensitive to disturb currents than known decoders. ~ ;
Yo976-067 -6-3~
1 ~he foregoing and other objects, features and advantages of 2 the invention will become apparent from the following more particular 3 description of the preferred embodiment of the invention as illustrated 4 in the accompanying drawings.
Brief Description of the Drawings 6 ~IGS. lA and lB are schematic drawings of a loop decoder in 7 accordance with the teaching of the present invention which utillzes a 8 plurality of serially disposed address loops each branch of which contains 9 at least one decoder circuit. Each stage after an input circuit stage includes an address loop each branch of which is controlled by an address 11 device disposed in series with a decoder circuit. The first address 12 loop contains two decoder circuits and each succeeding loop thereafter ;~
13 contains twice-as many decoder circuits as a preceding loop. Since each 14 decoder circuit has two outputs associated with it, these output portions control the actuable devices of the decoder circuits in a succeeding 1~ stage. The last stage of the decoder has 2N circuits and outputs only 17 one of which is selected to energize a driver which can be connected to 18 an array ~ine of a Josephson memory array.
19 FIG. 2 is a schematic diagram of a loop decoder in which the address devices of ~he decoder are all connected in series. Each decoder ~ -21 stage after the input circuit is controlled by a pair of address devices 22 and each of these is shunted by an associated address loop. The input 23 circuit of the decoder is an actuable device connected to a shunting 24 impedance by a transmission line. The latter contains two output portions which are utilized to control the actuable de~ices oE decvder circuits 26 which are disposed in series in each of the address loops of succeeding 27 decoder stages~ Each stage contains 2 decoder circuits and half of 1 these are associated with each of the address loops oE each stage.
2 Thus, the second stage has four decoder circuits ~wo of which are disposed 3 in each address loop of that stage. Each of the actuable devices of the 4 second stage is controlled by 2N outputs available from the first stage.The last stage of the decoder of FIG. 2 provides one out of 22 available 6 outputs which may be utilized to energize a driver circuit which is 7 associated with a losephson memory array. Depending on the type of 8 selection for such an array, at least two decod~rs, one for the horizontal 9 selection and one for the vertical selection may be utilized. FIG. 2 shows address loops both with and without reset gates. The former are 11 utilized where the decoder loop resistance is a value such that the 12 actuable gates associated with each decoder circuit are nonlatching or 13 self-resetting. Where the decoder circu:it resistance is of such a value14 that the decoder circuit actuable devices are latching, address loop resetting gates are required. ~ ;~
16 FIG. 3~ is a graphical representation of the current waveform 17 in an address loop of FIG. 2 when the resistance shunting a decoder 18 circuit is of such a value that the actuable device of the decoder ~ -19 circuit is nonlatching or self-resetting.
FIG. 3B is a graphical representation of a current ~raveform as 21 it appears in the output transmission line circuit of a decoder circuit 22 of FIG. 2 when the resistance in the output transmission line circuit is23 of such value as to make its associated actuable device nonlatching or 24 self resetting: ~eset gates are required in this regime.
FIG. 4A is a graphical representation of a current waveform 26 which appears in an address loop of FIG. 2 when its associated device is27 switched and ~rhere the value of resistance in the decoder circuits is 28 sufficient to render the associated actuable devices latching in character.
29 No reset gates are required in this regime.
Y0976~067 -8-1 FIG. 4B is tlle wavefor~ of the current which appears in the 2 output transmission line clrcuit of line decoder circuit of FIG. 2 and 3 are similar to those shown in FIGS. 3B and 3C.
4 ~ ion of Preferred Embodiments .
Referring now to FIGS. lA and lB, there is shown a schematic 6 drawing oE a loop decoder which utilizes a plurality of serially disposed 7 address loops each branch of which contains at least one decoder circuit.
8 Each stage after the input circuit includes an address loop each branch 9 of which is controlled by an address device disposed in series with a decoder loop circuit which can be identified ~7ith the input circuit.
ll The first address loop contains two decoder loop circuits and each 12 succeeding address loop contains twice as many decoder loop circuits as 13 the preceding loop. Since each decoder loop circuit has two outputs 14 associated with it, these output portions control the actuable devices of the decoder loop circuits in a succeeding stage. The last stage of 16 the decoder has 2N circuits and outputs only one of which is selected to17 energiæe a driver which can be connected to an array line of a Josephson18 memory array.
19 Referring now to FIG. 1~ in more detail~ a three-stage decodercircuit 1 is shown the individual stages of which are identified as 1-3.
21 The input consists of a Josephson device Jl shunted by an impedance 2 22 which may be a resistance or a Josephson device which is connected in 23 parallel with device Jl by means of an interconnection line 3 which may 24 be a transmissaon line of given characteristic impedance. Where interconnection line 3 is a transmission linel impedance 2 which is schematically shown 26 as a resistor in Input of FIG. lA would have a value equal to the characteristic 27 impedance of interconnection line 3. As will be seen hereinafter, other ;
YOg76-067 _9_ 1 criteria than the l~pedance of interconnection line 3 govern the value 2 of resistance shunting device Jl. For example, if it is desired that 3 device Jl be latching, impedance 2 will have a relatively high value of 4 resistance. If it is desired that device Jl be self-resetting or nonlatching, impedance 2 will have a relative low value of resistance. As has already 6 been suggested, impedance 2 need not be a resistance but may be a Josephson 7 device which is fabricated to provide a desired value of resistance when 8 its critical current is e~ceeded. This alternative is shown in FIG. lA
9 as a Josephson device 4 connected across Jl by dashed lines. A current source (not shown~ feeds a gate current, Ig to stage I while a control 11 current source (not shown) feeds a control current ID to a control line 12 5. The latter is disposed in electromagnetically coupled relationship 13 with device Jl and when currents I and ID a~e both present, device Jl 14 is switched from its zero voltage state to its voltage state in a manner well-known to those skilled in the Josephson art. The switching of 16 device Jl, as is also well-known, diverts current Ig into interconnection17 line 3 and impedance 2. Then, depending on the value of resistance of ~ -18 impedance 2, device Jl either latches in the voltage state or resets to ~-~
19 the zero voltage state when the control current ID is removed. In either instance, the diverte~ gate current otherwise designa~ed ln FIG.
21 lA as ILl flows in a path designated Ll in FIG. lA which is formed of 22 impedance 2 and interconnection line 3. Where control current, ID, does 23 not flow in control line 5, device Jl does not switch and gate current, 24 Ig, is not dive,rted into path Ll. Current ILl flowing in path Ll, as is well-known, can be adapted to control the switching of a Josephson 26 device dispoaed in an electromagnetically coupled relationship with it 27 to sense the presence of current in path Ll. In the present application, 2~
1 curreLIt ILl flowing in path Ll is used to control two Josephson devices2 J2, J3 which are associated with circuits iden~ical to ~hat described in3 connection with the input stage~ a pair of which make up stage II of 4 decoder circuit 1. The circuit of the input consisting of device Jl, impedance 2 and interco~nection line 3 will hereinafter be designated as 6 decoder loop circuit 6. Thus, stage I of decoder circuit 1 contains two 7 decoder loop circuits 6 each oE which is disposed in a branch 7 of an 8 address loop 8. Each branch 7 of address loop 8 has disposed in series 9 therein an address gate Al, Al to which true and complement address signals, respectively, are applied. Address gates Al, Al are Josephson 11 devices similar to device Jl and in the regime of the present invention,12 when device Al is switched to the voltage state, device Al is in the 13 zero voltage state and vice versa. Address devices Al, Al are utilized 14 to steer current, I , from input into one of the branches 7 of stage I.
At a time before address signals are applied to address gates Al, Al via 16 address control lines 9, current I splits proportional to the inductance17 of branches 7 of address loop 8. The application of an address pulse in ~:
18 control line 9 of device Al places that device in the voltage state 19 ca~sing gate current, I , to flow through address device Al which is in its zero voltage state as a result of the absence of current in its 21 associated control line 9.- When all the gate current i9 diverted from 22 address device Al, it resets to the zero voltage state, in a well known 23 manner as a result.of practically zero current flow through the device.
24 ~rom this, it should be clear that all the gate current, Ig, flows : : .
through device Al and this current has been designated Ig in stage I to 26 differentiate it from the current I C which would flow in the right-most27 branch 7 of stage I if device Al were switched to the voltage state and 28 device Al were in the zero voltage state.
Yo976-067 -11-1 Recalling now that portions of intercolmection line 3 are Z disposed in electromagnetically coupled relationship with devices J2, J3 3 to co~trol the switching of these devices when current II.l flows in path 4 Ll, control lines 10 adapted to carry cùrrent ILl are shown disposed inelectromagnetically coupled relationship with devices J2, J3 of stage I
6 in FIG. lA. To aYoid an unduly complicated drawing, dashed line 11 is 7 sho~n e~tending from the bottom of line 3 to control lines 10, to indicate 8 that control lines 10 are serially disposed portions of line 3 all of 9 which carry the same current, ILl. Current, ILl, of course, will flow in control lines 10 if device Jl of input is actuated by current, ID in 11 control line 5. Where device Jl is unactuated, no current will flow in ~;
12 control lines 10 and devices J2, J3 remain unactuated. Under such 13 circumstances, currents IgT or I C flows through devices J2, J3 depending 14 on which of the address gates Al, al is actuated. When current ILl flows in control lines 10, devices J2, J3 are actuated and the currents 16 IgT or I C flow in the impedances 2 associated with devices J2, J3 17 depending on which of the address gates Al, Al is actuated. In stage I
18 the currents IgT, IgC in paths L2, L3 are designa~ed IL2, IL3, respectively.
19 As with the current ILl of Input, the currents IL2, IL3 are u~ilized to each control a pair of Josephson devices in decoder loop circuits 6 of 21 the succeeding stage II. Thus, ILZ flows in control lines 10 electromagneticall~
Z2 coupled to Josephson de~ices J4, J5 of a pair of decoder loop circuits 6-23 one of the circuits 6 being disposed in one branch 7 of address loop 12 24 while the other is disposed in the other branch 7 of address loop 12 of stage II. Dashed line 13 indicates that control lines 10 of devices J4, 26 J5 electromagnetically coupled thereto are serially disposed portions of27 transmisslon line 3 associated with J2 of stage I and carry the same Y0976-067 -].2-1 current IL2. In a similar way, current IL3 is connected to control 2 lines 10 of devices J6, J7 which form portions of another pair of decoder 3 loop circuit 6 one of which is disposed in one branch 7 of address loop 4 12 and the other of which is disposed in the other branch 7 of address loop 12. Decoder loop circuit 6 which contains d~vice J6 i8 shown 6 disposed in series with decoder loop circuit 6 which contains device J4.7 Similarly decoder loop circuit 6 which contains device J7 is shown 8 disposed in series with decoder loop 6 which contains device J5. Dashed 9 line 14 indicates that current IL3 flows in control lines 10 which are associated with devices J6, J7 and that these control lines 10 form a 11 portion of interconnection line 3 which is associated with device J3 of 12 stage I.
13 Address devices A2, A2 are each shown disposed in series in a 14 different branch 7 of address loop 12 of stage II. ~ddress devices ~2, A2 which may be actuated from an address register in a well-known manner, 16 are utilized to determine into which branch 7 of address loop 12 current17 Igl will flow. Current Igl is the output current from address loop 8 13 and is equal in magnitude to the gate current Ig inl~ially applied to 19 the input of decoder loop circuit 6 of Input.
In a manner slmilar to that described in connection with stage 21 I, depending on which of the address gates A2, A2 are actuated and which22 of the devices J4-J7 of stage II are simultaneously actuated, only one 23 of ~he currents IL4-IL7 will be provided which will actuate a pair of 24 actuable devices out of a plurality of pairs of actuable devices.
Currents IL4, IL6 flow in paths L4, L6, respectively, when either J4 or 26 J6 is switched and are equal to IglT and Igl. I lT flows in left-most 27 branch 7 when address device A2 i9 actuated by means of curre~t flow in Yo976-067 -13-1 its associ.a~ed control line ~. Similarly, current IL5, IL7 flow in 2 paths L5, I7, respectively, when J5 or J7 is switched and are equal to 3 I lC and I 1. I lC flows in right-most branch 7 of address loop 12 when g g g 4 address gate A2 is ac~uaLed. The output current, I 2 of stage II is the S input curre~t to stage III of FIG. lB. Dashed lines 15-18 are shown 6 extending f rom lines 3 of each of the decoder loop circults 6 of stage 7 II to pairs of control lines 10 which are disposed in electromagnetically .
8 coupled relatiollship with actuable devices of pairs of decoder loop `-9 circuits 6 in stage III. Thus, current IL4 controls the actuation of devices J8, J9 disposed in different branches 7 of address loop 19.
11 Similarly, current IL5 controls devices J10, Jll; current IL6 controls 12 devices J12, J16 and current IL7 controls devices J14, J15. Address 13 devices A3, A3 are disposed in series in a different branch 7 of address 14 loop 19. Then, in a manner similar to that discribed in connection with the previous stages, depending on which of the address gates A3, A3 and 16 which of tlle currents IL4 IL7 are provided, one of the currents lL8-IL15 17 is provided in path L8-L15 of decoder loop circuits 6 of stage III.
18 Thus, the actuation of address gate A3 provides current Ig2T in the 19 left-most branch 7 Df address loop 19 while the actuation of address gate A3 provides current Ig2C in right--most branch 7 of address loop 19.
21 These currents are equal to Ig2 and currents Il.8-ILl5 are 22 equal to Ig2 if they appear in an impedance 2 associated with the decoder 23 loop circuits 6 of stage III. Interconnection lines 3 of decoder loop 24 circuit 6 of stage III are each shown disposed in electromagnetically coupled relati~nship with a Josephson device 209 ~hich, for example, may 26 be a portion of a driver circuit which provides current to a word Dr bit 27 line of Josephson memory array.
l Using the arrangement of FIG. lB, current Ig2 which Is equal 2 to current Ig initially applied to decoder circuit l is delivered to 3 only one of the interconnection lines 3 of the decoder loop circuits 6 of 4 stage III. This current is then utilized to actuate a selected driver circuit or other device depending on which oE the devices Jl, Al or Al, 6 A2 or A2, or A3 or A3 are actuated. ~or example, if devices Jl, Al, A2 7 and A3 are actuated, current Ig will appear in impedance 2 of Input as 8 current ILl which, in turn, actuates devices J2, J3. Since address g device Al is actuated, current Ig appearing as IgC is diverted into right-most branch 7 of stage I. Since device J3 of stage I is actuated, 11 current I C appearing as current IL3 in interconnection line 3 associated --g 12 with device J3 flows in interconnection line 3 and actuates devices J6, 13 J7 of the succeeding stage II. Current IL3 appears at the output of ~ ~
14 stage I as current Igl where, because address device A2 is actuated, it ~ -is diverted into left-most branch 7 of address loop 12 and appears in 16 that branch as IglT Since device J4 is unactuated, current flows 17 through that device until it encounters ac~uated device J6 which causes 18 it to be diverted into the interconnect:ion line 3 associated with that 19 device and current IglT appears in line 3 as current IL6. This current in turn actuates devices J12, ~13 of stage III via associated control 21 windings 10 which carry that current. Current IL6 now appears at the 22 output of address loop 12 as current I 2 where, as the input to address 23 loop 19, it is diverted into the right-most branch 7 of address loop 19 24 and appears therein as current Ig2C. The latter current flows through unactuated devices J9 and Jll until it encounters actuated device J13. ;~;
26 Then current Ig2C is diverted into interconnection line 3 associated 27 with that device where it appears as current IL13. Current IL13 is used 1 to actuate a device 20 disposed in electro~agnetically coupled relationship 2 with line 3 thereof which, in turn, is used to drive a word line of a 3 memory array, for example. From thence current IL13 passes through 4 unactuated device J15 to ground. From the foregoing example, it should be obvious that by actuating device Jl and various address gates, any 6 one out of 8 possible outputs can be provided. It should also be obvious 7 that the addition of other stages can provide for the selection of 1 out 8 of 16 outputs and so on.
9 Earlier in this discussion, reference has been made to the fact that decoder loop circult 6 associated with each of the address 11 loops 8, 12, 15, 19 can be latching or nonlatching by simply adjusting 12 the value of the resistance to impedance 2 of each of decoder circuits 13 6. If the value of resistance of impedance 2 is relatively large, the 14 Josephson devices shunted by such a value of resistance are latching in character and the circuit of FIGS. lA, lB would be unchanged from that 16 ~ust described. Ilowever, where the value of resistance of impedance 2 17 shunting each of the Josephson devices is relatively small, decoder 18 circuits 6 are nonlatching or self-resetting in character. Because of L9 the dynamics of the situation, and contrary to what might be expected, reset gates would be required in each of the branches 7 of address loops 21 8, 12, 15, and 19 to eliminate circulating currents. Thus, separately 22 actuated reset gates 21 would be disposed in each branch 7 of decoder 23 loops 8, 12, 15, and 19.
24 Refer~ing now to decoder loop 8 of FIG. lA and assuming that the resistance of impedance 2 of decoder loop 6 is~sufficient to render 26 such circuits latching in character and assuming address device Al to be 27 unactuated while address device Al is actuated, the dyna~ics of the 28 situation are as follows:
., .
~3~2~.~
1 Current I C is diverted into the left-most branch 7 of address 2 loop ~. Witll respect to address device Al, that device encounters a 3 current which is decaying while branch 7 encounters a current which is 4 rising and reaches a steady state in a time which is a function of the inductance oE address loop 80 When all the current has been removed 6 from right-most branch 7, device Al reset~s immediately because the 7 current has fallen below the I i ~ device Al. At this point, assuming that devices J2, J3 are actuated by control curren~ ILl, device J2 9 switches diverting current into path L2. Device Al which has already lQ reset to the zero voltage state as a result of having no current in it, 11 now presents a short circuit across left-most branch 7 of address loop 12 8. It should be noted that address device Al and device J3 are in the 13 zero voltage state thereby presen~ing a short circuit path across left-14 most decoder circuit 6 of address loop 8. Current IgT, upon switching Gf J2, now attempts to pass from left-most branch 7 into right-mos~
16 branch 7 which is a short circuit. It cannot do so immediately because 17 the branch current now sees the parallel combination of the resistance 18 of impedance 2 of path L2 and the device resistance~ Rj, of device J2 l9 and decays with the time constant L/R where R is the parallel combination of the resistance of path L2 and the device resistance, Rj, of device 21 J2.
22 The current in device J2 having been diverted to path L2 and 23 having provided an output IL2 now decays in the same manner as the loop 24 current and current builds up in device Al correspondingly. When the current in device J2 decays to a point where Imin of device J2 is r~ached, 26 that device resets to the zero voltage state. All the current is now in 27 right-most branch 7 and device Al is ready for another cycle.
YOg75-067 -17-l Where the resistance of path L2 is sufficiently small to 2 render decoder loop circuit 6 of left-most branch 7 of address loop 8 3 nonlatching or self-resetting, a slightly different situation is encountered 4 after device Al switches to the voltage state. I~hile the build-up of current in left-most branch 7 of address loop 8 is exactly the same as 6 that described in connection with operation in the latching mode described ~-7 hereinabove, the dynamics of decoder circuit 6 are different once device 8 J2 switches to the voltage state. At this point, the branch current IgT
9 drops a small amount as a result of the current being diverted into impedance 2 of path L2. When device J2 s~itches, because of the high 11 inductance of the address loop, the current in impedance 2 rises instantan-12 eously to a peak value while current in ehe address loops drops only 13 slightly as a function of the ratio of the inductances iD the decoder 14 loop to the inductance in the address loop. In the usual case, the ratio is 1:12. Further current drop in the address loop is precluded by 16 device J2 resetting instantaneously to the zero voltage state because of 17 the low resistance of impedance 2. The output pulse available in path ;
1~ L2 may be used to actuate a subsequent decodlng loop. Now, however, 19 because current remains in the address loop due t~ the zero voltage states in both devices J2 and Al, the initial conditions must be brought 21 about so a subsequent cycle can be carried out. This is accomplis~hed by 22 actuating reset gate 21 associated with right-most branch 27 of address 23 loop 8. Typical values for the resistance of impedance 2 in ioop decoder 24 circuit 6 is 1 ohms for the latching situation and 0.2 ohms for the self-resetting situation at current levels of 2ma.
26 Referring now to FIG. 2, there is shown therein a schematic 27 diagra~ of a loop decoder in which the address devices of the decoder Yo976-067 -18-.
1 are all connected in series. Each decoder stage a~ter the Input is 2 controlled by a palr of address devices and each of these is shunted by 3 an associated address loop~ The Input of the decoder is an actuable 4 device connected to a shunting impedance by a transmission line. The latter contains two output portions which are utilized to control the 6 actuable devices of decoder loop circuîts which are disposed in series 7 in each of the address loop3 of succeeding decoder stages. Each stage 8 contains 2N decoder clrcuits and half of these are associated with each 9 of the address loops of each stage. Thus, the second stage has four decoder circuits, 2 of which are disposed in each address loop of that 11 stage. Each of the actuable devices of the second stage is controlled 12 by 2N outputs available from the first stage. The last stage oE the 13 decoder of FIG. 2 provides one out of 2N available outputs which may be 14 utilized to energize a driver circuit which is associated with a Josephson memory array line.
16 Referring now to FIG. 2 in more detail, Input of decoder 17 circuit 30 is identical with decoder circuit 6 of FIG. 1 and the same 18 elements in FIG. 2 are designated with the same reference characters as 19 u~ed in FIG. lA and lB. Impedan~e 2 may have a value of resistance equal to the characteristic impedance of transmission line 3 and, in 21 addition, it may have values of resistance whi~h render loop decoder 22 circuit 6 of stage 1 either latching or self-resetting. As with Input 23 of FIG. lA, Josephson device Jl may be shunted by an actuable Josaphson 24 device instead of an impedance 2. FIG. 2 shows a Josephson device 4 connected across device Jl by dashed lines. If device Jl is actuated by 2~ a combination of the currents Ig and ID, then, as described in connection Y097~-067 -19-1 with FIG. lA, current I is diverted into path Ll and appears therein as 2 the current ILl. As wlll be seen in what follows, current ILl will be 3 utilized to ac~uate Josephson devices J2, J3 via control line portions 4 10 which are serially disposed portions oE transmission line 3 of decoder loop circuit 6 of Input.
6 Address devices Al, Al which are devices capable of carrying 7 Josephson currents are shown in FIG. 2 disposed in series with device Jl ;
and are shown shunted by address loops 31, 32, respectively. Address 9 loops 31, 32 include serially disposed actuable devices J2, J3, respectively which are capable of carrying Josephson current. Each of the devices 11 J2, J3 is shunted by an impedance 2 and transmission line 3 forming 12 paths L2, L3, respectively. Paths L2, L3 carry currents IL2, IL3, 13 respectively, when devices J2, J3 are enabled depending on which of the 14 address devices Al, Al is actuated. As indicated hereinabove, devices J2, J3 are actuated by an associated control line portion 10 which 16 carries current ILl through these serially disposed por~ions which form 17 a portion of transmission line 3 of decoder loop 6 o~ Input. To avoid 18 an unduly complicated drawing, dashed line 33 is shown extending from 19 the bottom of transmission line 3 to control lines 10 indicating that control lines 10 are serially disposed portions of line 3, all of which 21 carry the same current ILl. Address devices Al, Al are actuated by 22 applying address current to associated control lines 9 and, when one of 23 these devices is actuated, the other is unactuated. Thus~ if device Al 24 is actuated, current Ig appears in address loop 31 as current I T~
Similarly when address device Al is actuated, current I appears in loop 26 32 as current IgC. These same currents appear in paths L2, L3 as currents 27 IL2, IL3, respectively when J2, J3 are actuated.
Y0976~067 ~20-8~L~
1 Stage II of decoder circuit 30 is similar to stage I except 2 that the address loops 34, 35 thereo~ each contain an additional decoder 3 loop circuit 6 in the address loops. Thus, address devices A2, A2 are 4 shunted by address loops 349 35 respectlvely, and the former contains a S pair of serially disposed Josephson junctions J4, J5 while the latter 6 similarly contains a pair of serially disposed Josephson junctions J6, 7 J7. Each of these devlces is shunted by an impedance 2 which is connected 8 across each device by a transmission line 3. These elements make up 9 paths L4-L7 which are adapted to carry currents IL4-IL7, respectively O
Josephson devices J4, J5 are actua~ed by currents IL2, IL3 respectively.
11 In a similar way, Josephson devices J6, J7 are actuated by currents IL2 12 and IL3, respectively. These currents appear in associated control 13 lines 10 which for those that carry current IL2 are serial portions of ~ ~
14 transmission line 3 of path L2. For those that carry current IL3, ;
control lines 10 are serial portions of transmission line 3 of path L3.
16 Again, to avoid an unduly complicated drawing, dashed lines 36~ 37 are 17 shown extending from the bottom of paths L2, L3, respectively to control 18 lines 10 and indicate that control lines 10 a~e serially disposed portions -~
19 of line 3 of paths L2, L3, respectively.
As with the previously described address devices, devices A2, 21 A2, if actuated, divert current Ig into loops 34 or 35 and that current 22 appears therein as current IglT, IglC9 respectively. Thus, depending on 23 whether device Jl is actuated and which of the address devices is actuated, 24 none or one of ~he outputs IL4-IL7 is provlded as an output which may be utilized to actuate an associated Josephson device 38 disposed in electro-26 magnetically coupled relationship with paths L4-L7. Devi.ces 38 may for 27 example be utilized to energize a memory array line.
Yo976-067 -21-.. ....
1 FIG. 2 shows reset gates 39 serlally disposed in each of the 2 add~ess loops 31~35. Reset gates 39 are utilized in the same manner as 3 reset gates 21 of FIG. 1. They are utilized in the mode wherein the 4 value of resistance of impedance 2 associated with each of the devices Jl-J7 has a value of resistance sufficiently small to make the devices 6 self-resetting. Where this same impedance has a value of res-lstance 7 which is ~uch higher, devices Jl-J7 operate in a latching mode and no 8 reset gates 39 are required.
9 If device Jl is actuated and addre~s devices Al and A2 are actuated, current ILS is provided in the path LS actuating its associated 11 Josephson device 38. Thus, the actuatlon of Jl provides current ILl in 12 path Ll. This current appears in stage I as I 1 and passes through 13 address device Al which is unactuated. This same current, however, 14 encounters actuated address Al and it is diverted into loop 32 where it appears as IgC. Because device J3 is actuated as a result of current 16 ILl being present in its associated control line 10, current I C is 17 diverted into path L3 and appears therein as current IL3. Current IL3 18 leaves address loop 32 and appears as current I 1 as an input to stage 19 II. Because address device A2 i5 actuated, current Igl is diverted into loop 34 and appears therein as current IglT. This current, because it 21 encounters actuated Josephson device J5 as a result of current IL3 2~ appearing in its associated control line 10, is diverted into path L5 23 where it appears as output current IL5.
24 It should be appreciated, at this point~ that the arrange~ent of FIG. 2 can be extended to any number of stages to pro~ide for the 26 selection of 1 out of 8, 1 out of 16 or 1 out of 32 outputs, for example.
l Referring now to FLGS. 3A-3B, FIG 3A is a graphical representation 2 of the current wavefor~ in an address loop when the resistance shunting 3 a decoder circuit 6 is of such a value that the actuable device thereof 4 is nonlatch:lng or self-resetting and FIG. 3B is a graphical representation of the resulting current waveform as it appears i~ the output transmission 6 line of a decoder circuit 6.
7 Considering FIGS. 3A~3B, in conjunction with address device Al 8 and address loop 31 of FIG. 2, when device Al switches, current is 9 dlverted into address loop 31. Address loop 31 encounters a rising current which is a function of the inductance of loop 31 and reaches a 11 steady state condition as indicated at 40 in FIG. 3A. At this point, 12 device J2 switches diverting current IgT mo~entarily into path L2 as ~ -13 current IL2. However, because the resistance of the impedance in path 14 L2 is small, device J2 resets to the ~ero voltage state immediately~
lS causing current IgT to drop only a small amount as shown at 41 in FIG.
16 3A. When device J2 switched, because of the high inductance of address 17 loop 31, the current in impedance 2 of path 1,2 rises instantaneously to 18 a peak value as shown at 42 in FIG. 3B while current in address loop 31 19 drops only slightly as a function of the ratio of the inductance in decoder loop circuit 6 to the inductance in address loop 31. In a usual 21 case, the ratio may be 1-12. Further current drop in address loop 31 ls 22 precluded by device J2 resetting instantaneously to the zero voltage 23 state because of the low resistaDce of impedance 2. The output pulse 24 available in path LZ may be used to actuate a subsequent decoder loop c~rcuit 6. Now, however, because current remalns in address loop 31 due 1 to the zero voltage states of both devices J2 and Al, the initial conditions 2 must be brought about so a subsequent cycle can be carried out. This is 3 accomplished by actu~ting reset gate 39 associated with address loop 31.
4 Where the resistance of impedance 2 of decoder loop circuit 6 associated with device J2 is sufficient to render such circuits latching 6 in character, the situation is slightly different and reset gates 39 are 7 not required. When address device Al is actuated, the current I T
8 appears in address loop 31 and the current rises to a steady state value g shown at 40 in FIG. 4A in the same manner as described in connection with FIG. 3A. When all the current has been diverted into address loop ll 31, address device Al resets lmmediately because current has fallen 12 below the Imin of that deviceO At this point, device J2 is actuated by 13 current ILl and device J2 switches diverting current into path L2.
14 Device Al which has already reset to the zero voltage state as a result of having no current in lt, now presents a short circuit across address 16 loop 31. Current IgT now attempts to pass from address loop 31 into the .`
17 now short-circuited branch which contains address device Al. It cannot 18 do so instantaneously because the loop current now encounters the parallel19 combination of the resistance of impedance 2 of path L2 and the device resistance, Rj of device J2 and decays with the ~ime constant L/R where 21 R ls the parallel eombination of the resistance of impedance 2 and ~he 22 device resistance, Rj, of device J2.
23 The current in device J2 having been diverted and having 24 provided an out~ut 43 as shown in FIG. 4B now decays in the same manner as the current in addre.ss loop 31 and shown in FIG. 4A and 4B at 44.
26 When the current in device J2 decays to a point where I i of device J2 27 ls reached, that device resets to the æero voltage state. All the 1 current is now removed from address loop 31 and flows in device Al which 2 is in the æero voltage state. Address device Al is now ready for another 3 cycle.
4 The address devices and the actuable Josephson devices mentioned hereinabove in connection with FIGS. lA, lB and 2 may be any well-known 6 type of Josephscn junction or may be a multiple junction device known as 7 an interferometer. In addition, all the interconnection circuitry like ~ -8 transmission lines 3, control conductors 9, 10 and the conductors of the 9 various address loops are ~ade from materials which are superconductive ~ ~
at the tempe}ature of liquid helium (approximately 4.2K~. Typical ~;
ll Josephson junctions and interconnection circuitry which may be utillzed 12 in the practice of the present invention are shown in U.S. patent 3,758,795, 13 S.N. 267~841, filed June 30, 1972 and assigned to the same assignee as 14 the present invention. A typical fabricatio~ technique for form-ing Josephson junction devices is shown in U.S. patent 3,349,276, S.N.
16 125~993, filed March 19, 1971. Resistive terminations 2 which must not 17 be superconductive at the circuit operation temperature may be fabricated 18 with compatible materials which display resistance at the desired operating 19 temperature. U.S.patent 3,913,120, S.N. 429,461 filed December 28, 1973 and assigned to the saMe assignee as the present invention shows a 21 material and method of fabrication for circuitry and a terminating 22 resistor which may be utilized in the practice of the present invention.
23 While the invention has been particularly shown and described 24 wlth reference to preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in form 26 and details may be made ~herein without departing from the spirit and 27 scope of the invention.
TJK/ mm
9 Another decoder arrangement is shown in IB~I Technical Disclosure Bulletin, Vol. 17, No. l, June 1974, p. 280 in an article entitled 11 "Matrix Decoder" by W. Anacker et al. In this arrangement J one out of a ~ --12 plurality of array lines is selected by simultaneously providing gate 13 current to one group out of a pluralit~J of groups of devices simultaneously 14 wi~h control lines each of which connects to a different actuable device in each of tne plurality of groups. The application of a gate current ~;
selects one of the plurality of groups while the simultaneous application 17 of a control current selects one device out of the selected group.
18 Current then flows in the array line associated with the device that was 19 actuat~d by the simultaneous application of gate and control currents.
Summary of the In~ention 21 In accordance with the broadest aspect of the present invention, 22 a multistage decoder circuit is disclosed comprising an input stage ~`
23 circuit which includes an actuable device and a shunting impedance. The 24 ~mpedance and the actuable device are connected by an interconnection line which has at least two output portions. Also included is address 26 loop means associated with each decoder stage. The circuit has at 27 least a pair of address devices connected with each loop means.
1 The actuation of one or the other of the address devices accesses 2 /2 circuits like the input circuit. The output portions of the circuits 3 like the input circuit of the first stage to the ~th-l stage being 4 arranged so that 2N outputs are available per stage; each output portion controlling an actuable device of a circuit like said input circuit.
6 The output portions of the Nth stage are each electrically connected to7 2r3 circuits different from said input clrcuit and N has a value equal to 8 ~ 2, 3, 4 9 In accordance with the broadest aspects of the present invention, a multistage decoder circuit is disclosed which further includes means 11 connected to each of the pair of the address devices for actuating one 12 of said pair per stage to provide for the actuation of one of the circuits 13 different ~rom said input circuit at a time.
14 In accordance with the broader aspects of the present invention, a multistage decoder is provided wherein the actuable device and at 16 least one of the pair of address devices per stage is subjected to the 17 sa~e current.
18 In accordance with the broader aspects of the present invention, 19 a multistage decoder circuit is provided wherein said impedance is a resistor or an actuable device capable of carrying Josephson current.
21 In accordance with the broader aspects of the present invention, 22 a multistage decoder circuit is provided wherein said actuable device 23 and said address devices are devices capable of carrying Josephson 24 current.
In accordance with the broader aspects of the present invention, 26 a multistage decoder circuit is provided wherein said address means is a 27 closed conductive loop having first and second branches each of which is 28 connected to 2~/2 circuits, 2~;
1 In accordance with more particular aspects of the present 2 invention, a multistage decoder circuit is provided wherein said address 3 loop means is a pair of closed conductive loops each of which is connected 4 to 2N/2 circuits.
In accordance with still more particular aspects of the present 6 invention, a multistage decoder circuit is provided wherein the resistor 7 has values of resistance sufficient to render the associated actuable 8 device latching or self-resetting.
9 In accordance with still more particular aspects of the present invention, a multistage decoder circuit is provided further including 11 resetting means connected to said address loop means for suppressing 12 circulating currents in said loop means.
13 It is, therefore, an object of this invention to provide a 14 multistage decoder circuit which has reduced address and resetting times which, in turn, provides reduced memory cycle times.
16 Another object is to provide a loop decoder wherein the address 17 loops instead of being independent of the decoders are integral parts of 18 the decoder.
19 Still another object is to provide a loop decoder wherein the address loops do not cross any actuable device such as an interferometer 21 thereby providing reduced loop inductances. :
22 Still another object is to provide a loop decoder whereby ~he ;
23 providing of address loops eliminates memory address registers thereby 24 enhancing both circuit density and speed.
Yet another object is to provide a loop decoder which has 26 improved operating margins over known tree decoders.
27 Still another object is to provide a loop decoder which is ~
28 less sensitive to disturb currents than known decoders. ~ ;
Yo976-067 -6-3~
1 ~he foregoing and other objects, features and advantages of 2 the invention will become apparent from the following more particular 3 description of the preferred embodiment of the invention as illustrated 4 in the accompanying drawings.
Brief Description of the Drawings 6 ~IGS. lA and lB are schematic drawings of a loop decoder in 7 accordance with the teaching of the present invention which utillzes a 8 plurality of serially disposed address loops each branch of which contains 9 at least one decoder circuit. Each stage after an input circuit stage includes an address loop each branch of which is controlled by an address 11 device disposed in series with a decoder circuit. The first address 12 loop contains two decoder circuits and each succeeding loop thereafter ;~
13 contains twice-as many decoder circuits as a preceding loop. Since each 14 decoder circuit has two outputs associated with it, these output portions control the actuable devices of the decoder circuits in a succeeding 1~ stage. The last stage of the decoder has 2N circuits and outputs only 17 one of which is selected to energize a driver which can be connected to 18 an array ~ine of a Josephson memory array.
19 FIG. 2 is a schematic diagram of a loop decoder in which the address devices of ~he decoder are all connected in series. Each decoder ~ -21 stage after the input circuit is controlled by a pair of address devices 22 and each of these is shunted by an associated address loop. The input 23 circuit of the decoder is an actuable device connected to a shunting 24 impedance by a transmission line. The latter contains two output portions which are utilized to control the actuable de~ices oE decvder circuits 26 which are disposed in series in each of the address loops of succeeding 27 decoder stages~ Each stage contains 2 decoder circuits and half of 1 these are associated with each of the address loops oE each stage.
2 Thus, the second stage has four decoder circuits ~wo of which are disposed 3 in each address loop of that stage. Each of the actuable devices of the 4 second stage is controlled by 2N outputs available from the first stage.The last stage of the decoder of FIG. 2 provides one out of 22 available 6 outputs which may be utilized to energize a driver circuit which is 7 associated with a losephson memory array. Depending on the type of 8 selection for such an array, at least two decod~rs, one for the horizontal 9 selection and one for the vertical selection may be utilized. FIG. 2 shows address loops both with and without reset gates. The former are 11 utilized where the decoder loop resistance is a value such that the 12 actuable gates associated with each decoder circuit are nonlatching or 13 self-resetting. Where the decoder circu:it resistance is of such a value14 that the decoder circuit actuable devices are latching, address loop resetting gates are required. ~ ;~
16 FIG. 3~ is a graphical representation of the current waveform 17 in an address loop of FIG. 2 when the resistance shunting a decoder 18 circuit is of such a value that the actuable device of the decoder ~ -19 circuit is nonlatching or self-resetting.
FIG. 3B is a graphical representation of a current ~raveform as 21 it appears in the output transmission line circuit of a decoder circuit 22 of FIG. 2 when the resistance in the output transmission line circuit is23 of such value as to make its associated actuable device nonlatching or 24 self resetting: ~eset gates are required in this regime.
FIG. 4A is a graphical representation of a current waveform 26 which appears in an address loop of FIG. 2 when its associated device is27 switched and ~rhere the value of resistance in the decoder circuits is 28 sufficient to render the associated actuable devices latching in character.
29 No reset gates are required in this regime.
Y0976~067 -8-1 FIG. 4B is tlle wavefor~ of the current which appears in the 2 output transmission line clrcuit of line decoder circuit of FIG. 2 and 3 are similar to those shown in FIGS. 3B and 3C.
4 ~ ion of Preferred Embodiments .
Referring now to FIGS. lA and lB, there is shown a schematic 6 drawing oE a loop decoder which utilizes a plurality of serially disposed 7 address loops each branch of which contains at least one decoder circuit.
8 Each stage after the input circuit includes an address loop each branch 9 of which is controlled by an address device disposed in series with a decoder loop circuit which can be identified ~7ith the input circuit.
ll The first address loop contains two decoder loop circuits and each 12 succeeding address loop contains twice as many decoder loop circuits as 13 the preceding loop. Since each decoder loop circuit has two outputs 14 associated with it, these output portions control the actuable devices of the decoder loop circuits in a succeeding stage. The last stage of 16 the decoder has 2N circuits and outputs only one of which is selected to17 energiæe a driver which can be connected to an array line of a Josephson18 memory array.
19 Referring now to FIG. 1~ in more detail~ a three-stage decodercircuit 1 is shown the individual stages of which are identified as 1-3.
21 The input consists of a Josephson device Jl shunted by an impedance 2 22 which may be a resistance or a Josephson device which is connected in 23 parallel with device Jl by means of an interconnection line 3 which may 24 be a transmissaon line of given characteristic impedance. Where interconnection line 3 is a transmission linel impedance 2 which is schematically shown 26 as a resistor in Input of FIG. lA would have a value equal to the characteristic 27 impedance of interconnection line 3. As will be seen hereinafter, other ;
YOg76-067 _9_ 1 criteria than the l~pedance of interconnection line 3 govern the value 2 of resistance shunting device Jl. For example, if it is desired that 3 device Jl be latching, impedance 2 will have a relatively high value of 4 resistance. If it is desired that device Jl be self-resetting or nonlatching, impedance 2 will have a relative low value of resistance. As has already 6 been suggested, impedance 2 need not be a resistance but may be a Josephson 7 device which is fabricated to provide a desired value of resistance when 8 its critical current is e~ceeded. This alternative is shown in FIG. lA
9 as a Josephson device 4 connected across Jl by dashed lines. A current source (not shown~ feeds a gate current, Ig to stage I while a control 11 current source (not shown) feeds a control current ID to a control line 12 5. The latter is disposed in electromagnetically coupled relationship 13 with device Jl and when currents I and ID a~e both present, device Jl 14 is switched from its zero voltage state to its voltage state in a manner well-known to those skilled in the Josephson art. The switching of 16 device Jl, as is also well-known, diverts current Ig into interconnection17 line 3 and impedance 2. Then, depending on the value of resistance of ~ -18 impedance 2, device Jl either latches in the voltage state or resets to ~-~
19 the zero voltage state when the control current ID is removed. In either instance, the diverte~ gate current otherwise designa~ed ln FIG.
21 lA as ILl flows in a path designated Ll in FIG. lA which is formed of 22 impedance 2 and interconnection line 3. Where control current, ID, does 23 not flow in control line 5, device Jl does not switch and gate current, 24 Ig, is not dive,rted into path Ll. Current ILl flowing in path Ll, as is well-known, can be adapted to control the switching of a Josephson 26 device dispoaed in an electromagnetically coupled relationship with it 27 to sense the presence of current in path Ll. In the present application, 2~
1 curreLIt ILl flowing in path Ll is used to control two Josephson devices2 J2, J3 which are associated with circuits iden~ical to ~hat described in3 connection with the input stage~ a pair of which make up stage II of 4 decoder circuit 1. The circuit of the input consisting of device Jl, impedance 2 and interco~nection line 3 will hereinafter be designated as 6 decoder loop circuit 6. Thus, stage I of decoder circuit 1 contains two 7 decoder loop circuits 6 each oE which is disposed in a branch 7 of an 8 address loop 8. Each branch 7 of address loop 8 has disposed in series 9 therein an address gate Al, Al to which true and complement address signals, respectively, are applied. Address gates Al, Al are Josephson 11 devices similar to device Jl and in the regime of the present invention,12 when device Al is switched to the voltage state, device Al is in the 13 zero voltage state and vice versa. Address devices Al, Al are utilized 14 to steer current, I , from input into one of the branches 7 of stage I.
At a time before address signals are applied to address gates Al, Al via 16 address control lines 9, current I splits proportional to the inductance17 of branches 7 of address loop 8. The application of an address pulse in ~:
18 control line 9 of device Al places that device in the voltage state 19 ca~sing gate current, I , to flow through address device Al which is in its zero voltage state as a result of the absence of current in its 21 associated control line 9.- When all the gate current i9 diverted from 22 address device Al, it resets to the zero voltage state, in a well known 23 manner as a result.of practically zero current flow through the device.
24 ~rom this, it should be clear that all the gate current, Ig, flows : : .
through device Al and this current has been designated Ig in stage I to 26 differentiate it from the current I C which would flow in the right-most27 branch 7 of stage I if device Al were switched to the voltage state and 28 device Al were in the zero voltage state.
Yo976-067 -11-1 Recalling now that portions of intercolmection line 3 are Z disposed in electromagnetically coupled relationship with devices J2, J3 3 to co~trol the switching of these devices when current II.l flows in path 4 Ll, control lines 10 adapted to carry cùrrent ILl are shown disposed inelectromagnetically coupled relationship with devices J2, J3 of stage I
6 in FIG. lA. To aYoid an unduly complicated drawing, dashed line 11 is 7 sho~n e~tending from the bottom of line 3 to control lines 10, to indicate 8 that control lines 10 are serially disposed portions of line 3 all of 9 which carry the same current, ILl. Current, ILl, of course, will flow in control lines 10 if device Jl of input is actuated by current, ID in 11 control line 5. Where device Jl is unactuated, no current will flow in ~;
12 control lines 10 and devices J2, J3 remain unactuated. Under such 13 circumstances, currents IgT or I C flows through devices J2, J3 depending 14 on which of the address gates Al, al is actuated. When current ILl flows in control lines 10, devices J2, J3 are actuated and the currents 16 IgT or I C flow in the impedances 2 associated with devices J2, J3 17 depending on which of the address gates Al, Al is actuated. In stage I
18 the currents IgT, IgC in paths L2, L3 are designa~ed IL2, IL3, respectively.
19 As with the current ILl of Input, the currents IL2, IL3 are u~ilized to each control a pair of Josephson devices in decoder loop circuits 6 of 21 the succeeding stage II. Thus, ILZ flows in control lines 10 electromagneticall~
Z2 coupled to Josephson de~ices J4, J5 of a pair of decoder loop circuits 6-23 one of the circuits 6 being disposed in one branch 7 of address loop 12 24 while the other is disposed in the other branch 7 of address loop 12 of stage II. Dashed line 13 indicates that control lines 10 of devices J4, 26 J5 electromagnetically coupled thereto are serially disposed portions of27 transmisslon line 3 associated with J2 of stage I and carry the same Y0976-067 -].2-1 current IL2. In a similar way, current IL3 is connected to control 2 lines 10 of devices J6, J7 which form portions of another pair of decoder 3 loop circuit 6 one of which is disposed in one branch 7 of address loop 4 12 and the other of which is disposed in the other branch 7 of address loop 12. Decoder loop circuit 6 which contains d~vice J6 i8 shown 6 disposed in series with decoder loop circuit 6 which contains device J4.7 Similarly decoder loop circuit 6 which contains device J7 is shown 8 disposed in series with decoder loop 6 which contains device J5. Dashed 9 line 14 indicates that current IL3 flows in control lines 10 which are associated with devices J6, J7 and that these control lines 10 form a 11 portion of interconnection line 3 which is associated with device J3 of 12 stage I.
13 Address devices A2, A2 are each shown disposed in series in a 14 different branch 7 of address loop 12 of stage II. ~ddress devices ~2, A2 which may be actuated from an address register in a well-known manner, 16 are utilized to determine into which branch 7 of address loop 12 current17 Igl will flow. Current Igl is the output current from address loop 8 13 and is equal in magnitude to the gate current Ig inl~ially applied to 19 the input of decoder loop circuit 6 of Input.
In a manner slmilar to that described in connection with stage 21 I, depending on which of the address gates A2, A2 are actuated and which22 of the devices J4-J7 of stage II are simultaneously actuated, only one 23 of ~he currents IL4-IL7 will be provided which will actuate a pair of 24 actuable devices out of a plurality of pairs of actuable devices.
Currents IL4, IL6 flow in paths L4, L6, respectively, when either J4 or 26 J6 is switched and are equal to IglT and Igl. I lT flows in left-most 27 branch 7 when address device A2 i9 actuated by means of curre~t flow in Yo976-067 -13-1 its associ.a~ed control line ~. Similarly, current IL5, IL7 flow in 2 paths L5, I7, respectively, when J5 or J7 is switched and are equal to 3 I lC and I 1. I lC flows in right-most branch 7 of address loop 12 when g g g 4 address gate A2 is ac~uaLed. The output current, I 2 of stage II is the S input curre~t to stage III of FIG. lB. Dashed lines 15-18 are shown 6 extending f rom lines 3 of each of the decoder loop circults 6 of stage 7 II to pairs of control lines 10 which are disposed in electromagnetically .
8 coupled relatiollship with actuable devices of pairs of decoder loop `-9 circuits 6 in stage III. Thus, current IL4 controls the actuation of devices J8, J9 disposed in different branches 7 of address loop 19.
11 Similarly, current IL5 controls devices J10, Jll; current IL6 controls 12 devices J12, J16 and current IL7 controls devices J14, J15. Address 13 devices A3, A3 are disposed in series in a different branch 7 of address 14 loop 19. Then, in a manner similar to that discribed in connection with the previous stages, depending on which of the address gates A3, A3 and 16 which of tlle currents IL4 IL7 are provided, one of the currents lL8-IL15 17 is provided in path L8-L15 of decoder loop circuits 6 of stage III.
18 Thus, the actuation of address gate A3 provides current Ig2T in the 19 left-most branch 7 Df address loop 19 while the actuation of address gate A3 provides current Ig2C in right--most branch 7 of address loop 19.
21 These currents are equal to Ig2 and currents Il.8-ILl5 are 22 equal to Ig2 if they appear in an impedance 2 associated with the decoder 23 loop circuits 6 of stage III. Interconnection lines 3 of decoder loop 24 circuit 6 of stage III are each shown disposed in electromagnetically coupled relati~nship with a Josephson device 209 ~hich, for example, may 26 be a portion of a driver circuit which provides current to a word Dr bit 27 line of Josephson memory array.
l Using the arrangement of FIG. lB, current Ig2 which Is equal 2 to current Ig initially applied to decoder circuit l is delivered to 3 only one of the interconnection lines 3 of the decoder loop circuits 6 of 4 stage III. This current is then utilized to actuate a selected driver circuit or other device depending on which oE the devices Jl, Al or Al, 6 A2 or A2, or A3 or A3 are actuated. ~or example, if devices Jl, Al, A2 7 and A3 are actuated, current Ig will appear in impedance 2 of Input as 8 current ILl which, in turn, actuates devices J2, J3. Since address g device Al is actuated, current Ig appearing as IgC is diverted into right-most branch 7 of stage I. Since device J3 of stage I is actuated, 11 current I C appearing as current IL3 in interconnection line 3 associated --g 12 with device J3 flows in interconnection line 3 and actuates devices J6, 13 J7 of the succeeding stage II. Current IL3 appears at the output of ~ ~
14 stage I as current Igl where, because address device A2 is actuated, it ~ -is diverted into left-most branch 7 of address loop 12 and appears in 16 that branch as IglT Since device J4 is unactuated, current flows 17 through that device until it encounters ac~uated device J6 which causes 18 it to be diverted into the interconnect:ion line 3 associated with that 19 device and current IglT appears in line 3 as current IL6. This current in turn actuates devices J12, ~13 of stage III via associated control 21 windings 10 which carry that current. Current IL6 now appears at the 22 output of address loop 12 as current I 2 where, as the input to address 23 loop 19, it is diverted into the right-most branch 7 of address loop 19 24 and appears therein as current Ig2C. The latter current flows through unactuated devices J9 and Jll until it encounters actuated device J13. ;~;
26 Then current Ig2C is diverted into interconnection line 3 associated 27 with that device where it appears as current IL13. Current IL13 is used 1 to actuate a device 20 disposed in electro~agnetically coupled relationship 2 with line 3 thereof which, in turn, is used to drive a word line of a 3 memory array, for example. From thence current IL13 passes through 4 unactuated device J15 to ground. From the foregoing example, it should be obvious that by actuating device Jl and various address gates, any 6 one out of 8 possible outputs can be provided. It should also be obvious 7 that the addition of other stages can provide for the selection of 1 out 8 of 16 outputs and so on.
9 Earlier in this discussion, reference has been made to the fact that decoder loop circult 6 associated with each of the address 11 loops 8, 12, 15, 19 can be latching or nonlatching by simply adjusting 12 the value of the resistance to impedance 2 of each of decoder circuits 13 6. If the value of resistance of impedance 2 is relatively large, the 14 Josephson devices shunted by such a value of resistance are latching in character and the circuit of FIGS. lA, lB would be unchanged from that 16 ~ust described. Ilowever, where the value of resistance of impedance 2 17 shunting each of the Josephson devices is relatively small, decoder 18 circuits 6 are nonlatching or self-resetting in character. Because of L9 the dynamics of the situation, and contrary to what might be expected, reset gates would be required in each of the branches 7 of address loops 21 8, 12, 15, and 19 to eliminate circulating currents. Thus, separately 22 actuated reset gates 21 would be disposed in each branch 7 of decoder 23 loops 8, 12, 15, and 19.
24 Refer~ing now to decoder loop 8 of FIG. lA and assuming that the resistance of impedance 2 of decoder loop 6 is~sufficient to render 26 such circuits latching in character and assuming address device Al to be 27 unactuated while address device Al is actuated, the dyna~ics of the 28 situation are as follows:
., .
~3~2~.~
1 Current I C is diverted into the left-most branch 7 of address 2 loop ~. Witll respect to address device Al, that device encounters a 3 current which is decaying while branch 7 encounters a current which is 4 rising and reaches a steady state in a time which is a function of the inductance oE address loop 80 When all the current has been removed 6 from right-most branch 7, device Al reset~s immediately because the 7 current has fallen below the I i ~ device Al. At this point, assuming that devices J2, J3 are actuated by control curren~ ILl, device J2 9 switches diverting current into path L2. Device Al which has already lQ reset to the zero voltage state as a result of having no current in it, 11 now presents a short circuit across left-most branch 7 of address loop 12 8. It should be noted that address device Al and device J3 are in the 13 zero voltage state thereby presen~ing a short circuit path across left-14 most decoder circuit 6 of address loop 8. Current IgT, upon switching Gf J2, now attempts to pass from left-most branch 7 into right-mos~
16 branch 7 which is a short circuit. It cannot do so immediately because 17 the branch current now sees the parallel combination of the resistance 18 of impedance 2 of path L2 and the device resistance~ Rj, of device J2 l9 and decays with the time constant L/R where R is the parallel combination of the resistance of path L2 and the device resistance, Rj, of device 21 J2.
22 The current in device J2 having been diverted to path L2 and 23 having provided an output IL2 now decays in the same manner as the loop 24 current and current builds up in device Al correspondingly. When the current in device J2 decays to a point where Imin of device J2 is r~ached, 26 that device resets to the zero voltage state. All the current is now in 27 right-most branch 7 and device Al is ready for another cycle.
YOg75-067 -17-l Where the resistance of path L2 is sufficiently small to 2 render decoder loop circuit 6 of left-most branch 7 of address loop 8 3 nonlatching or self-resetting, a slightly different situation is encountered 4 after device Al switches to the voltage state. I~hile the build-up of current in left-most branch 7 of address loop 8 is exactly the same as 6 that described in connection with operation in the latching mode described ~-7 hereinabove, the dynamics of decoder circuit 6 are different once device 8 J2 switches to the voltage state. At this point, the branch current IgT
9 drops a small amount as a result of the current being diverted into impedance 2 of path L2. When device J2 s~itches, because of the high 11 inductance of the address loop, the current in impedance 2 rises instantan-12 eously to a peak value while current in ehe address loops drops only 13 slightly as a function of the ratio of the inductances iD the decoder 14 loop to the inductance in the address loop. In the usual case, the ratio is 1:12. Further current drop in the address loop is precluded by 16 device J2 resetting instantaneously to the zero voltage state because of 17 the low resistance of impedance 2. The output pulse available in path ;
1~ L2 may be used to actuate a subsequent decodlng loop. Now, however, 19 because current remains in the address loop due t~ the zero voltage states in both devices J2 and Al, the initial conditions must be brought 21 about so a subsequent cycle can be carried out. This is accomplis~hed by 22 actuating reset gate 21 associated with right-most branch 27 of address 23 loop 8. Typical values for the resistance of impedance 2 in ioop decoder 24 circuit 6 is 1 ohms for the latching situation and 0.2 ohms for the self-resetting situation at current levels of 2ma.
26 Referring now to FIG. 2, there is shown therein a schematic 27 diagra~ of a loop decoder in which the address devices of the decoder Yo976-067 -18-.
1 are all connected in series. Each decoder stage a~ter the Input is 2 controlled by a palr of address devices and each of these is shunted by 3 an associated address loop~ The Input of the decoder is an actuable 4 device connected to a shunting impedance by a transmission line. The latter contains two output portions which are utilized to control the 6 actuable devices of decoder loop circuîts which are disposed in series 7 in each of the address loop3 of succeeding decoder stages. Each stage 8 contains 2N decoder clrcuits and half of these are associated with each 9 of the address loops of each stage. Thus, the second stage has four decoder circuits, 2 of which are disposed in each address loop of that 11 stage. Each of the actuable devices of the second stage is controlled 12 by 2N outputs available from the first stage. The last stage oE the 13 decoder of FIG. 2 provides one out of 2N available outputs which may be 14 utilized to energize a driver circuit which is associated with a Josephson memory array line.
16 Referring now to FIG. 2 in more detail, Input of decoder 17 circuit 30 is identical with decoder circuit 6 of FIG. 1 and the same 18 elements in FIG. 2 are designated with the same reference characters as 19 u~ed in FIG. lA and lB. Impedan~e 2 may have a value of resistance equal to the characteristic impedance of transmission line 3 and, in 21 addition, it may have values of resistance whi~h render loop decoder 22 circuit 6 of stage 1 either latching or self-resetting. As with Input 23 of FIG. lA, Josephson device Jl may be shunted by an actuable Josaphson 24 device instead of an impedance 2. FIG. 2 shows a Josephson device 4 connected across device Jl by dashed lines. If device Jl is actuated by 2~ a combination of the currents Ig and ID, then, as described in connection Y097~-067 -19-1 with FIG. lA, current I is diverted into path Ll and appears therein as 2 the current ILl. As wlll be seen in what follows, current ILl will be 3 utilized to ac~uate Josephson devices J2, J3 via control line portions 4 10 which are serially disposed portions oE transmission line 3 of decoder loop circuit 6 of Input.
6 Address devices Al, Al which are devices capable of carrying 7 Josephson currents are shown in FIG. 2 disposed in series with device Jl ;
and are shown shunted by address loops 31, 32, respectively. Address 9 loops 31, 32 include serially disposed actuable devices J2, J3, respectively which are capable of carrying Josephson current. Each of the devices 11 J2, J3 is shunted by an impedance 2 and transmission line 3 forming 12 paths L2, L3, respectively. Paths L2, L3 carry currents IL2, IL3, 13 respectively, when devices J2, J3 are enabled depending on which of the 14 address devices Al, Al is actuated. As indicated hereinabove, devices J2, J3 are actuated by an associated control line portion 10 which 16 carries current ILl through these serially disposed por~ions which form 17 a portion of transmission line 3 of decoder loop 6 o~ Input. To avoid 18 an unduly complicated drawing, dashed line 33 is shown extending from 19 the bottom of transmission line 3 to control lines 10 indicating that control lines 10 are serially disposed portions of line 3, all of which 21 carry the same current ILl. Address devices Al, Al are actuated by 22 applying address current to associated control lines 9 and, when one of 23 these devices is actuated, the other is unactuated. Thus~ if device Al 24 is actuated, current Ig appears in address loop 31 as current I T~
Similarly when address device Al is actuated, current I appears in loop 26 32 as current IgC. These same currents appear in paths L2, L3 as currents 27 IL2, IL3, respectively when J2, J3 are actuated.
Y0976~067 ~20-8~L~
1 Stage II of decoder circuit 30 is similar to stage I except 2 that the address loops 34, 35 thereo~ each contain an additional decoder 3 loop circuit 6 in the address loops. Thus, address devices A2, A2 are 4 shunted by address loops 349 35 respectlvely, and the former contains a S pair of serially disposed Josephson junctions J4, J5 while the latter 6 similarly contains a pair of serially disposed Josephson junctions J6, 7 J7. Each of these devlces is shunted by an impedance 2 which is connected 8 across each device by a transmission line 3. These elements make up 9 paths L4-L7 which are adapted to carry currents IL4-IL7, respectively O
Josephson devices J4, J5 are actua~ed by currents IL2, IL3 respectively.
11 In a similar way, Josephson devices J6, J7 are actuated by currents IL2 12 and IL3, respectively. These currents appear in associated control 13 lines 10 which for those that carry current IL2 are serial portions of ~ ~
14 transmission line 3 of path L2. For those that carry current IL3, ;
control lines 10 are serial portions of transmission line 3 of path L3.
16 Again, to avoid an unduly complicated drawing, dashed lines 36~ 37 are 17 shown extending from the bottom of paths L2, L3, respectively to control 18 lines 10 and indicate that control lines 10 a~e serially disposed portions -~
19 of line 3 of paths L2, L3, respectively.
As with the previously described address devices, devices A2, 21 A2, if actuated, divert current Ig into loops 34 or 35 and that current 22 appears therein as current IglT, IglC9 respectively. Thus, depending on 23 whether device Jl is actuated and which of the address devices is actuated, 24 none or one of ~he outputs IL4-IL7 is provlded as an output which may be utilized to actuate an associated Josephson device 38 disposed in electro-26 magnetically coupled relationship with paths L4-L7. Devi.ces 38 may for 27 example be utilized to energize a memory array line.
Yo976-067 -21-.. ....
1 FIG. 2 shows reset gates 39 serlally disposed in each of the 2 add~ess loops 31~35. Reset gates 39 are utilized in the same manner as 3 reset gates 21 of FIG. 1. They are utilized in the mode wherein the 4 value of resistance of impedance 2 associated with each of the devices Jl-J7 has a value of resistance sufficiently small to make the devices 6 self-resetting. Where this same impedance has a value of res-lstance 7 which is ~uch higher, devices Jl-J7 operate in a latching mode and no 8 reset gates 39 are required.
9 If device Jl is actuated and addre~s devices Al and A2 are actuated, current ILS is provided in the path LS actuating its associated 11 Josephson device 38. Thus, the actuatlon of Jl provides current ILl in 12 path Ll. This current appears in stage I as I 1 and passes through 13 address device Al which is unactuated. This same current, however, 14 encounters actuated address Al and it is diverted into loop 32 where it appears as IgC. Because device J3 is actuated as a result of current 16 ILl being present in its associated control line 10, current I C is 17 diverted into path L3 and appears therein as current IL3. Current IL3 18 leaves address loop 32 and appears as current I 1 as an input to stage 19 II. Because address device A2 i5 actuated, current Igl is diverted into loop 34 and appears therein as current IglT. This current, because it 21 encounters actuated Josephson device J5 as a result of current IL3 2~ appearing in its associated control line 10, is diverted into path L5 23 where it appears as output current IL5.
24 It should be appreciated, at this point~ that the arrange~ent of FIG. 2 can be extended to any number of stages to pro~ide for the 26 selection of 1 out of 8, 1 out of 16 or 1 out of 32 outputs, for example.
l Referring now to FLGS. 3A-3B, FIG 3A is a graphical representation 2 of the current wavefor~ in an address loop when the resistance shunting 3 a decoder circuit 6 is of such a value that the actuable device thereof 4 is nonlatch:lng or self-resetting and FIG. 3B is a graphical representation of the resulting current waveform as it appears i~ the output transmission 6 line of a decoder circuit 6.
7 Considering FIGS. 3A~3B, in conjunction with address device Al 8 and address loop 31 of FIG. 2, when device Al switches, current is 9 dlverted into address loop 31. Address loop 31 encounters a rising current which is a function of the inductance of loop 31 and reaches a 11 steady state condition as indicated at 40 in FIG. 3A. At this point, 12 device J2 switches diverting current IgT mo~entarily into path L2 as ~ -13 current IL2. However, because the resistance of the impedance in path 14 L2 is small, device J2 resets to the ~ero voltage state immediately~
lS causing current IgT to drop only a small amount as shown at 41 in FIG.
16 3A. When device J2 switched, because of the high inductance of address 17 loop 31, the current in impedance 2 of path 1,2 rises instantaneously to 18 a peak value as shown at 42 in FIG. 3B while current in address loop 31 19 drops only slightly as a function of the ratio of the inductance in decoder loop circuit 6 to the inductance in address loop 31. In a usual 21 case, the ratio may be 1-12. Further current drop in address loop 31 ls 22 precluded by device J2 resetting instantaneously to the zero voltage 23 state because of the low resistaDce of impedance 2. The output pulse 24 available in path LZ may be used to actuate a subsequent decoder loop c~rcuit 6. Now, however, because current remalns in address loop 31 due 1 to the zero voltage states of both devices J2 and Al, the initial conditions 2 must be brought about so a subsequent cycle can be carried out. This is 3 accomplished by actu~ting reset gate 39 associated with address loop 31.
4 Where the resistance of impedance 2 of decoder loop circuit 6 associated with device J2 is sufficient to render such circuits latching 6 in character, the situation is slightly different and reset gates 39 are 7 not required. When address device Al is actuated, the current I T
8 appears in address loop 31 and the current rises to a steady state value g shown at 40 in FIG. 4A in the same manner as described in connection with FIG. 3A. When all the current has been diverted into address loop ll 31, address device Al resets lmmediately because current has fallen 12 below the Imin of that deviceO At this point, device J2 is actuated by 13 current ILl and device J2 switches diverting current into path L2.
14 Device Al which has already reset to the zero voltage state as a result of having no current in lt, now presents a short circuit across address 16 loop 31. Current IgT now attempts to pass from address loop 31 into the .`
17 now short-circuited branch which contains address device Al. It cannot 18 do so instantaneously because the loop current now encounters the parallel19 combination of the resistance of impedance 2 of path L2 and the device resistance, Rj of device J2 and decays with the ~ime constant L/R where 21 R ls the parallel eombination of the resistance of impedance 2 and ~he 22 device resistance, Rj, of device J2.
23 The current in device J2 having been diverted and having 24 provided an out~ut 43 as shown in FIG. 4B now decays in the same manner as the current in addre.ss loop 31 and shown in FIG. 4A and 4B at 44.
26 When the current in device J2 decays to a point where I i of device J2 27 ls reached, that device resets to the æero voltage state. All the 1 current is now removed from address loop 31 and flows in device Al which 2 is in the æero voltage state. Address device Al is now ready for another 3 cycle.
4 The address devices and the actuable Josephson devices mentioned hereinabove in connection with FIGS. lA, lB and 2 may be any well-known 6 type of Josephscn junction or may be a multiple junction device known as 7 an interferometer. In addition, all the interconnection circuitry like ~ -8 transmission lines 3, control conductors 9, 10 and the conductors of the 9 various address loops are ~ade from materials which are superconductive ~ ~
at the tempe}ature of liquid helium (approximately 4.2K~. Typical ~;
ll Josephson junctions and interconnection circuitry which may be utillzed 12 in the practice of the present invention are shown in U.S. patent 3,758,795, 13 S.N. 267~841, filed June 30, 1972 and assigned to the same assignee as 14 the present invention. A typical fabricatio~ technique for form-ing Josephson junction devices is shown in U.S. patent 3,349,276, S.N.
16 125~993, filed March 19, 1971. Resistive terminations 2 which must not 17 be superconductive at the circuit operation temperature may be fabricated 18 with compatible materials which display resistance at the desired operating 19 temperature. U.S.patent 3,913,120, S.N. 429,461 filed December 28, 1973 and assigned to the saMe assignee as the present invention shows a 21 material and method of fabrication for circuitry and a terminating 22 resistor which may be utilized in the practice of the present invention.
23 While the invention has been particularly shown and described 24 wlth reference to preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in form 26 and details may be made ~herein without departing from the spirit and 27 scope of the invention.
TJK/ mm
Claims (40)
1. A multi-stage decoder circuit comprising:
an input circuit which includes an actuable device and a shunting impedance, said impedance and said device being connected by an interconnection line which has at least two output portions, address loop means associated with each stage of said multi stage decoder circuit, at least a pair of actuable address devices electrically connected with each said loop means, the actuation of one or the other of which accesses 2N/2 circuits like said input circuit which are connected to said loop means, the output portions of said circuits like said input circuit of the first stage to the Nth - 1 stage being arranged so that 2N+1 outputs are available per stage each said output portion controlling an actuable device of a circuit like said input circuit, the output portions of said Nth stage being electrically connected to 2N circuits different from said input circuit and wherein N=1,2,3,4.....
an input circuit which includes an actuable device and a shunting impedance, said impedance and said device being connected by an interconnection line which has at least two output portions, address loop means associated with each stage of said multi stage decoder circuit, at least a pair of actuable address devices electrically connected with each said loop means, the actuation of one or the other of which accesses 2N/2 circuits like said input circuit which are connected to said loop means, the output portions of said circuits like said input circuit of the first stage to the Nth - 1 stage being arranged so that 2N+1 outputs are available per stage each said output portion controlling an actuable device of a circuit like said input circuit, the output portions of said Nth stage being electrically connected to 2N circuits different from said input circuit and wherein N=1,2,3,4.....
2. A multi-stage decoder circuit according to claim 1 further including means connected to each said at least a pair of address devices for actuating one of said pair per stage to provide for the actuation of one of said circuits different from said input circuit at a time.
3. A multi-stage decoder circuit according to claim 1 wherein said actuable device is a device capable of carrying Josephson current.
4. A multi-stage decoder circuit according to claim 1 wherein said actuable address devices are devices capable of carrying Josephson current.
5. A multi-stage decoder circuit according to claim 1 wherein said impedance is a resistor.
6. A multi-stage decoder circuit according to claim 1 wherein said impedance is an actuable device capable of carrying Josephson current.
7. A multi-stage decoder circuit according to claim 1 wherein said interconnection line is a superconducting transmission line.
8. A multi-stage decoder circuit according to claim 1 wherein said address loop means is a closed conductive loop having first and second branches each of which is connected to said 2N/2 circuits.
9. A multi-stage decoder circuit according to claim 1 wherein said address loop means is a pair of closed conductive loops each of which is connected to said 2N/2 circuits.
10. A multi-stage decoder circuit according to claim 1 wherein said address devices are devices capable of carrying Josephson current.
11. A multi-stage decoder circuit according to claim 1 wherein each of said actuable address devices is disposed in parallel with said loop means.
12. A multi-stage decoder circuit according to claim 1 wherein each of said actuable address devices is disposed in said loop means.
13. A multi-stage decoder circuit according to claim 1 wherein said circuits different from said input circuit are memory array line driver circuits.
14. A multi-stage decoder circuit according to claim 2 wherein said means for actuating one of said pair of address devices per stage includes at least one control line coupled to each of said address devices.
15. A multi-stage decoder circuit according to claim 5 wherein said resistor has a value of resistance sufficient to make said actuable device latching.
16. A multi-stage decoder circuit according to claim 5 wherein said resistor has a value of resistance sufficient to make said actuable device self-resetting.
17. A multi-stage decoder circuit according to claim 8 wherein said closed conductive loop is a superconductor.
18. A multi-stage decoder circuit according to claim 11 wherein each of said actuable address devices is disposed in series with the others of said actuable address devices and with said actuable device and said loop means is a conductive loop in parallel with each of said actuable address devices.
19. A multi-stage decoder circuit according to claim 12 wherein said loop means is a conductive loop having first and second branches each of said branches having one of said actuable address devices disposed therein.
20. A multi-stage decoder circuit according to claim 16 further including resetting means connected to said address loop means for suppressing circulating currents in said loop means.
21. A multi-stage decoder circuit: comprising:
an input circuit having a pair of outputs, a plurality of loop circuits each containing first and second branches disposed in series with said input circuit each said branch having an actuable address device disposed therein, the actuation of one or the other of which accesses 2N/2 circuits like said input circuit which are electrically connected in each branch of each of said plurality of loop circuits, the outputs of said circuits like said input circuit of the first of said loop circuits to the Nth - 1 of said looping circuits being arranged so that 2N+1 outputs are available per loop circuit, each of said last mentioned outputs controlling an actuable device in a circuit like said input circuit, the outputs of said Nth loop being electrically connected to 2 circuits different from said input circuit and wherein N=1,2,3,4,.....
an input circuit having a pair of outputs, a plurality of loop circuits each containing first and second branches disposed in series with said input circuit each said branch having an actuable address device disposed therein, the actuation of one or the other of which accesses 2N/2 circuits like said input circuit which are electrically connected in each branch of each of said plurality of loop circuits, the outputs of said circuits like said input circuit of the first of said loop circuits to the Nth - 1 of said looping circuits being arranged so that 2N+1 outputs are available per loop circuit, each of said last mentioned outputs controlling an actuable device in a circuit like said input circuit, the outputs of said Nth loop being electrically connected to 2 circuits different from said input circuit and wherein N=1,2,3,4,.....
22. A multi-stage decoder circuit according to claim 21 wherein said input circuit further includes an actuable decoder device, and a parallel impedance, said decoder device and said impedance being connected by a transmission line portions of which form said pair of outputs.
23. A multi-stage decoder circuit according to claim 21 further including means connected to said actuable address devices for actuating one or the other thereof per loop circuit to provide for the actuation of one of said circuits different from said input circuit.
24. A multi-stage decoder circuit according to claim 22 wherein said actuable address device 5 and said actuable decoder device are devices capable of carrying Josephson current.
25. A multi-stage decoder circuit according to claim 22 wherein said impedance is a resistor.
26. A multi-stage decoder circuit according to claim 22 wherein said impedance is an actuable device capable of carrying Josephson current.
27. A multi-stage decoder loop according to claim 22 wherein said loop circuits and said transmission line portions are super-conductors.
28. A multi-stage decoder circuit according to claim 25 wherein said resistor has a value of resistance sufficient to make said actuable decoder device self-resetting.
29. A multi-stage decoder circuit according to claim 25 wherein said resistor has a value of resistance sufficient to make said actuable decoder device latching.
30. A multi-stage decoder circuit according to claim 28 further including resetting means connected to each of said plurality of loop circuits for suppressing circulating currents in said loop circuits.
31. A multi-stage decoder circuit comprising:
an input circuit having a pair of outputs, a plurality of actuable address devices disposed in series with said input circuit, a pair of said actuable address devices being allotted per stage of said multi-stage circuit, an address loop circuit disposed in parallel with each of said actuable address devices the actuation of one or the other of any of said pair of actuable devices accessing 2N/2 circuits like said input circuits which are electrically connected in each of said address loop circuits, the outputs of said circuits like said input circuit of said first stage to the Nth-1 stage of said multi-stage decoder circuit being arranged so that 2N+1 outputs are available per stage, each of said last-mentioned outputs controlling an actuable device in a circuit like said input circuit, the outputs of said Nth stage being electrically connected to 2N circuits different from said input circuit and wherein N=1,2,3,4,......
an input circuit having a pair of outputs, a plurality of actuable address devices disposed in series with said input circuit, a pair of said actuable address devices being allotted per stage of said multi-stage circuit, an address loop circuit disposed in parallel with each of said actuable address devices the actuation of one or the other of any of said pair of actuable devices accessing 2N/2 circuits like said input circuits which are electrically connected in each of said address loop circuits, the outputs of said circuits like said input circuit of said first stage to the Nth-1 stage of said multi-stage decoder circuit being arranged so that 2N+1 outputs are available per stage, each of said last-mentioned outputs controlling an actuable device in a circuit like said input circuit, the outputs of said Nth stage being electrically connected to 2N circuits different from said input circuit and wherein N=1,2,3,4,......
32. A multi-stage decoder circuit according to claim 31 wherein said input circuit further includes an actuable decoder device, and a parallel impedance, said decoder device and said impedance being connected by a transmission line portions of which form said pair of outputs.
33. A multi-stage decoder circuit according to claim 31 further including means connected to said actuable address devices for actuating one or the other thereof per stage to provide for the actuation of one of said circuits different from said input circuit.
34. A multi-stage decoder circuit according to claim 32 wherein said actuable address device 5 and said actuable decoder device are devices capable of carrying Josephson current.
35. A multi-stage decoder circuit according to claim 32 wherein said impedance is a resistor.
36. A multi-stage decoder circuit according to claim 32 wherein said impedance is an actuable device capable of carrying Josephson current.
37. A multi-stage decoder loop according to claim 32 wherein each said address loop circuit and said trans-mission line portions are superconductors.
38. A multi stage decoder circuit according to claim 35 wherein said resistor has a value of resistance suffi-cient to make said actuable decoder device self-resetting.
39. A multi-stage decoder circuit according to claim 35 wherein said resistor has a value of resistance suffi-cient to make said actuable decoder device latching.
40. A multi-stage decoder circuit according to claim 28 further including resetting means connected to each said loop circuit for suppressing circulating currents in said loop circuit.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US80795177A | 1977-06-20 | 1977-06-20 | |
| US807,951 | 1977-06-20 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1098216A true CA1098216A (en) | 1981-03-24 |
Family
ID=25197511
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA298,267A Expired CA1098216A (en) | 1977-06-20 | 1978-03-06 | Loop decoder for josephson memory arrays |
Country Status (6)
| Country | Link |
|---|---|
| JP (1) | JPS547830A (en) |
| CA (1) | CA1098216A (en) |
| DE (1) | DE2806837C2 (en) |
| FR (1) | FR2395565A1 (en) |
| GB (1) | GB1600334A (en) |
| IT (1) | IT1111165B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4151605A (en) * | 1977-11-22 | 1979-04-24 | International Business Machines Corporation | Superconducting memory array configurations which avoid spurious half-select condition in unselected cells of the array |
| DE4220421A1 (en) * | 1992-06-22 | 1993-12-23 | Forschungsgesellschaft Fuer In | Superconductive switch matrix for digital transmission network nodes - combines switches and memories having steep-sided characteristics with comparatively slow circuit elements and delay lines |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3188488A (en) * | 1957-08-05 | 1965-06-08 | Little Inc A | Multi-stable superconductive electrical circuit |
| US3626391A (en) * | 1968-07-15 | 1971-12-07 | Ibm | Josephson tunneling memory array including drive decoders therefor |
-
1978
- 1978-01-25 JP JP628178A patent/JPS547830A/en active Granted
- 1978-02-15 FR FR7804976A patent/FR2395565A1/en active Granted
- 1978-02-17 DE DE2806837A patent/DE2806837C2/en not_active Expired
- 1978-03-03 IT IT20835/78A patent/IT1111165B/en active
- 1978-03-06 CA CA298,267A patent/CA1098216A/en not_active Expired
- 1978-03-15 GB GB10243/78A patent/GB1600334A/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| DE2806837C2 (en) | 1984-05-24 |
| GB1600334A (en) | 1981-10-14 |
| IT7820835A0 (en) | 1978-03-03 |
| DE2806837A1 (en) | 1979-01-04 |
| JPS5652398B2 (en) | 1981-12-11 |
| IT1111165B (en) | 1986-01-13 |
| FR2395565A1 (en) | 1979-01-19 |
| JPS547830A (en) | 1979-01-20 |
| FR2395565B1 (en) | 1983-01-28 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MKEX | Expiry |