CA1089946A - Shared direct memory access controller - Google Patents

Abstract

SHARED DIRECT MEMORY ACCESS CONTROLLER
ABSTRACT OF THE DISCLOSURE
A microprocessor system includes a microprocessor, a memory, and one or more direct memory access controllers, all connected to a common system bus which includes a system address bus and a system data bus. At least one of the direct memory access controllers is shared by a plurality of sub-system device controllers which may control peripheral devices having diverse characteristics. The microprocessor is limited in its instruction repertoire and may control peripheral de-vices only by means of an input and an output instruction.
The shared direct memory access controller includes no cir-cuitry which is specifically for controlling only a single type of peripheral device, the device dependent logic being located in subsystem device controllers. Data transfers may take place directly between the memory and, through the shared direct memory access controller, any selected one of the peripheral devices. In order to set up the actual data transfer, the microprocessor executes an Input instruction which addresses the status register in a selected subsystem device controller and returns this status to the micropro-cessor. Next, two Output instructions are executed to load a memory starting address into an address pointer counter in the shared direct memory access controller. Finally, an Output instruction is executed to address a control register in the selected subsystem device controller to load it with a command. After this last operation the actual data transfer takes place on a byte basis through the shared direct memory access controller between the memory and the selected sub-system device controller. The shared direct memory access controller includes an interrupt priority encoder and circuits responsive to an interrupt that is granted priority for placing the status and address of the interrupting subsystem device controller on the system bus. Circuits are included in the shared direct memory access controller for "handshaking"
between it and the memory, and between it and the subsystem device controllers.

Description

9~L6 This application is a di~ision of applica~ion Serial No.
269,349 filed January 7, 1977.
BACKGROUND OF THE INVENTION
The present invention relates to a data processing system employing a shared direct memory access controller for connecting a plurality of subsystem device controllers to a memory under the control of a microcomputer which serves as the central processing unit of the system.
Microprocessors are a fairly recent development and are receiving wide attention in the data processing art. See for example Fortune Magazine, November, 1975. While micro-computers are of extremely small size, can be extremely fast in operation, and are relatively inexpensive eompared to prior art computers, they sometimes have undesirable limita-tions, E'or exa~ple, the Intel 8080* microcomputer has only two instructions for communicating with external devices.
One of these is for controlling input operations and the other is for controlling output operations. This characteris-tie places severe limitations on the use of this paxticular microeomputer in a system employing a ~umber of peripheral deviees o~ diverse characteristics, particularly where it is desired to provide direct memory access whereby the peripheral deviees may eommunieate with the memory at the same time the mierocomputer is engaged in other operations.
The ~oncop~ o~ direet memory access is well known in the art. Generally speaking, this eoncept allows a eentral proeessing unit to load a subsystem device controller ; with the instructions and data necessary to initiate and carry out a data transfer between the memory and the peripheral ~0 device conneeted to and controlled by the subsystem device controller. Once the subsystem controller has been set up, the central processing unit is then ree to ca~ry out other *Trade Mark -3- ;

94~ii operations in the system while the subsystem device con-troller itself controls the transfers between memory and the peripheral device.
In the prior art, it has been customary to provide each subsystem device controller with all of ~he circuits necessary for carrying out the data transfers between its peripheral device and the memory. Further~ore, each of the subsystem device controllers has been directly connected to a system bus to which the memory and central processing unit 10 are also connected. There are some functions which must be ~..~ "; .; . .
performed by each of tha su~system device controllers regard-less of the type of the peripheral device they serve hence the presently utilized arrangement requires an unnecessary duplication of circuitry in each of the subsyc~em device controller~ in order to carry out these functions.
SUMMARY OF TI~E INVENTION
An object of the present invention is to p~ovide a direct memory access controller which is shared by a plurality of subsystem device controllers for the purpose o~
20 trans~erring data between the memory and a peripheral device through the direat memory access controller and the sub-sy~tem device controller.
To this end, the invention provides a microprocessor system comprising: a microprocessor having ,means therein ~or ,.
producing a ~irst output signal representing an INPUT
instruction and a second output signal representing an ou'rPU'r instruction; a memory; an addressable direct memory access cantroller; a system bus connected to said microprocessor, ' said memory and said memory access controller; a plurality 30 of peripheral devices; a plurality of subsystem device con-trollers each associated with and controlling one of said , ~ S9~46 plurality of peripheral devices, said subsystem device con-trollers being connected to said direct memory access con-troller for the transfer of control signals and data bytes therebetween; said subsystem device controllers each including a status register and means ~or returning the value in its status register to said addressable direct memory access :
controller; sai~ direct memory access controller including first means responsive to an INPUT instruction and an address on said system bus ~or selecting one of the subsystem device controllers and its associated peripheral device, and second means responsive ~o said status register value for inhibiting operation of said -first means if the direct memory access controller or a subsystem device contro~er connected thereto is busy. ..
The .invention also consists of a shared direct memory "
access controller ~or use in a system having a system address bus and a system data bus connected to a processor means, a memory and a plurality of direct memory access con~rollers, each said direct memory access controller controlling a plurality of subsystem device controllers and comprising:
interrupt priority encoder means responsive to interrupt signals from subsystem device controllers connected to said shared direct memory access controiler, said interrupt priority encoder means including means for producing a multi-bi~ value representing the address o~ the subsystem device controller granted priority to the direct memory access controller, register means receiving data from said subsystem devlce controller for applying said data to said system data bus; means responsive to said interrup~ priority encoder means for addressing the subsystem device con~roller granted priority to load the status o said subsystem device `

. .. . .. ....... A~.. ~, .. " ..

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controller into said register means; means for ge~erating an interrup~ r~quest signal requesting access to said system addre.ss bus and system data bus in response to the loading of said register means; means responsive to said interrupt ..
request signal for generating the address of said shared direct memory access controller and transmitting it to said system address bus; and status receiving means for receiving said shared direct memory access controller address and said status of said subsystem device controlleT.
Other features of embodiments of the invention and its mode of operation will become apparent on consideration o the llowing description and the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram of a data processing system employing a shared direct memory access controller; .
FIG. 2 is a block diagram illustrating the various elements contained within a shared direct memory access controller.
FIGS. 3A and 3B when arranged as shown in FIG. 3C comprise a lo~ic diagram illustratlng the main paths of flow - 6 - :

.
of data through a shared direct memory access controller;
- - FIGS. 4-8 are logic diagrams of the circuits for generating control signals within tile shared direct memory access controller;
FIG. 9 is a waveform diagram illustrating the timing of various signals occurring within the shared direct memory access controller during an input instruction;
FIGS. 10A-lOE illustrate various addressing formats `
utilized with tne shared direct memory access controller;
FIG. 11 is a waveform diagram illustrating the timing of various signals occurring during execution of the output instructions which load the address pointer counter; and, FIGS. 12~ and 12B are waveform diagrams illustrating the timing of various signals during output and input data transfers, respectively.

DETAILED DESCRIPTION OF THE EMBODIMENTS
In the subsequent description, the followiny conventions are employed. Each element is given a 3-digit reference numeral. The irst a~ these digits represents the 20 number oP the figure where the element will be found. With respect to input and output leads~ the first digits specifies the figure where the source or the lead will be ~ound.
Because of the particular logic elements employed, a high or positive voltage level represents th~ logic one state while a low or ground level represents the logic zero.
FIG. 1 sho~s a block diagram o~ a data processing system incorporating the features o the present invention.
The data processing~system includes a central processing unit (CPU) 100, a main storage or memory 102, a` bus manager 30 means 104, one or more ~isc direct memory access controllers -~LC38~9~16 106 and one or more shared direct memory access controllers (SDMA) 108, all connected to a common system bus 110. CPU
100 is a microcomputer such as, for example, the Model 8080 presently marketed hy the Intel Corporation. CPU 100 con-tains the usual circui~s, including an accumulator recJister 101, necessary for arithmetic computations and logical decision makin~ for the data processing system.
Memory 102 is of conventional desi~n and may, for example, com~xise a model T~IS 4060 stora~e unit such as that presently marketed by Texas Instruments.
Since all si~nal transfers between the various elemen~s connected to system bus 110 are made by way of the system bus, the bus manager 104 is provided for controllin~
access of tlle various elements to the system ~us. The use o~ a common system bus and a bus manager is well known ln the art, hence the details of the bus manager are not disclosed herein~
The direct memory access controller 106 may he a conventional direct memory access controller ~or connecting onn oE a plurality of floppy disc units 112 to the memory 102 by way o~ the system bus 110.
The present invention is directed toward a con-;ventional data processin~ system as described c~hove in combination with the sharecl direct memor~ access controller (S~M~) 108. SDMA 108 is provided to control the direct trans-~er oE ~ata hetween a plurality of suhsystem devlces and the memory ln2~ ~8 illustrated in FIG~ 1, the subsystem devices may comprise one or more card readers 116, one or more printers 114, one or more caxd punches 118, and/or one or 30 more data terminals 120 having a keyboard input with a ~;

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cathode ray tube display. Each subsystem de~ice has associated with it a subsystem device controller (SDC) 122 and all of the SDC's 122 are connected to SDMA 108 by way of a subsystem device controller bus 124. It will be understood that the SDCIs 122 may vary in their construction dependiIlg upon the type of subsystem device they are controlling. Such sub-system device controllers are well known in the art, hence their details are not disclosed herein. It might be noted, however, that in the prior art each of the SDCIs 122 has 10 been provided with its own circuit for performing certain functions such as memory addressing. As will become evident from the following description, the present invention eliminates thls undue multiplication of circuitry by pro-viding a single circuit within SDMA 108 or performing this ~unction for all SDC's. Except for this, and the provision of the SDMA 108, all of the elements of FIG. 1 may be of conventional design and are commercially available, hence their detaiIs are not disclosed herein.
FIG. 2 is a block diagram of the circuitry included ; 20 withln one S~M~ 108 ~all SDMA's are alike) and illustrates the paths of ~low of signals between the SDC bus 124 and the system bus 110. Actually, system bus 110 comprises a systam data bus 200, a system address bu~ 202 and a system control ~u~ 204. In like manner, the SDC bus 124 comprises an SDC
data bus 206, an SDC address bus 208 and an SDC control bus 210. System data bus 200 and SDC data bus 206 are bidirec-tional buses each capable of transferring one byte of information comprising eight parallel bits. Syste~ address bus 202 is a bidirectional bus capable of transferring 30addresses comprising sixteen hits. The SDC address bus 208 , . . . ...... .

. . .

9~

is a single direction bus for applying five-bit addresses to the SDC's 122 for ~he purpose of addressing a specific SDC or selecting a specific register in an SDC that has previously been ad~ressed. As will become evident from the subsequent description, up to 25 registers may be distributed between the SDCIs 122 serYiced by one SDMA.
The SD~ is provided with a sequential state logic circuit 212 and a data control logic circuit 214 both of which receive control signals from, or transmit control 10 signals to, the bus manager 104, memory 102, or the CPU 100 over the system control bus 204. The sequential state logic circuit 212 applies control signals to, or receives control Yignals ~rom, the SDC's 122 by way of the SDC control bus 210 and a set of control bus drivers and receivers 216.
Data control logic circuit 214 receives control signals from, and transmits control signals to, the SDCIs 122 by way of the SDC control bus 210 and a set of data control bus drivers and receivers 218. The logic circuits 212 and 214 are subsequently described in greater detail but it may be ; 20 noted at this time that they constitute the general controls over the flow of data through the SDMA and control the hand--shaking operations betwe~n the SDMA and SDCIs aæ well as between the SD~ and memorv.
'~he SDMA is provided with a data register 220 and all data passing throu~h the SDMA must pass through this data re~ister. ~he data register is capable of storing one 8-bit byte and has a multiplexer input for receiving data one byte at a time from the s~stem data bus 200 over a bus 222, or from the SDC data bus 206 over a bus 224. output 30 data from data register 220 is applied to one set of inputs : ~.

9~;

of a multiplexer (MUX) 226. rrhe output of MUX 226 is con-nected to the system data bus 200 through a set of data bus drivers 228, and is connected to the SDC data bus 206 through a set of SDC data bus drivers 230. Data derived from the accumulator register in CPU 100, or from the main storage 102 may pass over the system data bus 200, through data register 220, MUX 226, the SDC data bus drivers 230, and the SDC data bus 206 to the SDC~s 122~ On the other hand, data derived from the SDCIs 122 and appearing on the 10 SDC data bus 206 may be passed through data register 220, MUX 226, data bus drivers 228, and the system bus data bus ~00, to the CPU 100 and the memory 102.
~ he output of MUX 226 is connected to a 16-stage binary address pointer counter 232. The purpose of the address pointer 232 is to specify a particular address in memory 102. During an input operation, this addrass repre.-sents the address which is to store the next data byte passing through the SDMA from the SDC data bus. On an output operation the address pointer 232 contains the address 20 ~ the next memory location that is to be read out onto the aystem data hus 200 from whence it passes through the SDMA to the SDC data bus 2Q6. Since the address pointer ~32 has lG
stages, and since only 8 bits may be transferred over the systam data bus at one time in oxder to load the address pointer 232, the output o~ MUX 226 is connected to both the lowex eight stages and the upper eight stayes of the address pointer 232. Data control logic 214 produces a signal on a lead 234 to increment the address pointer counter by one for each b~te of data transferred through the SDMA. The eight 30 uppe~ order stages of the address pointer counter are con-'' g~6 nected throu~h a set of address bus drivers 236 to the eight high order leads in the system address bus 202~ The eight low order stages of the address pointer counter are connected through a set of address bus drivers/multiplexers 238 ~o the eight low order leads in the system address bus 202.
All of the disc direct memory access controllers 106 and shared direct memory access controllers 108 are capable of recognizing a specific combination of bits in an 8-bit address appearing on the 16-bit system address bus 202, 10 FIG. lOA shows the format of an address byte appearing on the system address bus 202. The three high order bits A7~AS
designate one of the direct memory access controllers 106 or 108. Since the address byte is provided with three bits for .`
this purpose, the described system may have up to eight direct memory access controllers 106 and 108 connectec1 to the system bus 110.
The five low order bits of the address byte are :`
interpreted in diferent ways depending upon the specific values of the bits. I~ bit A4 is a one and the four low 20 order bits o~ the address byte are zeros, the byte specifies the adclress of the upper portion of the address pointer counter 232 within the direct memory access controller speciied by bits A7 AS of the byte. As an illustration, ~IG~ lOB shows the address byte con~iguration ~or addressinc3 the upper portion o~ the address pointer counter withi~ the ~`~
direct memory access unit assigned the address 5. If bokh bits A0 and ~4 o the address byte are ones ancl bits A1-A3 are zeros then the address byte specifies that ~he word on the system data bus 200 is to be directed into the lower 30 half o~ the address pointer counter 232. FIG. lOC shows the 399~6 format of the address byte for addressing the lower half of the address pointer counter for direct memory access unit 5.
If bits A4 and A3 are both zero, then on an input instruction bits A7-A5 specify the direct memory access controller to be utilized while bits Al and A0 specify which of four SDCIs is being addressed. This format is illustrated in ~IG. lOD for the case where direct memory access unit five is specified by bits A7 A5.
Referring again to FIG. 2, each SDMA includes an 10 address recognition circuit 240 and all 8-bit address by~es appearing on the eight lower order leads of the system address bus 202 are applied to this address recognition circuit. Each address recognition circuit includes a circuit that is prewired to recognize the address of the direct memory access unit. For the purposes of the present descrip-tion, it is assumed that the SDMA shown is assigned address 5, i.e. 101, hence address recognition circuit 240 shown in FIG. 2 is wired to recognize and respond to each of the address bytes shown in FIGS. lOB~lOE. Each ~ime the address 20 reco~nition aircuit 240 recognizes its own address it provides output signals to control the sequential state lo~ic circuit 212 and the data control logic circuit 214.
A5 previously noted, up to 25 registers may be distributed between the SDC~s 122 and each register may be addressed by an address byte appearing on the system address bus 202~ The five low order leads of the system address bus 202 are connected to a multiplexer 242 and the output of the MUX is connected through a set of Register Select Line drivers 244 to the SDC address bus 208 so that the address 30 bits A4~A0 may be applied to the various SDC's 122.

99~6 The particular SDC 122 that is selected, and the particular register within the selected SDC that is addressed, is determined by ~he configuration of the address bits A4-AO. FIG. 10D ShOWS the address byte format for selecting oraddressing the. status register in one of the SDC's 122 con-trolled by an SD~ having the address 101. Bits A0 and Al :~
specify which of the SDCIs 122 contains the status reyister to be addressed, assuming that the SDMA controls only four SDC's, and the presence of zeros in bit positions A2-A4 10 speciies the fact that the status re~ister is to be selected.
FIG, lOE shows the configuration of an address byte for selecting a particular command register in an SDC~ .
'l'he one ~it in position A3 with A0, Al, A2 and A4 being all zeros, specifies that a command register is to be selected .
and acted upon in the SDC which has previously been selected by an address having the format shown in FIG. lOD.
Each SD~ is provided with an interrupt discrimi- :
nator means 246 for cletecting and alloting priority to interrupt requests received from the SDCIs 122 serviced by 20 khe SD~. Each SDC has an individual lead which extends from it over the SDC control bus 210 to An input o~ khe interrupt discrirninator. A signal is applied to this lead when th~ 5DC re~uests an interrupt. The i.nterxupt cliscrimi-natox 2~l6 determines which oE the four SDCIs has requested an intexrupt and gerlerates a two-bit address which identifies the SDC. This adc~ress is applied to an address latch 24a where it is stored, and is also sent back to the SDC to request the SDC to supply an indication of its status.
This status is loaded into the data register 220. The 30 output of address latch 248 is applied to one set of inputs of address bus drivers/MUX 23~ along with the address of the SDMA. As subsequently explained in greater detail, the interrupt discriminator also applies a signal to the sequential state logic and this causes the SDMA to send an interrupt request over the sys~em control bus 204 to the bus manager 104 once the SDC status is loaded into data register 220.
When the interrupt request of the SDMA is granted the SDMA
address and the output of address latch 248 are passed through the address bus driver/multiplexers 238 to the system address bus 202. At the same time, the SDC status is gated from the data register 220 onto the system addxess bus. The address and status are stored in two registers and the bus manager 104 generates a restart vector as disclosed in the Canadian application of Derchak and Monaco, Serial No.
269,013, filed December 31, 1976 (U.S. Patent 4,034,349 issued July 5, 1977).
DETAILED LOGIC DESCRIPTION
FIGS. 3A and 3B, when axranged as shown in FIG.
3C, show the logic circuits involved in the main data flow paths through the SDMA 108. The system data bus 200 and the SDC data bus 206 extend across the top of the figures while the system address bus 202 extends across the boktom o~ the figures. The data bits D0-D7 appearing on the system data bus 200 are applied to the B inputs of the data register whioh comprise two sets o latches 300 and 301 having multiplexed inputs~ The data bits ~ 7 appearing on the : SDC data bus 206 are applied to the A inputs of the MUX~s 300 and 301. The signal DRIVE SDC ~US is applied to the select input of both of the MUX~s. When the signal DRIVE
SDC BUS is at the low logic level the A inputs of the MUX's , -15- :

:

~0~9~

are selected so that data on the system data bus 206 may be gated into the register latches and appear at the outputs 0-3 of the MUX~s. If the signal DRIVE SDC sus is at the high logic level then the B inputs of the multiplexers are selected so that the data on the system data bus 200 may be stored in the latches and appear at the outputs of the MUXIs. Input data to the MUXIs may be gated into the latches only upon occurrence of a low level signal applied to a clock input, The signal LD DATA REG is applied to the clock inputs of both the MUXIs. The outputs of MUXIs 300 and 301 are applied to the A inputs o~ two QUAD MUXIs 3~2 and 303. l~he B3 input of QUAD MUX 303 receives the signal BUSY.
The remainin~ B inputs of QUAD MUX 303, as well as all of the ~ inputs of QUAD MUX 302 are connected through a resistor 304 to ~V. The purpose of the B inputs to ~UAD MUXIs 302 and 303 is to generate the hexadecimal status value 80 if the SDMA is busy at the time it is addressed by the CPU.
The signals DISABLE BREQ and READ are applied to the two inputs of an AND 306. The output of AND 306 passes 20 through an inverter 30~ to become the signal ENABLE STEP.
The output o~ AND 306 is applied the one input of a NAND 310 which receives as its other inputs the signals STEP ON and SDMA PROBE. The output of NAND 310 is connected to the at inputs o~ QUAD MUX's 302 and 303. If the output of NAND 310 is at the low level then the signals appearing at the ou-tput o~ MUX~s 300 and 301 are gated through to the ~utpu~s of QU~D MUX's 302 and 303. On the other hand, if tho output of NAND 310 is at the high level then the status value 80 i9 gated to the outputs of QUAD MUX~s 302 and 303 i~ ~he signal BUSY is low~

The outputs of QUAD MUX's 302 and 303 are connected to the inputs of eight NAND gates 311. NAND~s 311 correspond to the SDC data bus drivers 230 and have their outputs connected to the SDC data bus 206. The output of each NAND
is connected through a resistor 312 to ~V. NAND~s 311 are further enabled by the signal DRIVE SDC BUS and when this signal is at the high level the output of QUAD MUXIs 302 and 303 is gated through NANDIs 311 to the SDC data bus.
The outputs from QUAD MUX~s 302 and 303 are also applied to eight 3-state drivers 314, Drivers 314 correspond to the data bus drivers 228 and have their outputs connected to the system data bus 200. Drivers 314 are enabled by the signal ENABLE DATA DRV. When this signal is at the low level the output from QUAD MUXIs 302 and 303 is gated through drivers 314 to the system data bus 200.
An AND 316 received the signals SDMA PROBE, I/O
WRITE, and SST 2. When all of these signals are at the high level AND 316 produces a low level output signal to enable a decoder 318. The decoder has a fixst input D0 which receives the signal RADR-0 and a second input Dl which receives the signal DC BUSY ~. The signal appearing at input D0 is treated as having the binary value 1 while the signal appeaxing at input Dl is treated as having the binary value

2. I~ decoder 318 is receivlng a low level enabling signal ~rom N~ND 316 and i~ the signal DC BUSY A is at the high level, then a low level signal will appear at the 3 or 2 output o~ the decoder depending upon whether the input signal RADR-0 is at the high or the low level. The decoder is enabled only during the interval the SDMA is decoding an address having one of the formats shown in FIGSo 10B and , 10C. The signal RADR-0 is derived from the low order address bit and, as previously explained, determines whether the lower half or the upper half of the address pointer counter 232 is to be loaded. The address pointer counter is shown in FIG. 3A as comprising four 4-stage binary counters 320-323.
Each of the counters 320-323 has four data inputs D0-D3 by means of which an initial value may be loaded into the counters. The outputs from QUAD MUX 302 are connected to the data inputs of counters 320 and 322 while the outputs of QUAD MUX 303 are connected to the data inputs of counters 321 and 323. The counters 320-323 may accept data applied to their data inputs only when the counters are receiving a low level signal at an input designated load. The load inputs of counters of 320 and 321 are connected by lead 324 ; to output 3 of decodex 318. The load inputs of counters 322 and 323 are connected to output terminal 2 of decoder 318.
Therefore, if decoder 318 is enabled, the signal DC BUSY A
is at the high level, and the signal RADR-0 is at the high ~o level, the low level output signal on lead 324 enables counters 320 and 321 so that they are loaded with the value appearing at the output of QUAD MUX's 302 and 303. On the other hand, if the signal R~DR-0 is at the low level, then a low level signal on lead 326 enables counters 322 and 323 so that they are loaded with data from the outputs of QUAD
MUXIs 302 and 303.
once the counters 320-323 have been loaded, the value contained therein may be incxemented by applying a high level signal to the input terminals designated UP. The UP terminal of counter 320 receives the signal END MEM OP
'.'' ~18- ~

. . . . .. .. . .

1~ L6 FF. Counter 320 has a carry output terminal that is con-nected by lead 328 to the UP terminal of counter 321. In like manner, the carry outputs from counters 321 and 322 are connected to the UP inputs of the next hiyher order counters~
The counters 320-323 are up-down counters~ However, the down input terminals are connected through a resistor 330 to ~V so that the counters never count in the downward direction. The signal SD~ RESET is applied to a clear input terminal of each o~ the counters 320-323 and when this signal is at the high level it clears the counters.
The outputs from the four stages of counter 320 are applied to the B inputs of a 3-state MUX 332. The B
inputs of a 3-~tate MUX 334 are connected to receive signals ~rom the lowest order and the highest order of counter 321 and from the two lowest orders of counter 322. The two middle orders of counter 321 are connected by leads 336 and 338 to two 3-state drivers on a 3-state driver chip 340.
The two highest orders of counter 322 are connected to two drivers on a 3-state driver chip 342 while the four outputs from counter 323 are connected to four drivers on a 3-state driver chip 344. The signal INT SEQ EN FF is applied to the selec~t inputs o~ 3-state MUX~s 332 and 334. 'l`he signal BUS
GR~NT is applied to the strobe inputs o 3-state MUX's 332 i``
and 334 as well as the enabling inputs o~ 3-state drivers 342 and 344 and a decoder 346. Decoder 346 ~unctions in the ~ame manner a~ decoder 318. ~he D0 input o~ decoder 346 is tled to the logic 2ero level and the Dl input receives the ~i~nal INT REQ. The ~ero output of decoder 346 is the signal ENABLE DATA ADR and it is connected by leacl 348 to the enabling input of 3-state drivers 340, Decoder output --19-- ::

terminal 2 is connected to the enabling input of 3-state driver chip 350.
The contents of counters 320-323 may be gated onto the system address bus 202 for the purpose of addressin~
main storage. If the signal INT SEQ EN FF is at the high level when the signal BUS GRANT drops to the low level, the signals applied to the B inputs of MUX~s 332 and 334 are gated onto the system address bus 202 to become the address bits A0-A4 and A7-A9. At the same time, the signal BUS
GRANT enables 3-state drivers 342 and 344 so that the contents of counters 322 and 323 are gated onto the system address bus as the ~its A10-AI5. The signal BUS GRANT enables decoder 346 and since the signal INT REQ will be at a low level, a low level signal will appear on lead 3~8 to enable

3-state drivers 340. This gates the signals on leads 336 and 338 onto the system address bus as the address bit A5 and A6.
When an SDC 122 makes an interrupt request, lt is necessary to place on the s~stem address bus 202 an identi-fication of the particular SDC which is making the requestas well as an identification of the SDMA which services that SDC. The address is essentially an 8-bit address placed on th~ lower order leads A7-A0 o~ the system address bus 202 and havin~ the format shown in FIG. lOD.
Bits A5-A7 of the address identify the specific SDM~ and are determined by the physical location of the SDM~ card. Since it is assumed that the SDMA illustrated in FIGS. 3A and 3B has the identifylng number 5, bits A7-A5 should have the Yalue 101. In FIG. 3A, the A1 input of 3-state MUX 334 is tied through a resistor to -~V. In FIG. 3C, -20~

.

94L~

the 3-state drivers for driving address lines AS and A6 are tied to +V and ground respectively.
When an SDC 122 signals the SDMA that it is making and interrupt request, the SDMA circuits decode the request as subsequently described in order to generate two binary bits identifying the number of the SDC. These identifying bits, IDN-O and IDN-l, are sent back to the SDC to request that status be loaded into the data register of the SDMA.
IDN-O and IDN-l are applied to the A0 and Al inputs respec-tively of 3-state MUX 332. The A2 and A3 inputs of 3-state MUX 332 and the A0, A2 and A3 inputs of 3-state MUX 334 are all tied to ground. When an interrupt is recognized by the "
SDMA the signal INT SEQ EN FF drops to the low level to select the A inputs of 3-state MUXIs 332 and 334. Also, in FIG. 3B the signal INT REQ rises to the high level when tha interrupt is recognized and thus conditions the decoder 3~6 to produce a low level output signal on lead 351 if the ;
decoder should be enabled. When the signal BUS GRANT drops to the low level the A inputs of 3-state MUXIs 332 and 33 are ~ated through to tha system addxess bus 202. ~he BUS GRANT signal also enables decoder 346 and a low level output signal on lead 251 enables 3-state drivers 350 so as to place the binary value 01 on address bus leads A6S and ASS. The si~nals placed on the lower eight orders oE the 9y9t~m address bus thus represent the value lOlOOOXX where the X~9 are determined by IDN-0 and IDN-l. At the same time, and as subsequently described in detail, the SDC
~tatus is gated on the system data bus through drivexs 314.
FIG. 3B shows the circuits for generating certain memory control signals when an address in the counters 320--~8~ 6 323 is placed on the system address bus 202. At the time _ the signal B~S GRANT drops to the low level to strobe the address onto the address bus, it enables decoder 346 and the signal ENABLE DATA ADR drops to the low lev~l. Two drivers on the 3-state driver chip 340 receive the signals BUS REQ
WRITE and MEM oP respectively, and at the same time the address is strobed onto the address bus these drivers are strobed to produce the memory control signals MEM START
and wRI~rE~ These latter signals are applied to the memory controls over the system control bus 204 to cause the memory to perform a read or a write operation.
FIG. 4 shows the address recognition circuits and the path ~ollowed by an address in passing through the SDMA
~rom the system address bus 202 to the SDC address bus 208.
Address bits Al-A4 are passed through a set o~ inverters 400-404 having their outputs connected to the A inputs of a multiplexer 406. The strobe input of MUX 406 is tied to ground and the select input receives the signal INT SEQ EN
FF. If the signal INT SEQ EN FF is at the low level the address bits Al-A4 are gated through inverters ~00~404 and tlle MUX 406 to the SDC address bus 208. An AND 405 receives -the output o~ inverter 400 and the signal INT SEQ EN FF
hence when Al-~4 are gated through MUX 406, A0 is gated through AND 405 and NOR 407 to the SDC addre~s bus.
~ NAND 408 is provided ~or recognizing the address o~ the SDMA when that address appears on the system address bus 202. Since it is assumed that the present SDM~ is assigned address 5, address bits A7 and A5S are applied directly to NAND 408 while address bit A6S is passed through an inverter 410 before being applied to NAND 408. When the ~ . - , ., system address bus bits A7-A5S have the value 101, NAND 408 produces a high level output signal that enables one input of NAND's 412, 414 and 416. In actual practice, the address recognition circuits of all s~MA~s may be identical and the SDMA card position and back plane wiring utilized to determine exactly which address will be recognized by the SDMA.
The CPU places a signal CPU SYNC on the system control bus at about the time that an address is placed on the system address bus. The signal CPU SYNC is passed through an inverter 418 and applied to a second input of`` `
NAND 412. The signal I/O RD or WR is at a high level an~
time an input or an output instruction is on the system control bus. The signal I/O RD or W~ is applied to a further input of NAND 412 and is also applied to one input oE NAND
414, a NAND 420 and the reset input of a D-type flip-~lop 422. NAND 412 also receives the clock pulse ~lA. Therefore, if an input or an output instruction i5 present on the system control bus and the address on the system address bus :
2Q is that of the SDMA, NAND 412 produces a low level output signal that is applied to the set input of a GO FF 424.
This sets the flip-flop so that the signal GO FF on output lead 426 rises to the high level~ The signal on lead ~26 is passed through an inverter 428 to become the si~nal NOT
~E~DY. The signal NOT READY is sent back to the CPU over the system control bus 204 to stop execution of the instruction ..
and initiate a waiting state while the SDMA performs its task.
The low level output of NAND 412 is passed through an inverter 436 and applied to the clock input of flip flop 422. A NOR 438 receives the signals NAVAIL and INT SEQ-EN FF and has its output connected to the D input of flip-flop 422. If the SDMA is available ~o carry out the instruction the output of NOR 438 will be at the low level and the signal from inverter 436 will insure that the flip-flop 422 is reset. This drives the signal BUSY to the high level and prevents a busy status indication from being generated for the SDMA. Should the SDMA be busy then the D input of flip-flop 422 will be at a high level and the high level output 10 from inverter 436 will set the flip-flop thus driving the signal BUSY to the low level to generate the busy status.
At the same time, the set output of flip-flop 422 is applied over lead 440 to a NAND 442.
The high level output of inverter 436 is passed through a NOR 444 to the reset input of a flip-flop 446.
The reset output of this flip-flop is connected to one input of a NOR 448 so the ~lip-flop can produce an output signal through the NOR only when the flip-flop is reset. The output o~ NOR 448 is the signal STEP ON. This signal is 20 passed through an inverter 450 to become the signal STEP ON.
A NAND 452 is provided for recoynizing that an address on the system address bus 202 specifies that the address pointer counter 232 is to be loaded. NAND 452 is c~nnected to the outpu~s of inverters 401 ~03 and by lnverter 411 to the output o~ inverter 404. NAND 452 produ~es a high laval output signal when bits Al-A3 o~ the address are all ~ero~ and ~4 is a one. Thus, it recognizes eithex o~ the addreq3 ~ormats shown in FIGS. 10B and 10C. The output o~
NAND 452 is applied ~o NAND 414 which further receives the 30 s~gnals SDMA ADR and I/~ RD or WR. NAN~ 414 thus produces a ~8~9~6 low level output signal on an input or an output instruction if the address on the system address bus 202 specifies this particular SDMA and further specifies the address of the address pointer counter. The low level output signal from NAND 414 is passed through an inverter 454 to become the signal Sr~MA PROBE. The probe signal is applied to FIG. 3A
where it enables the decoder 318 controlling the loading of the address pointer counter, and further controls MUX's 302 and 303 so as to gate the data on the system data bus 200 10 through the MUX's to the address pointer counter.
The low level output of NAND 414 is applied to NOR
448 to generate the signal STEP ON. In addition, the output oE NAND 414 is connected to an input of NAND 420. NAND 420 ls urther energized by the output of NAND 416 during a read operation when address bits A3 and A4 are both zeros. NAND
416 is connected to an inverter 417 to generate the signal SELECTION when the CPU executes an input instruction to select an SDC and read into the accumulator the status of `
the selected SDC. The outputs of inverters 403 and 404 are 20 connected to the inputs oE a NAND 458 and the output of NAND
458 is applied to NAND 416. NAND 416 further receives the signal I/O READ, and is enabled by the output of NAND 408 when the SDMA address is recognized.
In addition to being conditioned by the outputs o NAND's 414 and 416, NAND 420 receives the signals D SACK
and I/O RD or WR. The output o NAND 420 is applied to still another input of NOR 448 for the purpose of generating the signal STEP ON.
The signal ENABLE SAI.T X is applied directly to 30 the K input o flip-flop 446 and is passed through an "" ''"' ' .. .
' ,";,, '"'.

9~

inverter 460 to the J input of the flip-flop. When the signal ENABLE SALT x is at a low level flip-flop ~a6 is set as the clocking signal ~lA goes to the high level. When the signal ENABLE SALT X is at the high level, the clocking signal has no effect on the flip-flop.
When an S~C 122 requests an interrupt it is applied to the SDMA and, if the SDMA is not otherwise occupied the interrupt request is granted. The SDMA generates the address of the recognized SDC 122 and applies it back over the SDC address bus to select the SDC. In FIG. 4, the signals IDN-0 and IDN-l represent the two bits of the generated SDC address. The si~nal IDN-0 is applied to one input o~ an AN~ 462 while the si~nal IDN-l is applied to the B0 input o~ QUAD MUX ~06. The signal INT SEQ EN FF is at a high level when the SDMA has recognized an interrupt request.
The signal INT SEQ EN FF is applied to the Bl input and the select control input of QUAD ~X 406 as well as to the second input o AND ~62. The output of NAND 462 passed through NO~ 464 to become the low order address bit. The B3 and B2 inputs as well as the strobe input o QUAD MUX 406 are all tied to ground level. Therefore, as soon as the si~nal INT SEQ EN FF rises to the high level, it selects the~
B inputs o~ QUAD MUX 406 for application to the SDC adclress bus ~08. Thus, there i8 placed on the addr~ss bus an address havin~ the ~ormat OOlXX where the X's may be zexos or ones and represent the address of the interrupting SDC. The 1 bit in RSL 3 signals the SDC to report its interrupt status as opposed to its selection status. The interrupting SDC
recognizes and responds to this address by placing its interrupt status on the SDC data bus.

. .: .

39~6 FIG. 5 shows the details of the major portion of the sequ~ntial state logic circuits 212~ The signal DATA
sUS IN is ~erived from t~le system control bus 204 and is passed throu~h an inverter 500 to become the signal READ
PULSE. DATA BUS IN is generated by the CPU 100 and drops to the low level at ~3A when an input instruction i9 being generated to tell the devices connected to the system bus that the CPU is ready to accept data into its accumulator re~ister any data placed on the system data bus. The si~nal : .
10 READ PULSE i~ passed throu~h a NOR 504 and applied to the D7 .
and D3 inputs of a multiple~er 506. The s.ignal W~ITE PULSE
i~ also derived from the syste~ control bus and it is passed :throu~h an inverter 508 and the NOR 504 to the D7 and D3 inputs o~ MUX 506. WRITE PULSE is generated by the CPU
durin~J output instructions to tell devices connected to the system b~s that data is present thereon and ready for samplin~.
MUX 506 receives the si~nal .ENABLE ST~P at its D~ input, the si~nal D FACK at i~s D2 input, D SACK at its Dl input, ~n~
GO FF at hoth its D0 and DA inputs. The signal ST~ ON is applied to the DS input as well as the A2 selection input of MUX 50G. The A0 and ~:l inputs o:E MUX 506 are connected to the output~ o~ the first and second sta~es of a modulo-

4 binary counter 510. The strobe input of MUX 506 is connected to ground and the output of the MUX is connec-ted by laad 51~ ~.o the CEP and CET terminals of the counter S10. ;~
;MUX 506 responds to the combinations of signals at it~ selection inputs A0 A2 to connect one of its data inputs D0-D7 to the output lead 512. For example, if the signals applied to A0-A2 are all at the low level then the D0 input .
of the MUX is connected to its Outpllt lead. If A2 and Al :`;
-27 ~ .

.:
' .

-are both at the low level and AO is at the hi~h level then the D4 input of the MUX is connected to its output lead.
The binary co~ter 51~ has four data inputs which are not utilized so its load terminal is connected through a resistor to +V. The counter is advanced by a positive-going clock signal ~2~ if the signal on lead 512 is at the high level at the time the clock pulse occurs. The counter has four binary stages only two of which are utilized in the present application. The counter may be reset by applying a low level signal SDMA RESET to its clear input terminal.
The zero and one stages of binary counter 5]0 are connected to the D0 and Dl inputs respectively of a decoder 51~. Th~ decoder 514 is permanently enabled by connecting its enablinq input to ground, hence the decoder continuously produces at one of its outputs a signal indicatin~ the value stored in the binary counter 510, if that value is betw~en one and three. The counter 510 normally contains a count of zero hence the decoder 514 normally produces a low level signal at its zero output which is not used. The three, two and one output terminals of the decoder are connected through inverters 516, 518 and 520 respectively to produce the signals SST3, SST2 and SSTl.
The lower portion o~ FIG. 5 shows the primary c~rcuits for initiating and controlling an interrupt sequenae.
These circuits include two ~X's 522 and 52~, a priority ~ncoder 526, two JK flip-Elops 528 and 530, thxee D-type ~lip-flops 532, 534 and 53~, and a decoder 538. The decoder 538 produces the signals IST 0, IST 1 and IST 2 which indicate the state of the SDMA during ~n interrupt sequence~

The signal IST 2 is passed through an inverter 5~0 to ' provide the signal IST 2.
The flip-flop 532 is the interrupt sequence enable flip-flop. It is set to respona to ~l interrupt request from an SDC provided the SDMA is not otherwise enga~ed.
These conditions are determined by a NAND 542. The signals D S~CK ancl DR LD FF are applied to a NOR 544 and the output of the NOR is applied to one input of NAND 542. The output of NOR 5~4 is the signal NAVAIL. The signal GO FF is applied to a second input of NAND 542 and a third input receives the ~3A clock signal. The GS output of priority encoder 526 is passed through an inverter 5~6 and applied to the fourth input of NAND 542 Priority encoder 526 has eight inputs D0-D7 witll inputs D~-~7 being inactive and tied to +V. ~ach of the clata input~ D0-D3 is tiecl to a line which extends throu~h -the SDC control bus to an individual one of the SDC I s . The _ signals INT REQ 0, INT REQ l, INT REQ 2 and INT REQ 3 are derived from the SDC's 122 which are assigned the device numbers 0, 1, 2 and 3 respectively. The priority encoder 526 is enabled by the signal IST 0 on lead 552~ This si~nal i9 derived rom the decoder 538 and is at a low level to enable the priority encoder anytime the SDM~ is in a condition to accept an interrupt request. The priority enc~der 526 accepts a signal at one of its inputs D0-D3 and, dependln~J
upon which input terminal is active, produces a two-hit bin~ry value at its output corresponding to the nlul~er a~si~ned to the SDC which made the interrupt request. The "one" output of the encoder is connected to the D input of flip-flop 534 while the "zero" output of the encoder is connected to the D input of flip-flop 536.

:~ ' - -29- ~

The priority encoder has a GS output that is active at any time the encoder receives an interrupt request si~nal provided the encoder input El is at the low levelO The output from the enco~er passes through inverter 546 and conditions NAND 542. If the SDMA is otherwise in condition to execute an interrupt, NAND 542 produces a low level output si~nal to set flip-flop 532. The set output of ~lip-flop 532 is connected to the clocking inputs of 1ip-10ps 534 and 536. When flip-flop 532 is set the signal on lead 554 sets flip-flops 534 and 536 in accordance with the two data outputs from the primary encoder 526. Thus, it is seen that the flip-flops 534 and 536 correspond to the address la~ch 2~8. 'rhe output of Elip-flop 534 is the signal IDN 1 on lead 556 and the output of flip-flop 536 is the signal IDN O in lead 558.
MUX~s 522 and 524 are similar in that they each have a strobe input connected to receive the clock signal ~2AS, four data inputs DO-D3 which may be selectively gated throu~h to the multiplexer output, cand two addressin~ inputs ~ ~0 c~nd Al ~or determinin~ whicil oE the data inputs is to be ~ated thxou~h to the output. Data inputs DO, Dl and D3 of MUX 522 are tied to the lo~ic zero level while the D2 input receives the si~nal BUS ~RANTED. MWX 524 receive~ the . . .
si~nal BUS GR~Nq'ED at its D3 input, BUS GRANTED at its 1)2 input, D SAC~ at its Dl input, and INT SEQ E~ FF at its DO
inpu~. ~his latter signal is derived ~rom the interrupt ae~uence enable Elip-flop 554 and rises to the high level ~hen an interrupt is reco~nized. The output of MUX 524 is connected to the clockin~ inputs of the flip-flops 528 and 530 which act as a two sta~e counterO The J input of 1ip-;:, " " "

., 3L~B9946 flop 528 is connected to +V while the K input is connected to ground. The set and reset outputs of FF 538 are connected to the J and K inputs of FF 53~. The set output of FF 530 is connectea to the Dl input of the decoder 538 and to the Al inputs of MUX' S 522 and 524. The set output of FF 528 is connected to t~1e DO input of decoder 538 and ~he AO input of ~X's 522 and 524.
When the interrupt enahle flip-flop 532 i~ set, then at the following ~2 time the signal from the flip-flop is strobed through MUX 524 to set FF 528. The output from FF 528 enables the AO inputs of ~UX's 522 and 52~ so that the~v are now able to respond to a high level signal on their Dl inputs. In addition, the output of FF 528 enables the DO
input of decoder 538 and the decoder produces the low level output signal IST 1. At the same time, the signal IST O
rises to the high level and disables the priority encoder 526 so that i~ cannot accept another interrupt request.
During IST l the circuits of FIG. 4 apply the address of ~he interrupting SDC 122 back to the SDC. ~s 2~ subse~1ently explained, the signal S~LT generated in FIG. 8 acts with this address to select the SDC whose interrupt is ~ranted priority. The SDC responds with a si~nal SAC
as s,uhsequently described, whic11 in turn results ln the si~nal DSACK risin~ to the hi~h level. At t:he next ~2AS, the si~nal D,SACK passes through MUX 524 to reæet FF 528 and ~et FF 530~ At this time the lead 570 drops to the low level and the lead 572 rises to the high level thus enablin~
the Al inputs to ~JX's 522 and 524 and the Dl input to decoder 538. With input Dl high and input DO low, decoder 538 terminate~ the low level signal IST l and clrops the 4~
signal IST 2 to the lo~ level. Durin~ the interval o~ the signal IST 2 the SD~ sends a signal F~LT to the selected SDC. The SDC responds with a signal FACK (FIG.6) to generate an interrupt request from the SDMA to the bus mana~er, and load the SDC status into the SDMA data re~ister.
When the SD~ is granted access to the bus the signal BIJS
GRA~ITED rises to the hi~h level. On the next following ~A
the suS GRANTED signal is strobed through MUX 524 to set FF
578. ~t the same time, the BUS GRANTED si~nal passes throug~ ~X 522 to reset the interrupt sequence enable flip-~lop 532. ;
With flip-flops 528 and 530 set the si~nals on leads 570 ancl 572 are both at the hiqh level and the decocler 53~ produces no Outpllt signal. The si~nals on leads 570 ancl 572 select the D3 inputs of MU~'s 522 and 524. ~fter the ~tatus information has been transferred over the system data bus, the si~nal BIJS GRANTED rises to the high level. On the next ~2 the signal BUS GR~NTED is strobed through MUX 52~
and resets flip-flops 528 and 530. At this time, the decoder ~ 538 a~ain prc~duces the si~nal IST 0 to thereby enahle the priority encoder 526 so that it may accept another interrupt request.
FIGS. ~, 7 ancl 8 show some o the logic circuits inclucled in data control lo~ic 214, and ~urther show some o~
the drivers and receivers responsive to or connected ~o the s~9tem control bus 20~ ancl the SDC control bus 21n. These circuits will be descrihed briefl~ at this time. Their full function will become evident when various sequences of operation are subsequently described.
In FIG. 6, the signal FACK i9 derived from the SDC
:

. . - . , ., . , .. :. . :

8~ 6 control bus and is inverted by an inverter 600. The output of inverter 600 is the siqnal DFACK which is applied to one input of two AND gates 604 and 606. The si~nal IST 2 is applied to one input of a NOR 608 c~nd the output of NOR S08 is connected to a second input of ~ND 604.
The si~nal INPUT is derived from the system control ~ .
bus 204 ~nd is applie~ to a 3-state Ariver on a logic chip 610. The signal INPUT is active and drops to the low level when the CPU decodes an instruction and finds that it is an input instruction. When the signal INPU-T drops to the low level the driver chip 610 produces a high level output aignal I/O R~. rrhis signal is applied to one input o~ a NO.~
61~ havin~ its output connected to an inverter 614. The `:
si~nal OUTPUT drops to the low level when the CPU decodes an instruction and determines that an output operation is to be performed. When the signal OUTPUT drops to the low level the driver chip 610 produces the si~nal I/O WR which is applied to a second input of NOR 612. Therefore, upon occu~rence of either INPUT or OUTPUT the signal I~O RD or WR ;~
~ ~t the output oE inverter 61~ rises to the high level~
~he si~nal I/O RD i5 also applied to one input o~
a NAND 616, The signal SST 2 is applied to a second input o~ NAND 616 and its output i5 connected to the NOR 608. The output of NOR 608 is connected to AND 604 which in turn has its output connected to one input of NOR 618. The output o~
~O~ 61~ is the low level signal LOAD DATA REG.
The signals LD RD DATA ~nd LR WR D~TA are applied to second and third inputs of NOR 618. The ~ourth input to NOR 618 i5 connected to the output o~ an AND 622.
The signal SDC BUSY comes from the SDC control bus .

-33- .

9~6 210 and is at a low level during data transfer time only when an SDC 122 is busy. The signal SDC BUSY is applied to an inverter 624 having its output connectecl through an inverter 626 one input of ~ID 622. ~ND 622 also receives the output of an AND 628. AND 628 receives the signal I/O
WR from dri.ver chip 610 and is further conditioned by a ~lA clock pulse. The signal SST 1 is applied to another input of ~D 622 hence the output of ~ND 628 may pass through A~D 622 only during sequential state SST 1 if the addressed SDC is not busy.
Tha signal I/O RD from driver chip 610 is applied to one input of an ~ND 630. AND 630 is further connected to receive the signals READ PULSE and SST 3. ~he output of ~ND
630 is connected to one input of a NOR 632 and the OlltpUt of NOR 632 is the signal ENABLE D~TA DRV. The si~nal ~N~BL~-, DATA DRV may also be produced by a combination of si~nalsapplied to a NOR 636 and an AND 638. NOR 636 receives the si~nals INT SEQ EN E~F and RE~D. ~ile output of NOR ~36 is applied to one input of AND 638. rrhe second input of ~ND
G3~ receives the slynal BUS GR~NTED and the ou~put of AND
638 is connected to a second input of NOR 632.
The output of inverter 624 is the si~nal DC BUSY-A and it i9 applied to one input o an ~ND 640. The si~nal READ is applie~d to a second input of ~ND 6~0 and the output of th~ AND is connecked to one input o~ a NOR 642I The output of NOR 642 is passed throu~h an inverter 64~ to become the si~nal DRIVE SDC BUS. NOR 642 also has an input connected to the output o~ an AND 648. AND 648 has three inputs connected to receive the siynal GO FF on lead 426, the output signal from inverter 626, and the siynal I/O WR

~L~8~ 6 from the driver chip 610.
The signal PIN on lead 286 is applied to the SDC
control bus 210 and defines the direction of data flow.
When it is at the low level, data is being sent from the SDC
to the SDl~A under control of the FALT and FACK si~nals.
When the signal PI~ is a~ the high level the direction of data transfer is defined as being from the SDMA to the SDC.
Tlle signal PIN is derived as follows: An AND 650 has one input connected to the output o inverter 626 and a second input connected to receive the signal I/O RD from driver chip 610. The output of AND 650 is connected to one input of an ~ND 652. AND 652 has a second input connected to receive the si~nal GO FF. The output of AND 652 is applied ~
to one input of a NOR 654. The signal INT S~Q EN FF is ~.
a~plied to both inputs of an AND 656 and the output of this AND is applied to the second input of NO~ 654.
An interrupt request flip-1Op 658 and a bus request flip-flop 660 are shown in FIG. 6. Both of these 1ip-1Ops are D-type flip-flops having their clockin~
input~ conneated to receive the cloc~s signal ~3A. Bo-th Elip-1Ops have a reset input which is connected to xeceive . _ the signal BUS GRANTED~ An AND 606 receives the signal IST
2 as well as the DFACK output from inverter 600. The output o~ AND 606 is a signal INTERRUPT REQUEST. rrhis si~nal i~ applled to th~ D input o flip-flop 658 so that the flip-~lop is set at the beginning o~ ~3A when an interrupt is requostefl.
The bus request flip-flop is set as follows. The si~nal ~EAD is applied to one Lnput of an AND 662. This~AND
receives the signals DREQ A and DISABLE BREQ at second and third inputs. The output of AND 6 62 iS connected to one in~ut of a NOR 664. AN ~ND 666 has three inputs for receiving the signals END ~EM OP FF, DR LD FF and D WRITE A. The output of ~D 666 is connec-ted tc) a second input of NOR 664.
The output of ~OR 664 is connected through an inverter 668 to the D input of the bus request flip-flop 660 so the flip-flop i9 set at ~3~ of the output of inverter 668 is at the high level. The set output of flip-flop 660 is connected through an inverter 670 to become the signal BUS REQUEST.
FIG. 7 shows the circuits ~or producing the clock pulses as well as certain ones of the drivers and receivers connected to the SDC control bus 210 for the purpose of generating and receiving the "handshaking" signals required in transfers ~etween the SDM~ and the SDCIs.
The clock pulses ~lA-~A are ~enerated by the CPU
100 and applied over the syste~ control bus 204 to a set o 3-state drivers 700 in each SDMA. Each clock pulse has a duration of 62.5 nanoseconds an~ the time between successive pulses of the same phase is 500 nanoseconds. The ~river chip 700 is permanently enabled "lence when any driver reaeives a low level signal it produces a logic one output sicJnal. The outputs from the drivers 700 are desiqnated 3A. In addition, the signal ~2~ is passed throu~h two inverters 702 and 704 to hecome the signals ~2~S and ~2~D~
This latter ~ignal is appliecl to all of the SDC's 122 by way o~ the SDC control bus 210. In addition, the signal ~ is pas~ed through ~ 3-state dxiver in a driver chip 7~6 to generate the si~nal ~ D which is also applied over the SDC
control ~us to the SDC's. With these exceptions, all output signals derived from the driver chip 700 are employed within ,.,",~., .

' ' 99L~, the SDJ~IA itself.
The signal SALT on lead 285 is connected throu~h the SDC control hus 210 to each of the SDC's When the SALT
signal drops to the low level, it provides an indication to all of the SDC's that the S~MA is presentin~ the address of one of them on the SDC address bus 208. SALT remains active until the addressed SDC recognizes its address and responds with a select acknowledge (SAC~) si~nal. SALT is generated as follows. A NAND 716 has three inputs connected to receive the signals SST 1, SELECTION, and STEP ON~ The output of NAND 716 is the siqnal EN SALT X and this signal is applied to one input of a NO~ 718. A second input of NOR 718 receives the si~nal IST 1. The output of NOR 71~ is connected to both the D and the reset inputs of a D-type flip-flop 720. The set output of the 1ip-flop is applied to an inverter 722 and the output of this inverter is the signal S~LT. A ~3A clock pulse is applied to flip-flop 720, hence the flip-flop is set at the beginning of ~3 if the output of NOR 718 is at the high level. If the output of NOR 718 20 drops to the low level then flip-flop 720 is reset immediately. ,, After the SDCIs receive the signal SALT and one of them recognizes its address ~n th0 SDC address bus, the reco~nizing SDC drops the signal SACK to the low le~el.
'rhi~ si~nal is pas~ed throu~h an inverter 724 to become the siqnal D SAC~. The D SACK signal is employed in FIG. 5 to advance the sequential state logic circuits thus terminating either the signal SST 1 or IST 1 depending upon the type of operation being performed. This will cause the output of NOR 718 to drop to the low level so that the flip-flop 720 .
is reset and the SALT si~nal terminated.

~8~ 6 The output of recei~er 724 is also applied to the reset input of a D-type flip-flop 728, and is passed through an inverter 730 to generate the signal D SACK.
The purpose of the flip-flop 728 is to signal an active SDC that a memory parity error or address error occurred during a memory operation. If one o these errors occurs then the memory circuits drop an appropriate signal on the system control bus 204 to the low level. If an addressing error occurs the signal MEM ADR ERR drops to the 10 low level to enable a NOR 732~ On the other hand, if a memory parity error occurs then the low level signal M~M-PAR ERR is applied to NOR 732. The output of NGR 732 is connected to one input of NAND 734 and the second input of the NAND receives a ~2A clock pulse. The output of NAND 734 is applied to the clock input of flip-flop 728 and ~ets the ~lip-~lop provided the signal BUS GRANTED is at the high level thereby indicating that an SDC associated with this SDMA is communicating with memory. The set output o~
~lip-flop 728 is applied to one of the 3-state drivers 706 20 to generate the low level signal MEM CHECK. This signal is sent to the active SDC to terminate its operation. When the SDC terminates the operation the signal SACK rises to the high level and the flip-flop 728 is reset.
The signal FALT is a control signal transmittecl ~rom the SDMA to an SDC that has already been selected.
When the 91gnal FALT is at the low level it in~orms the ~alected SDC that the in~ormation available on the SDC data bus should be acted on. The signal FALT is terminated after the SDC acts on the information and returns to the SDMA an 30 acknowledge signal designated FACK. The signal F~LT is '',.. ' " :

; `'`"

~ 399~6 generated as follows. The output of inverter 724 is connected to one input of a NAND 736. NAND 736 further receives the signals STEP ON and SST 2. The output of NAND 736 is connected to one input of a NOR 738. The signal IST 2 is applied to a second input of NOR 738 and the output of the NOR is connected to the D input of a D-type flip flop 740. The flip-flop is clocked by a ~3A pulse so the flip-flop is set on ~3A if the output of NOR 738 is at the high level. The set output of flip-flop 740 is connected to one 10 of the drivers in the chip 706 and the output of this driver is the low level signal FALT. Flip-flop 740 is reset when the output signal from NOR 738 drops to the low level.

-A ~K flip-flop 750 has its set output connected to one of the drivers on chip 706 for the purpose of producing the signal DACK. DACK is a data acknowledge control signal which ls sent from the SDMA to a selected SDC for the purpose of acknowledging a data re~uest. If a data write signal was active at the time the data request was received ~rom the SDC, then DACK informs the SDC that the character on the SDC
20 data bus has been written into the data register o~ the SDMA. If a data read signal was active at the time the data request was received from the SDC, then DACK informs the SDC

that the SDMA has a byte on the SDC data bus ready for acceptance by the SDC. The particular details oE thes~
operations will become clear when specific examples of certain operations are considered.
A D-type 1ip-flop 752 has its clock input connected to recelve the signal DR LD FF~ The set output of the flip-10p is connected to the J and K inputs of flip-flop 750 and 30 produces the signal DISABLE BREQ which appears on lead 754.

_39-.

~ 9946 Flip-flop 750 is clocked with a ~3A clock signal and both flip-flops 750 and 752 are reset as the signal DREQ A applied to their reset inputs drops to the low level. While flip-flop 750 is reset it gener~tes the high level signal DACK FF
and while flip-flop 752 is reset it generates the high level . . _ signal DISABLE BREQ. When the signal DR LD FF rises to the high level it sets flip-flop 752. At the next following ~3A the output of flip-flop 7S2 sets flip-flop 750 and the output of this flip-flop drives one of the drivers on chip 10 706 to produce the low level signal DACK. Both flip-flops are reset by the signal DREQ A.
In FIG. 8 the signal DREQ from the SDC control bus is passed through an inverter 800 to become the signal DREQ
A. A selected SDC drops DREQ to the low level to make a data request to the SDMA. The output of inverter 800 is also applied to one input of an AND 804 and a NAND 806. The signal D WRITE from the SDC control bus is passed through an inverter 808 to become the signal D WRITE ~. D WRITE is generated by an SDC throughout an interval the SDC is 20 transferring bytes of data to the memory. The D WRITE A
signal is applied to a second input of NAND 806 as well as one input o two further AND's 812 and 814. AND 812 receives the signal DAC~ FF at a second input if the DAC~ ~lip-~lop 750 is xeset. Thus, i~ the DACK flip-$10p is reset and the 9ignal D WRITE is at the low level, AND 812 is condltioned to produce a high level output signal to AND 704. When DREQ
drops to the low level the output of inverter 800 enables the second input of AND 804. If the data register load flip-flop 816 is reset at this time it is enabling the third input of AND 804 so the AND produces a high level output , : ' `
:

signal to the J input of flip-flop 816. The output of AND
804 is the signal LOAD W~ITE DAT~. The clock signal ~lA is applied to an inverter 820 and the outpu~ of the inverter is applied to the clock input of flip-flop 816, hence the flip-flop is set at the end of the ~lA clock signal if the output of AND 804 is at the high level to indicate that the data on the SDC ~ata bus has been loaded to the SDMA data register, When the flip-flop is set the signal DR LD FF rises to the high level while the signal DR LD FF drops to the low level.
10Flip-flop 816 may also be set for operations involving the transfer of data from memory through the SDMA
to an SDC. The output of inverter 808 is passed through a Eurther inverter 822 to become the signal READ. The REA.D
signal is applied to one input o~ an AND 826. MEM ACK : :
is a signal placed on the system control bus by the memory to indicate that data from the memory is on the data bus and may be strobed into the SDMA data register~ MEM ACK is applied to a driver in the 3-state driver chip 828 and when MEM ACK is active the output of the driver enables a second input o~ AND 826. AND 826 is further enabled by the signal BUS GRANTED which is derived from a 3-state driver chip 830.
BUS ~RAN5' is a control signal placed on the system control bus by the bus manager in response to a bus request b~ the SDMA and indicates to the SDMA that it has control over the -~y~tem bus. BUS GRAN5' is applied to a driver in the chip ~30 and when it drops to the low level the chip produces a high levol output signal BUS GRANTED on lead 832. This latter signal is connected back to the input of a further driver within the chip 830 so that this driver simultaneously produces the low level signal BUS GRANTED. The BUS GRANTED

~8~a46 signal enables AND 826 when it is at the high level so AND
826 may produce the high lPvel signal LOAD RD DATA on lead 836. The output of AND 826 is passed through an inverter 838 to set flip-flop 816 thereby indicating that the byte of data on the system data bus has been stored in the SDMA data register.
When DREQ rises to the high level after each data request on a read operation, D WRITE is at the high level AND 806 produces a high level output signal that is applied 10 through a NOR 840 to reset flip-flop 816.
The flip-flop 816 is also reset by the signal END
MEM OP FF from flip~flop 842 during a WRITE operation. The signal MEM ACK on lead 837 is applied to the J and K
inputs of flip-~lop 842 and the set output of the flip-flop is connected to one input of AND 814. The AND is further enabled by the output from inverter 808 and the ~2 clock pulse. The inverted ~1 clock pulse is applied to ~he clocking input of ~lip-flop 842, hence the flip-flop is set at the - end of ~1 if the signal MEM ACK is at a high level. AND 814 20 then produces an output signal that is passed through NOR
840 to the reset input of flip-flop 816. Flip-flop 842 is also reset when the signal BUS GRANT is terminated and the lead 832 drops to the low level. `
When flip-flop 842 is reset, it produces the high lovel signal END MEM OP FF. In addition, the low level signal ~rom the set output enables one input of a NAND 844.
This NAND is further enabled when the signal EN DATA ADR
drops to the low level. The output o~ NAND 844 is the high . . .
level signal MEM OP. This signal is passed through an 30 inverter 846 to become the signal B~S BUSY~ The BUS BUSY

, ~ ~4~~

signal is transmitted over the system control bus to the bus manager to inform the bus manager that the SDMA has accepted control of the bus in response to the BUS GRANT signal.
The signal PWR ON CLR is automatically generated when the CPU is turned on. It is a 500 millisecond pulse that is transmitted over the system control bus to each of the SDMA's. In each SDMA it is applied to a NOR 850. The output of NOR 850 iS the signal SDMA RESET. It is passed through NOR 840 to reset flip-flop 816. In ad~ition, SDMA
10 RESET is passed through an inverter 854 to become the signal SDMA RESET. The signals SDMA RESET and SDMA RESET are applied to various ones of the flip-flops and counters in the SDMA for the purpose of resetting or clearing them when the power is turned on. A similar function is accomplished when the operator depresses a reset key on the control panel. This generates the signal RESET which is applied to the second input of NOR 850 and results in the generation of the same signals as the PWR ON CLR. In addition, the signal RESET is passed through inverters 858 and 860 to become the ~ signal S RESE~. This latter signal is applied over the SDC
control bus 210 for the purpose of resetting each of the SDC's 122.

TYPICAL OPERATIONS
It takes a combination of one input and three output instructions from the CPU 100 to set up an SDMA and an SDC connected to that SDMA 50 that data may be transferred between the memory 102 and the SDC. This is true regardless of the direction in which the transfer of information is to take place. During the set-up sequence the CPU generates an input instruction followed by three output instructions~ In _43-~0~

the following description it will be assumed that the operation to be performed is the transfer of one line of data (132 bytes) from the memory to a line printer connected to the SDMA having the address 101 fo.r the purpose of printing that line of data~ The operations performed during each of these set-up sequence instructions are described below in separate sections. Generally speaking, the input instruction :` `
addresses the status register in a specific SDC 122 serviced by a specific SDMA 108. If the SDMA is busy its status is 10 returned to the accumulator in the CPU. If the SDMA is not :
busy then the status of the addressed SDC is reported back to the accumulator. Assuming that the addressed SDC is connected to the system, is turned on, and is not busy, the CPU issues the first output instruction and places on the system address bus an address having the format shown in FIG.
lOC. The SDMA responds to this output instruction by loading the lower half of the address pointer counter 232 with the data byte in the CPU accumulator. The CPU then .
executes another output instruction and places another .
address having the format shown in FIG. 10B on the system address bus. In response to this second output instruction, the SDMA loads the data byte on the system data bus into the .
upper half of the address pointer counter 232. Finally, the CPU executes a thlrd output instruction and sends a command to the selected SDC. An address on the system address bus identi~ies which re~ister .is to receive this command. Under the assumed conditions, this command is a print command, hence the address appearing on the system address bus has the format shown in FIG. 10E. After this third output 30 instruction has been executed, the CPU returns to its normal ~ :

~, .

... . . .. . ..

3t~9~6 program and the SDMA controls the actual transfers of the data bytes from the memory to the selected SDC by means of the address contained in ~he address pointer counter.
During the actual transfer of data, the SD~ must compete with other units connected to the system bus for access to the memory. Thus, for each by~e transferred the SDMA must maXe a bus request and after the SDMA is given access to the memory the bus manager responds with a BUS GRANT signal.
After the data transfer operation is completed the SDC
10 generates an interrupt request to the SDMA in order to report its status, i.e., it has loaded its buffer register and initiates a print cycle. The SDMA is now free to service another SDC. After the printer prints the line of data its SDC will make another interrupt request to the SDMA, this time to report to the CPU that it is now in a status to accept further data. Each of the input and output instructions employed to set up a transfer operation will now be consldered separately in detail.
INPUT INSTRUCTION. If the CPU 100 is an Intel 8080, it 20 takes three machine cycles of the CPU to execute an input lnstruction. During the first two machine cycles the instruction is read out from storage and decoded. At the irst ~3A of the third machine cycle M3 (See FIG. ~) an address, which should have the ~ormat shown in FIG. 10D, is placed on the system address bus 20~. At the same tlme, the CPU drops the signal CPU SYNC to the low level. In FIG.
4, NAND 408 recognizes the combination of bits in A7-A5 as being the address of the SDMA. The output of NA~'D 408 enables one input of NAND 412 which has a second input 30 enabled by the output of inverter 418~ The output of NAND

408 also enables one input oE NAND 416.
At ~4 the cPu places on the control bus the low level signal INPUT. This signal passes through a 3-state driver 610 to generate I/O READ thereby enabling a second input of NAND 416. Since both of the address bits A4 and A3 are zeros, NAND 458 produces an output signal to ~urther enable NAND 416. The output of NAND 416 passes through inverter 417 to generate the signal SELECTION. The SELECTION ~ .
signal is applied to NAND 716 but the NAND is blocked at 10 this time because the signal SST 1 is at the low level.~ ~-The I/O READ signal generated by driver 610 passes throu~h NOR 612 and inverter 614 to drive the signal I/O RD
or WR to the high level. This latter signal further enables NAND ~12 so at the next ~lA NAND 412 produces the signal START PU~SE~ START PULSE immediately sets the GO flip-flop 424 thereby generating the signals GO FF and NOT READY.
NOT READY is transmitted back to the CPU to stop the CPU in its third machine cycle of the input instruction. This effectively places the CPU in a wait state and during this 20 walt state the address remains on the system address bus and the signal INPUT is maintained on the control bus.
When the GO flip-flop is set, the signal GO FF
is applied to NAND 542. This blocks NAND 542 throuqh whlch all interrupt ~equests from the SDC's must be passed to ~et the Elip-~lop 532~ This insures that no SDC is able to lnitlata an interrupt request while the SDMA is busy processing th¢ input instruction.
Tha signal GO FF passes through MUX 506 and enables counter 510 so at ~2A the counter is incremented and the 30 output of the counter is applied to decoder 514 to produce -~6-~ ~9 ~ ~6 the signal SST 1.
SST 1 is applied to NAND 716 which is already receiving the high level signal SELECTION. The signal STEP
ON is also at the high level at this time provided, as subsequently explained, the SDM~ was not busy at the time START PULSE was generated. The output of NAND 716 passes through NOR 718 and at ~3A flip-flop 720 is set to produce the signal S~LT.
SALT iS applied to all of the SDCIs 122 over the 10 SDC control bus to alert the SDCIs to the fact that the address o~ one of them is present on the SDC address bus.
Th~ address wa9 placed on the SDC address bus at the same time it appeared on the system address bus. From the system address bus, the addr~ss bits pass through inverters 400-404 to MUX 406 and AND 405. Since the interrupt sequence enable flip-flop i5 reset at this time, bits A4-Al are gated through MUX 406 and bit A0 is gated through AND 405 and NOR 407 to become the address bits RSL 4-~-I on the SDC address bus.
Also, when the signal I/O READ was generated it passed 20 through AND 650 to enable AND 652, and when the GO 1ip~flop ~24 was set the signal GO FF passed through AND 652 and NOR
654 to become the signal PIN which is applied over the SDC
control bus to all of the SDC~s 122.
PIN tells all of the SDC~s that a trans~er is to take place from one of the SDC~s to the SDM~ while ~
t~lls all of the SDC~s to compare address bits RSL l and ~SL 0 with its own address. The SDC which recognizes bits ~SL 0 and RSL r as its own address will connect itself to the SDC bus and within 250 nanoseconds generate the signal 30 SACK thereby acknowledging to the SDMA that it is connected.

~8~399~6 At the first ~4A clock pulse after the SDMA
generates the signal SALT the addressed SDC generates the .
low level signal SACK and this signal is passed over the SDC
control bus to the SDMA where it passes through inverters 724 and 730 to generate the signals D SACK and D SACK. The signal SACK remains active until the end of the data transfer operation which will be set up by the present input instruction and the ~ollowing three output instructions~ After the data transfer operation is completed the SDC will terminate the ~
10 SACK signal to deselect itself. .~:
The signal D SACK is passed through NOR 544 to block NAND 542. This insures that no interrupt request fxom other .SDC~s will be honored even after the GO ~llp-flop is reset near the end of the present input instruction cycle.
The signal NAVAIL produced by NOR 544 is passed through NOR
438 to enable the busy flip-flop 422. The flip-flop is not set at this time and will be set only if an attempt is made to start another selection sequence to a different SDC
while the SDMA is connected to a first SDC.
The signal D SACK is passed through MUX 506 and at the first ~2~ after SACK becomes active~ counter 510 is advanced to a count of two and the output of the counter actiVates the decoder 514 to produce the signal SST 2. SST
1 is terminated at this time and the output o~ NAND 716 r~sets flip-10p 720 through NOR 718 to terminate SALT.
SST 2 and D SACK enables NAND 736 which is further enabled by the signal STEP ON which is at a high level. The output of NAND 736 passes through NOR 738 to enable the ':~
Function Alert flip-flop 740. At ~3A the flip-flop is set 30 thereby causing a drivers 706 to produce tha low level signal FALT (Function Alert). ~he signal F~LT is placed on the SDC control bus and is accepted by the SDC which was selected during SST 1. FALT tells the selected SDC that it should again look at the address on the SDC address bus, this time examining the function identifying bits RSL ~-RSL-. Since all of these bits will be zeros (FIG. lOD) the SDCrecognizes this as requiring that its status be placed on the SDC data bus.
The selected SDC decodes RSL 4-RSL 2 and reads out 10 its status register onto the SDC data bus 206 and the status is applied to MUXIs 300 and 301 as the data bits ~-BIT 0-S BIT r. The status is reported as one of four hexidecimal values 00, 80, 90 or 40.
1~ there is no SDC connected to the SDMA having an addre~s corresponding to that placed on the SDC address bus, then the status value 00 indicates that the addressed SDC is non-existent. In this case there is no actual readout of the status from the status register and the SDC. In this case the SDMA will generate the status bits as subsequently 20 de~cribed.
I~ the addressed SDC is busy per~orming another task it reports the status value 80. If the addr~ssed SDC
i~ conneated to a SDC bus, but is not on-line, it reports the stRtus value 90. Finally, i~ the addressed SDC does exist, is on-line and connected, and is available to proceed with another operation, lt reports the status value 40.
Shortly a~ter the status value is applied to the data register multiplexers 300 and 301, and at ~4A following the generation o~ the FALT signal by the SDM~, the SDC
30 generates the signal FACK (Function Acknowledge) to tell the .

SD~ that the SDC has placed its status on the SDC datA bus.
FACK passes through inverter 600 to become the signal D
~ACK. D ~ACK enables one input of AND 6040 The signals I/O
READ and SST 2 are both high so the output of NAND 616 passes through NOR 608 to condition AND 604~ Therefore, when D ~ACK occurs AND 604 produces an output signal that passes through NO~ 618 to become the signal LO~ A ~EG.
This latter signal is applied to the select inputs of MUXIs 300 and 301 and, since the signal DRIVE SDC BUS is high at 10 this time because all inputs to AND 648 ara high, the ætatus bits S7-S0 are gated into the data register.
As soon as the status is entered into the data register it is made availabla to the data bus drivers 314.
The signal STEP ON- is at the high level so the low level output of NAND 310 is applied to the select inputs of MUX~s 302 and 303. This selects the A inputs which are receiving the status data that has been latched into the latches in the data register ~UX's 300 and 301. The StAtUS is not placed on the system data bus at this time because the 20 drivers 31~ are not enabled.
The D FACK signal is passed through MUX 506 to enable counter 510, and at the next ~2A the counter is advanced so that decoder 514 produces the signal SST 3. 5ST
3 immediately resets GO flip-~lop 424 thereby te~minating the signals GO ~ and NOT REA~. In FIG. 7, SST 2 drops to the low level when SST 3 begins, hence the output of NAND
736 passes through NOR 738 to reset the function alert flip- :
flop and terminate FALT. This in turn causes the selected SDC to terminate the signal ~g.
The signal SST 3 is applied to AND 630 which is ..

9~

further enabled at this time by the signals I/O READ and READ PULSE. The output of AND 630 passes through NOR 632 and enables the 3-state drivers 314 so that the status is gated onto the system data bus. The status byte passes into the accumulator within the CPU 100.
~ hen the signal NO-~-READY rises to the high level at the beginning of SST 3, it terminates the wait state of the CPU 100 and the execution of the input instruction is resumed so that the status on the data bus may be gated into 10 the accumulator. Shortly thereafter, the CPU terminates the signal D~T~-~D~ , thereby acknowledging receipt of the data and the output o~ inverter 500 passes throu~h NOR 504 and MUX 506 to enable the counter 510. At the next ~2~
the counter is advanced thereby returning it to the zero state and terminating the SST 3 output from decoder 514.
This completes the response of the SDMA to the input in-struction. ~'he CPU now analyzes the status it has received from the SDMA and determines what steps to take in response to the reported status.
20 FIRST OUTPUT_INSTRUC1'ION. Assuming that the SDMA sent the status value 40 to the CPU thereby indicating that the SDMA
and the addressed SD~ are both ready to receive ~urt.her instructions, the CPU begins execution of an output instruction and load~ its accumulator with a byte of data representing -the eight least significant bits of a memory address. This address ~s -the address o~ the ~irst memory location where clata will be written or read once the SDMA and SDC have been set up and the actual data transfer begins. Referring to FIG. 11, at the first ~3A of the third CPU machine cycle 30 (M3) during which the output instruction is being executed, ', .. .

: . ... . .
.

~385~

th~ contents of the CPU accumulator are gated onto the system data bus and applied to the B inputs of data register multiplexers 300 and 301. At the same time, the CPU places on the system address bus an address having the format sllow~
in FIG. 10C and begins generation of the signal CP~
NAND 408 recognizes address bits A7-A5 as being the address of this SDMA and produces the signal SDMA ~DDRESS to enable NANDIs 412 and 414. At ~4A the CPU ~enerates the low level signal O-~TP~T which is passed through a driver 610 to become 10 the signal I/O WRITE. I/O WRITE passes through NOR 612 and inverter 614 to generate I/O RD or WR.
At ~lA, the GO flip-flop is set by the output o~
NAND 412 and the signals STAR~ P~LSE and NOT--RE-A~Y are generated in the same manner as for the input instruction.
The address bits A4-A0 pass through inverters 400- `
~04 and ~11 to generate the signals RAD~ ~ and RADR ~-RADR-O. The signal RADR 0 is applied to decoder 318 but the decoder is not enabled at this time. The signals RADR 1~
RADR 2~ RADR 3, and RADR 4 are all applied to NAND 452 which 20 recognize5 these ~our address bi~s as being the address of the address pointer counter. q'he output o~ NAND 452 conditions N~ND 414 which is receiving the signals I/O READ or WRI~E
and SDMA ADR at this time. NAND 414 produces a low level output signal that passes through i~verter 454 to become the high level signal SDM~ PROBEo SDMA P~OBE is applied to NAND
316 which is further enabled by I/O WRITE but the NAND is blocked at this time because the signal SST 2 is at the low level.
SDMA PROBE is also applied to NAND 310~ The 30 resulting low level output from NAND 310 is applied to the ~.' ' 108~9~

select inputs of MUX's 302 and 303 thus selecting the output of the data register for application to the counters 320-323.
The output of NAND 414 is passed through NOR 448 thus driving the signal STEP ON to the high level while clropping STEP O~ to the low level. STEP ON is applied to the A~ and D5 inputs o~ MUX 506. Since the counter 510 is standing at zero at this time, the STEP ON signal applied to the A2 input of MUX 506 selects the D4 input. This gates 10 the signal GO FF through MUX 506 to the counter 510 and at ~2A the counter is advanced to a ~ount of one. The output of the counter is decoded by decoder 514 to generate SST 1.
In FIG. 6, SS~ 1 enables one input of AND 622 which is further enabled by the high level signal DC BUS~ A. ``
AND 628 is enabled by I/O WRITE and at ~ A after SST 1 goes high the output of AND 628 passes through AND 622 and NOR
618 to generate the signal LOAD D~TA REG. Since the signal DRIVE DC BUS is at the high level, this loads the data byte on the system data bus into the data register MUX~s 300 and 20 301. Since the signal SDMA PROBE is causing the output o ; NAND 310 to select the A inputs o~ MUXIs 302 and 303, the byte of data loaded into the data register is immediatel~
gatad throu~h to the counters 320-323. However, the data is not entered into the counters at this time.
At this time, counter 510 contains the count o~
one and the signal STEP ON is at the high level. 'rhe combination of these two signals selects the D5 input of ~UX
506 so that the STEP ON signal is gated through MUX 506 to enable counter 510. At ~2A the counter is incremented to 30 the value two and the output o~ the counter is decodecl by 9~6 decoder 514 to produce the signal SST ~.
In FIG. 3, SS~ 2 enables NAND 316 and since the other inputs of the NAND are at the high level at this time it produces a low level outpu~ signal to enable decodex 318.
The decoder is receiving the high level si~nals DC ~USY A
and RRDR 0 at this time, hence it produces a low level output signal to enable ~he loadin~ of counters 320 and 321.
At this time the counters 320 and 3~1 are loade~ with the byte of data that has been held in the data register.
During the entire output operation the signal DISABLE BRE~ i 9 at a low level thus blocking AN~ 306. The low level output of AND 306 is passed through inverter 308 and applied to the D6 input of MUX 506. The signal STEP ON
is still at the hiyh level and during SST 2 the counter 510 contains a count of two, hence the signal ENABLE STEP is gated throu~h MUX 506 to the counter 510. At ~2~ the clock pulse increments the counter to a count o~ three and decoc~er S14 decodes this value to ~enerate th~ signal SST 3.
SST 3 resets the GO ~lip-flop 424 thus terminating 2~ -the si~nals GO FF ancllNOT REA~Y. NOT R~ADY is sent back to the CPU where it terminates the wait sta-te and the CPU
resumes execu-tion o the output instruction. ~he CPU
~se~uently terminates the si~nal WRI~E PULS~ s~ the inv~rter 50~ applies a low level input si~nal to NOR 5n~.
~rho NOR i9 xeceiving a low level signal at its other input a~ this ~me, h~nce a hi~h level output from NOR 504 passes tllxou~h ~X 506 to enable counter ~10~ At the irst ~A of the next machine cycle (~1) counter is advanced by a clock pulse thereby resetting it to the zero state. This concludes the output operation for loading the lower half of the .

~8~ 6 address pointer counterO
SECOND OUTPUT INSTRUCTION. After the output operation just descri~ed has been completed, the CPU executes another output instruction for the purpose of loading the upper half of the address pointer counter. This instruction is executed in exactly the same manner as the previous output instruction with one exception. The address placed on the system address bus has the format shown in F~G. 10B. Since bit A0 is a zero inverter 400 produces the low level signal RADR 0 which 10 is applied to the decoder 318~ The low level signal ~ADR 0 in combination with the high level signal DC BUSY A causes the decoder 318 to produce a low level output signal at terminal 2 to thereby enable the load terminals of the two high order counters 322 and 323. Thus, the data byte Erom the accumulator is passed through the data register and through MUX~s 302 and 303 to enter the high order counters 322 and 323.
With respect to both the first and second output instructions, it should be noted that no handshaking is 20 required with the selected SDC since all communication during these two output instructions is between the CPU and the SDMA itself. During SST 1 the low level signal STEP ON
blocks NAND 716 to prevent the setting of flip-~lop 720 ancl `
generation of the signal S~LT. During SST 2, ~ blocks NAND 736 to prevent the setting of ~lip-flop 740 and the generation of the signal FA~. Since ~ is not generated, the SDC will not ~enerate the signal ~g. However, the SDC
will still be producing the signal S~C~ which was rendered ~ active during the execution of the input instruction.
; 30 THIRD OUTPUT INSTRUCTION. After the two output instructions 39~9~6 are executed to load the address pointer counter, the CPU
executes a third output instruction which actually provides the command which tells the SDC what function is to be per~ormed. At the first ~3A of the third machine cycle ~M3) o~ the CPU~ during execution of the output instruction, the CPU places on the system address bus an address having the format shown in FIG. lOE, and places on the system data bus a byte representing the actual command. ~or purposes of the present explanation, it is assumed that the one bit in A3 ~-10 and the zero bit in A4 defines the address of an SDC command register and that the byte on the data bus is 40, designating a pxint command. From the syskem addxess bus, the low order a~dre~s hit passes through invert~r 400, ~ND 405 now enabled, and NOR 407 to become the signal ~ on the SDC address bu~. Signals Al-A4 are passed through inverters 401-404 and MUX 406 to become the signals ~ Rg~ on the SDC address bu5.
Address bits A5 A7 are recognized by NAND 408 and the output of the NAND enables one input o~ NAND 412. A
20 9econd input of the NAND 412 i8 enabled by CPU SYNC which becomes active at the same time that the address bits are placed on the address bus. At the n~xt clock pulse time, ~4~, the signal OUT~ drops to the low level so that driver 610 produces the signal I/O WRITE. This latter signal is passed through NOR ~12 and inverter 61~ to genera~e the signal I~O ~D or WR.
I~O RD or WR enables a third input of NAND 412 and at the next ~lA, NAND 412 generates the signal ST~RT--FI~
S~ART PULSE immediately sets flip~flop 424 to generate GQ
30 FF. GQ FF is inverted at 428 to become the NOT READY

.,.:
-56- :
','`: ~

signal that is sent back t~ the cPu for the purpose of placing it in the wait state as previously described.
The signal GO FF passes through MUX 506 to counter 510 and at ~2A the counter is advanced to the count of one so that decoder 514 produces the signal SST 1.
During SST 1 the actual command, now present on the system data bus, is loaded into the data register. In FIG. 6, the signals I/O WRITE, GO F~ and DC--BUSY A all condition AND 648 so that it produces an output signal that 10 passes through NOR 642 and inverter 644 to produce the high lavel signal DRIVE SDC BUS. In FIG. 3, DRIVE SDC BUS enables NAND's 311 so that the output of MUXIs 302 and 303 may be gatad onto the SDC data bus. The signal DRIVE SDC BUS
places the select input o~ data register MUX~s 300 and 301 at the high level so as to select the B inputs of the MUX~s which are connected to the system data bus. The signal ~
is at the high level and blocks NAND 310 thereby placing the select input o~ MUX~s 302 and 303 at the low level whereby these MUX's are conditioned to receive the outputs 20 from the data reglster MUX's 300 and 301. In FIG. 6, I/O
WRITE enable~ ~ND 628 and at eaah ~lA it produces an output signal to enable AND 622. E~ Y-~ ls at a high level and anables a second input of AND 622. SST 1 is applied to a third input o~ AND 622 so at olA o~ SST 1 and 622 pxoduaes an output signal that passes through NOR 618 to become the signal L~A-~ ~A~ RE-~. This latter signal enables the clocking o~ ~he command on the system data bus into the data register latches 300 and 301. Immediately upon loadlng of the data register, its contents pass through MUXIs 302 and 303 and 30 the gates 311 to the SDC data bus , '.' ;.

~?1!5i5~9~6 The SDC which acknowledged its selection back during the input instruction has maintained its select acknowledge signal at the low level. SAC~ passes throu~h inverter 724 to become the signal D SACK which enables the Dl input o~ MUX 506. With counter 510 containing a count o~
one, D SACK is passed through MUX 506 to enable counter 510 at ~2A the counter is advanced to a count o~ two so that the decoder 514 terminates the signal SST l and initiates the signal SST 2.
During SST 2 the SDMA sends a ~ to the SDC to tell the SDC that there is valid data available for it on the SDC data bus. ~he signal SST 2 passes through NAND 736 and NOR 738 to enable ~lip-flop 740 and at the next following ~3A the flip-flop is set to generate ~
In response to FA~ the SDC strobes the command on the SDC data bus into the register, whose address is speci~ied by the address on the SDC address bus. After it has stxobed the command into the register, the SDC generates ~ as an acknowledge signal. In E'IG. 6, ~ passes through inverter 20 600 to become the signal D FACK. In E'IG. 5, D FACK passes through MUX 506 to counter 510 and at ~2A the counter is advanced to a count of three thereby causing decoder 514 to terminate S5~ 2 and ini~iate SST 3. In FIG. 7 ~h~ ~rm~nation o~ SST 2 causes ~lip-flop 7q0 to be immediately reset thereby texminating FALT.
In FIG~ 4, SST 3 resets the GO ~lip-flop 424 theraby terminating the signal W-~T READY. This enables the CPU to resume execution of the output instruction. The CPU
then termînates the signal WRI~E P~S~ which is passed 30 through inverter 508 to block NOR 504 and apply a signal ~(~899~6 through the D3 input of MUX 506 to the counter 510. At the next ~2A the count~r is advanced to return it to the zero state. This causes decoder 514 to terminate SST 3.
This concludes the sequence of instructions for setting up a data transfer between a selected SDC and the memory. The sequence includes an input instruction and three output instructions. During the input instruction, the SDC to be involved in ~he data transfer operation is selected and its status reported back to the CPU. During 10 the first and second output instructions the address pointer ; counter in the SDMA is loaded with a value representing the ~ir~t address in memory to be involved in the data trans~er operation. ~inally, during khe third output instruction, a command is sent to the selected SDC to tell it what operation is to be performed. ~he CPU is now free to return to its program. The actual transfer of data between the selected SDC and the memory is accomplished by direct accessing of the memory with the address pointer counter in the SDMA.
D~TA TRANSFERS
20 OUTPUT TRANSFERS. The selected 5DC anàl~es the command it received during the third output instruction o~ the set up ~equence and determines what action should be kaken in response to the command. Assume ~or purposes of explana-tion that the sQlected SDC controls a line printer capable of printing 132 characters per line. Assume ~urther that the command instructs the SDC to load its buf~er register from the memory with 132 bykes o~ data in preparation ~or a print operation. Referring to FIG. 12A, as soon as the SDC has analyzed the command it begins the data transfer opexation 30 by generating the low level signals DREQ and SDC BUS~
;'.' .. ' ' ~S9- "

'"~ ' . " . . ,~

will be generated for each byte to be transferred, but SDC
BUSY will remain low throughout -~he data transfer operation.
Since this is to be an operation involving a read from memory, the SDC maintains the signal D ~RITE at a high level throughout the data transfer opera~ion. In FIG. 8, these signals from the SDC cause the signals READ, DREQ A, and DC
BUSY A to be at the high level while the signals D WRITE A
and DC ~U~Y-A are driven to the low level.
SDC BUSY is maintained at the low level throughout 10 the data transfer operation for the purpose of preventing the inadvertent changin~ of the contents of the address pointer counter, or the inadvertent destruction of data in the data register if the CPU should happen to execute an output instruction while the data trans~er operation is taking place. In ~IG. 6, the low level signal DC BUSY A
is applied to decoder 318, hence even if the decoder should receive an enabling input, its output would not select either the upper or the lower half of the address pointer counter. In FIG. 6, DC BUSY A disables AND's 622 20 and 648 to prevent L~D DATA REG and DRIVE DC BUS from being generated if the SDMA senses an output instruction which would generate I/O WRITE at driver 610. Also, DC BU9Y A
blocks AND 650 to prevent generation o~ the signal ~
i~ the SDMA senqe~ an input instruction which would cause the ~eneratlon o~ I/O READ at drivers 610.
DC ~USY ~ and RE~D enable AND 640 and it produces an output signal that passes through NOR 642 and inverter 644 to generate the signal DRIVE SDC BUS Because DC BUSY A
and READ are both at the high level throughout the data 30 transfer operation, DRIVE DC BUS seleats the B inputs to the data register MUX7s 300 and 301 and enables the NAND's 311, STEP ~N blocks NAND 310 thereby conditioning MUXIs 302 and 303 to pass the contents of the data register through to the NANDIs 311, once the data register has been loaded.
When the SDC generates the first DREQ an inverter 800 produces a high level signal DREQ A. This signal passes through AND 662 which is further enabled at this time by READ and DISABLE sREQ. The output of AND 662 passes through NOR 664 and inverter 668 to the bus request flip~flop 660.
10 At the first ~3A after the first DREQ A is generated, flip-flop 660 is set thereby driving the signal BUS REQUEST
to the low level.
The signal BUS REQUEST is sent to the bus manager to inform it that the SDMA requires the use of the bus for the purpose of addressing the memory. BUS REQUES-T- is actually applied to a priority encoder in the bus manager to generate a BUS GRANT, in essentially the same manner as that signal is generated in the aforementioned copending application.

.
When the bus manager determines that the SDMA may be granted 20 priority it sends back the signal BUS GRANT. BUS GRANT
enables decoder 346 and the decoder produces the signal ENABLE DATA ADR.
In FIG. 8, ENABLE D-ATA ADR passes through NAND 84 to generate the signal MEM OP. MEM OP is passed through inverter 846 to generate the signal BUS ~USY which is sent bac~ to the bus manager anA allows the SDM~ to t~ke control oE the system bus for one memory cycle of 940 nanoseconds.
BUS GRANT places the contents of the address pointer counter on the system address bus for the purpose of 30 addressing the memory. B~S GRANT is applied to the strobe - :~Q~ 6 inputs of MUX~s 332 and 334 and the enabling inputs of drivers 342 and 344. In addition, when BUS GRANT enables decoder 346 the decoder produces ~n output signal to enable drivers 3~0.
At the same time the address is placed on the system address bus, the control signals MEM START and WRITE
are sent to the memory over the system control bus from drivers 340. ~M oP con~itions one driver 340 to generate the low level signal MEM S-TART. In FIG. 6, the signal D
10 WRITE A is at the low level and blocks AND 666, hence the signal BUS R~Q WRITE is at the low level. This signal is applied to a driver 340, hence the signal WR-ITE is at the high level~
The memory responds to MEM START and the high level signal WRITE by performing a read operation for the purpose of reading out the byte of data stored at the addres~
specified by the address pointer counter. After the data byte has been placed on the system data bus by the memory, the memory generates the low level signal MEM ACK-. In FIG.
2Q 8, ~ drives a 3-state drive 828 to produce the signal MEM ACK. MEM ACK is applied to ~lip-flop 842 and at the next ~lA the output of inverter 820 sets the flip-flop thexeby blocking NAND 844 and terminating the signals MEM OP
and ~U-S BUSY.
; Back at the time the bus manager generated the si~nal BUS GR~NT, this signal acted through the drivers ~30 to produce the high level signal BUS GRANTED and the low level signal BUS GRANTED. BU-S GRANTED resets the bus request flip-flop 660. The BUS GRANTED signal and the READ
30 signal have both enabled AND 826 throughout the memory :::

9~6 cycle. At the same time the signal MEM ACK is generated to set flip-flop 842, it passes through AND 826 and NOR 618 to generate LOAD DATA RE~. This clocks the byte of data that has been read out of the memory from the system data bus lnto the latches in data register multiplexers 300 and 301.
Since the signal DRIVE SDC BUS i~ at the high level through-out the data transfer operation, the byte of data immediately passes through the data register, through MUX's 302 and 303, and through gates 311 to the SDC bus.
In addition to generating the signal LOAD D~qrA
, AND 826 produces the signal LOAD ~EAD DATA that is applied through inverter 838 to set flip-flop 816 thereby indicating that the data register has been loaded.
The set output of flip-flop 816 produces the high level signal DR LD F~ which is applied to flip-flop 752 so that flip-flop 752 is set immedia~ely upon the setting of flip-flop 816. With flip-flop 752 set, the high level 5iqnal DISABLE BREQ enables AND 306 which in turn blocks NAND ~10 to insure a low level signal i~ applied to MUX's 20 302 and 303 to gate the contents of the data register through MUX~s 302 and 303 to the gates 311. The gates 311 are conditioned throughout the data transfer operation by the signal DRIVE DC BUS, hence the data ~rom the data regist~r is placed on the SDC data bus.
When flip-~lop 752 is set, the low level signal DISABLE HREQ bloc~s AND 662 and terminates the high level input to flip-flop 660.
On the first ~3A after the data register is loaded and flip-flop 752 is set, the output o~ ~lip-flop 752 s~ts 30 flip-flop 750. When ~lip-flop 750 is set its output drives g~

a driver 706 to place the low level signal ~ on ~he SDC
control bus. This signal tells the SDC that a byte of data is available on the SDC data bus and should now be strobed into the SDC buffer register. When the SDC accepts the byte of data the SDC then terminates the signal DREQ and the signal DREQ A drops to the low level. In ~IG. 7, DREQ A
resets flip-~lops 750 and 752. In FIG. 6, it blocks AND
662. This prevents generation o~ another BUS REQUEST until the SDC signals that it wants to make another request by 10 a~ain generating the signal ~
One memory cycle (940 n.s.) after it was initiated, the signal BUS ~ANT is terminated by the bus manager~ In FIC. 3, ~F a~ blocks the drivers and multiplexers through which the contents of the address pointer counter are applied to the system address bus. In FIG. 8, the signal BUS GRAN~ED
drops to the low level and the signal BUS G~ANTED rises to the high level when BUS GRANT is terminated~ BUS GRANTED
resets flip-flop 842 and as the flip-10p is reset the positive-going siynal END MEM OP ~F is applied to the low ~0 order counter 320 of the address pointer counter thus incrementing the address in the counter by one. The counter is now ready to address the next higher memory location when thc next data request is made by the SDC.
This completes the trans~er of one byte o~ data ~rom the memory to the SDC. As soon as the SDC is .ready for another byte o~ data, lt will again generate the data re~uest signal DREQ and another transfer operation like that just described will take place. Ater 132 trans~ers like the one just described, the register in the printer will be .: -30 loaded and, sensing this, the SDC terminates the low level -6~- :

:

signal SAC~ which has been transmltted back to the SDk~
throughout the data transfer operation. When SAC-K- is terminated, the low level signal D-S~CK generated by inver~er 730 is terminated and this terminates the signal NA~AIL
generated by NOR 544. This will enable NAND 542 so that interrupts may be recognized or input instruc~ions executed without setting the busy flip-flop 422. The SDC may now initiate an interrupt request to tell the CPU that it is ready for printing. ~fter the print cycle of the printer, 10 the SDC will again report its status to the CPU.
INPUT TRANSFERS. Data transfexs from an SDC to the memory are initiated in much the same way as output transfers.
Each time the SDC has placed a byte o~ data on the SDC data bus Eor transfer to the memory it drops tlle signal ~
to the low level causing inverter 800 to produce the high level output signal DREQ A. Referring to FIG. 12~, at the same -time that DREQ is generated for the first byte to be transferred, the SDC generates the low level signals D WRITE
and SDC BUSY. Both of these signals remain at the low level 20 throughout the data trans~er operation, hence D WRITE A
- produaed by inverter 808 and DC BUSY A produced ~y inverter 624 are both at the hiyh level. D SAC~ is at the high l~vel because the SDC was selected during the inpu-t instruction oE
the ~et up se~uencq.
When D~EQ A rises to the high level, it enables AND 804 which i3 further enabled by DR LD F~. At the same ~im~, D W~IT~ A enables one input of AND 812 which i~ further ; ~nabled because the DACK flip-flop 750 is reset~ The output of AND 812 conditions AND 804 so that it produces the high 30 level signal LOAD WRITE DATA and, through NOR 618, the low '~

,, , . ~ . . ~ . ~ . : .

level signal LO~ r~
The signal LOAD WRITE DATA enables flip-flop 816 and at the next ~lA the flip~flop is set. The signal ~
DA~A REG is applied to data register ~IUXIs 300 and 301 and, since the signal DRIVE SDC BUS is at the low level, the data on the SCD data bus is clocked into the data register through the A inputs. Since the signal STEP ON is at the high level NAND 310 produces an output signal to MUXIs 302 and 303 to select the A inputs hence the byte of data in the data 10 register is passed through MUX~s 302 and 303 to the 3-state drivers 314 When the flip-~lop 816 is set, the signal DR LD F~
is applied to AND 666 and since the signals D W~ITE A and END MEM OP FF are both at the high level, the AND procluces the signal BUS REQ WRITE which is applied to a driver 340.
The output of AND 666 also passes through NOR 664 and inverter 668 to condition the bus request flip-flop 660. At the next ~3A the ~lip-flop is set to produce the signal ~ hr.
The bus manacJer acknowledges the bus request by returning 20 the low level signal EITrr~ . In FIG. 3, sus GRANT strobes the address from the address pointer counter through MUXIs 332 and 334 and the 3-state drivers 342 and 344 onto t~le system address bu~ to address the memory. ~S GRAN~also enables decoder 346 to produce the low level siynal EN~B~GE
~r~ . This latter signal enables drivers 340 and is applied to NAND 844 to yenerate the high level signal MEM OP
and the low level signal BU~ B ~Y. MEM OP passes through a driver 340 to become the signal M~ A~T. M~M~ in combination with the low level signal WRT~F causes the 30 memory to go through a cycle during which it stores the data ':,'"" :', ~l08~9g~6 :
byte on the data bus at the address specified by the address being read out of the address pointer counter.
The BUS GRANT signal from the bus manager is applied to drivers 830 to generate the high level signal BUS
GRANTED and the low level signal BUS GRANrED. BUS GRANTED
is applied to flip-flop 660 to reset the flip-flop and terminate the bus request. BUS GRANTED is applied to AND
638 which is already enabled because the R~AD siynal is low so A~D 638 drives the signal ENABLE DATA DRV to ~he low 10 level. In FIG. 3r this latter signal enables drivers 314 to place the byte of data on the system data bus so that it is stored during the memory cycle.
Back at the time the flip-flop 816 was set to 9igni~y that the byte of data on the SDC data bus had been stored in the data register, an acknowledgement was sent back to the SDC so that it may prepare the next byte of data for transfer. When flip-flop 816 is set the signal DR LD FF
immediately sets flip-flop 752 and at the next following ~3A the output of flip-flop 752 set the data aclcnowledge 20 ~lip-~lop 750. The output of the DACK ~lip-flop passes through drivers 706 and over the SDC control bus as the signal DAC~ to inform the SDC it may place another ~yte of data on the S~C data bus. In response to ~ZR the SDC
terminates its DR~`Q and DREQ A resets flip-~lops 750 and 752. However, while flip-flop 750 is set I~R ~F is at the low level and, in FIG~ 8, blocks ANDIS 812 and 804 thereby terminating the LOAD WRITE DATA and ~OA~ gE~ signals.
After the memory has accepted the byte of data on the system data bus, it generates M~-ACK which passes 30 through driver 828 and conditions END MEM OP 842 so that the -67~

; . .

~g9~6 flip-flop is set on the next ~lA. This siynifies that the memory operation is completed. The output of the flip-flop blocks NAND 844 thereby terminating ~M oP and suS BUSY. At _.. .
the same time, END MEM oP FF resets flip-flop 816 through AND gl4. END MEM OP F~ increments the address in the address pointer counters 320-323 to obtain the memory address of the next byte to be transferred.
As soon as the SDC receives the signal DACK it terminates its data request to the SDMA and goes through the 10 operations necessary for it to place another byte of data on the SDC data bus. As soon as it has palced this next byte o~ data on the bus it again drops the signal DREQ to the low l~vel to initiate another cycle to transfer another byte of data to the memory. This sequence of operations continues until the SDC determines it has transferred all the bytes it has available for transfer. After the data transfer is completed the SDC may request an interrupt through the SD~A
to report its status to the CPU.
INTERRUPT SEQVENCE
2~ At the conclusion o~ a data transfer operation either to or from the memory, an SDC generates an interrupt request ~or the purpose of telling the SDMA that it is ~ree to ~o on to another operation~ and for the purpose of ln~orming th~ CPU of the status o~ the SDC. In addition, SDC~s may request interrupts at other times or the purpose o~ reportin~ various status conditions.
The SDC control bus has a lead extending through it from each SDC to an input of the priority encoder 526. ~
For purpQses of illustration assume that the SDC having the ;i ; ~`
device address 3 has just completed a data transfer operation , ~ ~
-6~-99~6 and desires to free its SDMA and report its status to the CPUO In FIG. 5, the SDC generates the low level signal INT~
REQ 3 which is encoded by the priori~y encoder 526 to produce ~wo high level signals that are applied to flip-flops 534 and 536. The priority encoder also produces an output signal ~hat passes through inverter 546 to enable NAND 542.
At the next following ~3A NAND 542 produces an output signal to set the interrupt sequence enable flip-flop 532. I~he output of this flip-flop clocks the value 11 into the address 10 latch flip-flops 534 and 536. The output o~ flip-flop 534 is the signal IDN 1 and it is applied to MUX 406 and MUX
332. The output of flip-flop 536 is the signal IDN 0 and it i5 applied to AND 462 and MUX 332~ When flip-flop 532 is set the low level signal INT SEQ EN FE is applied to MUX's 332 and 334 and selects the A inputs of thase MUX~s for connection to the system address bus when a BUS GR~NT
occurs. In FIG. 4, the high level signal INT SEQ EN FF
enables NAND 462 to pass the IDN 0 signal, enables the Bl input of MUX 406, and places a high level signal on the 20 select input of MUX 406~ This causes the addressing bits ; 00111 to be placed on the SDC address bus lines RSL -~-RSL ~.
At the same time, INT SEQ EN F~ passes through NAND 656 ancl NOR 65~ to generate PIN. ..
At the first ~2A ater the interrupt sequence enable ~lip-flop 532 is set, the signal INT SEQ EN FF
passes through MUX 524 and sets the ~lip-~lop 528. ~he ~et ~ondition of ~lip-~lop 528 and the reset condition of flip- ;
flop 530 is decoded by decoder 538 to produce the low level signal IST 1. At the same time, the decoder termi~ates 30 signal IST 0 and this blocks the enabling input of the -69- . .

9~6 priority encoder 526 so that no further interrupts may be recognized while the present interrupt is being processed.
In FIG~ 7, ~ST l passes through MOR 718 to enable flip-flop 720 and at ~3A the flip-flop is set to produce the signal ~AL~-. This signal is sent back to the SDC to inform it that an addrsss is on the SDC address bus and ready for the SDC
to sample it. This address is the address of the interrupting device and its purpose is to simulate a selection of the interrupting device in much the same manner as occurs duxing 10 the input instruction of a set up sequence. The only difference is that in this address RSL 2 indicates to ~he SDC that this ~`
is an interrupt sequence rather than a selection sequence.
After the SDC samples the address on the SDC
address bus it responds with a SACX signal. In FIG 4, ~AC~
is inverted at 724 to generate D SAC~ In FIG. 5, D SACK
passes through MUX 524 to reset flip-~lop 528 and set flip-flop 530. The outputs from the flip-flops cause decoder 538 to terminate the si~nal IST-r and initiate the low level signal ISl'-~ and the high level signal IST 2. In E'IG. 7, 20 when IST l is terminated the SALT flip-flop 720 is im~ediately reset by the output of NOR 718.
I~ 2 passes through NOR 738 and enables ~lip-~lip 740 so tbat the flip-flop is set at the next ~3A.
Flip-~lop 7~0 produces tlle ~ signal through driver 706 and this signal i9 sent back to the SDC to ask it to supply the interrupt status. When the SSC recognizes ~ it placos ~he in~-errupt status on the SDC data bus and responds with a ~AC~ signal.
In FIG. 6,FACK is inverted at 600 to become D FACK
30 which enables one input of AND 604. Since T3~-~ is at the :: .
~70~ ``
. ' .
,' .

1~8~

low Ievel the output of NOR 608 further conditions AND 604 and the output the AND passes through NOR 618 to generate LOAD DA~A REG. The signal DRIVE S--DC BUS is at the low level at this time hence the status byte is loaded into the da-ta register MUXIs 300 and 301. STEP ON is disabling NAND 310 so the contents of the data register are gated through MUXIs 302 and 303 to drivers 314.
D FAcK is also applied to AND 606 and in combination with IST 2 generates the signal INT REQ which is applied to 10 decoder 346 thereby selecting terminal 2 as the output terminal of the decoder. The IN~ REQ signal also enables ~lip-flop 658 and at the next ~3A the flip-flop is set to produce the signal INT REQ ~. This signal is passed through driver 828 and onto the system control bus as the signal ~EQ.
After some indeterminate time the CPU will determine that it can now process the interrupt and at this time the :.
CPU generates a BUS GRANT as fully explained in the above-mentioned copending application.
In ~IG. 3, BUS GRANT strobes onto the system address bus an address corresponding to the si~nal applied to the A inputs of MUXIs 332 and 334. In addition, ~-enables decoder 346 and it produces an output to ~nable driver~ 350 to place on the system data bus two bits o~ the three bit address identi~ying the SDMA. There is thus placed on the system address the address 10100011 where the two low order bits identifying the interrupting SDC and the three high order bits identifying its SDMA.
In ~IG. 8~ BUS GRANT passes through drivers 830 to 30 generate the high level signal BUS GR~NTED and the low level ;

: ' ~ . ' . ' ' signal BUS- GRANT-ED. In FIG. 6, BUS GRANTED enables AND 638 and since INT SEQ EN F~ is at the low level -the output of NOR 636 further enables AND 638 so that NOR 632 produces the low level signal ENABLE DATA DRV. In FIG. 3, this latter signal enables drivers 314 to place on the system data bus the output signals from MUXIs 302 and 303. Since tne output signal from I~ND 310 is low at -this time -this output corresponds to the content of the data register and is the status being reported by the interrupting SDC.
10In FIG. 5, BUS GRANTED is applied to MUXIs 522 and

5~4 and is clocked through the MUX~s at the next ~2A. The output of MUX 522 immediately resets the interrupt sequence enable flip-~lop 532 and the output of MIJX 524 advances the count in flip-flops 528 and 530 to a count of three.
~ ith both flip-flops 528 and 530 set, the outputs condition decoder 538 to terminate IST 2. The decoder produces an output at its number 3 output terminate but this ;
signal is not used.
When I5T 2 is terminated, the flip-flop 740 is 20 immecliately reset by the output o~ NOR 738 and the signal ~ALT is terminated. In response to this the SDC kerminakes the signal ~
Tha address placed on the system address bus and the status placed on the system data bus are entered into two hardware registers (not shown) in the bus manager 104.
The bus manager interrupts the CPU as explainecl in the aforementioned copending application. After the CPU processes the status, it may then initiate another operakion of the SDC by first generating an input instruction and then a 30 sequence of three output instructions. It will be understood : , . .

-72~
~.~.."... .

9~6 that -the final output instruction need not specify a data transfer operation as described above, but may designate a particular function of the devic~ connected to the addressed SDC, such as selecting print or punch, or designating a hopper, if the peripheral device attached to the SDC is a data recorder.
REPORTING STATUS DURING INPUT INSTRUCTION
The set-up sequence of one input and three output instructions described above assumed that the SDMA was not 10 busy and the SDC specified b~ the input instruction address did exist. If either o~ these conditions is not true, the status is reported to the CPU and the ou-tput ins~ructions may not follow.
I~ the 5DMA is busy at the time it recogni2es its address and generates sTARrr- PULSE~ then the input instruction sequence described above is modified. If the data regtster of the SDMA is loaded then the flip-flop 816 i5 set to indicate this fact and the signal DR LD FF will be at a low level to indicate that the SDMA is busy. In like manner, if 20 any SDC connected to the SDMA is producing a low level signal SACI~ indicating that it is communicating with the SDMA, the signal D SACK in FIG. 7 at the low level. Both D~ LD--FF and D~S~ are applied to NO~ 544 to g~n~xate the 5i~nal NAV~IL. NAVAI~ iq applied to NOR 438 which receives th~ low level signal INT S~Q EN FF. r~his latter signal is at tlle low level any time an interrupt sequence is being per~ormed by the SDMA. I~herefore, if the SDMA is busy NOR
438 pxoduces an output signal to enable the busy flip-flop , 422. When START--PULSE is generated to set the GO flip-flop, 30 it also passes through inverter 436 and sets busy ~lip-flop , .
, . . .

422 thereby enabling one input of NAND 442. The SELECTION
signal will be at a high level as previously described so NAND 442 produces an output signal that passes through NOR
448 to drive the signal STEP ON to the high level. In FIG.
; 5, STEP ON enables the A2 input of MUX 506 and the signal from the GO flip-flop passes through the D4 input of MUX 506 to the counter 510. This advances the counter to the count of one and decoder 514 produces SST 1. ~owever, the signal STEP ON is at the low level and blocks NAND 716 so that 10 SALT is not generated by flip-flop 720 during SST 1.
With counter 510 containing a count of one the STEP ON signal applied to the D5 input of MUX 506 passes through the MUX to the counter and at the next ~2A SST 1 is termlnated and SST 2 begins. Normally F~I.T would be generated during SST 2. However, this is not necessary since the SDC
is otherwise busy so the low level signal STEP ON bloc~s NAND 736 and prevents the setting of the ~unction alert flip-flop 740.
The combination o~ a count of two in counter 510 20 and the high level STEP ON signal selects the D6 input of MUX 506. In FIG. 3, the signal DISABLE DREQ is at the low level so inverter 308 produces the high level signal STEP
ENABLE that is applied through the D6 input of MUX 506 to the counter 510. ~t the next ~2A the counter is advanced to : ,.
a count of three thereby causing the decoder 51~ to ter-minate SST 2 and begin SST 3. In FIG~ ~, SST 3 resets the GO 1ip-1Op thereby terminating NOT READY. This enables the CPU to resume execution of the input instruction. The CPU then texminates the signal DATA BUS IN and the output of 30 NOR 504 rises to the high level. Th~ output of NOR 504 -7~--passes through MUX 506 to the counter 510 and at the next ~2A the counter is incremented again to return it to a count o~ zero. This terminates the SST 3 output from decoder 514.
The busy flip-flop 422 is reset when the signal INPUT
terminates thereby driving the signal I/O RD or WR to the low le~el.
The reset output of flip-flop 422 is connected to the D3 input of MUX 303 as previously explained in connection with FIG. 3 for the purpose of generating the busy status 10 value 80. All inputs to NAND 310 are at the low le~el so the output of the NAND selects the B inputs of MUX's 302 and 303 for application to the 3-state drivers 314. Durin~ SS~`
3 AND 630 is enabled so NOR 632 produces the low level ~iqnal ENABLE ~ATA D~ and this signal enables the drivers 314 to gate the busy status onto the data bus. From the data bus it is returned to the accumulator in the CPU.
After the status is analyzed by the CPU, it then determines what action to take.
If the addressed SDC is non-existent, the input ~0 instruction sequence also varies from the normal sequence.
In this case tlle sequence takes place in the normal manner until SST 1 when NAND 716 produces an output siynal to set flip-~lop 720 and generate 3~ he output o~ NAND 716 i9 the signal EN SALT X which is applied to the J lnput, and through inverter 460 to the K input of 1ip-flop 446. Now, iP th~ addressed SDC do~s exist, it normally xesponds to SAL'r with SACIC be~ore the next ~lA and SACK is inverted at 724 to become D SACK which is applied through NOR 444 to hold flip-flop 446 reset. If the addressed SDC is non-30 existent then it cannot generate SACK and there will be no ,,'; :

~ g94~

reset signal applied to the flip-flop ~46. In this case the flip-flop is set at the first ~lA following generation of . The output of flip-flop ~46 passes through NOR 448 to generate STEP ON. STEP ON immediately resets flip-flop 720 thereby terminating ~ , and further prevents the setting of flip-flop 740 which generates FALT.
STEP ON enables NAND 310 because SDMA PROBE is at the low level to enable a second input of NAND 310 and DISABLE BREQ is at the low level to block NAN~ 306. The 10 output of NAND 306 generates the high level signal ENABLE
STEP and NAND 310 applies a high level siynal to the select input of MU~Is 302 and 303 therehy selecting the B inputs.
All of these B inputs are tied to ~V except the B3 input of MUX 303 which is receiving the high level signal ~Y.
Therefore, all outputs from MUXIs 302 and 303 are at ~he - logic zero level and these outputs are applied to the drivers , 314.
In ~IG. 5, the STEP ON signal passes through the D5 input of MUX 506 and at the next ~2A advances counter 510 20 ~o a count of two. This terminates SST 1 and begins SST 2.
Nothing happens during SST 2 which is the time that the status would normally be loaded into the data regi9ter. Since the addressecl SDC is non-existent it cannot provide the signal D~ to enable AND 604 and load the data register.
With the count of two in counter 510 and the signal STEP ON at the high level the signal ENABLE STEP is gated through MUX 506 to the counter 510. At the next ~2A
the counter is advanced to a counter of three, decoder 514 30 terminates SST 2, and SST 3 begins.

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9~1l6 During SST 3 AND 630 is enabled and NOR 632 produces the low level signal ENABLE DATA-DRV which is applied to the enabling inputs of drivers 314 thereby gating the status byte oo onto the data bus. SST 3 resets the GO flip-flop and terminates the signal NOq~-READY thereby permitting the CPU to resume execution of the input instruc-tion. Subsequently, the signal DAT~ BUS IN terminates and a high level output from NOR 504 passes through MUX 506 to enable counter 510. At the next ~2A the counter advances to 10 the zero state thereby terminating SST 3 at the output of decoder 514. This concludes the generation of the status byte for a non-existent SDC. As before, the status byte is sent back to the CPU accumulator for analysis.
In summary, the present invention provides means whereby a plurality of SDCIs controlling peripheral devices having diverse characteristics may have direct access to a memory even though the controlling central processor unit has only two instructions ~or controlling the set up of data trans~ers between the memory and the SDC's. These two 20 instructions are INPUT and OUTPUT. The INPUT .instruction is utilized in the manner START I/O instructions of the prior art used to address an SDC and to obtain the status of the addressed SDC. The OUTPUT instruction is then utilized three times, ~wice to load an address pointer counter in a shared direct memory access controller, and once to send a command to the SDC that was addressed by the INPUT instruction.
The SDMA ser~ices a plurality of SDC's and includes no device dependent logic, i.e., no logic speci~ic to any one type of SDC or peripheral device controlled thereby. The 30 SDMA includes only circuitry which would otherwise have to ' :10~946 be duplicated in each of the SDC~s.
While a preferred embodiment of the invention has been described in speci~ic detail, it will be understood that various modifications and substitutions may be made without departing from the spirit and scope of the invention as defined ~y the appended claims.

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Claims (7)

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. A microprocessor system comprising:
a microprocessor having means therein for producing a first output signal representing an INPUT instruction and a second output signal representing an OUTPUT instruction;
a memory;
an addressable direct memory access controller;
a system bus connected to said microprocessor, said memory and said memory access controller;
a plurality of peripheral devices;
a plurality of subsystem device controllers each associated with and controlling one of said plurality of peripheral devices, said subsystem device controllers being connected to said direct memory access controller for the transfer of control signals and data bytes therebetween;
said subsystem device controllers each including a status register and means for returning the value in its status register to said addressable direct memory access controller;
said direct memory access controller including first means responsive to an INPUT instruction and an address on said system bus for selecting one of the subsystem device controllers and its associated peripheral device, and second means responsive to said status register value for inhibiting operation of said first means if the direct memory access controller or a subsystem device controller connected thereto is busy.

2. A microprocessor system as claimed in claim 1 wherein said address includes a first address portion representing the address of said direct memory access controller, and a second address portion representing the address of subsystem device controller to be selected, said direct memory access controller including means responsive to said first address portion for applying said second address portion to all said subsystem device controllers.

3. A microprocessor system as claimed in claim 1 and further comprising: a status receiving means; and, means in said direct memory access controller responsive to the selected subsystem device controller for placing the status of the selected peripheral device on said system bus for transfer to said status receiving means.

4. A microprocessor system as claimed in claim 3 and further comprising:
an addressable counter within said shared direct memory access controller;
means responsive to an OUTPUT instruction for loading a pointer address into said counter;
means connecting said counter to said system bus for addressing a memory location whereby data bytes in said memory may be transferred to the selected subsystem device controller on data bytes may be transferred from the selected subsystem device controller to said memory; and, means incrementing said counter after each data byte has been transferred.

5. A microprocessing system as claimed in claim 4 and further comprising:
means in said shared direct memory access controller responsive to a further OUTPUT instruction and a predetermined combination of bits on said system bus for transferring a control byte from said system bus to the selected subsystem device controller to thereby control the operation to be performed by said selected subsystem device controller and its associated peripheral device.

6. A shared direct memory access controller for use in a system having a system address bus and a system data bus connected to a processor means, a memory and a plurality of direct memory access controllers, each said direct memory access controller controlling a plurality of subsystem device controllers and comprising:
interrupt priority encoder means responsive to interrupt signals from subsystem device controllers connected to said shared direct memory access controller, said interrupt priority encoder means including means for producing a multibit value representing the address of the subsystem device controller granted priority to the direct memory access controller, register means receiving data from said subsystem device controller for applying said data to said system data bus;
means responsive to said interrupt priority encoder means for addressing the subsystem device controller granted priority to load the status of said subsystem device controller into said register means;
means for generating an interrupt request signal requesting access to said system address bus and system data bus in response to the loading of said register means;
means responsive to said interrupt request signal for generating the address of said shared direct memory access controller and transmitting it to said system address bus; and status receiving means for receiving said shared direct memory access controller address and said status of said subsystem device controller.

7. A shared direct memory access controller as claimed in claim 6 in combination with data processor means responsive to said interrupt request signal for generating a bus grant signal said shared direct memory access controller including means responsive to said bus signal for gating said subsystem device controller address and said shared direct memory access controller address onto said system address bus while gating the subsystem device controller status from said register means onto said system data bus.