CA1089570A - Data entry/data retrieval terminal - Google Patents

Abstract

DATA-ENTRY/DATA-RETRIEVAL TERMINAL

ABSTRACT OF THE DISCLOSURE
A data collection terminal for displaying data and for transmitting to and receiving data from a central station has a keyboard and facility for peripheral devices for entering data.
A numeric readout is provided and may be used if desired. Further, a grid of light emitting diodes (LED's) is provided. A remov-able mask may be placed over the LED's so that each LED corres-ponds to a specified field of terminal operation, depending upon the particular use to which the terminal is put. Function keys and a set of numeric keys are provided, the former for causing operations to be performed and the latter for entering numeric data.
The terminal is controlled by a microprocessor and associated circuits, particularly including a read-only memory (ROM) which is configured to control the microprocessor in a desired manner to provide the terminal with a specified con-figuration to perform a particular task or tasks. Tutorial circuitry is provided for optionally displaying sequential prompting steps on the numeric readout and/or the LED
grid to permit an operator of the terminal to follow the prompt-ing steps for proper entry of a desired transaction.
Circuit means are also provided for identifying data as to its peripheral device source or keyboard source as it is written into temporary storage in consecutive memory locations irrespective of the source, the data being reidentified as to its source when read out and transmitted to the central station.
The numeric readout in the preferred embodiment is a vacuum fluorescent display whose filament is activated by a DC
potential. To compensate for the progressive voltage drop along the DC filament, the characters are activated for varying lengths of time depending upon their position within the vacuum fluorescent display, providing apparent equal brightness to each character displayed.

Description

10~9'j7() BACKGROUND OF THE INVENTION
Field of the Invention:
This invention relates to a data-entry/data-retrieval terminal. More particularly, it relates to a data collection terminal primarily for on-line use with a central station, the terminal being controlled by a microprocessor and associated circuitry including a ROM permanently programmed to cause the , microprocessor to operate in a prescribed manner.
Description of the Prior Art:
In recent years, video terminals have become popular for ~;
communicating with a central computer. Originally, these were on-line devices in which the terminal communicates with a com-puter at a central station commonly through a telephone line.
Ordinarily data is entered through a keyboard and is visually s displayed to the operator and then transmitted to the central ; station computer.
In more recent times, it was felt that off-line terminals would make more effective use of both central station computer and communication link time. Such a terminal is described in ~, 20 U.S. Patent Nc. 3,760,375 issued September 18, 1973 to Irwin ~ et al. The terminal of that patent employs an audio type ,` magnetic tape cassette for the recording of digital data from the terminal keyboard. Data is collected on the cassette tape and at an opportune time is sent to the central station computer. The terminal is controlled by a microprocessor having a ROM that has been permanently programmed to cause the microprocessor to control the terminal in a desired manner.
Also, prior art terminals may provide a section in the RAM
for each peripheral device and for the keyboard. Any entry from the keyboard must be written into an address within a plurality of addresses earmarked for keyboard data. Likewise, data entered from a magnetic stripe card reader must occupy one location of many .;.................................................... .. ... . . .
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earmarked for the card reader. The same is true of any other peripheral devices. This arrangement is wasteful of memory space and the present terminal has a system of identifying all data as it is received and entering such data, irrespective of its source, in sequential order in the RAM. When it is read out, it is reidentified and appropriately grouped and trans-mitted to the central station. The RAM is therefore much more efficiently used, permitting more flexibility of use than in the past.

. . .
In accordance with an aspect of the invention there is provided an on-line data collection terminal for transmitting to and receiving data from a central station, in response to a polling signal from the central station, the terminal having keyboard entry means for providing data signals corresponding to each key when selected and storage means for temporary storage of received data and data to be transmitted, comprising:
display means for selectively displaying received data and data to be transmitted; read-only memory means, permanently pro-grammed with instructions for controlling the operation of thedata collection teminal; tutorial means, included in the read-only memory means, selectively actuated for optionally displaying sequential prompting steps on the display means to permit an operator of the terminal to follow the steps for proper entry of data; central control means, responsive to the instructions from the read-only memory means, for controlling the tutorial means, the keyboard data entry means, the display ~, means and the storage means; input/output port means for connecting peripheral equipment to the terminal for bilateral communication of data therebetween; storage buffer means, included in the read-only memory means, operatively connected , to the storage means and to the central control means, for `

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;denti~ying data ~ritten into the storage means with a unique tag designating the source peripheral equipment and the keyboard input means to permit full utilization of the storage means;
- and data identification means, included in the read-only memory means and in the central control means, operatively connected to the storage means, the central control means being controlled by the read-only memory means for identifying data read out of the storage means by reading each tag and sequentially trans-mitting data having identical tags to the central station in an ~ 10 order determined by the central control means.
v The terminal of this invention is an on-line type terminal s which communicates with a central station computer in conjunction with many more such terminals. The central station computer has an input/output channel arrangement for continually ; polling each of the terminals or an intermediate controller `. which itself polls the terminals. The sophistication of the microprocessor employed in the present terminal is of a degree of sophistication not heretofore available, permitting the '~ terminal to perform tasks which in the past had to be done at the central station. The combination of polling and task performance in situ permits the desirable on-line configuration without the undesirable inefficient use of central station computer and communication link time.
The terminal of this invention has a numeric readout and is also provided with a grid of LED's for identifying fields of a transaction. An inexperienced operator may wish to enter a transaction identified by a number, or by a function key, without knowing the proper sequence of entry of data. By entering the transaction number and requesting a tutorial sequence, a random access memory (RAM) is loaded with the instruction steps required to provide prompting steps to the operator. These instruction steps - 4a -;~

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may be permanently stored in a ROM controlling the micro-processor which in turn controls the terminal in a desired mode of operation, or the sequence of instructions may come from the central station. In either case, the instructions -read out sequentially from the loaded R~5 or the ROM cause either alpha-numeric prompting step or a lighted LED at an appropriate position to enable the operator to enter data corresponding to the prompting step. The prompting steps are continued until the transaction is completed, at which time ,': r~
.0 - the entered data is transmitted to the central station.
Also provided is a system of identifying the source of incoming data. That is, data from the keyboard is identified as ;~ coming from the keyboard and data from the peripheral devices is identified with the respective peripheral device. This identi-fication step takes place when the incoming data is written into s~ the RAM in sequential order irrespective of the source of the data.
Tne data is sequentially read out, effectively grouped by source and transmitted to the central station.
!O The numer;c readout device of this invention is a 1 `
vacuum fluorescentdisplay having a plurality of characters arrayed along a filament wire. A DC voltage is applied to the filament wire in such a manner that a high voltage is applied to the character closest to the source of potential ;~nd ~ a low voltage is applied, by reason of the voltage drop along I' the filament wire, to the character farthest from the DC source, with varying degrees of voltage at the c~aracters in ~ between these two extremes. If uncompensated, the first i~ character would appear bright with the last character appearing dim and intermediate characters progressively dimming from the DC source to the extreme end. This terminal ~as an arrangement ~5~

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~RIEF DESCRIPTION OF THE DRAWINGS:

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FIGURE 1 is a perspective view of the outside of the terminal of this invention.
FIGURE 2 is a block diagram of the component parts of the terminal.
10 - FIGURE 3 is a block diagram of the interconnection between the microprocessor, the ROM, the RAM, and the input/
output controller of th~ terminal.
FIGURE 4 is a block diagram illustrating the intercon- t nections of the address decode of FIG. 2.
FIGURE 5 is a schematic diagram of the system clock and a reset circuit associated therewith.
FIGURE 6 is a schematic diagram of the communication line interface. ~r' FIGURE 7 is a flow diagram illustrating the procedure ~ ;
for timing the numeric display characters.
FIGURE 8 is a flow diagram illustrating the identifying of data source. r~
DETAILED DESCRIPTION OF THE INVENTION:
- Referring first to FIGURE 1, the terminal 10 is shown having a housing 11 and a numeric readout 12. Of course, an alpha-numeric readout is a].so contemplated and is employed -n o~ner emDoalments o~ thiS invention. A keyboard 17 Aas function keys 13 and 15 and numeric keys 14. Function keys are designated for performing certain functions, depending upon the _ terminal configuration, such as "START", "BACK-SPACE", "FIELD" and "END". LED's 16 have a ~..

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removable mask 18 superimposed thereon, mask 18 containing words printed adjacent the LED's, identifying operational entry fields and data display fields, depending upon the terminal configuration. For example, if the terminal is configured as a Merchant Terminal, operational entry fields could be "ACCT. #', LICENSE ~", "AMOUNT" and "DATE OF BIRTH".
Data display fields could be identified as "DECLINED", "OVER
' FLOOR LIMIT" and "DATA SOURCE DOWN". Also, others of the LED's ;~ are used as status indicators and are accordingly identified 10 _ by the mask 18 as, for example, "ENTER", "WAIT", "RE-ENTER"
1~ and "OUT OF ORDER". These LED's are illuminated in accordance with predetermined conditions set up in the microprocessor 40 as controlled by the ROM 42, 44 of FIGURE 2. The field identi-fication LED's are lighted one at a time and may be used in a ~' tutorial data entry sequence.
The tutorial data entry sequence is used in a simple p collection of data for inclusion in the central station computer data base. If the operator is unfamiliar with the transaction, ~, he may request a tutorial sequence of field identification data.
This sequence contains a series of field identification bytes ~. ~
' (8 binary bits) that are used to illuminate the associated field identification light and to provide a length byte for each ~ field. Optionally, this sequence may display, on the numeric -~ readout, underscores for each digit position to be entered, there-by illustrating the length of the field to be entered. Also, tne ~' numeric readout may be replaced by an alpha-numeric readout which ~5~ may be used instead of the field identification lights to provide a visual sequence of instructions.
The operator simply enters a transaction number, or depresses a specified function key that calls for a transaction and the tutorial sequence. This transaction number is displayed on the numeric i~ readout, a function key (END) is depressed l~ causing the displayed transaction number to ~ :
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be stored in the RAM 45, 46 of FIG. 2. This causes the display to be cleared, the keyboard inhibited, the "ENTER" light to 7 go off, and the "WAIT" light to come on. The tutorial sequence g is then initiated at the terminal by the central station com-puter which provides a series of instructions entered into the RAM 45, 46, or by the ROM 42, 44 of FIG. 2. When the tutorial sequence has been initiated, the "ENTER" light will come on, the j-"WAIT" light will go off, the keyboard will become enabled, and the field identification light associated with the first _ 10 _ field;to be entered is illuminated. Also, an underscore may be illuminated for each digit position for the first field. The ~, s operator then enters the data called for by the first field and depresses the "FIELD" function key. This causes the data to be stored in the RAM 45, 46. The next field identification light comes on and the operation is continued until the last field of data has been entered. Upon depressing the "FIELD" key r-for the last field, the "ENTER" light goes off, the "WAIT" light comes on, the keyboard is inhibited and all stored data is transmitted to the central station computer.

If the operator is trained and familiar with a particular ;
transaction, he will not require the tutorial sequence but will achieve the same result by simply entering the transaction i, identification followed by activating the "FIELD"key, the first '~ field data, the "FIELD" key, the second field data, etc.
~ FIGURE 2 illustrates a microprocessor unit 40 which pro~
', vides the overall control for the terminal. Microprocessor 40 ; is a TMS 8080 manufactured by Texas Instruments Incorporated and described in tne publication "TMS 8080 Microprocessor", :, .
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,, , Second Editio~, the Engineering Staff of Texas Instruments Incorporated Semiconductor Group, Copyright 1975. Intimately associated with the microprocessor 40 is the I/O controller 48 which provides time intervals and input/output communication between many o the other devices shown and the microprocessor 40. I/O controller 48 is a T~S 5501 manufactured by Texas Instruments and described in the publication "TMS 5501 Multi- r function Input/Output Controller for a TMS 8080 System", by the Engineering Staff of Texas Instruments Incorporated, 10 - Semiconductor Group, Copyright 1975. The buffer 64 which ,;, receives an 8 bit word over 8 lines from I/O controller 48 is comprised of a single open collector output type inverter on each of the 8 lines. The inverters are identified as SI~7406, "Hax Inverter Buffers/Drivers with Open-Collector High-Voltage h Outputs" illustrated at pages 6-13 to 6-16 of "The Integrated , t , Circuit Catalog for Design Engineers", by the Engineering Staff "
of Texas Instruments Incorporated, Components Group, CC-401, 10072-41-US. The 8 outputs from the buffer 64 go to drivers 69a and 69b. Driver 69a is a display driver, type DM8897, manufactured by National Semiconductor Corporation of Santa Clara, California. Driver 69b consists of a pair of registers each identified as SN74174, manufactured by Texas Instruments Incorporated and described as "Hex/Quadruple D-Flip-Flops with Clear" on pages 363-366 of the "TTL Data Book for Design Engineers" by the Engineering Staff of Texas Instruments ~-Incorporated, Components Group, Copyright 1973. These devices consist of 6 flip-flops each, accommodating 12 LED's which are controlled by the outputs of the flip-flops. More or less LED's may, of course, be employed. The address decode 70, 71, in the preferred embodiment, receive six address bits from a total of ~-' '7 L.
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,, 10~'3~0 16 address bits. These six address bits are decoded to deter-mine which of the two ROM's and which of the two RAM's are to be selected. Also, information is provided for selection of numeric characters and the decoders are two type SN74LS138 and one SN74LS155, manufactured by Texas Instruments Incorporated and described as "Decoders/Demultiplexers" in "The TTL Data Book for Design Engineers" - Texas Instruments Incorporated, Copyright 1973 at pages 274-276 and 312-315 respectively.
FIGURE 4 illustrates the interconnection between these decoders. The highest order six bits of the 16 address bits are shown as A10, All, and A12 serving as inputs A, B and C to decoder 70a and inputs A, B, lC and ZC of decoder 71 and bits A13, A14 and A15 serving as inputs A, B, and C to decoder 70b. Input Gl of decoder 70a is provided by the signal DBIN t from microprocessor 40 and input G2A of decoder 70b and input ~
2G of decoder 71 is provided by signal WR from microprocessor 40. - ~ -These devices, as interconnected, provide outputs predictable ' ~ -upon the inputs received as specified in the descriptions listed above. R~.
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The particular interconnections shown provide for a selection of ROM' s 42 and 44, and RAM' s 45 and 46. It should be noted that at least two more ROM' s and one more RAM could be selected if so desired.
Outputs E15, E16 and E17 from decoder 71 serve as clock inputs to display driver 69b. Outputs E18 and El9 from ' decoder 70b serve, respectively, as the clear and clock inputs to synchronize counter 66.

Output 2 from decoder 7Ob serves as an input to NAND circuit 72a which, together with NAND gate 72b, is connected as a latch, , with NAND gate 72b having as an input output 3 from decoder 70b, NAND gate 72a providing output E14.
Output 4 from decoder 70b serves as an input to NAND gate 72c and output 5 from decoder 70b serves as an input to NAND gate 72d which is connected with NAND gate 72c to provide a latch circuit with RTS as an output. NAND gate 72e has one input grounded and is connected with NAND gate 72f to form a latch circuit. NAND gate 72f has as one input the RTS output from NAND gate 72c and provides an output RTS (Request to Send). The ~? 20 required connections of inputs provide outputs as described ~; in the above mentioned publication and need not be described herein.
, Referring again to FIGURE 2, auxiliary I/O port 76 pro-`;f~ vides access to two input and two output devices. Port 76 ~ is made up of two Intel Corporation 8212 "Eight Bit Input/Output ',f, Port", described at pages 8-75 through 8-78 of "Intel Data Catalog, 1976". Outputs D0 through D7 from microprocessor 40 interconnect with input pins Dll-D18 of one device and with ' output pins D01-D08of the other device. The remaining output '~ 30 pins on the one device and input pins on the other device are j}. ~

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attached to appropriate interfacing for communication with de-sired external devices (not shown).
Keyboard 17 is connected to decoder 67 as is driver 68.
The numeric display 12 is connected to driver 6~ and together with keyboard 17 is scanned periodically. United States Patent No. 3,892,957, entitled "Digit Mask Logic Combined with Sequentially Addressed Memory in Electronic Calculator Chip", assigned to the assignee of this application, teaches the scanning mechanism employed herein.
I . It should also be noted that the power supply employed in the present invention is essentially that of United States Patent No. 3,889,173, entitled "Switching Regulator Power Supply" assigned to the assignee of this invention. To obtain :
,~ an additional voltage level in the present invention, an ad- ;
y ditional secondary winding is used in the storage transformer.
B FIGURE ~ illustrates in more detail the connection between _ ;
microprocessor 40, input/output controller 48, ROM's 42 and 44 and RAM's 45 and 46. Microprocessor 40 has 16 address output ;
$~ lines 52. The lines that carry bits A0 through A9 of the -~' address word are coupled to the 10 address inputs of each of ROM's 42 and 44. The lines carrying bits A0 through A7 of the `~ address word are connected to the 8 address inputs of RAM's 45 s and 46, while bits A0 through A3 are connected to the address ~
' input pins of input/output port 48. The lines carrying bits ;
~ A10 through A15 are connected to address decode 70, 71, as shown -~ in FIG. 4. f i An 8 line data bus 50, 51 interconnects microprocessor 40 and input/output controller 48. The lines carrying bits D0 through D7 are connected to the output pins of ROM's 42 and 44.
~' The lines carrying data bits D0 through D3 are connected to the ~ . "'7", ,~' , ~'.'',' -12- ~ _ :~ ;-'' .,, , . ~ :

TI `1 iO~3-~ 70 appropriate input/output pins of RAM 45, while the lines carrying data bits D4 through D7 are connected to the appropriate input/
output pins of RAM 46. The lines carrying data bits D0 through D7 are also connected to I/O controller 48 as described above.
The clock inputs from clock 75 are provided on lines 54 and 56. ,-The sync output of microprocessor 40 is coupled by line 58 to the sync input of I/O controller 48. Interrupt signals from I/O controller 4S are coupled by line 60 to the interrupt input of microprocessor 40. The microprocessor DBIW signal is coupled i~
by line 62 to address decode 70, 71. The WR output from micro- ;
processor 40 is connected to the R/W inputs of RAM's 45 and 46.
ROM's 42 and 44 are Texas Instruments Incorporated type ~ 5.
TMS 4700 "1024-Word by 8-Bit Read-Only Memory" described at pages 107 through 110 of "The Semiconductor Memory Data Book for Design Engineers" by the Engineering Staff of Texas Instruments Incor-porated, Semiconductor Group, Copyright 1975. ROM's 42 and 44 are thus interconnected to provide 2048, 8-bit words of read-only storage. ROM's 42 and 44 have two select inputs OEl and OE2.
OEl is selected from the address decode 70, 71 as shown in FIG.
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4. Select input OE2 is kept enabled by connecting to ground. if,~

R~M's 45 and 46 are Texas Instruments Incorporated type TMS 4042 "256-Word by 4-Bit Static Random-Access Memory" des- ;

cribed at pages 61 through 64 of the aforesaid "Semiconductor , -Data Book for Design Engineers". Enable input CE to RAM's 45 ~, and 46 comes from the address decode 70, 71 as shown in FIG. 4.

FIG. 5 shows details of clock circuit 75 and reset circuit 'f 73.
.~ '~; ' The clock circuit includes a crystal oscillator made up ,f' of 12 MHz crystal 81, inverters 82 and 83, capacitor C10 and ~i ~'. ', .
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resistor R17. The output of the oscillator is applied through resistor R18 to the clock input of counter 89. ~ounter 89 is-a Texas Instruments Incorporated SN74161 "Synchronous Counter with Direct Clear" described at pages 9-41 through 9-48 of "The Integrated Circuits Catalog for Design Engineers" by the Engineering Staff of Texas Instruments Incorporated, Com-ponents Group, First Edition. The counter divides the frequency of the oscillator and a two phase clock is provided, with each phase having a two MHz frequency. TTL phase 1 is shown as an output of NAND gate 79 and TTL phase 2 is shown as an output of inverter 77. TTL to MOS conversion circuit 80 provides ~ -:1 ' .
MOS phases 1 and 2 as shown.
Reset circuit 73 is provided to initialize the circuits when power is first applied. A 20 to 40 millisecond pulse is developed out of NAND gate 85, which is applied to the circuits in a well known manner, to keep those circuits in desired states until the pulse ends. This provides time for the clock circuit to stabilize and for all of the circuits to be set in the desired initial states. Also, if power is momentarily lost, the -5 volts ~ -of the power supply is the first of the secondary voltages t affected. When that voltage drops, transistor Q4 is turned on, discharging capacitor C12 and thereby providing a reset pulse. ;~
FIGURE 6 illustrates details of line IF 65. This circuit si~ply connects the terminal to either a local line or to a MODEM. ;~
For example, if a MODEM is to be used to connect the terminal _ to a telephone line, then the ground connection of terminal 98 - is made so that one input to NAND gate 95 remains low at all r times, thereby effectively eliminating all of the local line ¦;
~ circuitry. Transmit line 32 from input/output controller 48 _ f ~ serves as one input to NAND gate 93, the other input being the RTS signal from NAND gate 72f. The RTS signal must therefore ¦~
~s~ equal 1 for transmission to occur. When the RTS signal is 14- s '"''- '.

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.s . . , ~, iv~t:j7o equal ~o 0, transistors Q2 and Q3 are cut off. When the RTS
signal is a 1, then transistors Q2 and Q3 are alternately on and off providing complementary data signals which provide the advantage of noise immunity for the two wire plus shield local line system.
When information is to be received on the local line, differential amplifier 90, across the local line, receives and amplifies signals from approxima-tely 50 millivolts to one half volt and drives transistor Ql.
-c~ As can be seen, when the MODEM is used, the transmit , line 32 and receive line 34 go directly to the transmit and receive pins of terminal 98.
s This circuit represents merely one of many circuits that $ could be used as an interface circuit for the inventive terminal of this application. Therefore, a detailed description of the operation of the circuit is not necessary.
MODE OF OPERATION
Referring to FIGURE 7, a flowchart is shown by which ~ characters of the number readout are displayed for s 20 varying times. When the numeric readout is to be activatec,, a numeric clock is cleared as shown at 101, the par-'t~ ticular digit to be displayed is determined by adding 1 to the s number of the digit previously displayed as shown at 102. The time that the particular digit is to be displayed is determined by dividing the digit position by 2, adding 10 and multiplying :f the result by 64 microseconds as shown at 103. At 104, the numeric clock is loaded with the time determined at 103, and at 105 the digit is determined to be more or less than 15 (since in the preferred embodiment there are 16 digits). If the alpha- ~ `
numeric readout is provided, then the embodiment may have 20 or more characters with the testing of the total number adjusted accordingly. If the digit is less than number 15, the numeric readout is loaded at 107 and the digit read from the key at 108 with an exit at 109. Reference should be again A ~ ~

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made to FIG. 4 where output E14 is shown and which turns on the numeric display and outputs E18 and El9 which clear and clock the synchronous counter 66 respectively in accordance with the time determined. If, at 105, the digit is in excess of 15, then the digit is set at -1 at 106 so that at 102 the first digit will be 0.
Referring to FIG. 8, a flow diagram illustrating the identification of the source of incoming data is shown. When an input command 111 is received in the instruction register of microprocessor 40, the keyboard at 112 is queried and if ready, the data incoming will be tagged with a 0 as shown at 113, such data necessarily being from the keyboard as shown at 114 with the f tag being multiplied by 64 and added to the data as shown at 122 so that any number between 0 and 63 comes from the keyboard.
The memory location is updated at 121 and the process is repeated.
If the next input comes from, for example, auxiliary device

2, then the tag will be 2 as indicated at block 119 and 120. The tag of 2 is multiplied by 64 at 122 and added to the data so that any number between 128 and 191 is necessarily from auxiliary device 2. This number is stored at the address next following s that at which the information from the keyboard was stored.
Likewise, information with a tag of 1 from auxiliary device 1 could next be recorded at the next successive address. When this information is read from the RAM, it is identified in order, starting with the information from the data keyboard. When a number occurs between 0 and 63, it is identified as coming from ;~
the keyboard and it is transmitted to the central station computer. This is determined by finding all of that data which '~-has a number larger than 63, but less than 128. Next, the 'r ~' ' ' ' ' .

lVb~9S~7() information having a tag of 2 is sent to the central station .x' computer. That information is identified by reason of the . number being between 128 and 191. The data is stripped out r by subtracting 64 when the tag equals 1 and 128 when the tag equals 2.
,, The detailed programming of both operations of FIG. 7 and FIG. 8 may be found in the following map of the contents of the ROM 42, 44.

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180 9301CDlC043E12CD8B0pllC0C0CDDC01 .. ~ lA0 01CD7E00CD0C033EFF32381079F6404F
'f lB0 CD6300FE04CAEDp0FE15CA2901FE18CA
lC0 D301FE05C2AC01311E10218607222610 ~: lD0 CDFD02CD0C03C30301CD2306D77EFEp3 ' lE0 C8A2ABC2DC017EE60FF630C9CDCC02CD
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330 6F7E111306835FlA3200DC32007C3200 350 lE043A01142E32040FDA5D03701DC257 360 0378FEllD8462E3170C936FFAF323210 3A0 CDA603C39903FE0CD2DEp32E393A3A10 i 3B0 B7CAB603BEC83A6610BECABE03345E16 `':.' '

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T I - 6 4 21 iV8!3~: i 7() The mode of operation with respect to the tutorial sequence has been described earlier. It is not necessary to describe the detailed operation of the microprocessor 40. With reference to . FIGURE 3, the operation is simply that of the microprocessor reading data from the ROM 42, 44 or the RAM 45, 46 into the instruction register and then performing the instruction. Data , from ROM 42, 44 and/or RAM 45, 46 may also be read into the microprocessor 40 for processing. Data may also be written into ~7~. the R~M 45, 46 by the microprocessor in accordance with a 10 - received instruction.
The input/output controller 48 is used generally as an interface between the microprocessor and all of the devices peripheral to the microprocessor except for the input/output port 76. As set out in the publication cited above, input/output controller 48 also provides time periods for various uses.
While particular types of components are listed in this disclosure, it should be noted that those skilled in the art may freely substitute other components such as a different s, microprocessor! different ROM's and RAMIs, etc. Such changes do ~ 20 not depart from the spirit and scope of this invention.
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Claims (4)

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. An on-line data collection terminal for trans-mitting to and receiving data from a central station, in response to a polling signal from the central station, the terminal having keyboard entry means for providing data signals corresponding to each key when selected and storage means for temporary storage of received data and data to be transmitted, comprising:
a. display means for selectively displaying received data and data to be transmitted;
b. read-only memory means, permanently programmed with instructions for controlling the operation of the data collection teminal;
c. tutorial means, included in the read-only memory means, selectively actuated for optionally displaying sequential prompting steps on the display means to permit an operator of the terminal to follow the steps for proper entry of data;
d. central control means, responsive to the instruc-tions from the read-only memory means, for controlling the tutorial means, the keyboard data entry means, the display means and the storage means;
e. input/output port means for connecting peripheral equipment to the terminal for bilateral communication of data therebetween;
f. storage buffer means, included in the read-only memory means, operatively connected to the storage means and to the central control means, for identifying data written into the storage means with a unique tag designating the source peripheral equipment and the keyboard input means to permit full utilization of the storage means; and g. data identification means, included in the read-only memory means and in the central control means, operatively connected to the storage means, the central control means being controlled by the read-only memory means for identifying data read out of the storage means by reading each tag and sequentially transmitting data having identical tags to the central station in an order determined by the central control means.

2. The terminal of claim 1 wherein the display means comprise a visual, alpha-numeric readout.

3. The terminal of claim 2 wherein the display means further comprise:
indicator lights; and a removable mask adapted to encompass and identify the indicator lights.

4. The terminal of claim 2 wherein the alpha-numeric readout is a vacuum fluorescent display having a plurality of characters.