CA1087695A - Multi-mode control logic circuit for solid state relays - Google Patents
Multi-mode control logic circuit for solid state relaysInfo
- Publication number
- CA1087695A CA1087695A CA278,530A CA278530A CA1087695A CA 1087695 A CA1087695 A CA 1087695A CA 278530 A CA278530 A CA 278530A CA 1087695 A CA1087695 A CA 1087695A
- Authority
- CA
- Canada
- Prior art keywords
- relay
- signal
- control logic
- logic circuit
- solid state
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
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Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/78—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used using opto-electronic devices, i.e. light-emitting and photoelectric devices electrically- or optically-coupled
- H03K17/795—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used using opto-electronic devices, i.e. light-emitting and photoelectric devices electrically- or optically-coupled controlling bipolar transistors
- H03K17/7955—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used using opto-electronic devices, i.e. light-emitting and photoelectric devices electrically- or optically-coupled controlling bipolar transistors using phototransistors
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/30—Modifications for providing a predetermined threshold before switching
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- Electronic Switches (AREA)
- Relay Circuits (AREA)
- Power Conversion In General (AREA)
Abstract
MULTI-MODE CONTROL LOGIC CIRCUIT
FOR SOLID STATE RELAYS
ABSTRACT OF THE DISCLOSURE
For providing an interface between a low level input control signal and a power switch, a control logic circuit is presented for permitting operation of a solid state relay in any one of a plurality of modes of operation including operation as either a normally open relay, a nor-mally closed relay, or a latching relay, and also to make possible combinations of such relays for operation in paral-lel with a second relay operating in or out of phase with a first relay. The control logic circuit includes logic gates with means for selective interconnection of external terminals to set the operation in the desired mode as well as to permit one relay to be responsive to the condition of another.
FOR SOLID STATE RELAYS
ABSTRACT OF THE DISCLOSURE
For providing an interface between a low level input control signal and a power switch, a control logic circuit is presented for permitting operation of a solid state relay in any one of a plurality of modes of operation including operation as either a normally open relay, a nor-mally closed relay, or a latching relay, and also to make possible combinations of such relays for operation in paral-lel with a second relay operating in or out of phase with a first relay. The control logic circuit includes logic gates with means for selective interconnection of external terminals to set the operation in the desired mode as well as to permit one relay to be responsive to the condition of another.
Description
~ACKGROUND OF T.h:F I~ NTION
This invention relatss ~o elsctron c circuitry for ; control of electrical power 2nd p~rticularly to digital logic circuitry for controlling the mode of c? r2~ion of a solid state relay.
In electrical power systsms there ~.-s been increaC-ing interest in the use of solid state relays for controlledenergization of a load from a power supply. ~or DC circuits, this usually takes the form of some kind of t.ansistorized ~ switching circuit such as is snown in Ea'~er ~_~ent 3,898,552, : issued August 5, 1975.
In various ap?lications, different modes of operation .
46,602 1()87695 are requlred from a solld state rel~y. Whlle the same basic power swltching clrcult may be employed generally in each of these modes of operation, they each require a dlfferent sort of control circuit in order to make the power switch operate in the requlred manner.
The ~unctions desired of a solld state relay are dlrectly analogous to the functions of electromechanlcal relays. The required functlons include those re~erred to as normally open (NO), normally closed (NC), and latched.
In normally open operation, the solid state relay (SSR) ls to be OFF or to present an open clrcult between the source and the load unless and until a control signal is applled to the power switch to close it and complete the circuit between the source and the load. In the normally open mode, the power switch will remain closed only so long as such a control signal is applied to it. In normally closed opera-tion, the converse is to occur with the switch ON and the load circuit closed except when a control signal of a certain type is present that causes and maintains interruption of the load circuit. In both the normally open and normally closed modes of operation, a change of state of the relay occurs only as a result of a change in the applied control signal. In the third mode o~ operation, the latched mode, lt is the case that the state of the relay can be changed by application of a control signal and will remain in the same changed state when the control signal is removed until a further control signal is applied to change the state again.
All of the types of operation referred to in the preceding paragraph reIate t~ relays that may be called 3~ single pole, single-throw (SPST) relays because the operation - ' - ~
, . , , ~ ~ .
lV8'~6~5 46,602 of the relay is to connect or disconnect between a slngle llne or power pole and a single load. There are, however, systems that require operation between a plurality of lines and a single load or a single line and a plurallty of loads wlth some interrelation of the individual relay functions such that one is to remain in or out of phase with the other.
For this purpose, it is necessary that the relays be adapted for associating different control circuits in master-slave relationship.
Because of the number and variety of functions desired of an SSR, it has been previously necessary to make and use dif~erent specific control circuits for different ones of the required SSR functions with the natural conse-quence of poor economics as compared with a single circult that could serve multiple purposes. -SUMMARY OF THE INVENTION
In accordance with the present invention, a multi-mode control logic circuit provides the interface between a low level input control signal and a power switch in a solid ~.
- 20 sbate relay. Any one of a plurality of modes of operation ~ :
is made possible with a single control circuit, including operation as either a normally open relay, a normally closed relay, or a latching relay. The same control circuit also makes ~ ~:
possible combinations of such relays for operation in parallel ~:
with a-second relay operating in or out of phase with a first relay. ..
The control logic circuit includes digital logic gates and associated components, preferably in a single package with certain internal interconnections within the package being fixed but also wi*h a plurality of external terminals .. . .
46,602 1087695i extending from the package. The external termlnals are dlstinctly identified and lnclude olle termlnal referred to as a "mode" terminal which is associated with the lnternal logic gates in such a manner that the external connection of the mode terminal to a llne terminal ti.e., on the supply - side of the power switch) provides a control circult for normally open relay operation. The mode terminal is, alter-natively, connectable to a power ground terminal in order to achleve normally closed operation. The mode terminal may also be left unconnected, in which casej a latching relay results.
The differences in operation result because the mode terminal has a fixed connection internally in the pack-age to one input of a logic gate which may be an "exclusive OR" gate whose output is a "1" when any one but not all its inputs has a "1" on it. The use o~ an "exclusive OR" gate gives the mode terminal the functions as ~ust described in the circuit to be specifically described as an example hereafter. Other logic gates may be used and may be associated with the rest of the control logic circuitry such that the mode terminal achieves other modes of operation than those referred to. The point is that circuits in accordance with the present invention take advantage of the fact that by having a logic gate with an externally available terminal (the mode terminal) one may achieve any of the different modes of relay operation by tying that terminal to a point which maintains a "l" on that input to the gate (e.g., by tying it to the supply or line), or to a point that maintains a "zero" te.g.~ power ground), or by leaving that terminal unconnected (not tied to "1" or "zero") but, internally, .
:, - ~
46,602 1(~8769S
that gate input sees a "1" or a "zero" accordlng to the state of other internal elements in the control logic clrcuit.
In addition to the mode terminal, circuits in accordance with this lnvention have separate "master" and "slave" terminals avallable for interconnecting between the two relay units to achieve the requlred two pole arrange-ments. The master terminal is one that bears an output "1"
or "zero" from an internal lo~ic gate. Thls output slgnal may be the same or different, by choice of design of the internal circuitry, than the output of the control logic circuit that goes to the power switch. The master output terminal, when used, is connected to the slave terminal, or slave input terminal, of another relay's control logic circuit. The second control logic circuit therefore has one of its logic gates with an input tied to an output of the first so they can be made to operate in or out of phase.
. .
Since the control logic circuits in accordance with this invention need include only a relatively small number of individual logic gates and their associated components,
This invention relatss ~o elsctron c circuitry for ; control of electrical power 2nd p~rticularly to digital logic circuitry for controlling the mode of c? r2~ion of a solid state relay.
In electrical power systsms there ~.-s been increaC-ing interest in the use of solid state relays for controlledenergization of a load from a power supply. ~or DC circuits, this usually takes the form of some kind of t.ansistorized ~ switching circuit such as is snown in Ea'~er ~_~ent 3,898,552, : issued August 5, 1975.
In various ap?lications, different modes of operation .
46,602 1()87695 are requlred from a solld state rel~y. Whlle the same basic power swltching clrcult may be employed generally in each of these modes of operation, they each require a dlfferent sort of control circuit in order to make the power switch operate in the requlred manner.
The ~unctions desired of a solld state relay are dlrectly analogous to the functions of electromechanlcal relays. The required functlons include those re~erred to as normally open (NO), normally closed (NC), and latched.
In normally open operation, the solid state relay (SSR) ls to be OFF or to present an open clrcult between the source and the load unless and until a control signal is applled to the power switch to close it and complete the circuit between the source and the load. In the normally open mode, the power switch will remain closed only so long as such a control signal is applied to it. In normally closed opera-tion, the converse is to occur with the switch ON and the load circuit closed except when a control signal of a certain type is present that causes and maintains interruption of the load circuit. In both the normally open and normally closed modes of operation, a change of state of the relay occurs only as a result of a change in the applied control signal. In the third mode o~ operation, the latched mode, lt is the case that the state of the relay can be changed by application of a control signal and will remain in the same changed state when the control signal is removed until a further control signal is applied to change the state again.
All of the types of operation referred to in the preceding paragraph reIate t~ relays that may be called 3~ single pole, single-throw (SPST) relays because the operation - ' - ~
, . , , ~ ~ .
lV8'~6~5 46,602 of the relay is to connect or disconnect between a slngle llne or power pole and a single load. There are, however, systems that require operation between a plurality of lines and a single load or a single line and a plurallty of loads wlth some interrelation of the individual relay functions such that one is to remain in or out of phase with the other.
For this purpose, it is necessary that the relays be adapted for associating different control circuits in master-slave relationship.
Because of the number and variety of functions desired of an SSR, it has been previously necessary to make and use dif~erent specific control circuits for different ones of the required SSR functions with the natural conse-quence of poor economics as compared with a single circult that could serve multiple purposes. -SUMMARY OF THE INVENTION
In accordance with the present invention, a multi-mode control logic circuit provides the interface between a low level input control signal and a power switch in a solid ~.
- 20 sbate relay. Any one of a plurality of modes of operation ~ :
is made possible with a single control circuit, including operation as either a normally open relay, a normally closed relay, or a latching relay. The same control circuit also makes ~ ~:
possible combinations of such relays for operation in parallel ~:
with a-second relay operating in or out of phase with a first relay. ..
The control logic circuit includes digital logic gates and associated components, preferably in a single package with certain internal interconnections within the package being fixed but also wi*h a plurality of external terminals .. . .
46,602 1087695i extending from the package. The external termlnals are dlstinctly identified and lnclude olle termlnal referred to as a "mode" terminal which is associated with the lnternal logic gates in such a manner that the external connection of the mode terminal to a llne terminal ti.e., on the supply - side of the power switch) provides a control circult for normally open relay operation. The mode terminal is, alter-natively, connectable to a power ground terminal in order to achleve normally closed operation. The mode terminal may also be left unconnected, in which casej a latching relay results.
The differences in operation result because the mode terminal has a fixed connection internally in the pack-age to one input of a logic gate which may be an "exclusive OR" gate whose output is a "1" when any one but not all its inputs has a "1" on it. The use o~ an "exclusive OR" gate gives the mode terminal the functions as ~ust described in the circuit to be specifically described as an example hereafter. Other logic gates may be used and may be associated with the rest of the control logic circuitry such that the mode terminal achieves other modes of operation than those referred to. The point is that circuits in accordance with the present invention take advantage of the fact that by having a logic gate with an externally available terminal (the mode terminal) one may achieve any of the different modes of relay operation by tying that terminal to a point which maintains a "l" on that input to the gate (e.g., by tying it to the supply or line), or to a point that maintains a "zero" te.g.~ power ground), or by leaving that terminal unconnected (not tied to "1" or "zero") but, internally, .
:, - ~
46,602 1(~8769S
that gate input sees a "1" or a "zero" accordlng to the state of other internal elements in the control logic clrcuit.
In addition to the mode terminal, circuits in accordance with this lnvention have separate "master" and "slave" terminals avallable for interconnecting between the two relay units to achieve the requlred two pole arrange-ments. The master terminal is one that bears an output "1"
or "zero" from an internal lo~ic gate. Thls output slgnal may be the same or different, by choice of design of the internal circuitry, than the output of the control logic circuit that goes to the power switch. The master output terminal, when used, is connected to the slave terminal, or slave input terminal, of another relay's control logic circuit. The second control logic circuit therefore has one of its logic gates with an input tied to an output of the first so they can be made to operate in or out of phase.
. .
Since the control logic circuits in accordance with this invention need include only a relatively small number of individual logic gates and their associated components,
2~ they may be readily miniaturized and included in a single package along with the rest of the relay components. All required functions are provided by use of eight external terminals: line, load, control input, control ground, mode, master output, slave input and power ground. Control logic circuits in accordance with this invention therefore provide much greater flexibility in use than if distinct control logic circuits were required for each individual mode of operation.
THE DRAWING
Figure 1 is a general schematic diagram of a solid - - - . .: . . :
: .
- . .. : : . : :-' : : ;' ~
1()~7~95 state relay in which the present invention may be incorporated;
Fig. 2 is a schematic diagram of a solid state relay including an embodiment of the present invention;
Figs. 3 to 6 found on the same sheet as Fig. 1 are - schematic diagrams of single unit relays in accordance with this invention;
Fig. 7 is a set of waveforms for understanding the operation of the relay in the mode of Fig. 6; and Figs. a to 11 are schematic diagrams of master-slave combinations of relays in accordance with the present invention.
PREFERRED EMBODIMENTS
Referring to Figure 1, there is shown a genera-lized circuit schematic of a solid state relay (SSR) con-nected between a Direct Voltage Source and a Load. The SSR
principally comprises a Power Switching Circuit that is directly connected between the Source and Load and has a control input from a Control Logic Circuit which in turn has an input from a Control Input Circuit.
The Control Input Circuit is one that is respon-sive to some system condition to produce a signal which may influence the operation of the relay. U.S. Patent No.
4,086,503 issued April 25, 197a to Fox et al and assigned to the present assignee, discloses a suitable Control Input Circuit. The Control Input Circuit preferably also includes means providing electrical isolation between the source of in-put signal and the Control Logic Circuit.
The Control Logic Circuit preferably incluùes at ' - . : -, . ~ . : . :
: -. ' ' : - . ' . . ~ . :
~7695 46,602 its input a threshold sensing circult portion for determining if the character (~or example, the n~agnltude and polarity) o~ the signal from the Control Input Circuit is of the type desired for the operation o~ the Control Logic Circuit. ~he Control Logic Circuit principally includes logie gates for ' - producing a signal applied to the Power Switching Circuit in accordance with a predetermined logic design.
The Power Switching Circuit may take various ~orms in accordance with known practice of which one preferred form is generally in accordance with Baker~Patent 3,898,552, issued August 5, 1975.
It is particularly to the Control Logic Circuit ` that the present invention is directed. Although of more `~ general utility, the invention will be principally described by an example of a circuit developed for use where high reliability (e.g., good noise immunity), low power dissipation, and suitability for miniturization are important, such as in aerospace applications.
Referring to Figure 2, a circuit schematic is shown of an example of an SSR including a Control Logic Circuit in accordance with one embodiment of the present invention. The input is developed by a control input circuit 10 that may, for example, include an optical lsolator Pl, but which could instead have a transistor,'op-amp, or a relay for the purpose.
Optical isolator Pl provides electrical isolation which is desirable.' The'Control and Control Ground terminals have no coupllng to the rest of the SSR except through Pl.
The Control terminal ln this example recei~es a signal from
THE DRAWING
Figure 1 is a general schematic diagram of a solid - - - . .: . . :
: .
- . .. : : . : :-' : : ;' ~
1()~7~95 state relay in which the present invention may be incorporated;
Fig. 2 is a schematic diagram of a solid state relay including an embodiment of the present invention;
Figs. 3 to 6 found on the same sheet as Fig. 1 are - schematic diagrams of single unit relays in accordance with this invention;
Fig. 7 is a set of waveforms for understanding the operation of the relay in the mode of Fig. 6; and Figs. a to 11 are schematic diagrams of master-slave combinations of relays in accordance with the present invention.
PREFERRED EMBODIMENTS
Referring to Figure 1, there is shown a genera-lized circuit schematic of a solid state relay (SSR) con-nected between a Direct Voltage Source and a Load. The SSR
principally comprises a Power Switching Circuit that is directly connected between the Source and Load and has a control input from a Control Logic Circuit which in turn has an input from a Control Input Circuit.
The Control Input Circuit is one that is respon-sive to some system condition to produce a signal which may influence the operation of the relay. U.S. Patent No.
4,086,503 issued April 25, 197a to Fox et al and assigned to the present assignee, discloses a suitable Control Input Circuit. The Control Input Circuit preferably also includes means providing electrical isolation between the source of in-put signal and the Control Logic Circuit.
The Control Logic Circuit preferably incluùes at ' - . : -, . ~ . : . :
: -. ' ' : - . ' . . ~ . :
~7695 46,602 its input a threshold sensing circult portion for determining if the character (~or example, the n~agnltude and polarity) o~ the signal from the Control Input Circuit is of the type desired for the operation o~ the Control Logic Circuit. ~he Control Logic Circuit principally includes logie gates for ' - producing a signal applied to the Power Switching Circuit in accordance with a predetermined logic design.
The Power Switching Circuit may take various ~orms in accordance with known practice of which one preferred form is generally in accordance with Baker~Patent 3,898,552, issued August 5, 1975.
It is particularly to the Control Logic Circuit ` that the present invention is directed. Although of more `~ general utility, the invention will be principally described by an example of a circuit developed for use where high reliability (e.g., good noise immunity), low power dissipation, and suitability for miniturization are important, such as in aerospace applications.
Referring to Figure 2, a circuit schematic is shown of an example of an SSR including a Control Logic Circuit in accordance with one embodiment of the present invention. The input is developed by a control input circuit 10 that may, for example, include an optical lsolator Pl, but which could instead have a transistor,'op-amp, or a relay for the purpose.
Optical isolator Pl provides electrical isolation which is desirable.' The'Control and Control Ground terminals have no coupllng to the rest of the SSR except through Pl.
The Control terminal ln this example recei~es a signal from
3~ elsewhere,'such''as the'trip eircuit of roferrcd to patent , lV876~5 46,602 3,697,~13 issued October 10~ 1972 to D. A. Fox, but that trip circuit could also be in the relay p~ckage as part of the con-trol input circuit; also see the referred to U.S.Patent ~,0~6,503.
When control current begins to flow through the llght emitting diode Dl of Pl, radiation turns on the photo transistor Ql of Pl. When the transistor portion of Pl begins to turn on, its collector voltage will drop to the threshold of ZlA which is an exclusive OR gate connected as a non-inverting (or buffer) amplifier.
The output of ZlA goes to "zero" when the control signal is applied (both inputs "zero") and now begins to charge capacitor Cl at a rate determined by the current source capability of ZlA and the size of capacitor Cl. This -controlled fall time provides the required control noise immunity for the circuit. Since ZlA acts as a controlled current source in both the high and low states, symmetrical nolse immunity is obtained.
; The voltage across Cl is sensed by ZlB, also an exclusive OR gate connected as a non-inverting amplifier.
ZlB, along with R3 and R4, forms a Schmitt trigger with positive snap action around the threshold voltage of ZlB.
This provides a clean logic signal for the remainder of the control circuit. ZlA has a pair of inputs o~ which one is connected to the regulated B+ supply through resistor Rl and to the collector of phototransistor Ql. The other input of ZlA
is connected to the power ground. ZlB also has an input connected to the power ground while its other input is connected through resistors R2 and R3 to the output of ZlA
and resistor R4 is connected in a circuit branch between that input and the output of ZlB. Capacitor Cl is connected " , , . . . - .. .. ~ . ..
1~8'76~S 46,602 from the B~ line to a point between resistors R2 and R3.
The element~ ZlA, ZlB, Rl, R2, R3, RL~ and Cl, connected a~
shown, may be referred to as the thr~shold sensing portion 12 of a control logic circuit 14 which also includes logic circuit portion 13 in which are located the principal elements of the inventlon.
The logic circuit portion 13 includes excluslve OR
logic gates ZlC and ZlD of whlch ZlC may be regarded as the "main" gate as it ls operatlve in all modes and comblnations.
It has an lnput 16 with a fixed connectlon, through R6, to the output of ZlB. The same input 16 ls connected to the 4g~ ~esis ~ ~7 slave input terminal of the relay~ The output of ZlC goes to the power switch as well as to one input of ZlD. ZlD is an "auxiliary" gate operative only when the illustrated relay is connected from the output of ZlD (the Master Output terminal) to another relay as will be described.
The main gate ZlC has a second input 18 that is permanently connected, through R8, to Z2 at terminal Q. Z2 is a D type flip-flop connected to toggle. The toggling action occurs when the clock input (C) of Z2 goes positive.
Input 18 of ZlC is also connected through R9 to the external mode terminal.
Before proceeding with the description of logic circuit 13, Power Switching Circuit 20 should be introduced primarily to show how the Line, Load, and Power Ground terminals come out of the relay. While a specific example of switch 20 is shown for ¢ompleteness, it is generally in accordance with the referred to Baker patent and will not be discussed in detail.
The SSR of ~ig. 2 wi11 now be recognized to lnclude _g_ :: :
.
. .
46,602 i~7~S
the bullding blocks of Flg. 1 and will also be seen to have elght external termlnals illustrated ln Fig. 3. Here the SSR ls contalned in a unitary packa~e with the eight ter minals identified on the package in some manner, such as:
L - Line; LD - Load MD - Mode; PG - Power Ground S - Slave Input M - Master Input CG - Control Ground C - Control Proceeding now to a description of operation o~
the loglc circuit portion 13:
With no connection to the Slave Input and wlth the Mode input tied to Line, as shown in Fig. 4, the output of ZlB goes through R6 to ZlC which, with a "one" on the Mode input, acts as an in~erter. The output of ZlC, in phase with the Control Input, then goes to "one" and turns on Q2 and Q3 which control the power stage 20. Thus the SSR acts as a Normally Open switch in the connection of Fig. 4.
Resistors R8 and R9 are sized such that inputs at the Mode input dominate over any signals from Z2.
If the Mode input is connected to Power Ground, as shown in Fig. 5, ZlC becomes non-inverting, and the switch becomes Normally Closed.
If the Mode terminal is left open, Fig. 6, the functlon of the circuit is best understood by reference to the waveforms of Fig. 7. Waveform A shows a possible shape of the input sign~l to ZlA~ ignoring noise~ and B is the ZlB output which follows the input to ZlA and i5 applied to the Z2 clock at terminal C o~ Z2.
With the Mode terminal open, the output of Z2 at terminal Q (wave C) is now effective. It and the output of - 1 0 - ~ ~
: :.. .: . . . . :
:
46,602 ~(~87~95 ZlB are connected to the inputs 16 and 18 Or excluslve OR
gate ZlC whose output is as shown at wave D. The swltch thus toggles on and o~ only at the falling edge of the ZlA
input signal ~hus providing Latched operation of the relay (wave E). The initial state of the switch is determined by the connection of CRl and R5 to the input terminal S of Z2.
Gate ZlD ls connected as an inverter to provide a Master output signal inverted with respect to the state of ZlC ("one" when ZlC is orf). The Slave input is designedJ
through R6 and R7, to override normal control input signals and to directly control the state of ZlC. With the Mode control connected to the Line input (~igs. 8 and 9), a Slave switch will'assume the same state as the Master it is connected to. With the Mode control connected to Power Ground (Figs.
10 and 11), a Slave switch will assume the opposite state as , the Master it is connected to. '~
Power for the control logic is derived ~rom the ''~
:
line input through R16 and regulated by CR3. ' The following table summarizes the operation of the SSR in the various connections aescribed:
Function Connect Mode Terminal To Single Unit or Master Normally Open Line Single Unit or Master Normally Closed Power Ground Single Unit or Master Latching (Not Connected) Slave Unit Non-Inverting Line Slave Unit Inverting Power Ground The following table identifies components~ merely by way of further example,'suitable'for use in the Control Logic clrcuit 14 of Fig. 2 and operable'to'mee't the following .
.
1()~7~9S
requirements:
Control voltage 16-32 v. DC
Control current less than 50 mA
Control isolation greater than 5000 Mohm Control Noise Immunity 1-5 m Sec.
Components:
Resistors Rl and R4 1 Megohm Resistors R2 and R5 20,000 ohms Resistors R3, R6 and R8 100,000 ohms 10 Resistors R7, R9 and R10 10,000 ohms - Capacitor Cl 0.1 microf.
Zener diode CRl 3.3 V.
Zener diode CR2 8.2 V.
Exclusive-OR gates Zl MC 14507 D Flip-Flop Z2 MC 14013 The circuit in accordance with this invention is particularly advantageous because all of the electrical components of the entire relay can be mounted on a single substrate in a single package. The general nature of the 20 components assembly and packaging may be in accordance with U.S. Patent 4,059,849 issued November 22, 1977 and assigned to the assignee of the present application.
The present invention has been developed with a particular intention to provide a small lightweight device that is suitable for aerospace applications or which may be subjected to severe environmental conditions. The invention is, of course, not so limited and where space and durability considerations are not so critical, it may take other forms while retaining the advantages of providing a single control ~ ... .
' . . ' . :: ' : ' - . . - : . . .
' ' ,........ ' : - ' . . . . .:
108~695 46~602 h;'~ loglc circuit~the capability through select~ble interconnecting external terminals to provide the various functions of the relay including normally open, normally closed and latched in single or two pole configurations.
The general principles of this invention are, for example, applicable to AC, as well as DC, power relays. An AC version would require merely an AC Power Swltching Circuit with a DC power supply for the Control Logic Circuit in accordance with this invention. The AC Power Switching Circuit may be selected from various known forms with the Control Logic Circuit supplying gating signals.
.
`'~ .' , . ' '"
... .
:, .
When control current begins to flow through the llght emitting diode Dl of Pl, radiation turns on the photo transistor Ql of Pl. When the transistor portion of Pl begins to turn on, its collector voltage will drop to the threshold of ZlA which is an exclusive OR gate connected as a non-inverting (or buffer) amplifier.
The output of ZlA goes to "zero" when the control signal is applied (both inputs "zero") and now begins to charge capacitor Cl at a rate determined by the current source capability of ZlA and the size of capacitor Cl. This -controlled fall time provides the required control noise immunity for the circuit. Since ZlA acts as a controlled current source in both the high and low states, symmetrical nolse immunity is obtained.
; The voltage across Cl is sensed by ZlB, also an exclusive OR gate connected as a non-inverting amplifier.
ZlB, along with R3 and R4, forms a Schmitt trigger with positive snap action around the threshold voltage of ZlB.
This provides a clean logic signal for the remainder of the control circuit. ZlA has a pair of inputs o~ which one is connected to the regulated B+ supply through resistor Rl and to the collector of phototransistor Ql. The other input of ZlA
is connected to the power ground. ZlB also has an input connected to the power ground while its other input is connected through resistors R2 and R3 to the output of ZlA
and resistor R4 is connected in a circuit branch between that input and the output of ZlB. Capacitor Cl is connected " , , . . . - .. .. ~ . ..
1~8'76~S 46,602 from the B~ line to a point between resistors R2 and R3.
The element~ ZlA, ZlB, Rl, R2, R3, RL~ and Cl, connected a~
shown, may be referred to as the thr~shold sensing portion 12 of a control logic circuit 14 which also includes logic circuit portion 13 in which are located the principal elements of the inventlon.
The logic circuit portion 13 includes excluslve OR
logic gates ZlC and ZlD of whlch ZlC may be regarded as the "main" gate as it ls operatlve in all modes and comblnations.
It has an lnput 16 with a fixed connectlon, through R6, to the output of ZlB. The same input 16 ls connected to the 4g~ ~esis ~ ~7 slave input terminal of the relay~ The output of ZlC goes to the power switch as well as to one input of ZlD. ZlD is an "auxiliary" gate operative only when the illustrated relay is connected from the output of ZlD (the Master Output terminal) to another relay as will be described.
The main gate ZlC has a second input 18 that is permanently connected, through R8, to Z2 at terminal Q. Z2 is a D type flip-flop connected to toggle. The toggling action occurs when the clock input (C) of Z2 goes positive.
Input 18 of ZlC is also connected through R9 to the external mode terminal.
Before proceeding with the description of logic circuit 13, Power Switching Circuit 20 should be introduced primarily to show how the Line, Load, and Power Ground terminals come out of the relay. While a specific example of switch 20 is shown for ¢ompleteness, it is generally in accordance with the referred to Baker patent and will not be discussed in detail.
The SSR of ~ig. 2 wi11 now be recognized to lnclude _g_ :: :
.
. .
46,602 i~7~S
the bullding blocks of Flg. 1 and will also be seen to have elght external termlnals illustrated ln Fig. 3. Here the SSR ls contalned in a unitary packa~e with the eight ter minals identified on the package in some manner, such as:
L - Line; LD - Load MD - Mode; PG - Power Ground S - Slave Input M - Master Input CG - Control Ground C - Control Proceeding now to a description of operation o~
the loglc circuit portion 13:
With no connection to the Slave Input and wlth the Mode input tied to Line, as shown in Fig. 4, the output of ZlB goes through R6 to ZlC which, with a "one" on the Mode input, acts as an in~erter. The output of ZlC, in phase with the Control Input, then goes to "one" and turns on Q2 and Q3 which control the power stage 20. Thus the SSR acts as a Normally Open switch in the connection of Fig. 4.
Resistors R8 and R9 are sized such that inputs at the Mode input dominate over any signals from Z2.
If the Mode input is connected to Power Ground, as shown in Fig. 5, ZlC becomes non-inverting, and the switch becomes Normally Closed.
If the Mode terminal is left open, Fig. 6, the functlon of the circuit is best understood by reference to the waveforms of Fig. 7. Waveform A shows a possible shape of the input sign~l to ZlA~ ignoring noise~ and B is the ZlB output which follows the input to ZlA and i5 applied to the Z2 clock at terminal C o~ Z2.
With the Mode terminal open, the output of Z2 at terminal Q (wave C) is now effective. It and the output of - 1 0 - ~ ~
: :.. .: . . . . :
:
46,602 ~(~87~95 ZlB are connected to the inputs 16 and 18 Or excluslve OR
gate ZlC whose output is as shown at wave D. The swltch thus toggles on and o~ only at the falling edge of the ZlA
input signal ~hus providing Latched operation of the relay (wave E). The initial state of the switch is determined by the connection of CRl and R5 to the input terminal S of Z2.
Gate ZlD ls connected as an inverter to provide a Master output signal inverted with respect to the state of ZlC ("one" when ZlC is orf). The Slave input is designedJ
through R6 and R7, to override normal control input signals and to directly control the state of ZlC. With the Mode control connected to the Line input (~igs. 8 and 9), a Slave switch will'assume the same state as the Master it is connected to. With the Mode control connected to Power Ground (Figs.
10 and 11), a Slave switch will assume the opposite state as , the Master it is connected to. '~
Power for the control logic is derived ~rom the ''~
:
line input through R16 and regulated by CR3. ' The following table summarizes the operation of the SSR in the various connections aescribed:
Function Connect Mode Terminal To Single Unit or Master Normally Open Line Single Unit or Master Normally Closed Power Ground Single Unit or Master Latching (Not Connected) Slave Unit Non-Inverting Line Slave Unit Inverting Power Ground The following table identifies components~ merely by way of further example,'suitable'for use in the Control Logic clrcuit 14 of Fig. 2 and operable'to'mee't the following .
.
1()~7~9S
requirements:
Control voltage 16-32 v. DC
Control current less than 50 mA
Control isolation greater than 5000 Mohm Control Noise Immunity 1-5 m Sec.
Components:
Resistors Rl and R4 1 Megohm Resistors R2 and R5 20,000 ohms Resistors R3, R6 and R8 100,000 ohms 10 Resistors R7, R9 and R10 10,000 ohms - Capacitor Cl 0.1 microf.
Zener diode CRl 3.3 V.
Zener diode CR2 8.2 V.
Exclusive-OR gates Zl MC 14507 D Flip-Flop Z2 MC 14013 The circuit in accordance with this invention is particularly advantageous because all of the electrical components of the entire relay can be mounted on a single substrate in a single package. The general nature of the 20 components assembly and packaging may be in accordance with U.S. Patent 4,059,849 issued November 22, 1977 and assigned to the assignee of the present application.
The present invention has been developed with a particular intention to provide a small lightweight device that is suitable for aerospace applications or which may be subjected to severe environmental conditions. The invention is, of course, not so limited and where space and durability considerations are not so critical, it may take other forms while retaining the advantages of providing a single control ~ ... .
' . . ' . :: ' : ' - . . - : . . .
' ' ,........ ' : - ' . . . . .:
108~695 46~602 h;'~ loglc circuit~the capability through select~ble interconnecting external terminals to provide the various functions of the relay including normally open, normally closed and latched in single or two pole configurations.
The general principles of this invention are, for example, applicable to AC, as well as DC, power relays. An AC version would require merely an AC Power Swltching Circuit with a DC power supply for the Control Logic Circuit in accordance with this invention. The AC Power Switching Circuit may be selected from various known forms with the Control Logic Circuit supplying gating signals.
.
`'~ .' , . ' '"
... .
:, .
Claims (8)
1. A control logic circuit capable of controlling the operation of a solid state relay in any one of a plurality of modes of operation, said circuit comprising:
threshold sensing means for responding to an input voltage signal of a given polarity and at least a given magnitude by producing a logic signal of a relatively fixed, predetermined magnitude that follows the input in polarity;
a logic gate having a first input terminal opera-tively connected to receive said logic signal from said threshold sensing means and a second input terminal, said second input terminal having a fixed interconnection to means for generating a first signal changing in logic state only upon a predetermined change in the waveform of said logic signal from said threshold sensing means, means for selectively overriding said first signal comprising a line connected to said second input terminal with an externally available MODE terminal on said line, said logic gate also having an output terminal providing an output signal for operation of a solid state relay;
said MODE terminal requiring no connection for an output signal from said logic gate to provide latching type operation of the relay.
threshold sensing means for responding to an input voltage signal of a given polarity and at least a given magnitude by producing a logic signal of a relatively fixed, predetermined magnitude that follows the input in polarity;
a logic gate having a first input terminal opera-tively connected to receive said logic signal from said threshold sensing means and a second input terminal, said second input terminal having a fixed interconnection to means for generating a first signal changing in logic state only upon a predetermined change in the waveform of said logic signal from said threshold sensing means, means for selectively overriding said first signal comprising a line connected to said second input terminal with an externally available MODE terminal on said line, said logic gate also having an output terminal providing an output signal for operation of a solid state relay;
said MODE terminal requiring no connection for an output signal from said logic gate to provide latching type operation of the relay.
2. A control logic circuit in accordance with claim 1 wherein: said logic gate has an output terminal that is connected to an input terminal of an auxiliary logic gate which has another input terminal for connection to a line potential point, said auxiliary logic gate having an output terminal for connection to a control logic circuit of a second solid state relay.
3. A control logic circuit in accordance with claim 1 wherein: said first input terminal of said logic gate also has connected thereto an external terminal for receiving a logic signal from a control logic circuit of a second solid state relay.
4. A solid state relay comprising a power switching circuit connectable between a line and a load and a control logic circuit in accordance with claim 1 whose output signal controls the operation of said power switching circuit.
5. A solid state relay in accordance with claim 4 wherein: said power switching circuit, said control logic circuit, and a control input circuit are contained within a unitary package having external terminals for connection respectively to line, load, power ground, control input and control ground points and a mode terminal for selective con-nection to determine the mode of relay operation.
6. A solid state relay in accordance with claim 5 wherein: said unitary package further has a master output terminal available for connection to supply a signal to a control logic circuit of a second solid state relay and a slave input terminal available for connection to receive a signal from a control logic circuit of a second solid state relay.
7. A control logic circuit as in claim 1 wherein:
said MODE terminal is connected to a system line potential point to override said first signal and to cause said logic gate output signal to produce normally open relay operation.
said MODE terminal is connected to a system line potential point to override said first signal and to cause said logic gate output signal to produce normally open relay operation.
8. A control logic circuit as in claim 1 wherein:
said MODE terminal is connected to a system power ground potential point to override said first signal and to cause said logic gate output signal to produce normally closed relay operation.
said MODE terminal is connected to a system power ground potential point to override said first signal and to cause said logic gate output signal to produce normally closed relay operation.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US69822776A | 1976-06-21 | 1976-06-21 | |
| US698,227 | 1976-06-21 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1087695A true CA1087695A (en) | 1980-10-14 |
Family
ID=24804403
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA278,530A Expired CA1087695A (en) | 1976-06-21 | 1977-05-16 | Multi-mode control logic circuit for solid state relays |
Country Status (7)
| Country | Link |
|---|---|
| JP (1) | JPS52156364A (en) |
| CA (1) | CA1087695A (en) |
| DE (1) | DE2727130A1 (en) |
| FR (1) | FR2393475A1 (en) |
| GB (1) | GB1561406A (en) |
| IT (1) | IT1080844B (en) |
| NL (1) | NL7705854A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11496132B2 (en) | 2019-03-25 | 2022-11-08 | Vishay Semiconductor Gmbh | Drive circuit |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4786826A (en) * | 1986-02-19 | 1988-11-22 | International Rectifier Corporation | Power interface circuit with control chip powered from power chip |
| JP2019092010A (en) | 2017-11-13 | 2019-06-13 | 株式会社東海理化電機製作所 | Signal processor |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB919231A (en) * | 1959-02-20 | 1963-02-20 | Havilland Engine Co Ltd | Multiple-engine aircraft power plant |
| GB1368604A (en) * | 1970-10-29 | 1974-10-02 | Westinghouse Brake & Signal | Static relaying circuit |
| US3697813A (en) * | 1971-03-15 | 1972-10-10 | Westinghouse Electric Corp | Tripping circuit for static switches |
| US3898552A (en) * | 1974-02-21 | 1975-08-05 | Westinghouse Electric Corp | DC Static switch circuit with improved transistor surge current pass capability |
| US3963947A (en) * | 1974-08-29 | 1976-06-15 | Westinghouse Electric Corporation | Digital time delay relay utilizing logic elements |
-
1977
- 1977-05-16 CA CA278,530A patent/CA1087695A/en not_active Expired
- 1977-05-17 FR FR7715120A patent/FR2393475A1/en active Granted
- 1977-05-27 NL NL7705854A patent/NL7705854A/en not_active Application Discontinuation
- 1977-06-14 GB GB2482077A patent/GB1561406A/en not_active Expired
- 1977-06-16 DE DE19772727130 patent/DE2727130A1/en active Granted
- 1977-06-20 IT IT4162577A patent/IT1080844B/en active
- 1977-06-21 JP JP7291777A patent/JPS52156364A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11496132B2 (en) | 2019-03-25 | 2022-11-08 | Vishay Semiconductor Gmbh | Drive circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| DE2727130C2 (en) | 1987-05-21 |
| GB1561406A (en) | 1980-02-20 |
| DE2727130A1 (en) | 1977-12-29 |
| IT1080844B (en) | 1985-05-16 |
| JPS52156364A (en) | 1977-12-26 |
| NL7705854A (en) | 1977-12-23 |
| JPS5747858B2 (en) | 1982-10-13 |
| FR2393475B1 (en) | 1982-10-29 |
| FR2393475A1 (en) | 1978-12-29 |
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| MKEX | Expiry |