CA1087317A - Process for receiving unique words - Google Patents

Abstract

ABSTRACT OF THE DISCLOSURE
A method for detecting a predetermined code word contained in received signals in a transmission system which operates with a four-phase type of modulation at the transmitter and coherent demodulation at the receiver, the code word being transmitted only as signals in two phases which are 180° apart and the received signals being divided into orthogonal voltage components during demodulation. The method comprises: forming a representation of the algebraic difference of the orthogonal voltage com-ponents of a received signal increment; determining which of the sum and difference has the larger absolute magnitude value; and evaluating a rec-eived signal increment in accordance with the algebraic sign of that one of the sum and difference which has such larger absolute value.

Description

~ 373~L7 This application is a division of our Canadian patent application Serial No. 249~784 filed April 7, 1976.
The present invention relates to data transmission procedures and particularly procedures involving four-phase modulation of digital signals.
In data transmission systems it is usually necessary to transmit, in addition to the useful information~ certain code words of fixed content and agreed-upon meaning, for example, to define those certain points in time which identify the beginning of a long sequence of signals or an address.
At the receiving end, these particular code words must be recog-nizable with the greatest possible certainty. This is made difficult due to noise which is superposed on the signals as well as superposed inter-ference signals, mainly when transmission takes place in multiple phase modulation. ~ith two-phase, or quadrature, modulation the identification of particular code words is more dependable.
In the system described by A. Ogawa and Mo Ohkawa under the title "A New Eight-Phase Modem System for TDMA" as contribution D4 to the confer-ence report of the Second International Conference on Digital Satellite Communication, Paris, France, November, 1972, these particular code words are transmitted in two-phase modulation. A special two-phase demodulator~
which has its input connected in parallel with the input of the multiple-phase demodulator, is provided to receive these particular code words.
While this arrangement seems to be unacceptably expensive, the fabrication expense for the transmitting end, however, is relatively low. One reason for this is that~ with a suitable selected code word, a multi-phase modulator will furnish two-phase signals.
Codeword receivers are customary and there are known embodiments - 1- .,,~

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This is called "soft" code word correlation in contrast to "hard" code word correlation in which all bit positions of the particular code word must be received correctly.
In order to solve a different problem, a "soft" evaluation of the individual binary signals has also been proposed in which the evaluator emits not only "0" and "L" (L representing binary one) signals or "~ and 141" signals~ respectively, but also intermediate value signals in a range around the zero point. Another term for this mode of operation is '!half-analog''0 It is an object of the present in~e~tion to make possible, in a simple manner, the determination from the four-phase signals of the code words contained therein, which are transmitted as two-phase signals.
These and other objects according to the invention are achieved by a method for detecting a predetermined code word contained in received signals in a transmission system which operates with a four-phasè type of modulation at the transmitter and coherent demodulation at the receiver and in which successive signal increments are transmitted and received during successive clock periods~ the code word being transmitted only as signals in two phases which are 180 apart and the received signals being divided into orthogonal voltage components during demodulation, which method com-prises: forming a representation of the algebraic sum and a representation of the algebraic difference of the orthogonal voltage components of a rec-eived signal increment; determining which of the sum and difference has the - _ 2 ~` 1087317 larger absolute ~agnitude value; and evaluating a recei~ed signal incre~ent in accordance with the algebraic sign of that one of the sum and diference which has such larger absolute value.
According to a further feature of the invention, the probability of dependable detection of the particular code words in the received signals can be increased e~en in the presence of a greater noise component.
With four-phase modulation, the bits at two bit positions of the binary sequence to be transmitted are combined into a dibit. Since there are four possible combinations, 00, OL, LO and LL of two successive bits, four dibits are possible which are distinguished during transmission by one of the four possible phase positions of a carrier. The individual phase positions have different phase angles which are each equal to an odd num-ber multiple of 45 with respect to the phase of a reference carrier. Usual-ly, the phase positions of the dibits of combinations OO and lL and of combinations OL and LO differ by an angle of 180, i.e. are in phase opposi-tion to one another.
It is assumed that the period of a bit of a particular code word is twice as long as the period of a bit of a useful information sequence.
For the four-phase ~odulator at the transmitting end, a period of twice the length is equivalentto two periods of the useful information or two half-periods with respect to the signal of the particular code word. When two half-periods of the code word in which the same binary value is present are combined into a dibit, only combinations OO and LL are possible and thus only two different dibits which furnish two-phase signals.
In the known four-phase demodulation processes, the values ob-tained to fix the phase position of the coordinates are initially scanned in ~- - - - : . , ::: . " ; . ~ ; , , .: : , 1~73~

succession by a sequence of clock pulses for each one of the four phase quadrants. Ittis easy to derive a clock sequence from the received signals with which, of the four quadrants, only two oppositely disposed quadrants will be scanned, but no process is known which forces this clock sequence into that one of the two possible phase positions in which the two-phase signals are being received.
With the above-described method according to the invention, the two-phase signals of the particular code word are derived from the coordinate values obtained by four-phase demodulation.
According to the invention, the coordinate values from one of two possible pairs of two oppositely disposed quadrants will furnish different, new, and greater values while the second pair furnishes values near zeroO
The decision will then be made in dependence on the polarity relationships of the coordinate values in which way the greater values are to be obtained or whether the greater value obtained in the one way or in the other way is to be processed further.
Figure 1 is a block diagram of a circuit which can be employed for practicing the present invention.
Figure 2 is a block circuit diagram of an embodiment of a device which can be used in the circuit of Figure 1 for carrying out the method according to the invention.
Figures 3, 4 and 5 are characteristic curves of different evalua-ting circuits which may be used in connection with the invention.
Figures 6~ 7 and 8 are exemplary block circuit diagrams of differ-ent correlating arrangements each of them suited to work with a distinct one of the different evaluators and applicable in connection with the ' ' ,, ' . " " ", ~ ' ' , ' " ~':

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Figure 1 shows the basic components of the receiving portion of a conventional four-phase system and additionallyJ in the dash-dot box ZPh, the location for the insertion of the components required to practice the inven-tion in order to obtain two-phase signals, and Figure 2 illustrates an exem-plary embodiment of a ciruit ZPh.
Four-phase modulated signals arriving via input E in the arrange-ment of Figure 1 are demodulated in demodulators Dl and D2, which are control-led, respectively, by the reference carrier frequency signal F and that sig-nal phase shifted by 90, and thus produce representations of the component values along the orthogonal coordinates x and y. The subsequently provided : -data receiver DE obtains from x and y values the original useful information emits it via output A and also furnishes a clock pulse T. Figure 1 further shows the known components including an evaluator B, scanning switch AS and correlator K.
The x and y components of the demodulated signals are also supplied ~ to a circuit ZPh operating according to the invention and one embodiment of whichis shown in Figure 2. In this arrangement the x and y values are mul-tiplied together in a first multiplier Ml, which, if x and y have the same sign, emits a positive output signal and if x and y have opposite signs it emits a negative output signal, A series connected lowpass filter TP design- :
ed to simultaneously act as an integrator which, if the sign relationships remain the same for a plurality of clock periods, furnishes, for example, a direct voltage signal to a sign, or polar~ty, indicating element, also known as a signum element, S which, when the signs are identical and thus the in-put voltage is positive, furnishes a "~1" signal to a polarized :: `: ., ' ,, , ' ' '` ` . ': : ' ' ':;: : , ` '; : . ' ' ' , , ' ' :' ., . ' , " ' . `

1 o~731`7 electronic switch PS and if the signs are opposite, and thus the input vol-tage is negative, it furnishes a "-1" signal to the electronic switch PS.
The arrangement of Figure 2 further includes a summing member ~ 1 and a difference circuit ~, whose inputs receive the x and y values and ~hose outputs provide x+y sum values or x-y difference values, respectively.
The polarity of the output signal of element S can determine whe-ther the values x and y are fed to the inputs of summing member ~1 or differ-ence circuit~ , or whether the summing member or the difference circuit are to be enabled, or whether the output of the summing member or that of the difference circuit is connected to the subsequent evaluation arrangement.
The output signals from element S control the polarized electronic s~itch PS for this purpose so that the arrangement will furnish the sum of the coordinate values if they both have the same sign and the difference of the coordinate values if the signs are opposite.
The arrangement shown in Figure 2 furnishes higher amplitude out-put signals if coordinate value x and y have the same sign only for phase signals in the first and third quadrants and if the coordinate values have opposite signs only for phase signals in the second and fourth quadrants.
Phase signals from other pairs of quadrants will not be considered.
The further processing of output signals provided by the arrange-ment of Figure 2 may be effected in different ways. In Figure 1~ this out-put signal is first fed to an evaluator B whose output signal is fed to cor-relator K via a scanning switch AS which is controlled by clock pulses T.
Determinative for the type of further processing is the type of evaluator employed. This may be a kn~wn signum, or sign identifying, ele-ment or, in modification of the above-described process for even more 73~7 dependably detecting a particular code word, it may operate in a half-analog manner. Half-analog operating evaluators are understood to include those which oper~te in an analog manner and linearly around the zero point and which are also known as limiters, and those which have a stepped charac-teristic around the zero point, which quantize small analog values and emit binary numbers to identify the respective quantizing stage and which are known as analog-digital converters.
Signum elements and limiters differ in their effect only by the slope of their characteristic around the zero point. This slope is essen-1~ tially infinite for the signum element as shown in the characteristic Figure 3 and generally finite for the limiter the characteristic of which is shown in Figure 4 (see DIN 40700, sheet 18, Nos. 23 and 24). In the borderline case of infinite slope, the limiter becomes a signum element.
As can be seen from the characteristic of Figure 3 a signum ele-ment will deliver a unitary output value As with any input value Es and distinguishes only the polarities, i.eO it operates purely digitally and gives a hard evaluation to the individual binary signals. The subsequent correlator must then also operate binarily. The correlator can~ however, also be designed to emit an output signal if it determines coincidence with the particular code word in the received signals at a given minimwm number of binary bit locationsO If this given minimum number is equal to the number of bits in the code word, it must be received correctly~
If the given minimum number is less than the number of bits of the code word, reception of the particular code word is assumed even if individual binary bits have been received in a mutilated fashion as a result of interferenceO This is the case of the above-mentioned soft code word : - , ~ . : .................. .. : :: . ~ . :-, .,, ~ . .. .

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correlation.
A simplified block diagra~ of a correlator K suited to work in connection with a signum element serving as an evaluator B is shown in Figure 6.
The simplification in the diagram as in the diagrams of Figures 7 and 8, too, is that only a three-bit particular code word is assumed, whilst in general the particular code word consists of 20 or more bits for example. The sampling switch AS shown in Figure 1 can be omitted, as its task in all the examples is fulfilled by the used clock controlled shift -register The linear output signals of the signum element are fed in the clock T controlled binary shift register SR. The known particular code word is stored in the code word store C~S, e.g. a read only memory. The contents of the individual stages with the same order number of the shift register and the code word store are compared by equivalence circuits EC, which deliver a binary output signal if the contents of the supervised stages have the same value. The output signals of all equivalence circuits are added by a summing element ~. If the sum exceeds a give value the sub-sequent threshold switch SS will deliver an output signal. The adjustable threshold is decisive for a hard or a soft correlation of the complete particular code word.
The half-analogously operating evaluators also permit soft e~al-uation of the individual binary signals.
A limiter ~ith a characteristic as per Figure 6 will deliver unitary output values Al if the input values Dl are equal or higher than a gi~en value, ~1 or -1 in the figure~ but proportional output values if the . , ~

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input values are below the given value. The limiter ~hich serves as evalua-tor B is advisably dimensioned or controlled so that it ~urnishes the values ~1 or -1, respectively, if signals are received uithout interference. It can also furnish values between -1 and +1 i~ the signals contain noise, The block diagram of a correlator which is suited to operate in connection with a limiter serving as an evaluator B, shown in Figure 7 is very similar to that of Figure 6. Instead of a binary shift register an analog shift register ASR is used, and the e~uivalence circuits are replaced by multipliers Ml. The values furnished by the limiter are written into the analog shift register in the correlator and each one of the values is mul-tiplied with the bipolar values of the particular code word store in the code word stock, again resulting in analog values between -1 and ~1.
If an analog-digital converter is used as the evaluator, a few quantizing stages are sufficient. An exemplary characteristic curve of such an evaluator is shown in Figure 5. It will furnish in parallel the indivi-dual values of two ~as shown~ or three positions of a binary number, which corresponds with a quantisized step of its input value.
A block diagram of an exemplary correlator suited to work in con-nection with an analog-digital converter as an evaluator is shown in Figure 8.
The correlator comprises a code word store CWS and a number of clock controlled binary shift registers SRlJ SRh equalling the number of out-puts of the analog-digital converter B. The signals of each individual out-put of the converter are written in a separate shift register. The values in the individual stages of the shift registers are then multiplied by mul-tipliers Ml ... M3 and M4 .., M6 with the bipolar values o the bit places _ 9 _ '.' ~ ` ''` ''' ':: ;`. ' ' '' '~ ' :'.` ' ' ' ' `' ' ' ; j ; ' . ' '` ` ' ' ,, ', `, ,' '',: , : ` .~ .: .'' ' ,, , '`, ' ' :
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1~373~7 with the same order number of the particular code word. Furthermore are provided as many multiplexers Mxl, Mxh as shift registers. During one clock period each multiplexer samples the output signals of all multiplers coor-dinated to one of the shift registers and delivers the sampled signals to one distinct input of a binary adder BA. The two or three different inputs correspond to different position values of a binary number. The multiplexers are controlled by a clock sequence with a clock frequency which is n times higher than that of the clock T, wherein n is equal to the number of bits in the particular code word. The summing capacity of the binary adder BA is also equal to n. Selected higher stages of the binary adder may be super-vised by a logic circuit, e.g. an AND-gate, which delivers an output signal if the adder has reached a given position. -In the given examples of correlator exceeding or not exceeding a given sum value may then be decisive for a sufficiently great probability of reception of a particular code word.
The signal emitted by correlator K when a particular code word is received, which can be considered with sufficient probability to be the cor-rect code word, is fed, for example, to data receiver DE as a start signal.
In summary and to provide a comparison with the prior art, it can be stated that the evaluation of the sum obtained by the above-described method by means of a signum element permits any desired hard or soft code word correlation. The half-analog evaluation of the sum with soft evalua-tion of the individual binary signals in conjunction with the desired hard or soft code ~ord correlation results in the highest degree of certainty for recognition of the particular code word in received signals containing greater noise components.

_ _ - 10 _ 1~1373~

It will be understood that the above description of the present invention is susceptible to various modifications, changes and adaptations and the same are intended to be comprehended within the meaning and range of equivalents of the appended claims.

Claims (6)

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:

1. A method for detecting a predetermined code word contained in received signals in a transmission system which operates with four-phase or four-phase difference modulation at the transmitter and coherent demodulation at the receiver and in which successive signal increments are transmitted and received during successive clock periods, the code word being transmitted only as signals in two phases which are 180° apart, and the received signals being divided into orthogonal voltage components during demodulation, said method comprising: forming a representation of the algebraic sum and a rep-resentation of the algebraic difference of the orthogonal voltage components of a received signal increment; determining which of the sum and difference has the larger absolute magnitude value; and evaluating a received signal increment in accordance with the algebraic sign of that one of the sum and difference which has such larger absolute value.

2. A method as defined in claim 1 wherein said step of evaluating com-prises providing a signal indicating the algebraic sign of that one of the sum and difference which has such larger absolute value by means of an eval-uator which operates in a binary manner, and correlating, in a correlator connected in series with the evaluator and operating in a binary manner, the algebraic sign indicating signal to furnish an output signal upon occurrence of coincidence of a given minimum number of signal increments with the predetermined code word.

3. A method as defined in claim 1 wherein said step of evaluating comprises providing a signal indicating the algebraic sign of that one of the sum and difference which has such larger absolute value by means of an eval-uator which operates in an analog manner over a selected range around the zero amplitude signal level, supplying the signals provided by the evaluator to individual stages of an analog shift register in a correlator connected in series with the evaluator, and effecting analog multiplication, in the cor-relator, of the stored signals with the individual binary values of the pre-determined code word.

4. A method as defined in claim 3 wherein said step of evaluating fur-ther comprises adding together the products of the multiplication performed in the correlator and emitting an output signal from the correlator when the adding step produces a given minimum value.

5. A method as defined in claim 1 wherein said step of evaluating comprises providing a signal indicating the algebraic sign of that one of the sum and difference which has such larger absolute value by means of an eval-uator which presents a stepped response in a selected range around the zero amplitude signal level and which quantizes the voltage applied to it to produce a binary value, supplying such binary values to a correlator connec-ted in series with the evaluator, and effecting multiplication, in the cor-relator, of the binary values with the individual binary values of the pre-determined code word.

6. A method as defined in claim 5 wherein said step of evaluating further comprises adding together the products of the multiplication perfor-med in the correlator and emitting an output signal from the correlator when the adding step produces a given minimum value.