CA1084630A - Stretch and stall clock - Google Patents

Abstract

ABSTRACT
A system clock mechanism which can be either stalled (i.e. held indefinitely in a high state) or stretched (i.e.
change the rate of pulse occurrence). A first electronic circuit provides pulses having a first predetermined pulse period T1 with each pulse being generated at a first pre-determined rate. A second electronic circuit cooperating with the first electronic circuit modifies the first elec-tronic pulses to generate pulses at a second predetermined rate having a second predetermined pulse period T2. A third electronic circuit cooperating with the first and second electronic circuits holds the clock circuit indefinitely in a high state.

Description

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BACKGRoUND OF THE INVENTION

Thi~ invention relates to computer timing circuits and -~
more particular to a method and apparatus having the capability of generating pul~eg at more than one rate (i.e. stretching the pul~e period of the computer clock system) or stalling the com- -:
puter clock sy~tem (i.e. holding the clock ~yst~m indefinitely in a high ~tate).
Description of the Prior Art For any computer manufacturing company to remain c~mpetitiYe it must provide features in its equipment reflecting user needs and requirements, and this equipment must be offered to the user- `~
at the lowest cost possible. Two prlmary demands compa~ible with the lowest C08t have ~urfaced in ~he marketplace. ~ne i8 to provide a greater "throughput capability"; while another i8 to provide broader capabllity for providing a broader 8pectrum of services to the u~er. These requirements translate into one broad general requirement --maximum data handling capabiliti0s with minlmum hardware requirements. Accordingly, the computer designer is aced with a problem of reducing the ultimate C08t of the computer system and increasing capabilitie~ of the computer ~ystem, These requirements act in oppo6ition to each other.
Generally, addltional features and capabilities require increased ~ardware which translates to increased cost; whereas reducing C08t8 translates into a reduced number of feature~ ~nd capabiliti~s by reducing hardware, Cne particular piece of hardware which is utillzed in all camputer systems and 18 addltionally utilized in different portions of computer systems i~ the clock system of a computer ~y~tem, Dlfferent portions of a computer sy~tem aperate at ~y~

, - - : . , , '''',", ' , ~ , , , ~ 3 different clock rates. For example, card readers and pri~tera operate at one inherent rate; disk drives and tape drives -operate at another rate; the main memory of a computer system - ;~
operates at still another rate; whereas the central proce~sing unit CPU operate~ at still another rate. A~ computer 8y6tem8 ~; become more complex and have multiprogramming, multiproces~ing and communication tasks, timing requirements al80 become further complex. Moreover, some computer systems operate in a synchronou~
~low manner; other computer systems operate in a synchronous fast manner; ~nd 6till others operate in an asynchronous manner. It becoGes obvious, therefore, that not only clocks with different clock rates may be required for any given computer system, but al80 clocks that can ~tart and stop themselves upon command. For example, a computer sy~tem comprising a ~PU and main memor~ re-quires that the CPU access main memory at a rate Rl which i~ the cycle time of the main memory. When a ~ape drive is added to the system, both the CPU and main memory may be required to c~mmunicate with the tape drive at a different rate R2 which i8 the rate of the tape drive. This would require a different clock ra~e.
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Moreover, if operation of the computer system is asynchronous (i.e. the performance of each operation star~s as a result of a ~ignal either when a previous operation has been completed, or when the parts of the computer ~ystem requ~red for the next operation are available), the CPU clock may be required to stop itself ~ 25 unt~ receives the signal that the information i~ available -I for it O~ cour~e, one way to handle this start-6top problem is to permit the clock to idle at its normal rate; however, when information i~ available at the middle of the idling cycle, it cannot be immediately receivecl in the middle of the cycle, but must await for the beginning of the cycle. Thi~ i~ inefficient :' ;:' ' , , ' , . ., ',.', " ' "' , and cau~es 108s of valuable computer time. Hence, lt is better to ~tall the clock and permit immediate restart whcn information is available.
One obviou~ Rolution to the problem of differen~ clock - -~;
rates i~ to provide a different clock for each different re- ~
quirement. However, as previously noted, ~his ls incompatible ~i, with the requirements of the marketplace and competition.
Another prior art solution iS to provide mean~ for 610wing down or speeding up a clock system. However, since computer .
clock sy~tems must al80 be extremely accurate and maintain their accuracy over long periods of time, this 601ution i8 not commercially practical except in s~me exceptional circumstanceE, because expensi~e precisely controlled oscillators-are required which do not lose their accuracy when ~heir speed i8 va~ied. ~.
This means that not only must the oscillator circuit be accurate but the control ~ircuit mu~t be very accurate; thus addi~g two i expen6ive components instead of one.
~ What iR required in the way of timing clrcuits, particularly ,~ .
for the cheaper, mini-computer sy~tems w~ich nonetheless are required to have many of the features of larger system~, i8 a computer ciock eystem whlch can automatically provide a ~eries , of pul~es which can be stretched upon reques~; moreover, the clock system should be capable of stalling itself to ~atisy the needs of some asynchronous operations, and restar~ing immediately upon request.
OBJF.CTS OF THE I~ NTION
,, , It i~ a primary object o~ the invention therefore to provide a means for ensuring maximum data handlin~ capabilities ; with minimum hardware requirements.
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It is another prlmary ob~ect of the invention to provide an improved computer clock system.
It is still a further object of the invention to provide a clock sy~tem that can be ~tretched (i.e. generate 5~ pulses at more than one rate).
It i8 yet another ob;ect of the invention to provide a clock system which can be stalled and can subsequently be started immediately upon request.
Still another object of the invention is to provide a computer clock 6ystem which is capable of providing a series .! of pulses each pulse having a first predetermined pulse period Tl, and upon request to provide at least one other series of ; pulses each pulse having a second predetermined pulse period T2; furthermore thi~ clock system is to further have the capability of being held indefinitely in a high state upon " command.
S~DMARY OF THE INVENTIO~I
., -1 In accordance with the above and other ob~ects of the in- ~
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vention, there is provided a system clock mechanism which can ~, 20 generate at lea~t two series of pulses with each pulse in a fir~t serie~ of pulses having a pulse period Tl, and with each pulse in a second serie~ of pulses having a pul~e period T2.
A first electronic circuit provides a first series of pulses ~-' each pulse having a time duration tl. A second electronic circuit cooperating ~Jith a irst electronic circuit modi~ies the rate o~ ~enerating pul~es so as to provide a second series of pulses; each pulse in the 3econd serie~ having a pulse pér~od T2 and a time duration t2. Moreover, a third electronic circuit cooperating ~7ith the first two electronic circuits provides ~or holding the computer clock system in a hi8h state indefinitelyj and re~tartin~ immediately upon request.

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;30 In accordance with the invention there is provided a stretch and stall clock circuit comprising: (a~ a first electronic circuit for delaying an electronic signal by a first pre-determined amount of time; (b) a second electronic ... .
circuit controllably coupled to said first electronic circuit for delaying the electronic signal by a second pre-determined amount of time; (c) a third electronic circuit coupled to said first electronic circuit for generating first alternating square wave signals having a pre-determined time period Tl; and (d~
a fourth electronic circuit coupled to said first, second, and third electronic circuits and responsive to a first request signal for increasing the time period Tl of the first alter-nating square wave signals by a pre-determined amount.
~ In accordance with another aspect of the invention ; there is provided the stretch and stall clock circuit compris-ing: (a) an AND gate; (b~ a first circuit coupled to said AND
~ gate and including a first NA~D gate responsive to a stretch j request signal for enabling said first NAND gate in a high electrical state when said stretch request signal is low; (c~
a second circuit coupled to said first circuit by delaying an electronic signal by a first pre-determined amount; (d~ a third circuit coupled to said second circuit for delaying the ~;' electronic ~ignal by a second pre-determined amount; ~e) a :1 , fourth circuit coupled to said second and third circuits and to ~aid AND gake and including a second NAND gate for elec-tronically coupliny and decoupling said third circuit to said .
~1 AND gate.

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BRIEF DESCRIPTION OF THE DRAWINGS
Figure lA is a schematic drawing of a prior art c~mputer clock system for generating clock pulses.
Figure lB is a timing diagram of the states of ~he prior computer clock system of Flgure lA at various position~ of the circuit.
Figure 2 is a logic block diagram of the invention.
Figures 3A and ~B are timing diagram~ of a feature of the invention providing modified pulses o~ longer pulse periods.
Figure 4 i8 a timing diagram of a feature of the lnvention w~ich holds the clocking system of Figure 2 in a high state .- .
;` for an inde~inite time period.
`; ~ 7~' ' General :. .
Referring to Figure lA there is shown the ba~ic prlo~
art technique of a computer clock system for generating computer ;, .
clock pulses. The basic clock ~ystem i6 very simple in that a delay line 101 is coupled in ~eries with a NA~D gate 102.
Although other co~,ponen~s ~uch as power supplies are required, they are no~ essential in describing the basic concept of pulse generation and accordingly are not shown. Referring to Figure lB
there is ~hown the timing diagrams at varlo~a positions in the schematic diagram of Flgure lA. Assuming that delay line 101 provides a 100 nanosecond delay, the pulse forms denoted ~ on Figure lB are generated at position ~ of Figure lA, Moreover, the pul~e forms denoted ~ and ~ esult at po~itions P and ., of ~igure 1~. A~suming that the system of Figure lA has ~u~t been initialized at time ~from a negative to a positive 8tate at position ~ and ~ This is accompli~hed manually from some con~ole (not shown) by cau6ing the INITIALIZ~ signal on one ., , . ,:
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input terminal of NAND gate 102 to go low from its normally high pos1tion. With one input low then the output goe~ high -~
and stays high 80 long as one input is low. To completely initlalize the sy~tem, the INITIALIZE 3ignal is maintained in a low state for at least 100 nanoseconds. Since at time ~ the system was initialized to a high state, posltions ~ and ~ will remain in the high state so long a~ the initialize signsl remains low. Similarly, position ~ will re.~.ain in the high state for - at least a lO0 nanosecond ~ime interval. When the initialize - 10 signal is released, it goes high and since the other input ~, terminal of N~ gate 102 is high, the output of NA~ID gate 102 will go low at positions ~ and ~ At a time interval ~1 s ~ 100 nanoseconds, the low state of position ~ ill emerge and 3witch position- ~ to a low state. This state will remain low for an .~ 15 additional 100 nanosecond~ because of delay line 101, and will in turn be inverted to a high state during these 100 nanoseconds by ~ D gate 102 whereupon at a time interval ~ ~ ~ ~ 100 nano- -seconds, the high signal o~ posi~ion ~ ill emerge from delay line 101 and change the ~tate of position ~ to a high state once ..
again; whereupon the cycle i8 repeated over and over again. If it is required to have a pulse having either ~horter or longer .. . .
duratlon, it i~ obvious to ~ub~titute a delay line which has either a shorter or longer duration than that of delay line 101.
This is generally done by adding additional circui.ts and cutting out the old circult and switchi.ng in a new circuit. Not only doe~ thls scheme re~uire additional control, bu~ it requires additional circuits. Moreover, if it is required to keep the same pul~e dur~tion but have it repeated at a ~lower or fAster rate, merely adding additional delay line~ to the device of Figure lA will not accomplish this result; nor will ~witching in different circuits with additional delay accomplish this re~ult~

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~etailed Description of the Invention Referring now to Figure 2 there is shown an AND gate 104 coupled to amplifier.105 which in turn is coupled to one ~-terminal of delay line l0l. Delay line I0l provides a l00 nanosecond delay for this specific ~mbodiment of the invention;
however, a delay line may be chosen which provides any pre- :
determined delay which the designer wishes for the basic time duration of the pulses. Another delay lin~ 102 ig coupled to a .:
. second terminal of delay line l0l. ~elay line 102 ha~ several . .
taps for providing ~arious amounts of delay. In this embodiment, ~: the tap at position denoted Q provide~ 60 nanosecond delay, ~ and this tape is coupled to one input terminal of NAND gate : 103, thu~ providing a signal CLl60+00 to one input terminal of NAND gate 103. A stretch signal CL0~OH i9 normally low and is applied to another input termina~ of ~AND gate 103. The output .
:~ : terminal of NAND gate 103 is coupled to one input terminal of ~: AND gate 104 and provides a signal CL0+0G to AND gate 104. On :~ a second input terminal of AND gate 104 a signal MSCL-00 is applied. The MSCL-00 signal is normally high, and is utilizad to initialize the computer clock system of Figure 2. When a user want~ to clear the clock of unwanted signals (l.e. initialize the clock. system), he manuslly depres~e~ a switch in the computer . ~ console or panel (~ot shown) which change~ the ~tate of tha ~: ~ M~CL-00 ~ignal rom high to lo~7. Thu~, AND gate 104 i8 dis-: 25 abled which in turn disables the basic omputer clock system and "flu~hes out" any prior sign~.ls. ~1ence, a new cycle can be c~mmence~ ~r~l this ~tar~ing point At a third input terminal o AND ga~e 104 a ~ignal CLO~OF i~ applied. As will be more fully described under ~he heading o Operation of the Inv~ntion, input ~i~nals CLo+n~ and MSCL-00 will normally be high under normul ,. . . .
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operating conditions of the clock s~stem, and AND gate ~04 will : be enabled and disabled in accordance with the signal CL0+0F
`~ to be described infra. At a point in the circuit between delay line 101 and delay line 102 the output terminal of delay line 101 is coupled to one input ~erminal of NAND gate 108. A signal CL100+00 delayed bv ~ 100 nano~econdR is applied to this input terminal. A second input terminal of NAND gate 108 i~ coupled to the output terminal of NA~ gate 106; and the third input terminal of NAND gate 108 is coupled to the output terminal of NAND ~ate 107. The output signal from NAND gate3 106 and 107 CL0+0C is applied to these second and third input terminals of NAND gate 108. Of coursej the output of NAND gate 108 as previously described provides a ~ignal CLOfOF and i5 coupled to .
an input terminal of AND gate 104. NAND gates 106 and 107 perform the same ba~ic function.-- that of stalling the cloek.
The reason more than one NAND gate is used i8 that the command .for a stall may come from a different unit; hence gtall signal ;~ CL0~OD on N~ID gate 106 may come from the main memory, whereas , 6tall ~ignal CL0~OE on NAND gate 107 may come from the tape 20 drive It fihould be Imderstood that as additional units are added to the system, additional NAND gates similar to 106 and 107 would be u~llized to receive the command for stalling the clock. An lnput ~ignal CL0~OD which represents the timing command for ~talllng clock 106 is applied to one terminal of NAND gates 106. On a second input terminal of NA~ID gate 106, A
slgnal CL0~OF i~ applied and represents the feedback signal : from the output of NAND gate 108. Similarly, a command signal CL0~0E which is normally high is applied to one termina~ o~ NAND
~ate 107, whereas the feedback ~i.gnal CL0~nF is applied to a second .
terminal of NAND gate 107 Referring again to AND gate 104, when _g_ lV~at;3(1 it iB enabled, the output signal is amplified in ~mplifier 105 and provides an amplified signal CL0~0B which i8 then ; applled to the input of delay line 101 Since AND gates, NAND gates, amplifiers and delay lines are well known to the prior art, the structure o~ the ~nvention has been adequately disclosed and accordingly the operation of the invention and its various features will now be de~cribed.
Operation of the Invention .
Referring now to Figure 2, the normal operation of the ;~ 10 invention will first be de~cribed. ~or this embodiment, pul~es having a positive state of 100 nanoseconds and a negative state of 100 nanose~onds or a pulse period T of 200 nanoseconds are generated. However, it should be u~derstood that by proper choice of delay line, pulses havi~g any other perlod t ~ 15 may also be generated.
Briefly, the stretch circui~ may be v;sualized a~ one AND
, ~1~ gate 104 with two ~A~ID gates 103 and 108 in parallel and with , . 1 , the output of each ~N~ gate applying input signals to AND gate 104. The third ~nput signal to ~ID gate 104 for purposes o~
~20 generatlng "the ~tre~ch pulses" can be disregarded as it is , . . .
alwaya high except during initialization. From a given cammon point then, input signals are directed to both NAND gates 103 and 108 The lnput signal to NA~D ~ate 103 is delayed by a total of 160 nanoseconds whereas the lnput signal to NAND gate 108 is delayed by only 100 nanoseconds. Under normal operation, the output o NA~D gate 103 is caused to be high, as will be more fully de~cribed infra; and thus the controlling gate i8 NAND
gate 108 which will generate alternate high and low pulses of 100 nanosecond~. By ~ome "s~retch demand signal", to be more ~ully de~cribed inr~, MA~D gate 103 is ~witched into the 8tretch ~: .

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circuit and becomes operative. Then in order to enable and disable AND gate 104 the cooperation of both output signal3 from ~AND gate 103 and 108 is required, since the output signal from NA~D gate 103 will not constantly remain high, Assuming that AND gate 103 is switched to the circuit by a "~tre~ch signal" just when the output of AND gate 104 has gone low. Under normal operation this output of AND gate 104 would turn high 100 nanoseconds later because the output of NAND gate 108 ~7Ould go high at that time. However, since NAND gate 103 i8 operative, it doe~n't go high ~or an additional 60 nanoseconds becau~e of the additional delay, an~ accordingly the output o AND gate 104 remain~ low for 160 nanosecond~.
However, with the output low, which is then fed again to each input of NA~ gates 103 and 108, NAND gate 103 i8 ~neffective as a cor.trol in that i~s output will remain high 60 long as its , input is low, and control rever~s to NAND gate 108. NA~D gate - 103 operates on 100 nanosecond delay since it is tied direc~ly to delay line 101 and will generate a 100 nanosecond positi~e signal which is applied to AN~ gate 104 thu~ generating a ~-~ 20 positive signal of 100 nanosecon~s. This process is r2peated over and over again alternately generating a low signal of 160 nanoseconds and a high signal o 100 nanoseconds. A more , detailed descrlption of the "stretch" operation together with `~ the timing diagrams i~ presented below.
As previously noted, input signal MSCL-00 applied to one i terminal of AND gate 104 is normally high. Also, in normal operation gince the "stretch signal" L0+0H is nonmally low, the output signal CL0~0G of N~ND gate 103 is normally high regardle~s o~ what the other input signa], CL160~00 to NAND
gate 103 i8. Accordingly, a s~econd high input slgnal CL0~OG
i8 applied to a ~econd input terminal of AND gate 104. With 1~ 0 both of these input signal~ high, AND gate 104 i~ enabled - and disabled by thé state of the third input signal CLO~OF
to AND gate 104. However, prior to the commencement of generation of clock signals, the clock circuit is initlalized by causing the state.o~ input ~ignal ~SCL-OO to go low. As was previously described, this is done by deT?ressing a switch in the console or panel (not shown). Thi.s di~ables AND gate 104t regardless of the state of the other input signals, and accordingly, "flushes out" previous signals in the clock circuit.
Thus, with thi~ as an initial condition, when the.manual switch on the console or panel is allowed to re~urn to its : normal state, two of the input signals CLO~O~J and ~SCL-OO will be normally high. The third signal CLO+OF will also be in the ~ high state because CL100~00 applied to NAN~ gate 108 i~ low . ~ . .
and hence the output 8 ignal CLO~OF is high. ~Ience, the output ~; ~ signal CI,O~OB of amplifier 105 will be applied to delay line 101 and will be high. ~ne hundred nanoseconds later, signal i ,:
CL100+00 which is in the high state will be applied to one i~ terminal of NAND gate 10~. Another input signal CLO~OC will be ~ 20 applied to ~he other input terminals of NAND gate 108 It should '~ ~ be no~ed that ~or thi~ embodiment, the CLO~OC input signal is 1 derived from two ~TA~D gates ln6 and 107 and is applied to two i , , separate input terminals of NAND gste 108. It could have been derived from any number of NA~ID gates. NAND gates 106 and 107 have flt lea~t 1 input signal CLO~OD or CLO~OE applied respectively to each of N~MD gate~ 106 and 107 and represent a request signal ~or ~talling the clock. It ~hould be understood that a reque6t ~ignal or stalling the clock may originate in the main memory, and may be received by NrAND gate 106; or, a reque~t for stalling the clock may ori~inate in the tape drive, and may be received , i,:, ., , ' ' ',' ., ' ' ' , , ~t~ 3~

by NAND gate 107. 5imilarly, requests from other units such as card readers, printers, etc. may be initiated and received by their own individual NAND gates similar to 106 or 107. With the request signals CL0+OD and CL0~0E normally low, at least - 5 one input terminal on each of NAND gate~ 106 and 107 is low, and accordingly the output terminals on these ga~es is high regard-; le6s of whether the other input signals on NANn gates 106 and 107 are low or high. Hence, the CL0~0C input signal on the two input termir.als of NAND gate 108 are high. However, as pre-viously noted, the CL100+00 ~ignal is high. Accordingly, the output signal CLOtOF of NAND gate 108 will be low. This signal i8 applied to the third input terminal of AND gate 104 thus dls-abling AND gate 104. The low outpu~ signal from AND g~te 104 i~
pas6ed through amplifier 105 and i6 then applied to delay line 101. This signal will remain low for 100 nanoseconds whereupon it will go high, because at that in~tant, input signal CL100~00 to NAND gate 108 will go low thus enabling NAND ga~e 108 and applying a high signal CL0~OF to AND gate 104. This cycle is repeated until either a "~tretch signal" CL0~OH is received at position 2 of the circuit, or else "stall signal" CL0~OD or CL0+OE i6 received at position ~ of the clock c~rcuit.
Referring now to Figure6 3A and 3B, the "stretch" operation of the invention will be described where a series of pU16e8 are ger.erated a~ shown on dia~ram ~ of Figure 3B. Figure 3A sh~ws ; 25 the timing diagrams for at least one cycle of normal operation as previously described supra before the stretch aignal CL0+OH
goes high. It ~hould be noted that the numbers in a circle on Figures 3A, 3~ and 4, identify the timing diagrams a~ various positions on Figure 2 which are also identified by the sEme number in a circle. Hence, it will be noted by inspecting Figure 3A

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that when the stretch signal CL0~OH at position W is 1~N
the invention operat~s in its normal mode a~ previously described and as shown on Figure 3A for at least one cycle.
Hence at point Q two 100 nanosecond pulses are shown one being high, the other one being low. Diagram ~ ~hows the pulses of diagram ~ delayed by 60 nanoseconds. Diagram shows that the output of NAND gate 103 remains high 60 long as diagram ~ representing the point at which the s~retch signal is applied is low. Diagram ~ when the "stall" signal i8 inoperative, i~ the inver~e of diagram ~ because of the ih-; version of the signal of NA~lD ga~e 108. Hence, as previously noted in the discussion supra, with signals CL0~0~ at point and initiate signal MSCL-00 high, AND gate 104 is enabled and disabled by the output ~ignal CL0+OF of NAND gate 108 which-is applied as an input signal to AND gate 104 at position ~ .
Hence, under normal opera~ion, the diagram ~ provides 100 nanosecond p.ulses in accordance with the oscillation of diagram Q
Now for ease of explanation, as~ume that a stretck signal CL~+OH is applied at pofiition ~ of Figure 2 a~ a point in t~me ;. denoted by AlAl on Figure 3A. Up to the time that this signal went high, the output signal of NAND gate 103 at position ~ was high No~, however, it will oscillate in accordance to input signal CL160~00 at position ~ , but in an inverse ~a~hion.
Signal CL160~00 at po~ition ~ will however Eollow signal at position ~ but delayed by ~ nanoseconds. Let us see therefore, what happens to ~ignal at position ~ hen the stretch signal goe~ high, it~ effect will no~ be immediatelv felt at position ~ . There it will be note~l that the state had changed rom 1~J to high and would continue to be hi.gh for at least 100 nano-; ~econds because a high signal was applied at the input to delay ; -14-. .

line 101, 100 nanoseconds earlier. After 100 nanosecond~
have elapsed, the signal at position ~ would go low. Mean-while the signal at position ~ would not go low for at leas~
60 nanoseconds later. When the signal at position ~ goes low, then the signal in position ~ goes high. When the signal at ~ goes high, the signal at position ~ ha~ been low for at least 60 nanoseconds. This high signal is applied as one input of AND gate 104 and is high. As previously noted, MSCL-00 applied to another terminal of ~D gate 104 is normally high.
Hence, ~wo input signals on AND gate 104 are high. Also, at this point it should be noted that the signal at position ~
is high, since it is the output of ~AND gate 108, and since the input CL100+00 at position Qof NAND gate lOB is low. Thus, ; with all inputs to AND gate 104 enabled, signal CLO+OB at the output of amplifier 105 at position ~ will go high. This high i signal i8 applied to the input of delay line 101 and emerges 100 nanoseconds later ~t posi.tion ~ . Accordingly, during this period, pos~tion ~ has been in a low state for 160 nanoseconds -- the 60 nanoseconds previously noted and the 100 nanoseconds that it took the high state to emerge at position ~ . This pattern will be repeated over and over again for the state o~ the sign2i at position Q As previously noted, the state of the signal at position ( 3 )will be similar to that of the ~ignal at po~ition ~ but delayed by 60 nanoseconds. The state of the signal at position ~ will be the inverse of the signal at position ~ , since with the "stretch signal" high on NAND gata 103 the output will ~ollow the other input signal but in an inverse fashion.
The signal at po~ition ~ will be the inverse of the sign~l at pogi~ion ~ ; since the 6ignal at position ~ i~ applied as one input to NAND gate 108 the output of NAND gate 108 at :, .~,~ ,.

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position ~ will be in the inverse of the input at position W when the other inputs are high. Hence by inspection of Figure 3B, the states of the signal at position ~ can be derived by observing the states of the signal at positions ~ and ~ since they are two of the three inputs on AND gate 104 and the third input is normally high. Hence these two inputs are controlling.
By inspecting Figure 3B it will be noted that when both diagrams and ~ are high, the state of the signal at position will be high, and conversely when the input positions ~ or 10 ~ are low, the output at position ~ will also be low. It will be seen therefore that at position ~ the signal remains in the high state for 100 nanoseconds and in the low state for 160 nanoseconds. This condition will be repeated over and over again until the "stretch signal" is removed hence the 100 nanosecond high signal has been stretched out by 160 nanoseconds.
Referring now to Figure 2, and the timing diagrams of Figure 4, the stall feature of the invention will be described by irst -~, describing the invention without the stall and creating a stall ~' condition, and then getting out of the stall condition. Diagram number 1 show~ four alternations up ~o dotted line D, Dl of normal ... .
operation of the clock wherein alternate high and low 100 nanosecond pulses are generated. Di~.gram 5 also shows Eour alternations of the state of this signal of the clock at position ~ It should be noted that the states of signal CLn~OF at position ~ are the 25 lnver8e of signal CL100~00 at po~ition ~ This is 90 becau8e NAND gate 108 inverts signal CL100~00. As previously described supra, durin~ normal operation of the clock when there i8 no stall request, all ~tall reques~ signals CI~OD and CL0+OE at po~ition ~ at one input te~ninal each of NAND gates 106 and 107 '~:
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respectlvely are low; accordingly, the output signals from ~AND gates 106 and 107 at position ~ are high and are applied as input signals to NAND gate 108, With these , ignals high, the output of NAND gate 108 alternates in ~; 5 accordance with the input signal CL100~00 but in inverse relation as previously described. On diagram ~ there is a ~` request to stall the clock when one of the request signals (it does not matter which) either CL0~OD or CD0+OE at ' position ~ goes high. An important property of this ~ 10 circuit is that there is no timing restriction on theoccurrence : of a stall request. This is due to the feedback, from gate -~ 108 to gates 106, 107 etc. Thus, if a request occurs while is low (at any instant during ~he low interval) the effect is delayed until ~ is high. Also, if a request occurs while ~ is high (at any,instant during the high ~ lnterval) it i8 soon enough since the resultant low,out ', of 106/107 simply reinforces the concurrent low frcm 101.
Assuming for the purposes of this discussion that the signal is received by NAND gate 106 and it is input'signal CL0+OD
that goes high. (It should be understood that it makes no difference to the end result i the stall signal on NAND
ga~e 107 were to become active), The other input signal CL0~OF at poRition O of NAND gate 106 is derived from the output of NAND gate 108 at position ~ which is fed back to the input of ~' 25 NAND gate 106. When the atall signal Cl,0~0D at position ~ goes , ' high the other input signal of NAND gate 106 CL0~OF at position '~, ~ is low ,as shown on diagram ~ of Figure 4, Hence the output ,, of NAND gate 106 at position ~ ~ remains low untiL the output of NAND gate 108 at position ~4~ goe6 high and i8 applied as an input to NAND ga~e 106. Whe ~hls happens, one alternation later, ' , ..... . .

'~V ~ 30 the output of NAND gate 106 at position ~ goe~ low and is applied as one input signal of NAND gate 108.
- With one input low on NAND gate 108, its output at position ~ goes high and is applied as a high input to NAND gate 106 at position ~ . With two high inputs on NAND gate 106, the output at position O of NAND
gate 106 is low and remains low, and is applied as an input signal CLO+OC to NANV gate 108 which holds the output signal of NAND gate 108 high indefinitely until ,-, the stall signal at pOSitiOII ~ of NAND gate 106 is ' removed. As previously described, in normal operation of the clock two input signals CLO~OG and MSCL-OO to AND
gate 104 are high; accordingly, when the output signal CLO+OF of N~JD gate 108 is applied as a high input signal.
to ~D gate 104, it goes high and remains high indefinitely until the stall signal is removed. Hence the output position of amplifier 105 at point ~ latches high and stays high until the stall signal is remo~ed. It can ~ , be readily appreciated that there is no timing restriction -~ 20 on the occurrence o~ a stall reques~. This is due to the ~i feedback from gate 108 ~o gates 106, 107, etc.
Some time period after the dottecl line Dl Dl on Figure 4 the stall signal CLO~OD at position ~ o~ NAND
gate,106 i.8 removed a.~ shown on diagram ~ of Figure 4.
Immediately the outpu~ of NAMD gate 106 at positlon ~ goes ' high as shown on dlagra ~ . Hence all input signals to NAND gate 108 are high an~l accorclingly the outpu~
si~,nal CLO~OF of N~D gate 10~ at, posi~ion ~ imme(liately goes low and is shown on liagramO This in turn will be applied, as an input signal t:o AND gate 104 at ~osltlon ~

.

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.
:',',', """ .' '', ' ,' ", : ' ' i,. . . . .. . . .. .
, . . . . . . .

and will cause the output of AND gate 104 and ampLifier 105 at position ~ to go low as shown on diagram ~ . This output signal CLO+OB at position ~ is then fed through delay line lOl and the normal cycle of the clock begins all S over again and the output of NAND gate 108 at position oscillates inversely to the output of delay line lOl at position ~ , which in turn causes the input signal CLO~OF
to AND gate 104 to alte~nate as shown by diagram ~ fter the stall signal has been released on NAND gate 106. Hence position ~ will oscillate alternately generating high and low lO0 nanosecond pulses as shown on Figure 5.

, . . .

:, ' . . , ,,~ . , i, ~. .
,:

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'' _Lg_ ~ ' .
., .,, " , " " ,, .
,. . , .i . .

Claims (9)

In the claims:

1. A stretch and stall clock circuit comprising:
(a) a first electronic circuit for delaying an electronic signal by a first pre-determined amount of time;
(b) a second electronic circuit controllably coupled to said first electronic circuit for delaying the electronic signal by a second pre-determined amount of time;
(c) a third electronic circuit coupled to said first electronic circuit for generating first alternating square wave signals having a pre-determined time period T1; and (d) a fourth electronic circuit coupled to said first, second, and third electronic circuits and responsive to a first request signal for increasing the time period T1 of the first alternating square wave signals by a pre-determined amount.

2. The stretch and stall clock as recited in Claim 1 including a fifth electronic circuit coupled to said third electronic circuit and responsive to a second request signal, said fifth electronic circuit for stalling said stretch and stall clock in the high state.

3. The stretch and stall clock as recited in Claim 2 wherein said fourth circuit includes a NAND gate responsive to the first request signal for electronically coupling said first electronic circuit to said second electronic circuit.

4. The stretch and stall clock as recited in Claim 3 including in said fifth electronic circuit a NAND gate responsive to the second request signal for disabling the generation of alternating square wave signals.

5. The stretch and stall clock circuit as recited in Claim 4 including in said fifth electronic circuit a second NAND
gate responsive to a third request signal for disabling the generation of the first alternating square wave.

6. The stretch and stall clock circuit comprising:
(a) an AND gate;
(b) a first circuit coupled to said AND gate and including a first NAND gate responsive to a stretch request signal for enabling said first NAND gate in a high electrical state when said stretch request signal is low;
(c) a second circuit coupled to said first circuit by delaying an electronic signal by a first pre-determined amount;
(d) a third circuit coupled to said second circuit for delaying the electronic signal by a second pre-determined amount;
(e) a fourth circuit coupled to said second and third circuits and to said AND gate and including a second NAND gate for electronically coupling and decoupling said third circuit to said AND gate.

7. A stretch and stall clock as recited in Claim 6 including at least one fifth circuit coupled to said fourth circuit and responsive to a stall signal for stalling said stretch and stall clock in a low electrical state.

8. A stretch and stall clock as recited in Claim 7 including in said at least one fifth circuit a NAND gate.

9. A stretch and stall clock circuit comprising:
(a) a first electronic circuit for delaying an electronic signal by a first pre-determined amount of time;
(b) a second electronic circuit controllably coupled to said first electronic circuit for delaying the electronic signal by a second pre-determined amount of time;
(c) a third electronic circuit coupled to said first electronic circuit for generating first alternating square wave signals having a pre-determined time period T1;
(d) a fourth electronic circuit coupled to said first, second, and third electronic circuits and responsive to a first request signal for increasing the time period T1 of the first alternating square wave signals by a pre-determined amount;
(e) a fifth electronic circuit coupled to said third electronic circuit and responsive to a second request signal, said fifth electronic circuit for stalling said stretch and stall clock in the low state; and, (f) sixth means in said fifth electronic circuit responsive to the second request signal for disabling the generation of alternating square wave signals.