CA1082823A - Time division system for synchronizing functions controlled by different clocks - Google Patents

Abstract

TIME DIVISION SYSTEM FOR SYNCHRONIZING
FUNCTIONS CONTROLLED BY DIFFERENT CLOCKS

ABSTRACT OF THE DISCLOSURE:
Synchronization control circuit for a time divisional data transmitting and receiving system. Data is received at an exchange at a clock rate determined by the transmitting station and is stored in memory at the incoming rate. The memory has cells for temporarily storing each bit of a coded combination, as received. Read-out of data from the memory is based on the internal clock rate of the exchange. Since only one operation - read or write - can occur on a memory at any one time ant the operations are controlled at rates which may be out of synchronism with one another, conflicts may occur. To prevent such conflicts, an exclusion circuit is provided to evaluate the interval separating reading and writing operations and to produce a time shift of predetermined duration between operations when the out-of-synchronism interval is less than a predetermined time interval.

Description

lOB2~23 Rasynchronizing ~rocess and deYice ___ ___ __ _ _ __ _ ____________ for frame-structured incoming information ___ _ _________ ____________________ Thc present invention has for object a process and means for re-synchronizing framc-structured incoming information. It is to be applied in the time-division switching systems of coded signals and, namely, in the telephone exchanges applying the time-division switching of pulse code modu-lation signals.
At the inputs of such an exchange, the signals originating from the lines in operation are sampled at 8 kHz, and each sample is translated by a coder into an eight binary signal combination. Each combination is transmit-ted in series along a conductor, within a very short time interval making up a time channel. It is thus possible to time-multiplex 32 channels, for instance.
Repetition period of the successive combinations of a channel is of 125 ~us;
consequent to which, the time slot alloted to each channel has a duration of about 3.9Jus. In the general case, an input primary multiplex group routes ; the signals originating from 30 lines occupying 30 time channels, two time channels being used for the signalling and the synchronization. A similar out-put primary multiplex group routes the signals intended for these same 30 lines.
Inside the exchange, there will generally be numerous input and output multiplex groups. It is necessary that a coded combination originating along a time channel of a multiplex group might be transmitted along a time -. i channel of a whatever multiplex group. This implies space switching operations for the group-to-group connections, and, time switching operations for the channel-to-channel connections. They will be performed with the help of a network which will include switching units and memories, this network can be of a well-known type so called time - space - time.
In a multiple exchange network, each exchange will be connected to a neighbouring exchange by multiplex groups of the type described above.
At the output of an exchànge, the output multiplex group is accomplished by a local clock whi~ch delimits the frames, the time slots, as well as the eight ,`~ - 1 -, bit intervals or moments of each time slot.
At the input, in the exchange considered here, it is not possible to use thc local clock for operating the signals from the input multiplex group, sincc it is not necessarily in frequency synchronism nor -and above all -in phase synchronism with the clock of the distant exchange such as it would appear through the middle of transmission. It is therefore necessary to reconstitute the distant clock for detecting and identifying the received ~, signals.
Due to frequency differences between the distant clock and the local clock, and/or due to propagation time variations along the transmission channel, the position of the regenerated binary signals is a whatever one with respect to the local clock. I~hen the digital flow from the input multiplex is more important than the local digital flow determined by the local clock, it is received more bits than the bits the exchange is able to process. In the other case where the digital flow from the input multiplex is smaller than ;, . , the local digital flow, a number of bits is received smaller than the number of bits that the exchange requires.
-~ I The previously above mentioned switching operation should prefer-ably bear upon synchronous multiplex groups for obvious simpliflcation reasons.
Well now, it already was seen, the input groups originating from distant ex-changes are associated wlth a reconstituted clock whose frequency and phase are different from those of the local clock and different one another. It is ~t.. , therefore advisable to proceed with a resynchroni7ation which will result into a time shift of the signals and, according to the direction of the frequency shift, into periodical doubling or suppression of incoming signals.
That problem lS well known. The solution consists in storing the input combinations into a memory at the rate of the distant clock, a memory location being assigned to each channel, and then to read therein the combinations at the rate of the local clock. But that sets a problem in case ; 30 it is required to use a memory having simple storing and reading control cir-`` - 2 -. ~ . .... .. ... .
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1~)82823 cuits, bccause it will periodically happen that a storing operation might be requircd at thc same time as a reading operation whereas the memory can only accomplish onc of these two operations at a time.
This problem has alroady rcceived various solutions implying, most often, the use of two memories and requiring complex and costly logic control circuits.
The present invention provides a solution to this problem both sure and simple, enabling the full resynchronisation with the help of only one memory.
The invention has for object therefore a process of resynchroni-sation of incoming frame-structured information, repetitive of time intervals, constituting time channels and conveying each a coded combination so as to provide outgoing information-having same structure - with the help of a distant clock reconstituted from the incoming information structure, and with the help of a local clock determining the structure of the outgoing informa-tion. The present invention, according to its main feature, consists in storing the input information into a junction memory at the rate of one stor-ing operation per input combination, in reading the output information in the junction memory at the rate of one reading operation per output-combination -~
; 20 and in order that the storlng and reading operations should always be dis-tinct, in *ime shifting one of these operations by a predetermined duration in case of collision, that is to say when the interval separating them has - become shorter than a predeterminea value.
` Another feature of the process in the present invention is that one of the two operations - storing or reading - is performed at one of two ~ predetermined moments inside each time interval and the shifting of the opera-`1 tion is thus obtained by changing moments.
~ The present invention also has for object a resynchronizing de-`1~ vice for frame-structured incoming information, repetitive of time intervals, constituting time channels and conveying each a coded combination, whose func-.
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tion i<; to provide outgoing information having the same structure and which compriscs, namcly, circuits so-called distant clock providing clock signals dorived from thc structure of the incoming information, as well as a local clock detcrmining the structure of the outgoing information. This device com-priscs essentially a junction memory with cells for storing each, temporarily, the successive coded combinations of an input time channel and to provide them along an output time channel; circuits controlled by the distant clock for receiving the input coded combinations and store them then into the approp-riate memory cells; circuits controlled by the local clock for Teading the output combinations in the appropriate memory cells and then transmit them;
as well as an exclusion circuit provided in order that the storing and writing operations performed in the memory should be time split and which to that end comprises means for evaluating the interval separating the storing and reading operations, and, means controlled by the foregoing ones for time shifting one the operations for a predetermined duration in case of collision. . .
Another feature of the device in present invention is that the means provided in the exclusion circuit for evaluating the interval separating the storing and reading operations comprise means for originating a pre-- collision damping signal delimiting a time space enframing one of the said operations, storing or reading; and, means for detecting the coincidence of this damping signal with a signal controlling the performance of the other said operation, reading or storing, and thus originate, a signal announcing a collision ; Another feature of the device in present invention is that the means provided in the said exclusion circuit, for time shifting one of the operations by a predetermined duration, comprise means for originating from - one of the distant or local clocks two control signals of one of the said . operations - storing or reading - distinct one from the other inside each time interval; as well as switching means controlled by said signal announcing a collision and arranged for delecting and operation one of the two control signals.
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l.o82823 This time shifting of the reading operation, for instance, does not bring any perturbation as long as the two clocks are sufficiently out of phase. Same does not apply when these two clocks are in quasi-synchronism and tllat the rcconstituted distant clock shows a jitter with respect to the local clock. Indeed, there may then be intended to perform relatively often a shifting of the reading operation alternately in one direction and then in the other. Now then, this shifting in some cases, so-called critical cases, causes either a doubling or a skipping of a frame. Each of these perturbations is in itself acceptable, but it is not possible admitting, in case of important jitter, to proceed to repeated shiftings causing alternately a doubling and then a skipping of a frame.
The present invention has therefore for object a resynchronizing ~ ~ -process and device avoiding these disadvantages by increasing the phase gap between the reading and storing operations of one same time slot in the most unfavourable time configuration, that is to say during the carrying out of a critical shifting having brought about a perturbation The resynchronizing process for repetitive frame structured incom-ing information of present invention is characterized in that into the reading and storing of combinations in the memory there is introduced a sliding in of a time slot being added algebraically to the above mentioned shifting so as to increase the phase margin and protection against jitter.
Thus, in the case where the time shifting relates to the reading operations, the local clock being faster than the distant clock, the shifting of the reading from a time position, located at the end of a channel time slot to a time position located at the beginning of this channel time slot, makes this reading to pass, according to the storing operation, before that opera-tion. When both operations take place at the same memory address, the result is the double reading of one same frame. It then suffices that a reverse ` jitter, equal at most to the interval separating the two time positions of the reading, should superpose itself to the continuous drift of one clock with respect to the other, that it be necessary to start the reverse shifting thus causing the skipping of a frame. The present invention provides in that case ' ~ , , .... .

lUB2823 to introduce in the storing operations, for instance, an additional shifting of a time slot in the direction that suits. Thus, in order that it be neces-~ary to start the said reverse shifting it is required that a reverse jitter, o(luuL to thc intorval separating the two time positions of the reading opera-tion increased by a channel time slot, should be superposed to the drift.
The description has also for object a resynchronizing device for repetitive frame structured incoming information characterized in that it also comprises, on the path of the storing or of the reading out of the memory, an additional buffer register making it possible to introduce a delay exactiy equal to a channel time slot into the storing or reading out of the memory;
and not to perturb the input or output multiplex in the transmission circuit of storing or reading addresses, a buffer register making it possible to intro-duce a delay identical to the foregoing one in the transmission of the said addresses is provided, as well as control circuits associated with these two additional registers and enabling including or excluding these additional registers of the said circuits.
Various further features and objects of present invention will now be disclosed from the following description which is given by way of non-limited example and with reference to the accompanying drawings which represent:
Figure 1, the block diagram of a resynchronizing circuit according the present invention;
Figure 2, chronograms defining the various signals utilized in the - circuit of Figure l;
Figure 3, an embodiment of the exclusion circuit XC in Figure l;
Figure 4, chronograms illustrating the operation of the exclusion circuit XC in Figure 3;
Figure 5, chronograms that illustrate the progressing of the coded combinations when a time-shifting of the reading operations takes place, conformable to present invention;
Figure 6 to 7, chronograms illustrating the time-shifting opera-tions of the reading out of the memory, conformable to present invention, when the storing and reading operations or the reading and storing operations ~ - 5a -..:

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~08Z~23 are performed in succession on the same address in the memory.
Figurc 8, a preferred embodiment of the resynchronizlng circuit in Fi~ure l;
Figurc 9, chronograms defining the various signals utilized in the circuit of Figurc 8;
Figure 10, an embodiment of the control circuit EX in Figure 8;
Figure 11, chronograms illustrating the operating process of the routing circuit XB in Figure 10;
- Figures 12 and 13, chronograms illustrating the operations of stor-ing into memory and critical time shifting of the reading out of the memory conformable to present invention.
First will be described, in referring to Figure 1, the block diagram of a resynchronizing circuit for incoming information in a digital switching exchange designed in conformity with present invention.
Thirty two input lines leO, lel, ..., le31, belonging to a distant , exchange are multiplexed upon an incoming group gpe through means not shown i here.

In the circuit of Figure 1, a transcoder TC receives the signals of ,~ group gpe and provides, in ct, the corresponding binary signals and, in _, a distant clock signal, which includes one impulse per bit received with the ; . .
' appropriate phase with respect to the signals provided in ct.
~- A shift register RE, having eight stages O to 7, controlled by the reconstituted clock impulses _, receives in series the eight bits ct of each coded combination. As soon as the eighth bit is received, it retransmits in parallel the eight bits to a junction memory MD and to a supervision block SB.
The junction memory MD is a random access memory comprising 32 mem-f, ory cells mdO, mdl,... ,md31 being each provided for storing the eight bits of a coded combination. Every one of these cells is associated with a time channel, therefore with an input line. Thus, the coded combination originat-ing from the input line leO is stored into the memory cell mdO, the coded combination originating from the input line lel is stored into the memory cell mdl and so on; the coded combination originating from input line le31 being ~ - 5 b -'.', ' ' ' : ., ' lOB21~23 stored into memory cell md31.
~ccording to the time-multiplexing principle, the time is divided into ;dcntical sampling periods of 125 ~s so-called frames. Each frame is dividod into 32 idantical time intervals of about 3.9 ~s. During every time interval an 8 bit coded combination at the rate of one bit every 488 ns is transmitted. To make possible the identification of the frames, a synchronisa-tion code is transmitted during a determined period of time, say for instance at the frame beginning. The supervision block SB has for function the detec-tion of this synchronisation code. It will provide, namely, in the absence of that code, a blocking signal em. It will also provide, at the starting of the system and at the first reception of that code, a resetting signal in towards a counter device CC.
The counter device CC, controlled by impulses _ of the distant clock, comprises counters NB, NT and PT. Counter NB is a three stage-counter. It steps one step at each impulse h. It restores to 0 position at the beginning of each input combination of 8 bits and it constantly provides the number, from 0 to 7, of the bit received. As will be seen subsequently, for a certain ': position this counter provides a signal ecr and a signal tam. The counter NT
~ is a five stage counter. It steps one step under the control of a clock y 20 impulse h when the counter NB restores to 0 position. It is in 0 position at the beginning of each input frame and it provides the number, from 0 to 31, of the incoming time channel inside a frame; therefore also, as was already seen above the number of the cell of the junction memory MD in which is stored ~' the coded combination provided by the input register RE. This number is there-: fore provided to a storing addresses decoder DE associated with memory MD.
Counter PT is a one bit counter which defines the parity of each frame.
The exchange considered here comprises a local clock HL common (mul-' tipling arrows) to all the circuits such as the one in Figure 1. This clock provides impulses H to counter device NL and to an exclusion circuit XC.
` 30 The counter device NL, controlled by impulses H and restored to zero by a signal in'originating from the local clock HL, comprises two counters LB
and LT and their associated decoding circuits DB and DT~
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lOB2823 M.A.R. Henrion-A. L. Coudray 9-2 Counter LB comprises 3 stages. It steps one step at each impulse H. It constantly defines the number, from O to 7, of each 488 ns characteristic moment mO
to m7 of each of the time slots tO to t31 assigned respectively to the time channels of an outgoing multiplex group ~e~. It restores to zero at the beginning of each outgoing combination. The decoding circuit DB which is associated with it provides impulses MO, Ml, M5 and M7 when counter LB occupies positions O, l, 5 and 7 respectively.
Counter LT comprises 5 stages. It steps one step under the control of a clock impulse H when counter LB restores to position O. It is in position O at the beginning of each output frame and it provides the number tl, from O to 31, of the outgoing time channel inside a frame, therefore also, the number of the cell of the junction memory hlD to be read. This number is therefore provided to a reading addresses decoder DL associated with memory MD. The decoding circuit DT
associated with the counter LT provides an impulse t'31 when this counter is in position 31.
The exclusion circuit XC which receives signals tam, MO, Ml, M5, M7, t'31 and clock impulses H provides in response a reading signal lec to the reading addresses decoder DL. In the presence of that signal, the coded combination stored in the memory cell defined by the address tl is read. This coded combination is stored in a first output register RM under the control of an impulse oec provided by the exclusion circuit ~C. It is then transferred into a second output register RS, under the control of an impulse MO, and then to the recipient output line of an outgoing multiplex group ~ via a blocking circuit BC controlled by the blocking signal em originating from the supervision block SB. It will be assumed that the transmission is accomplished in parallel form. In that case, the blocking circuit is a simple logic gate.
Now will be described, in also referring to the chronograms in Figure 2, the operating process of the circuit in Figure 1.
On the first line of Figure 2 is being shown the coded con binations ct, originating from the input lines leO, lel and le2 of group gpe, and which occupy the time slots ITO, ITI and IT2 respectively. Each coded combination comprises eight bits .

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M.A.R. Henrion-A. L. Coudray 9-2 O to 7 transmitted at the rate of one bit at about every 488 ns to the input register RE.
This register receives also the distant clock impulses h provided by the transcoder TC.
E~ch combination is stored into a cell of the junction memory MD as soon as the eighth bit has entered into the input register RE. To that end, the counter NB provides a storing impulse ecr. This impulse is illustrated by the chronogram ecr in Figure 2. The counter NB provides also a damping impulse tam which starts 488 ns before storing impulse ecr and which ends 488 ns after the end of that impulse.
This operating process is of a systematic nature. As long as the transcoder TC provides the reconstituted impulses h of the distant clock, the counters of block CC step on and when counter NB provides signal ecr, the address provided by counter NT is used to store the contents of register RE into a cell of memory MD. In normal operation, the supervision block SB has synchronized one another the counters NB, NT
and PT; and the combinations ct are stored one by one into cells mdO to md31 for each frame of the input group.
There now remains to determine the instant of reading at the local clock rate of the stored coded combinations. According to the process of the present invention in order to avoid any simultaneity between the reading operations and the storing operations, a reading impulse lec will be provided in the absence of impulse tam and distant enough from that impulse so as to be safe at the maximum from the buffer-reading collisions due to a possible jitter from the distant clock with respect to the local clock.
The combinations stored in the memory MD are read at the rate of the local clock HL once every 3.9 ,us. The stepping of the counters constituting NL is controlled by a clock signal H to 2.048 MHz (identical to h); a synchronization signal in initiates counters LB and LT when the synchronization system is set into operation.
Counter LT of the arrangement NL defines, namely, the 3.9 ,us time slots tO to t31, assigned respectively to the output lines of the multiplex group ~; and the counter LB defines the eight 488 ns characteristic moments, mO to m7 of each of these time ' slots .

,, ~,~82~23 M.A.R. Henrion-A. L. Coudray 9-2 lt will now be assumed that the reading impulse lec is provided during the characteristic moment ml, that is to say, at the same time as impulse Ml provided by the decoding circuit DB, and that the storing operation takes place at an instant distant enough, for instanceS during the characteristic moment m4, in order that impulse tam does not coincide with impulse Ml.
If the distant clock deviates with respect to the local clock, the time interval, which separates pre-collision damping impulse tam - originated from impulses h - from impulse Ml - originated from impulse H - will get reduced. ~s soon as there is collision, the exclusion circuit XC, at the end of an output frame - that is to say, in presence of impulse t'31 provided during each time slot t31 by the decoding circuit DT-does no longer provide, as previously, the reading impulse during moment ml.
According to the principle of the invention, the reading impulse lec is then provided during the moment m5. Since the time interval separating impulse Ml from impulse M5 is longer than the duration of the pre-collision impulse tam, it is assured that the latter and the reading impulse lec do not coincide. The deviation of the distant clock being continuous, at the end of a relatively long period of time, the deviations being slow with respect to the duration of a frame, the impulses lec and tam will again be in coincidence. In the manner, as described above, the impulse lec will no longer be provided during the characteristic moment m5 but will be provided during the characteristic moment _. Chances of writing/reading simultaneity are tllerefore avoided.
Now will be described, in referring to Figures 3 and 4, an embodiment of the exclusion circuit XC.
The exclusion circuit XC in Figure 3 comprises essentially four AND gates ANI, AN2, AN3 and AN4, an RS flip-flop FFI, a D flip-flop FF2, a circuit RT
introducing a delay 0 and an OR gate PSI.
~` Gate ANI receives, namely, the impulses Ml, lec and tam as vell as the impulse t'31. It provides an output signal anl to the set input of flip-flop FFI.

Gate AN2 receives, namely, the impulses M5, lec, tam and t'31. It provides an output signal an2 to the reset input of flip-flop FFI.

, ~082~23 M.A.R. Henrion-A. L. Coudray 9-2 Flip-flop FFI provides a signal ffll on its direct output connected to the inplut D of flip-flop FF2. This latter receives also the impulses M7 on its clock input.
It provides a signal ff21 on its direct output connected to an input of logic gate AN3, and a signal ff20 on its complementary output connected to an input of logic gate AN4.
Impulses M5 and Ml are provided to another input of gates AN3 and AN4 respectively.
These two gates provide a signal an3 and an4 respectively to logic gate PSl.
OR gate PSI provides signal lec, in direction of the reading addresses decoding circuit DL, to an input of AND gates ANl and AN2, and to the input of circuit RT.
Signal lec delayed by a period of time ~ by circuit RT becomes signal oec and enables the storing into output register RM in Figure 1 of the word read in memory MD.
It is assumed that, with respect to the output frame, the storing operations are performed during the characteristic moments ~; the reading operations are performed during moments ml.
Flip-flop FFI is originally in position O as well as flip-flop FF2. This latter's output signal ff20 is "1". The gate AN4 therefore retransmits impulse Ml in the form of an impulse an4. Gate PSI provides therefore a reading signal lec practically identical to impulse Ml. The result is that the reading in the memory is performed during moment ml and that the storing into the output register RM of the read ....
$ combination takes place after a delay ~. The transfer of that combination into register RS takes place at the next moment mO.
~It will then be assumed that the local clock being, for instance, faster than ; ~the distant clock, the trailing edge of the pre-collision signal tam is provided after the apparition of the trailing edge of impulse Ml (Figure 4). The impulse lec remains '~ `provided in response to impulse Ml until the end of the frame.

~`As soon as impulse t'31 originates, provided by the decoding circuit DT
during the first time slot t31 following the coincidence of impulses Ml and tam, gate ANl - all the inputs of which are at logic level 1- provides a collision signal anl of logic .level 1 to the set input of flip-flop FFI. This flip-flop triggers and provides a signal ffll ,...
of logic level I to input D of flip-flop FF2.
... _ g_ s i,, ~B2823 M.A.R. Henrion-A. L. Coudray 9-2 At the originating of the leading edge of impulse M7, provided during the last characteristic moment m7 of the time slot t31 to the clock input of flip-flop FF2, this latter triggers onto position 1. It therefore provides a signal ff21 of logic level I
and a signal ff20 of logic level 0.
At the originating of impulse Ml, provided during the characteristic moment ml of the time slot t0 of the next frame, gate AN4 - an input of which receives a signal ff20 of logic level 0 - provides a signal an4 of logic level 0. Gate AN3, an input of which receives an impulse M5 of the logic level 0, provides a signal an3 of logic level 0.
Gate PSl, the two inputs of which are at logic level 0, provides a signal lec of logic level 0.
Thus, the exclusion circuit XC in Figure 3 has detected the imminence of a simultaneity between the reading and writing operations in the memory and, in order to avoid this simultaneity, has cancelied the reading operation which normally had to take place during the characteristic moment ml of time slot t0.
As soon as the next impulse M5 appears, provided during the characteristic moment m5 of the time interval t0, gate AN3, whose two inputs are at logic Jevel 1, provides a signal an3 of logic level I to an input of the OR gate PSI. This latter provides therefore a signal lec of logic level 1.
This signal is provided, on the one hand, to the gates ANl and AN2, which remain blocked by the signals tam and t'31 at logic level 0 and, on the other hand, to the circuit RT which therefore provides a signal oec of logic level I after a period of time ~. This storing order signal is transmitted to the output register RM (Figure 1).
When signal lec passes onto logic level 0, the signal oec will then pass onto logic level 0 after a delay 0.
At the originating of the trailing edge of next impulse M7, provided during the characteristic moment m7 of the time slot t0, flip-flop FF2 remains in position 1, flip-flop FFI being maintained in position 1.

It is assumed that the progressing goes on and that the signal tam arrives into coincidence with impulse M5. At end of frame impulse t'31 is provided and gate ' .

lV8282;~

M.A.R. Henrion-A. L. Coudray 9-2 AN2, all the inputs of which a~e at logic level I at the moment m5 of time slot t31, is enaibled. It provides a coilision signal an2 of logic level 1. This signal triggers flip-flop FFI into position 0. The output signal ffl of this flip-flop passes onto logic level 0. At the beginning of next impulse M7 (during the time slot t31), flip-flop FF2 passes onto position 0 and therefore provides a signal ff20 of logic level 1. At the originating of next impulse Ml provided during the characteristic moment ml of the time slot tO of next frame, gate AN4 is enabled and it retransmits impulse Ml to the gate PSI which retransmits it in the form of a reading impulse lec.
Signal oec of logic level I is provided in an identical manner to the one described above.
This then leads back to initial state of conditions.
Thus, as soon as there is a risk of simultaneity between the reading operations and the writing operations, the exclusion circuit will detect that risk and will command, at end of frame, the time shifting of the reading operations. This time shifting consists in providing the reading signal in the same time slot but in another moment distant enough for keeping back any risk of writing/reading simultaneity in the next frame. Thus, one reading operation and one only is always performed during each time slot.
Now will be described, in referring to the chronograms of Figure 5, the progressing of the bits of coded combinations in the various elements of the circuit in ~ Figure 1, when a time shifting of the reading operations takes place.
- It is assumed that the local clock HL, being faster than the distant clock, the time interval separating the storing impulse ecr - provided at the end of the storing of the eighth bit of the coded combination into the input register RE during the time slot ITI0 of frame n - from the reading impulse lec - provided during the characteristic moment ml of the time slot t31 - reduces sufficiently so that the impulse Ml of that time slot be provided before the corresponding pre-collision impulse tam should disappear. The exclusion circuit XC undertakes the shifting operations in the manner described above.

-Il-~, ~082~23 M.A.R. Henrion-A. L. Coudray 9-2 The reading operation out of memory MD is performed at the address tl provided by counter NL (Figure 1). At that instant, cells mdO to mdlO of the junction memory MD contain the coded combinations itO (n) to itlO (n) respectively, and memory cells mdll to md31 contain the coded combinations itll (n-l) to it31 (n-l).
According to the example chosen here, the contents of memory cell md31 is read. This memory cell contains the coded combination it31 of the time slot IT31 of the foregoing frame, that is, the combination it31(n-1), as is indicated by the chronogram lmd. As was already seen above, a storing order impulse oec is provided after the ~ delay. This impulse determines the storing of the coded combination 1_(n-l) into the output register RM which contained previously the coded combination it30(n-1) as is indicated by the chronogram crm.
The originating of impulse M5 provided during the characteristic moment m5 of the time slot t31 is without any effect on the routing of the coded combinations.
The originating of the next storing impulse ecr causes the storing of the coded combination i_(n) into cell mdll of the junction memory MD in lieu of combination i_(n-l) which is thus removed.
An impulse MO is provided at the first characteristic moment mO of the time slot tO. This impulse causes the storing of the contents of register RM, that is to say, the coded combination 1_(n-l) into the second output register RS. This latter enables either the availability of the eight bits of that combination during the 3.9 us of the time slot tO, or the retransmission in series of these eight bits at the rate of

2.048,106 bits per second (chronogram srs in Figure 5).
' Impulse Ml, provided subsequently, is without any effect: the exclusion circuit having triggered provides a reading signal of logic level O in the manner already i described above.
Impulse M5, provided during the sixth characteristic moment m5 of the time slot tO, causes the passage of the reading signal lec to logic level 1. The contents of memory cell mdO is read. This cell contains the coded combination i_(n). At the originating of the storing order impulse oec, this combination is stored into the output `
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~0828Z3 M.A.R. Henrion-A. L. Coudray 9-2 register RM, whose previous contents - combination 1_(n-l) - has been stored into the second output register RS.
The next storing impulse ecr causes the storing of the coded combination itlZ(n) into cell mdl2 of the junction memory MD, and operation of the resynchroni-zation circuit in Figure 1 proceeds in the manner described above. It is seen therefore that the shifting of the reading operations in memory from characteristic instant ml to characteristic instant m5 was performed without any perturbation and that, at the output of register RS, the coded combinations are provided in synchronism with the time intervals of channels t0 to t31. It is worth noting a shift of a time slot t (3.9 us) between the local clock and the output of the second output register RS. Indeed, during the time slot t0, that register retransmits the coded combination 1_. A 5 stage shift register, associated with counter DT, storing the code of the IT's delayed by a time slot, enables to palliate this delay.
It could be shown that same applies at a shifting of the memory reading operations from characteristic moment m5 to characteristic moment ml whatever be the relative variation direction of the two clocks.
The local clock, according to the example chosen here, is faster than the distanct clock. On the chronograms in Figure 5, this can be illustrated by a shifting of the three first chronograms ct, ecr and tam onto the right. The successive shiftings of the reading operations will then be performed, without any perturbation, in the manner described above. Nevertheless, perturbations may arise when the two clocks are going to be in phase.
There will therefore be described now, in referring to the chronograms in Figures 6 and 7, the routing of the bits of the coded combinations in the various elements of the circuit in Figure I at a time shifting of the memory reading operations, the dephasing between the local clock and the distant clock being inferior to 3.9 us.
As previously assumed above, it will be assumed that the local clock HL is faster than the distant clock.

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M.A.R. Henrion-A. L. Coudray 9-2 It is first supposed that, as the chronograms in Figure 6 show, the reading operations take place during the moment ml. The storing impulse ecr provided at the end of the time slot IT31(p), controls the stor;ng of the coded combination I_(p) in the cell md, md31 of junction memory MD. The cells mdO to md31 of that memory therefore contain coded combinations itO(p) to I_(p) respectively.
The reading impulse lec subsequently provided during the time slot t31 controls the reading of contents 1_(p) of the memory cell md31. According to the process already described, this combination is stored successively into tne output registers RM and RS.
The storing impulse ecr provided at end of the time slot ITO(p+l) controls the storing of the coded combination i_(p+l) into the cell mdO of memory MD.
A collision happens between signal Ml and the pre-collision signal tam ` during reading of the output frame p in the conditions already described. Conse-quently, the exclusion circuit XC generates a reading signal lec at the originating of impulse M5 of time slot tO of the frame p+l. This impulse controls the reading of contents of memory cell mdO, that is to say of the coded combination i_(p~l).
The operation proceeds in the manner already described. Time shifting of the reading operations of ml in m5 has not therefore brought any perturbation.
The local clock being more rapid than the distant clock after several frames, time interval separating impulse M5 from impulse tam, diminishes so as to finally cancel as is shown by the chronograms in Figure 7.
- The storing impulse ecr, provided at end of the time slot IT31(q), controls the storing of coded combination it31(q) into the cell md31 of memory MD. Cells mdO
to md31 of that memory contain therefore the coded combinations i_(q) to it31(q) respectively.
Reading impulse lec provided at the instant m5 of time slot t31 controls the reading of coded combination it31(q). The collision of impulses M5 and tam will trigger the exclusion circuit XC. This latter provides a reading impulse lec at the moment ml of time slot tO. This impulse is therefore provided before the next storing impulse ecr.
It controls the reading of contents of the memory cell mdO, that is to say the coded ., .

108Z~23 combination itO(q).
lhe next storing impulse ecr controls the storing of the coded combination itO(q+l) into memory cell mdO and, the next reading impulse lec controls the rcading of combination itl(q) stored in memory cell mdl; and so on.
The time shifting of the reading operations of m5 to ml therefore has, this time, brought a perturbation : frame q is read twice. This perturba-tion is inevitable in asynchronous operation.
Therefore, when the local clock is more rapid than the distant clock, the time shifting of the reading operations will not bring any perturbation (Figure 6) or cause the doubling of a frame (Figure 7).
By means of an identical reasoning it can be shown that the local , clock being less rapid than the distant clock, the time shifting of the read-ing operations will bring no perturbation or cause the skipping of a frame.
These two inevitable perturbations set apart, the resynchronisation circuit in present invention - which is a simple circuit little costly and easily adaptable to operation in synchronous network. Therefore enables . detecting and avoiding any collision between the reading and writing operations.

3 But, same does not apply when the two clocks are in quasi-synchron-ism and that the reconstituted distant clock shows a jitter with respect to ~i~ the local clock. Indeed, there may then be intended to perform relatively often a shifting of the reading operation alternately in one direction and ~- then in the other. Now then, this shifting in some cases, so-called critical cases, causes either a doubling or a skipping of a frame. Each of these it~ perturbations is in itself acceptable, but it is not possible admitting, in case of important jitter, to proceed to repeated shiftings causing alternately a doubling and then a skipping of a frame.
~; Now will be described, in referring to Figure 8, the block diagram , of the modified circuit in Figure 1, in which these drawbacks are overcome.
; 30 The resynchronizing circuit in Figure 8, comprises the different $ devices of the circuit in Figure 1 in which the shift-eight-stage register RE

~, has been replaced by a first eight-stage shift register RA and a second eight-stage-shift register RR. As will be seen this makes it possible to introducc a delay equal to a channel time slot into the storing; and not to perturb the input multiplex in the transmission circuit of storing addresses, a buffcr register RD making it possible to introduce a delay identical to the foregoing one in the transmission of the said addresses is provided, as well as control circuits associated with these additional registers and enabling including or excluding these registers of the said circuits.
The first input shifting register RA, having eight stages 0 to 7, controlled by the reconstituted clock impulses _, receives in series the eight bits ct of each input coded combination. The output of each stage of this register is connected to an input of an AND gate. In order not to com-plicate unnecessarily the figure, only two of these gates are being shown; a gate PAO, one input of which is connected to the output of stage O of register RA and a gate PA7, one input of which is connected to the output of stage 7 of register RA. Each of these gates is controlled by a signal ra applied to its other input. The output of each of these gates is connected to the first input of an OR gate. Thus, the output of gate PAO is connected to the first input of a gate PXO and the output of gate PA7 is connected to the first input of a gate PX7.
; The output of the last stage of input register RA is also connected to the input of the second input shifting register RR, having eight stages 0 to 7, controlled by the clock impulses h. The output of each stage of register RR is connected to an input of an AND gate. Only gate PRO, one input of which is connected to the output of stage O of register RR, and gate PR7, one input of which is connected to the output of stage 7 of this register have been shown. Each of these gates is controlled by a signal rr applied to its other input. The output of each of these gates is connected to the second input of the corresponding gate PXO/7. Thus, the output of gate PRO is connected to the second input of gate PXO, the output of gate PR7 being ` connected to the second input of gate PX7.

In presence of signal ra, signal rr be1ng absent, the eight bits ct stored in the first input register RA are retransmitted, via gates PAO to PA7, to the outputs of gates PXO to PX7.
In prcscnce of a signal rr, signal ra being absent, the eight bits ct storcd in thc sccond input register RR are retransmitted v:ia gates PAO to PA7, to the outputs of gates PXO to PX7.
These bits are then retransmitted, in parallel, to the random access and non-erase reading junction memory MD.
The storing address is provided to a storing-addresses decoder DE
associated with the memory MD via five OR gates PEO to PE4 which receive, respectively, the output signals of five AND gates PCO to PC4 and the output signals of five AND gates PDO to PD4.
The AND gates PCO to PC4 are controlled by signal ra and their in-puts are, respectively, connected to the outputs of counter NT.
The AND gates PDO to PD4 are controlled by signal rr. Their inputs are respectively connected to the outputs of a five stage buffer register RD.
, This register receives the five bits originated from counter NT; it is con-trolled by signal C7 originated from counter NB.
: As will be seen subsequently, for certain positions, the counter NT
also provides signals IT'O and IT'31.
The resynchronizing circuit in Figure 8 also includes a control circuit EX instead of the exclusion circuit XC of the resynchronizing circuit in Figure 1.
The control circuit EX, which receives signals CO, C6, tam, MO, Ml, ~ M5, M7, t'l5 and t'31 as well as the clock impulses H, provides, in response, !. a reading signal lec to the reading-addresses decoder DL. In presence of this . signal, the coded combination, stored in the memory cell defined by address ~: tl, is read. This coded combination is stored into a first output register ` RM under the control of an impulse oec provided by control circuit EX. It is then transferred into a second output register RS under the control of impulse ~ 30 MO, and then to the outgoing line recipient of the output multiplex group `` gps via a blocking circuit BC controlled by the blocking signal em originated from the supervision block SB.
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lOB2823 Now will be described, in also referring to the chronograms of ligure 9, the general operating process of the circuit in Figure 8.
On the first line of Figure 9 are shown the coded combinations ct origillatirlg ~rom thc in~ut channels le31, lc0 and lel, and which occupy respectively the time slots IT31, ITO and ITl. Each coded combination com-prises eight bits cO to c7 transmitted at the rata of one bit every 488 ns to the first input register RA. This same coded combination is then trans-mitted at the same rate to the second input register RR whereas the next coded combination is transmitted, same as the previous one, to the first in-put register RA, and so on.
Therefore, when register RA contains the coded combination originat-ing from the input channel le(;) which occupies the time slot IT~j), the register RR contains the coded combination originating from channel le(j-l) which occupies the time slot IT(j-l). Number i, from 0 to 31, of time slot IT(j) which is also the number of the memory cell md(j) into which is stored the coded combination contained in the first input register RA, ls provided by counter NT and gates PCO to PC4 and PEO to PE4 to the storing addresses decoder DE. Number (j-l) of the preceding time slot, IT(j-l), which is also the number of the memory cell md(j-l) into which is stored the coded combina-tior. contained in the second input register RR, is provided by register RD
and gates PDO to PD4 and PEO to PE4 to decoder DE.
Each combination is stored into the junction memory MD as soon as the eighth bit is stored into an input register. To that end, counter NB
provides a storing impulse ecr. This impulse is illustrated by the chronogram -' ecr in Figure 2. This counter provides also a damping impulse tam which, ~ according to example chosen, begins 488 ns before the storing impulse ecr and '; which finishes 488 ns after the end of that impulse.
On the other hand, according to whether it is required to store the coded combination written in the first input register RA, or the one written 3 30 in the second input register RR, the control circuit EX will provide either signal ra, or signal rr. As was already seen above, these two signals enable also the transmission of the writing address which suits to decoder DE.

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.' 1082~23 This o~erating process is of a systematic nature. As long as trans-coder IC provides the reconstituted impulses h of the distant clock, the counters o~ block CC keep operating. When counter NB provides signal ecr, tho a~ldress provide~ at t'nat very instant by counter NT, or the address writ-ten into register Rl) when the preceding impulse ocr orig;nated, helps to store the contents of register RA, or of register RR, into a cell of memory MD. ln normal operation, the supervision block SB has synchronized one another counters NB, NT and PT; and the combinations ct are stored one by one into the cells mdO to md31 for each frame of the input group.
It now remains to determine the reading moment, at the rate of the local clock, of the stored coded combinations. According to the principle described in the main patent, in order to avoid any simultaneity between the reading operations and the storing operations, a reading impulse lec is pro-vided in the absence of impulse tam and sufficiently distanced from this impulse so as to keep safe at the maximum from the successive storing-reading simultaneities due to a possible jitter of one clock with respect to the other.
The combinations stored into the memory MD are read out, at the rate of local clock HL, once every 3.9 ~s. The stepping of the counters of counter device NL is controlled by the clock signal H at 2.048 MHz identical to signal h. A synchronizing signal in', originated from the local clock HL, initiates counters DT and DB when the equipment is set into operation. Counter DT
defines, namely, the 3.9~us time slots, tO to t31, alloted respectively to the output channels of the multiplex group gps. When it is in position 15 and in position 31 it provides impulses t'l5 and t'31 respectively. Counter DB defines the eight 488 ns characteristic moments _0 to _7 of each of the time slots tO to t31. When it is in position 0, 1, 5 and 7 it provides im-pulses MO, Ml, M5 and M7 respectively. These various signals are illustrated by the corresponding lines in Figure 9.
It is assumed that the reading impulse lec is provided during the characteristic moment ml, that is to say at the same time as impulse Ml, and that - taking into account the relative shifting of the two clocks - the storing operation is performed at quite a distant moment, during the character-, 10~2823 istic moment m5 according to the example illustrated by chronograms in Figure 9, ill ordcr that impulse tam should not coincide with impulse Ml.
[f thc distant clock deviates with respect to the local clock, the timc i~terval scparating the damping impulse tam - originated Erom impulses h - Erom impulse Ml - originated from impulses H - diminishes. As soon as therc is a risk of collision, the control circuit EX, at end of local frame, that is to say in presence of impulse t'31 provided during each time slot t31, stops generating - as previously - the reading impulse during moment ml but will henceforth generate it during moment _5. The time interval separating impulse Ml from impulse M5 being longer than the duration of damping impulse tam, it is assured that this latter and impulse lec do not coincide. At the end of a relatively long time, the deviation of the distant clock being con-tinuous, but slow with respect to the duration of a frame, the impulses lec and tam will again be in coincidence. In the same manner as is described $ above, impulse lec will no longer be provided during the characteristic moment m5 but during the characteristic moment _1. Thus are therefore avoided the risks of storing-reading simultaneity. These successive shiftings of the ,~ reading operations are performed at different memory addresses.
Now will be described, in referring to Figure 10, an embodiment of the control circuit EX.
The control circuit EX in Figure 10 includes the exclusion circuit EC of Figures 1 and 3 and a routing circuit XB which provides, namely, the control signals ra and rr of the gates associated with the outputs of the in-put registers RA and RR and of the register RD.
Routing circuit XB comprises, essentially, six AND gates GAl to GA6, two OR gates GOl and G02~ an RS flip-flop FF4 and a D flip-flop FF5.
Gate GAl receives impulses Ml and tam as well as impulse C6 provided by counter NB (Figure 1) during moment c6 of each time slot ITO to IT31. It provides a signal ~ to an input of gate GA3 and of gate GA6.
Gate GA2 receives impulses M5 and tam as well as impulse CO provided by counter NB during moment cO of each time slot ITO to IT31. It provides a signal ga2 to an input of gate GA4 and of gate GA5.

'i ~082823 Gate GA3 receives also reading impulse lec originated from circuit XC, impulse t'31 and impulse IT'31 provided by counter NT (Figure 8) during oach time slot IT31.
Gatc CA 4 rcceives also impulse lec, impulse t'l5 provided by countcr DT during each time slot tl5 and impulse IT'0 provided by counter NT
during each time slot ITO.
Gate GA5 receives reading impulse lec and impulses t'31 and IT'0;
and gate GA6 receives impulses lec, t'l5 and IT'31.
Gates GA3 and GA4 provide respectively signals ga3 and ga4 to gate GOl which provides in response a signal gol to the se* input of flip-flop FF4.
Gates GA5 and GA6 provide respectively signals ~5 and ga6 to gate GO2 which provides in response a signal go2 to the reset flip-flop FF4. This latter provides, on its direct output, a signal ff41 to input D of bistable FF5 whose clock input receives impulses M7. Bistable FF5 provides signal ra on its direct output and signal rr on its complementary output.
Now will be described, in also referring to Figure 11, the operating process of routing circuit XB. It will first be assumed that the local clock, being slower than the distant clock, there is a collision between reading signal lec - provided during moment _l of time slot tl5 of the outgoing frame - and damping signal tam enframing the storing signal ecr provided at end of time-slot IT31 of the incoming frame.
It is also assumed that flip-flops FF4 and FF5 are set, therefore that the routing circuit XB provides a signal ra of logic level 1, and a signal rr of logic level 0.
, Gate GAl which receives simultaneously signals tam, C6 and Ml, pro-vides a signal gal of logic level 1.
`- Gate GA6, whose inputs IT'31, lec, t'l5 and gal are at logic level 1, provides a signal ga6 of logic level 1.
OR gate GO2, one input of which is at logic level 1, provides a - 30 signal go2 of logic level 1. The restoring to logic level 0 of signal C6 causes the passing of signal go2 to logic level 0. Flip-flop FF4 triggers to logic level 0 on the leading edge of that signal. This flip-flop therefore ,.:
: . .. . .

~082823 provides a signal ff41, of logic level 0, to the input D of bistable FF5.
The leading edge of next impulse M7, provided during characteristic momont m7 of the time slot tl5, causes flip-flop FF5 to trigger into position 0.
Signal ra, provided by this flip-flop therefore passes to logic level 0, signal rr passing to logic level 1.
As was already seen above, during all that operation, the exclusion circuit XC does not cause any shifting of the reading operation, such a shift, according to the example chosen here, being able to take place only at the end of output frame.
The operations described have merely for purpose, on the one hand, to detect the direction of the collision and, on the other, to pre-select the input register in view of the next shift. Indeed, in the example chosen here, a collision was met between damping impulse tam and the trailing edge of -impulse lec (local clock slower than distant clock~. This collision will be so-called "rear collision".
As will be seen here subsequently, during a critical shifting of the reading operation which will take place several frames later, in order to increase the phase margin ~ the storing willalso be shifted by a time inter-val forward in storing into memory no longer the coded combinations originated from register RR (Figure 8) but the coded combinations originated from register RA. It is therefore the passing of register RR to register RA that will enable increasing the phase margin. It was therefore indeed necessary, ~; beforehand, to arrange that the coded combinations,originated from register ~ RR and not those originated from register RA, be stored.
jJ Now it is necessary to place oneself in the time configuration of a critical shifting illustrated by the right-side part of the chronograms in Figure 11, that is to say at the moment of a rear colli,ion between reading impulse lec provided during moment _1 of time slot t31 of the output frame and damping signal tam enframing the storing signal ecr provided at end of time slot IT31 of the input frame, flip-flops FF4 and FF5 being in position 0.
- Gate GAl provides a signal gal of logic level 1, during the simul-.,~
~.;

.

~ o~2~Z3 taneity of impulses Ml, tam and C6.
Gate GA3, whose inputs lec, t'31, IT'31 and gal are at logic level 1, provides a signal ga3 of logic level 1. This signal is retransmitted, in the fo~n of a signal gol of logic level 1, by the OR gate COl to set inpùt of ~lip-flop FF4. This latter triggers to position 1 on the leading edge of signal gol and provides a signal ff41 of logic level 1, to the input of flip-flop FF5.
As soon as the leading edge appears of the next impulse M7, provided during moment m7 of time slot t31 of the output frame, the flip-flop FF5 triggers to position 1. It therefore provides a signal ra of logic level 1 and a signal rr of logic level 0.
, Thus, in the case of a critical shift required by a rear collision, the routing circuit XB routes, in view of their storing into junction memory MD, the coded combination originated from the first input register RA (Figure , 8) towardsthat memory, instead of the coded combinations originated from the second input register RR.
~ In the same way it can be shown that in the case of a critical shift '~ required by a front collision, that is to say a collision between damping impulse tam and leading edge of the reading impulse lec, the routing circuit XB routes, in view of their storing into junction memory MD, the coded combina-tions originated from the second input register RR towards that memory, in-~;- stead of the coded combinations originated from the first input register RA, this operation being preceded, if necessary, by a pre-selection of the input - register RA.
Now will be described, in also referring to Figure 12, the routing ;~ of the bits of the coded combinations in the various elements in Figure 8 during a critical time shifting of the out of memory reading operations when the local clock being faster than the distant clock the storing and reading I operations are performed successively on the same memory address.
. 30 It will first be assumed, as is shown by the chronograms in Figure :, .
12, that the reading operations take place during moment m5, and that the con-trol circuit EX pr~vides a signal ra of logic level 1 and a signal rr of logic ) .. . .

lV828Z3 lcvel 0. Logic gates PA0 to PA7 and PC0 to PC4 are therefore enabled whereas gates PRO to l'R7 and PDO to PD4 are unabled.
~ t thc cnd of time slot IT30 of the rank u input frame, the first -inl~ut rogistcr I~A conta-ins the codcd combination Lt30(U) and the second input rcgistcr RR contains the codcd combination _29(u). At the same instant, counter NT of device CC provides the address of memory cell md30 to the stor-ing addresses decoder DE via gates PC0 to PC4 and PE0 to PE4; register RD is containing the address of memory cell md29.
The storing impulse ecr provided at end of the time slot IT30(u) controls the storing of coded combination _30(u), provided to memory MD by the register RA via gates PAO to PA7, into memory cell md30 and noted _30(u)A
on the chronogram ecr in Figure 12.
Reading impulse lec, provided during characteristic moment m5 of local time slot t30, controls the reading of the coded combination _30(u) stored into memory cell md30 whose address tl is provided by counter DT.
As it was already seen above, a storing control impulse oec is pro-vided after the 0 delay. This impulse controls the storing of coded combina-tion _30(u) into output register RM which contained previously the coded combination _29(u).
An impulse M0 is provided during the first characteristic moment m0 of time slot t31. This impulse causes the storing of the contents of register RM, that is to say the coded combination _30(u), into the second output register RS. This latter enables either the availability of the eight bits of this combination during the 3.9/us of time slot t31, or the retransmission in series form of these eight bits at the rate of 2.048,106 bits per second.
Impulse Ml provided subsequently is without any effect.
Storing impulse ecr provided at end of time slot IT31(u) controls the storing of the coded combination _31(u), originated from register RA, ` into cell md31 of memory MD.
The local clock being faster than the distant clock, the time separating impu]se lec from impulse tam cancels, as is shown by the chronograms in Figure 12, line ct.

~08Z8Z3 The shifting operations are then started and progress during that time slot t31 in the manner already described above.
A rcading impulse lec is provided during moment m5 of the time slot t31. It controls the rcading of the coded combination _31(u) stored in the memory cell md31. In the way already described above, this combination is retransmitted to the output group gps via output registers RM and RS.
The control circuit EX which as detected the collision of the read-ing impulse and of the damping impulse (front collision) controls, on the one hand, the passage of signal rr to logic level 1 - signal ra passing to logic i 10 level O as soon as appears the leading edge of impulse M7 provided during the time slot IT31 - and, on the other hand, the time shifting of the reading operations of m5 to ml, in the manner already described above.
The result is that gates PAO to PA7 and PCO to PC4 are unabled, and that gates PRO to PR7 and PDO to PD4 are enabled. Thus, only the coded combinations stored in the second input register RR can be provided to memory MD to be stored into the cells defined by the five address bits provided by register RD.
; Reading impulse lec provided therefore during characteristic moment ml of time slot tO controls the reading of the coded combination stored into , 20 memory cell mdO, that is to say of combination _O(u).
~ Storing impulse ecr provided at end of time slot ITO(u+l) controls -- the storing, into memory cell md31, of the coded combination _31~u) provided ` ~ by the second input register RR (impulse ecr reference _31Cu)R on the chrono-gram ecr in Figure 12).
Impulse M5 provided during the characteristic moment _5 of time slot tO is without any effect on the operation of the device.
` ~ Reading impulse lec, provided during moment ml of time slot tl, con-trols the reading of coded combination _l(u) stored in memory cell mdl; and the operation of the device of present invention proceeds in the manner al-ready described above.
Thus, collision of the reading signal and of the damping signal has been detected and has brought a shifting of the reading operations of _5 to ml. As the case has been here of a critical shifting intended to bring about a do~lblc roading of the rank (u~ frame, the routing circuit XB (Figure 10) has controlled the rctransmission to memory MD of the coded combinations originatcd from thc second input register RR instead of the combinations originated from the first input register ~.
In this way, in case of reverse jitter of the considered derivation of one clock with respect to the other - that is to say a phase derivation which can be represented by a shifting to the right of chronograms t and lec in Figure 12 - the new phase margin _~ is equal to the preceding phase margin _~ increased by a time slot (3.9~us).
Therefore, when the local clock is faster than the distant clockJ
and in the case of a critical shift - that is to say a time shift bringing about the double reading of one same frame - the process and the resynchroniz-ing circuit of present invention enable increasing the phase margin of reverse jitter, by a time slot at the price only of a double storing into memory of a coded combination (_31(u) in the example chosen here).
Now will be described, in short, the operating process of the circuit of present invention during a critical shift, the local clock being slower than the distant clock ~rear collision), by also referring to the chronograms in Figure 13.
It was seen above (chronograms in Figure ll) that such a collision . would cause the preselection of input register RR during time slot tl5. It is assumed therefore that this preselection has been performed and that the `~ signal rr is at logic level 1.
~` The coded combinations which are stored into memory MD are therefore the coded combinations originated from input register RR.
Thus, storing impulse ecr, provided at end of time slot IT31 of the rank w input frame, controls the storing of coded combination _30(w), ori-ginated from register RR (impulse ecr referenced it30(w)R on the chronogram ` 30 ecr in Figure 13) into memory cell md30 identified by the five bits originated from register RD.

~` Reading impulse lec, provided during characteristic moment ml of ., lV82823 .

time slot t31, controls the reading of the codcd combination stored in memory ccll md31 therefore of the combination _31(w-1).
Storing impulse ecr, provided at end of time slot ITO(w-l), controls the storin~ of coded combination _31(w), provided by input register RR, into tho memory cell md31.
Control circuit EX, which has detected the collision between the damping impulse tam and the trailing edge of the reading impulse, proceeds with the time shifting of the reading operations from _l to _5 and routes towards memory MD the coded combinations stored in the first input register RA.
Thus, leading edge of impulse M7, provided during characteristic moment _7 of time slot t31, controls the triggering of flip-flop PF5 of the circuit XB (Figure 10) into position 1. Signal rr passes to logic level 0, signal ra passes to logic level 1.
Impulse Ml, provided during moment _l of time slot tO, is without ?
any effect on the operating process of the system.
Storing impulse ecr, provided at end of time slot ITlCw+l), controls the storing of the coded combination _l~w+l), originated from input register RA (impulse ecr referenced _l~w+l~A on the chronogram ecr in Figure 13), into memory cell mdl.
Reading impulse lec, provided during characteristic moment m5 of - time slot tO, controls the reading of contents of the memory cell mdO, that is to say of combination _O(w).
Operation of the circuit in present invention proceeds then normally in the manner already described above.
The new phase margin ~ in case of reverse jitter is defined by the time separating the leading edge of the reading impulse pro~ided during the time slot tl, for instance, of the trailing edge of the damping impulse enframing the storing signal ecr of the coded combination _l(wll). It is therefore superior by a time slot (3.9 ~s) to the phase margin m~ which would have been obtained without the changement of input register, this margin m~
being defined by the time separating the leading edge of the reading impulse, . .

.

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~OB2~Z3 provided during the time slot tl, for instance, from the trailing edge of the damping impulse enframing the storing signal of the coded combination _2(w+1) originatcd from rcgistcr RA, which, without changement of register, would in-docd havc bocn thc storing signal of the coded combination _l(w~l) originated from rcgistor RR .
Then the only perturbation brought about by this changement of register is the absence of storing into memory of the coded combination _0(w+1) - that being of little importance - this combination being all the same operated by the supervision block SB. Indeed, the reading skip of the frame w is inherent to the time shift of the reading operation and is inevit-able in asynchronous operation.
In the above description, it was assumed that impulse tam enframes the storing signal ecr. Operating process of the device in present invention ~, would be identical in the case where a damping signal enframing the reading signal lec would be used.
Likewise, without departing from the scope of present invention, shlfting of a channel time slot of the reading operations can be considered, the coded combinations stored in the junction memory still being the combina-tions originated from the first input register RA.
; 20 It is clearly understood that the preceding descriptions are made only by way of unrestrictive example and that numerous alternatives may be considered without departing from the scope of the invention. More particular-ly, the numerical details have been given only to make the description easier and may vary with each case of application.

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Claims (5)

WE CLAIM:

1. A synchronizing circuit for a time division multiplex system having an exchange in which a series of plural bit words is received during successive time frames comprising a time slot for each word with each bit being received serially during a time element of a time slot and with each word being received at the clock rate of a distant office from which the series of words is transmitted, each word being forwarded within said exchange at a local clock rate of the same duration and extent as the clock rate of the distant office, said circuit including a memory for storing therein a word in parallel form in response to a storage signal based on said distant clock rate during a time element thereof, means in said exchange for sensing the occurrence of a storage signal, means responsive to a read signal during a preselected time element for reading a bit from said memory, means for comparing a check signal derived from said storage signal but longer in duration than said storage signal against said read signal for reading a word from said memory to ensure that only one word is read during a time slot, means responsive to a condition in which a check signal coincides with a read signal for shifting said read signal to a time element spaced in time a predetermined plural number of time elements from the present time interval, and means for causing reading of words at successive shifted time elements of subsequent time slots to prevent reading and storing of words at the same time.

2. A synchronizing circuit as claimed in Claim 1, in which said comparing means comprises a gate circuit, said shifting means comprises a second gate circuit and a bistable member, and said causing means comprises a further bistable member.

3. A synchronizing circuit as claimed in Claim 1, in which there are further gate circuits for restoring said read signal to said preselected time element on coincidence of signals at said shifted element.

4. A process for preventing coincidence of writing operations into and reading operations out of a plural bit memory within a time division controlled system in which each operation occurs in a certain time element within a plural element time slot, in which the writing operation is controlled by one signal generated by one clock and the reading operation is controlled by a signal derived from another clock, and in which a write control signal is generated to control the writing operation and a read control signal is generated to control the reading operation during a preset time element, and in which the control signals are spaced apart with the clocks in synchronism, the process including the steps of deriving a check signal from the write control signal with the check signal extending for a like time period before the start of and after the end of the write control signal, feeding the check signal for a coincidence check against a read control signal, and for responding to a coincidence of the last-mentioned signals for shifting the read control signal to another predeter-mined time element within the time slot, with the other time element spaced from the check signal by more than one time element when the clock derived signals are in synchronism, and for maintaining successive read control signals at like predetermined elements within subsequent time slots.

5. A process as claimed in Claim 4, in which a coincidence check is continuously made between check signals and the read control signal for shifting the read control back to the preset element.