CA1080847A - Charge coupled circuits - Google Patents

Abstract

Abstract Charge coupled circuits which may be arranged in arrays and interconnected to form long registers of either the open-ended or the circulating type. Features of these circuits include new electrode structures which permit close spacing between electrodes, self-alignment of electrodes of very small size and which may be layed out to achieve high packing density. They also permit two or higher numbers of voltage phases to be employed for unidirectional charge signal propagation. The circuits also include improved structures including a floating junction for coupling one register to another for charge regeneration and for reset purposes. Biasing arrangements are employed for optimizing the amount of charge to be propagated and for providing potential wells of a contour to insure unidirectional signal propagation. Additional features of a circuit are discussed in detail below.

Description

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RC~ 63,6~6 The present invention is directed to charge cou~led devices and may he particularly useful in serial reg;sters.
The use of charge coupled devices is described in the papers, W.S. Boyle and G.n. Smith, "Charge Coupled ~emiconductor Devices", Bell System Technical Journal, April 197~, page 587, and G.F. Amelio, ~.~. Tompsett; (~.F. Smith, "Experimental Veri-fication of the ~harge ~oupled ~evice Concept" page 59.~ of the same periodical; and M.F.Tompsett, G.F. Amelio and ~.F. ~Smith, Charge Coupled ~-Bit Shift Register", Applied Physics Letters, Vol. 17, 3,p. 111, A~gust 1970,discuss charge coupled semi-conductor devices. ~harges are stored in potential wells created a~ the surface of a semiconductor and voltages are em-ployed to move the charges along this surface. In more detail, these charges are minority carriers store~ at the silicon ~S;)-silicon-dioxide tsi~2) interfaces of M~S capacitors. They are transferred from capacitor-to-capacitor on the samë subst~rate by manipulating the voltages across the capacitors. ~`
- The present invention may be practiced in a circuit-having a substrate formed of a semiconductor material ` 20 of one conductivity typé-- ~ According to a preferred emhodiment of the in-vention, the circuit fiurther includes a source of charge carriers comprising a region of other conductivity type con-tacting the substrate, and means close to the source for forming a potential well in the substrate into which carriers from the .., source may flow. ~he circuit also includes a means coupled to said source for controlling the flow of charge carriers from ~ ; said source ~o said poten~ial well, and means for reverse j biasing the source relative to the suhstrate.

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1 According to another preferred emhodiment oF the invention, the circuit includes means responsive to a ; single pulse for creating a potent-ial well in the suhstrate which is substantially deeper at one edge of said well, than a~ the opposite edge of the well.
According to another preferred emhodiment of the invention, the circuit includes a plurality o-f rows of a relatively thin insulating layer formed on said suhstrate, with each such row defining a length of the substrate a~ong lo with charges are to proPagate. The circuit further inc]udes a plurality of electrode means adjacent to one another along thè length of each row. Each such means creates an asymmetrical potential well in the s~hstrate which is substantially deeper at the portion of the well facing the desired direction of signal propagation along the length of its row than the portion of the well facing opposite to the desired direction of signal propagation.
The circuit also includes means for ap~lying one phase of a two-phase shift voltage to alternate electrode means of each row and the second phase of the shift voltage to the other eIectrode means of each row.
According to another preferred embodiment of the invention,~the circuit includes first and second spaced ;~
: regions contacting the suhstrate~ hoth formed of a semicon~uctor material of a conductivity type different than that of the substrate, means for maintaining the first ~ .
region at a Potential such that it is availahle as an acceptor ~ of minority charge carriers and a control electrode spaced ,~ from the suhstrate and extending hetween the regions for controlling the flow of minority charge carriers from the ~ 3 .

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1 second to the first region. The circuit also includes means coupled to the substrate for placin~ a minority carrier charge at the portion of the substrate at which the second region is located an output terminal connected to the second region at which a signal maY he sensed, and means for applying a signal to the control elect~ode of a sense to cause any charge present at said region to pass to the first region and the second region thereupon to become reset to a reference voltage level.
lo According to another preferred emhodiment Or the invention, the circuit includes a pair of charge-coupled shift registers, means for concurrently shifting charge signals through one of the registers and complements of these charge signals through the other o-f the regis~ers~ 15 Wherein the circuit further includes a différential signal detector coupled at one input terminal to a stage of onc of the registers and at its other input terminal to a correspon~ing stage of the other of the shift registers.
According to another preferred embodiment of the invention, the circuit inclu~es first and second reIative]~
closely spaced region in the suhstrate of opposite conduc-- ~ tivity than the substrate, means coupled to the sccond ; ~ region for creating in the suhstrate during one time ;nterval -~ a conduction path extending from said second region to a ~`
reference potential source (~+) for resetting the second region to a reference voltage level. Also included is electrode means coupled to the second region and to the portion of the suhstrate extending het~een the first and .
second regions for resetting the first region during a ~ 30 ~

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second time interval to a voltage level.
Another preferred emhodiment of the invention, may be in a method of propagating a charge at high speed ; from a potential well in a substrate beneath one electrode S to a region of the suhstrate beneath an adjacent electrode.
This method is compriséd of spacing the electrodes a distance apart w~ich is not greater than the spacing of the electrodes from the suhstrate and creating in the suhstrate beneath the adjacent electrode a depletion depth comparable to the electrode width.

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RCA 63,696 1 In the cletfliled description o the invention which ~ollows, reference is made ~.o the drawings accompanyin~ and forming a part o~ the present s~ecification and in which;

FIGURE l is a schematic showing, partially in block form and partially in cross-section 9 0~ a portion of a system embodying the invention;
FIGURES 2 and 3 are bIock circuit diagrams o~
different systems embodying the invention;
FIGURE 4 is a cross-section showing the input end of a shift register according to one form o~ the in-vention; ~ .
FIGURE 5 is a drawing of waveforms present in : the circuit of FIGURE 4;
; FIGURES 6a through:6e are drawings showing the ~ .
potential wells which are formed in response to various voltages applied to the circuit of FIGURE 4;
FIGURE 7 is a schematic showing in cross-section of another form of input end of the system embodying the invention;

:: FIGURE 8 is a drawing o~ wave~orms employed in ;

the operation o~ the circuit of FIGURE 7;

FIGURE 9 is a more realistic cross-sectional view through a portion of a shift register according to one embodiment of the invention;
FIGURE lO 1s a schematic cross-sectional view through another embodiment of a shift register embodying : 30 the invention;

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RCA 63,696 ~7 I FIGURE 11 is a more realistic cross-sectional ~ view of the form of the invention shown in FIGURE 10;
: FIGURE 12 is a cross sectional view of another ' form of shift register embodying the invention;
FIGURE 13 shows both waveforms and potential - wells and is employed in explaining the operation of the circuits of FIGURES 9 through 12;
FIGURE 14 is a plan and partially schematic view of a two-dimensional shift register array according to another embodiment of the invention;
FIGURES 15 and 16 are cross sections taken along : ~ :
lines 15-15 and 16-16, respectively, of FIGURE 14;:, , FIGURE 17 is a plan and partially schematic view : of another form of two-dimensional shift register array .
~embodying the invention;
~- FIGURES 18 and 19 are cross-sections taken along lines 18-18 and 19-19, respectively, of FIGURE 17; ~ ~
FIGURE 20 is a plan view of another form of a :
, : shift reg~ster embodying the invention; ~~
FIGURE 21 is a plan view of a portion of a multi-. -~ channel shift register embodying the invention;
FIGURE 22 is a cross section taken along line . . . .
22-22 of FIGURE 21;
FIGURE 23 is a plan view of a portion of another form of shift register embodying the invention; ~:
., FIGURE 24 is a cross-section taken along line - 24-24 o~ FIGURE 23; ~:~
FIGURE 25 is a plan view of a portion of another form of shift register embodying the invention;
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1 FIGURES 26, 27 and 28 are cross-sections taken along lines 26-26, 27-2~, ~nd 28-28, respectively, of FIGURE 25;
FIGURE 29 is a schematic, cross-section through one form of coupling structure embodying the invention for a three-phase shift register system, that is, one form of structure for coupling the output end of one register to the input end of a second register;
FIGURE 30 is a drawing to illustrate the propaga-tion of charge in the circuit of FIGURE 29;
FIGURE 31 is a drawing of waveforms employed in ~ :
the circuit of FIGURE 29; : -FIGURE 3Z is a schematic cross-section showing ~:
: another form of coupling structure embodying the invention, ~:
this one for a four-phase shift register system;
FIGURE 33 is a drawing of waveforms employed in the operation of the circuit of FIGURE 32;
FIGURE 34 is a cross-section of another form ot : : coupling circuit embodying the invention;
: 20 FIGURE 35 is a drawing of waveforms employed in ~ the operation of the circuit of FIGURE 34;
.
FIGURE 36 is a drawing to help explain the operation of the circuit of FIGURE 34;
FIGURE 37 is a more realistic showing of another ?5 form of coupling circuit embodying the invention, this one for a four-phase shift register system;
FIGURES 33 and 39 are cross sections showing mod1fications in the input circuit of the receiving register of FIGURE 37;

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I FIGURE 40 is n cross-section of another form of coupling circuit embodying the invention, this one operated by a 2-phase voltage swpply;
~ FIGURE 41 is a drawing of waveforms employed in : 5 the operation of the circuit of FIGURE 40;
: FIGURE 42 .is a plan view showing how the circuit I of FIGURE 40 may be layed out;
: FIGURE 43 is a cross-section through another form of coupling circuit operated by a 2-phase power supply;
FIGURE 44 is a drawing of waveforms employed in ;: the operation of the circuit of FIGURE 43;
FIGURE 45 is a plan view of how the circuit of FIGURE 43 may be layed out; .
FIGURE 46 is a block and schematic showing of another form of coupling circuit embodying the i:nvention;
FIGURE 47 is a block diagram showing a coupling circuit for a form of the circuit such as shown in FIGURE
21;
FIGURE 48 is a cross-sectional and schematic showing of the actual structure of the circuit ot' FIGURE
: 47;
FIGURE 49 is a schematic showing of nnother form of the circuit of FIGURE 47 may take;
FIGURE 50 is a cross-sectional and schematic 25~ showing of another form of coupling circuit embodying the invention;
FIGURE 51 is a schematic drawing showing both a circuit for coupling the output end of one register to the - input end of another register and input-output circuits :30 for tbe system;

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I FIGIIR~S 5?a-h are a grou~ of sketches to help explain a method of fabricating the systems shown above. Be-Fore descrihin~ the invention in detail, genéralized explanation of an overall svste~ is offered. In the explanation, a serial memory made up of a plurality o~ shift registers and which can he operated a.s a circulating memory is usecl as an example. This discussion is followed by a more ~;
detailed discussion of (1) the input end of the system;
(2) the middle of the sYstem; ~3) the coupling between the lo shift registers of the system; ~4) the output end of the system; (5) general considerations in the design of charge-coupled shift circu~s; (fi) considerations for high-speed operation; and (7) methods of fabrication.
The common substrate 10 of FI~ttRE 1 is shown in two IS parts for ease of illustration. The suhstrate is formed of a semiconductor such as n-type silicon. nther alternatives, discussed later, are possible. A thin ilm o insulating material such as one forme~l of sil;con dioxide ~sin2) is located on the portions o~ th~e surface of the semiconductor suhstrate under which the charge signals move. The actual thickness may he - ~ rom 500 to 2~0n Angstroms (A). The remaining ~ !

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1 regions of the silicon sur~ace (not sh~wn) may be covered by a thick SiO2 layer, perhaps 10,000 A or more thick.
A plurality of conductive plates or electrod~s 14-0, 14-1, 14-2 . . . 14-(n+l) ~ormed of a metal such as aluminum are located on the silicon dioxide layer. A
source of charge carriers Sl is located in the substrate 10 and in close proximity to the control plate or electrode 14-0 and another means Cl including a collector o~ charge carriers is located in the substrate in close proximity to the control plate 14-(n+l). The source Sl and means Cl are shown only as rectangles in FIGURE 1. Their actual structure is shown in following drawings and is discussed `
later. The complete structure acts as a shift register in a manner shortly to be discussed.
A second shi~t register similar to the ~irst is located adjacent to the first shi~t register. It includes a source of minority carriers S~, a plurality of eonductive plates 16~0, 16-1, 16-2 and so on located on the silicon dioxide surface 12 and a means C2 which may have the same structure and function as the means Cl located adjacent to - the control plate 16-(n~
The output terminal 18 of the first shift register is connected to the input circuit of the second shift - register by a signal regeneration circuit. This signal re-generation circuit may include simply a single connection, hetween the two re~isters shown hy dashed line 171, or in-stead may he an externa] circuit il]ustr~ted hy hlock 19, coupled hetween the two registers. The outPut léad 18-1 of the second shift register may be coupled to the input terminal of the following shift register (not shown). This :.

I coupling may be accomplished in the same manner as already discussed. Altern~tively, the output lead 18-l may be coupled via a regeneration circuit to the source of char~e carriers Sl to provide a circulating memorY. As a third alternative or ad~itionally the output lead 18-1 may be the output terminal of the system. These various alt~rnatives are discussed shortly in connection with FI~IJ~F/S 2 and 3.
The information supplied ~o the serial memory of FIGlrRE 1 may be propagated from stage to stage hy a multiple-supply a 3, 4 or higher phase signal hut preferahly it is a 2-phase voltage source as this permits the structure of the memory to be more compact and, under some conditions, to be faster. Howèver, the use o~ a 2-phase voltage source does not naturally provide unidirectlonal signal propagation.

The arrangement of FIGURE 1 also includes various~
direct-voltage bias means. These are not shown in FIGURE l but are shown in later figures and their function is dis~
cussed in the explanation of these figures.
Before discussing the operation of the FIGURE 1 arrangement, lt is in order to conslder the general theory ~ ;~
of operation of charge coupled devices. If a negative voltage pulse is applied to a plate or electrode such as :
2, there is for~ed a so-called deep depletion region in ~` 25 the portion of the n-type substrate immediately beneath this~
electrode. In other words, the applied negative voltage pulse ropels majority carriers, electrons in the case of ;~n n-type su~str;lte, from the surface of the substrate directly under the electrode such as 14-2. This causes a 3 potentlal well to be formed at the surface of the n-type ~ . . . .. . .
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1 ~ilicon which corresponds to the induced depletion region.
The depth of the potential weLl i~ proportional to the square of the depth o~ the depletion region. The higher the substrate resistivity, the gr~eater the depletion depth for a voltage pulse o~ given amplitude. The thicker the layer of silicon dioxide beneath the electrode, the ; -shallower the depletion depth for a given voltage amplitude applied to the electrode.
Any potential well formed at the sur~ace of the silicon substrate will tend to accumulate minority carriers (holes in thi~ example). If available from no other place, they will come ~rom the substrate itself. In this case, the carriers are thermally generated and are produced mainly by a surface generation process. They ~orm an in~

ver~ion layer at the surface of the silicon substrate in which the potential well is ~ormed in a time of the order of one second. In other words, the potential well created beneath the eiectrode in response to a negative voltage pulse "naturally" becomes ~illed with minority carriers.
The amount of charge that can be collected in such a potential well is equal to the charge required to sub-;~ stitute for the number of previously "exposed" immobile ~ i ions (ions which previously have given up charge3 in the deep depletion region plus the additional charge accumulated in response to the capacitance between the substrate and ;; ~the said elect~ode. ~ ~ "
In t~e preferred embodîment, shown ;n figure l thermal generati~n of charge carr;ers iS not depended upon to `~
provide the charge Which is ;ntroduced into a potential well 30 as a signal. Instead, a source Sl is employedJ which source~
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1 may be a heavily dop~d p~ region locate~l in th~ substr~Ltc, ~s will be discussed in more detail shortly. rn resJ~onse to a voltage Vc applied to the control plate 1~-0, whLch voltage is more negative than the source potential~ and a negative v~lta~e applied to the electrode 14-1 whose leadin~ edge may overla~
; the lagging edge of the voltage ~Vc (or simply by ~pplying a voltage pulse Vc to electrode 14-n which is in time coinc;-dence with the voltage applied to electrode 14-1) an i.nversion layer is formed hetween the source ~1 and the ~otenti~]. w~ll created beneath the electrode 14-1. ~harge carriers travel from the source through thIs inversion layer or "channel"
created under the 14-n electrode into the potential well ~e-neath electrode 14-1 very rapidl.y, in a time of the order of from ones to tens of nanoseconds with appropriate circuit ` 15 design. Control of the passage of this charge may be via the ~
control plate 14-0 and, alternatively, or in addition, the ~.
: source itself may be pulsed as will be discussed shortly. ~; :
The storage of charge under ~n electrode or plate may represent the presence of a binary digit (bit) such as "l". The absence o~ charge carriers in the region of a substrate beneath an electrode may represent storage of the bit "O". Other alternatives are also possible and will be :~
- discussed briefly later.

In the arrangement of FIGURE l, charges are tran~erred from one potential well to the next, that is, from the region of the substrate beneath one electrode to the region of the substrate beneath the next adjacent electrode by multiple-phase voltages. In other words, the ; transfer occurs under the influence of an electrical field which may be re~erred to as dri~t field. Another mechanlsm ' : ' -, ,. . , ~ , :

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" -, , r~cl\ fi3,696 34iif 1 that may be involved in the transeer of charge from ~capacitor" to "capacitor" (where a capacitor may be con~
sidered to be an electrode such as 14-1, the region ot the n-type semiconductor substrate beneath this electrode, and the silicon dioxide layer separating the two) is diffusion which in the case of charge coupled devices, normally al90 results in an induced drift field. As will be discussed brlefly later, for high speed operation the ctlarge coupled circuit should be designed to operate under the influence of the drift field rather than diffusion.
When a charge reaches the last electrode 14-n of the shift register it may be sensed and the sensed signal employed to control the passage of charge to the input ~ stages to the next register. Involved in the transfer are .~- 15 a control plate 14-(n+l) and structure within the means Cl. The function of the means Cl is to detect the presence~
of charge by producing a voltage level that can regenerate the signal in the second shift register and to remove the ~ , charge signal from the first shift register. As one example, a floating junction within Cl may be employed to couple a signal to the control plate 16-0 for permitting the source - S2, or not, to transfer charge to the region beneath the - electrode 16-1 when an appropriate negative voltage pulse ~ ~ , is applied to the plate 16-1 from source 20. This connec- `
25 tion is illustrated by the dashed line 171 or by 18, 19.
In the former case, the connection is such that the comple~
ment of the bit present at 14-n is transferred to the region under 16-1. In the latter case, either the bit or its ~; ;
complement may be transferred. All of this will be dis-; 3 cussed in greater detail later~

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RCA 6~,696 ~0~0~34~

1 FIGURE ~ shows schematically one form tha-t a system of shift registers may take. The shi~t registers are connected end-to-end through signal regeneration circuits to provide one large ring. These are use~ul in many data processing applications such as large capacity serial memories, and large circulating registers o~ this type are use~ul also: as refresh memories for cathode-ray tube displays; in communication applications; and in video processing applications. The circuit of FIGURE 2 also shows schematically an input-output circuit 20 whic'h in-cludes means for accepting new information and means ~or supplying output information. Circuit details are ; ~ illustrated and discussed later.
-~ The system of FIGURE 3 is arranged in a different way. Here each pair of shift registers forms a ring which, depending upon the size of the shift register, may store from say 32 to 256 bits. The signal regeneration and control circuits 21 may include decoder means responsive to the signals on address lines and control means responsive to signals present on the control lines. The circuits may ~ be`of the same type as employed in a memory. They may be (~ used to permit readout of the bits stored in any loop. As an alternative, the various ring connected registers may be considered to be analogous to the tracks of a drum memory ;~ 2S and the bits read-out in parallel. It is to be understood - that here and in FIGURE 2 the multiple-phase voltage source, while not explicitly illustrated, is implied.
Although not spec1fically referred to in the following text, the charge-coupled structures and circuits ~ ~30 to be described are also useful in random access charge ,:;
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~C~ 63,~96 ~ t7 1 storage memories and self-scanned photosensor arrays. In the latter application, the light signal (rather than an electrical pulse) may be employed as the source of charge carriers for the charge-coupled shift register. In the two-phase structures described in more detail later, the light input may be applied to the polysilicon electrodes and the system operated as a self-scanned photosensor array. In these uses~ if an analog output signal is desired, it can be obtained from a common drain region fed 10 by parallel charge-coupled shift registers shifting the signal in only one direction. A simple selection of the desired row in an array is possible if one of the multiple phase voltages is unconditionally applied while the other one of these voltages is applied only to the selected row.
Tbis one phase is varied between a direct voltage level at which a shallow potential well forms and a voltage at which . .
` a deep well forms so that at the electrodes receiving this one phase, a potential well always is present which fluctuates between two levels. The light generated carriers 2G thus accumulate at these electrodes and, when desired, they (the stored carriers in a row) can be shifted to an output terminal by the application to the row of the other phase(s).
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Input End of the System In the prior art, the source of charge carriers (Sl in FIGURE l) for the charge-coupled shift register was described as a gate controlled PN junction (for an n type substrate, a p+ region) operated at the substrate potential.
In the operation of the shift register, the signal charge 3 was transferred from this p+ region to the first potential ,: .

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, I well by the applicatlon of a negat:ive pulse (corresponding to Vc of FIGURE 1) to the gate electrode such as 14-0 in FIGUR~ 1. To control the amount O:e charge to be introduced into the first potential well, careful control of the magnitude and duration of this app:Lied voltage V~ was required.
In charge coupled devices, during the prop~gation of charge from the source to the potential wel.l bene~th the first storage plate (such as 14-1 in FIGURE 1) and later from the region of the substrate beneath one storage plate to the region of the substrate beneath the next adjacent plate, the rate of flow of charge is dependent upon the amount that the potential well of the next adjacent plate is to be filled. Thus, for example, i~ there is charge ~ :
.~ l5 present under plate 14-2 (FIGUNE 1) and this charge begins ;;
: to flow into the "empty" depletion region beneath plate 14-3, initially the charge flows very rapidly. However, .
j. .
as the charge fills the region beneath the plate 14-3 to a ~ -greater and greater extent, it becomes more and more ~: 20 difficult for additional charges to enter. The reason is ~ -that as the well becomes full, the surface potential of the well gets closer to that of the substrate ($he difference ;.
in potential decreases). Moreover, the present inventor ~.

has discovered that if it is attempted comple-tely to fill each well from the preceding one, som0 charge tends to ` remain in the preceding well. This residual charge in the case in which the next bit to be transferred to the pre-~: ~ ceding well is to be a 0 (the absence of the charge), adversely affects the signal-to-noise ratio as it tends ~ ~ to make a stored 0 look like a stored 1. This effect :~ , . . .
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~: -RCA 63,696 1 ls cumulative and with a large nu~lber of stages becomesquite serious.
~ ne aspect of the preferred e~hodi~ent reslrl~s in the means for obtaining a desired degree o:t' partial ~illing of the first potential well (the well under plate 14-1) substantially independently o~ the magnitude o~ the voltage applied to the control electrode 14-0 (as long as the amplitude o~ the control pulse Vc i~ sufficiently large).
The details of how this is done are given shortly a~ter - 10 the description of the structure.
FIGURE 4 should now be referred to. The source of charge carriers Sl consists o~ a conductive line ~ormed in the n-type silicon substrate. This structure may be made by diffusing a substantial amount of p-type material such as boron into a restricted region of the substrate.
This makes this region of the substrate relatively highly conducting and a good source o-P positive charge carriers.
The n-type silicon substrate is maintained at an elevated ;~ voltage such as +5 volts. The reason is to deplete the Z surface of the silicon adjacent to the silicon dioxlde layer - the surface along which charge carriers representing the signal move during the operation o~ the register. This biasing tends to eliminate the loss of signal due to surface recombinations by not allowing the majority carriers (electrons in this example) o~ the silicon substrate to come to the sur~ace to reset the traps ~or the minority carriers (holes in thls example) that represent the signal.
In order to achieve control o-f the -filling of the ~ potential wel], the source S] is not tied to the same po-;~ 3 tential as the substrate, it is instead reverse biased :, .

RC~ 63,696 to the extent o-f say -5 volts with res~ect to groun~ lO

~ volt~ with res~ect to the substrate) As will he shown .~ . .... . .
shortly, this reverse hiasing, together ~hth the choice oF
pulses Vc and ~l of appropriate amp]i~uc1e and timing, ;nsure that the potential well created ~eneath the f;rst ~late 14-l fills only to a predetermined level, which may be only a fraction of the capacity of this potential well.
In the discussion which follows of the operation of the portion o~ the system shown in FIGURE 4, FIGURES 5 and 6a-6e should be referred to. The quiescent potential conditions, that is, the conditions before time to f -`
; FIGURE 5 are as illustrated in the FIGURE 6a. The well ` beneath the source region Sl, which region is at -5 volts, ~ is deeper than that beneath the plates l~-O and 14-l so ~-- l5 that the charge carriers in Sl remain in Sl.
When a negative voltage pulse Vc, such as one of an amplitude of -lO volts, is applied to plate 14-0, an inversion layer, 23 in FIGURE 6b, is formed. This layer extends from the p+ region Sl, along the surface of the silicon substrate beneath the control or gate electrode -~ 14-0. This inversion layer or conduction channel is analogous to the conduction channel which is formed when the gate electrode of a metal-oxide-semiconductor (MOS) transistor is forward biased. The condition necessary for 1 25 forming the conduction channel is that the negative voltage ~- applied to the control electrode 14-0 be more negative than the bias vol$age at which the source electrode is maintained by an amount which e~ceeds the threshold voltage Vt of the n-type substrate. This threshold voltage Vt is 3 the same parameter as the similarly termed parameter in the - 2n -. . : .

RCA 63,696 ~` ~L[)8()~7 1 metal-oxide-semiconductor transistor art. The conduction of the induced inversion layer 23 is proportional to the difference between the applied voltage Vc and (Vt -~ Vs )~
where Vs is the source potential.
The input pulse Vc must be concurrent with the ~1 pulse to transfer the charge signal into the ~irst potential well. The following example illustrates the case in which the lagging edge of pulse of Vc overlaps the leading edge of pulse ~1 and pulse Vc terminRtes before -, 10 the ~1 pulse terminates.
As indicated in FIGURE 5, at time tl, while the - control voltage Vc is still present, the leading edge of ; the negative pulse ~1 applied to the first plate 14-1 occurs. This pulse may be more negative than the control voltage and in the present example is shown to be -15 volts in amplitude. The resulting operation is depicted schematically in FIGURE 6c. The negative voltage applied to plate 14-1 causes a potential well to form in the region of the substrate beneath this plate. The minority carriers, positive charges in the present instance, there-upon flow from the souroe Sl, through the induced con-duction channel 23 beneath the control electrode 14-0, to the~ potential well under the electrode 14-1. This flow of charge continues only until the surface potential beneath the i'irst electrode 14-1 reaches the potential of the source Sl (provided that sufficient time, of the order ,i of nanoseconds, is allowed -for this process). Thus, i~
th~ dirl'elell~e l)e~weell thc soul~ce voltage alld tl~e control ~ voltage Vc is sufficiently large (in this example 5 volts is used but a smaller voltage dif~erence also would be : : . . . .

RCA 63,696 ~8V~34~
1 suit~ble), the first potential well may be filled -to the desired level. This desired level may be only a fraction of the capacity of the potential well and, as contrasted with the prior art, is precisely controllable without the necessity for accurate control either of the duration or amplitude of the control pulse Vc.
FI5URE 6d illustrates the operation at ti~e t2 which is after the termination of the control pulse Vc but before the termination of the pulse ~. Note first that as the control electrode 14-0 is at 0 volts, that is 9 is more positive than the source Sl, the conduction channel is of high impedance. Thought of in another way, the charge carriers stored in the potential well beneath the first storage plate 14-1 see a potential hill that prevents their escape back to the source. Thus, these charges remain stored under the plate 14-1 until they are shifted ~ by the next voltage phase ~ to the following plate 14-2.
- This will be discussed shortly.
The description above covers the writing of a 1 - 20 into the first stage of the shift register. To write 0, no voltage pulse is applied to the control plate 14-0 during the period to ~ t3. The result is that as long as the surface potential under the gate electrode is more positive (actually less negative in this example) (by about one volt) than the potential at which the source is maintained, no charge will be transferred from the source to the first potentinl well. (The value of one volt pro-vides ;l ~noLe than sufficient potential barrier to prevent the transfer of charge by the process of diffusion and 3Q also provides a safety factor to take into account . . _ .

RC~ 63,696 ~638~

I variations in the device parameters.) The operation above is depicted ln a number of the figures. FIGURE 6a still represents the quiescent circuit condition. At a time between to and tl~ the situation is still as depicted in FIGURE 6a. As the control plate 14-0 is still reverse biased with respect to the source, no inversion region ~orms beneath the plate 14-0. At a time such as t2, the situation is as depicted in FIGURE 6e. While there is a potential well created beneath the first plate 14-1, no charge carriers can flow from the source into this potential well in view of the fact that the control plate is still at 0 volts. As already mentioned, no charge present under plate 14-l represents storage of a 0.
A second form of input circuit according to the ; invention is illustrated in FIGURE 7. The difference between this circuit and the FIGURE 4 circuit is that in ~ the FIGURE 7 circuit the source Sl is normally sufficiently ;~
; reverse biased (to the extent of -15 volts with respect to the substrate, -20 volts with respect to ground in this , example) that in its quiescent condition, the source does not act as a source of minority charge carriers for potential , ~ .
wells with higher surface potentials than the source. In fact, any such bias may make the source region act as a sink (drain electrode) for the charge carriers present in a potential well. The source may be "turned on" by applying a voltage pulse V3 to the source, at an appropriate time, as illustrated in FIGURE 8.

In the operation of the arrangement of FIGURE 7, in the absence of a pulse V3, the pulses Vc and ~l transfer :
~, , . ..

~ .
... , , :

:- i RCA 63,696 ~08(~9L7 1 a 0 (no charge) to the potential well beneath the lirst storage plate 14-1. However, in the presence o~ a posi-tive ; pulse V3 during the pulses ~ and Vc~ a 1 is stored uncler the ~irst plate 14-1.
The timing of the pulses o~ FIGURE 7~ shown in FIGURE 8, is of interest. At timle to the ~1 pulse is applied to storage plate 14 1. This causes a potential well to form beneath the ~irst plate 14-1. Shortly after the start of the pulse ~1~ that is, at time tl, the control pulse Vc starts. This causes a potential well to -t'orm beneath electrode 14-0 which connects to the potential well beneath the control electrode 14-1. As no charges are yet available at Sl no inversion layer or conduction channel is yet formed. Shortly therea~ter at time t2 the positive pulse V3 is applied to the source Sl. This pulse may have an amplitude o~ 10 volts so that Vsl has a swing from -15 volts to -5 voits. The conditions are now exactly the same as depicted in FIGURE 6c - a conductive channel is formed ~rom Sl to the potential well under electrode 14-I ~nd the .
positive minority charge carriers ilow from the source and partially fill the potential well beneath plate 14-I to the known-in-advance ~raction o~ its capacity. The lagging ~, ' edges o~ the pulses occur as shown in FIGURE 8, pulse Vc - terminating before the other pulses to prevent the reverse flow o~ charge, that i~, back irom the partially ~illed well under 14-1 to the source Sl.

An important feature of the circuit o~ FIGURE 7 is that the timing o~ when the charges are introduced may be precisely controlled by controlling the timing oi the pulses V3 and Vc with the pulse sequence as shown in ,~

. . .
,, . , :

RCA 63,696 FIGURE 8. In the general case, the pulse Vc provides the tlming while the source potential Vsl determines the level to which the ~irst potential well i9 filled (or emptied).
In this general case, the timing is such that the entire pulse V occurs within both pulse V3 and the pulse ~
In the embodiments of the input circuits discussed so ~ar, a signal such as Vc is employed as the control signal. It is also possible readily to perform logic on the input signals. For example, the first two plates which are legended 14-0 and 14-1 in FIGURE 4 may be control plates which can be re~erred to as 14-01 and 14-02. Here, tbe s1gnals applied to the two control plates may represent two bits of information and in this case the two control plates will simulate the AND function. I~ desired, the first electrode 14-01 may receive a relatively longer signal and the electrode 14-02 may receive a shorter signal which is concurrent with the signal applied to 14-01. Here, either or both signals may represent ihformation or the ~irst, that is, the longer signal, may represent information and the shorter signal may be a timing or strobe pulse.
As an alternative to the above, the two input signals may be the signals V3 and Vc of FIGURE 7, the ~irst such signal being applied to the source and the second to the control electrode 14-0. Here, the positive-going pulse 25 V3 may represent a 1 and the negative-going pulse Vc also may represent a 1 and with this convention, the circuit also performs the AND function.
In general, in charge-coupled circuits such as discussed above, multiple input AND gate operation may be realized by concurrently applying a plurality of negative RCA 63,~96 )89~
I pulses to a corresponding number of gate electrodes, re-spectively, and a positive pulse to the source Sl. An OR
function may be realized by employing a plurality of sources, all providing charge inpllt, in parallel, to the first ~ 5 potential well ~under electrode 14-1). Here a positive ; pulse applied to any source electrode concurrently ~ith the unconditionally applied positive~going control pulse Vc will couple a charge signal to the first potential well.
Other alternatives also are possible.
It is also possible to operate the input circuit in such a way that charges of dif~erent magnitude represent the bits 1 and 0 respectively. Input signals at these two levels can be obtained by using the direct voltage level of the signal applied to the gate electrode 14-O to generate the O at a lower charge level than the 1 input or by con~
trolling the potential of the source so that the first potential well is filled to a lower level for O and to a higher level for 1, or by a combination of these methods.
; , .
`20 Middle of System The transfer of charge from under an electrode such as 14-1 (FIGURE 4) to under an adjacent electrode such as 14-2 is accomplished by applying a negative voltage pulse ~i to electrode 14-2 while the voltage pulse ~1 is being ~ 25 reduced in amplitude. The result is that while the i potential well under the electrode 14-1 is being made -~
shallower, the potential well under the electrode 14-2 is being made deeper and the charge spills from the shallower to the deeper well. The use of overlapping clock pulses is usual for 2, 3, 4 and higher phase operated charge .
:. , : .
,' '; ' ~ ', . ' " ' ' . ' RCA 6~ gf;

08~7 1 coupled circuits. However, it rnay be pointed out, in passing, that non-overlapping clock pulses may be employed in connection with two-phase operatlon (and also in three and Your-phase operation) if cert~in conditions are met~
as discussed shortly.
In an arrangement such as shown in FIGURE ]., there is no problem of unidirectionality,of signal propagation if the source 20 is a $hree or higher phase source. In these cases, when charge is being transferred, for example, from under electrode 14-2 to under electroda 14~3 (FIGURE l) 9 . there is no negative voltage pulse being applied to ; electrode 14-l. Accordingly, the very shallow potential well under electrode l4-l (the only such well present will be one due to a direct voltage bias between the electrode and the substrate) acts as a barrier to the flow of charge in thè backward direction so that only the f'orward direction "~ is available for the flow of charge when the source 20 pro-vides three or more phases. Such unidirectionality of charge flow is not present in the case of a -two-phase ,, 20 source. Here, to obtain unidirectional charge flow special . techniques must be employed as discussed below.
: ~n~ aspect of the preferred embodiment resides in ,`- the discovery by the present inventor special electro~e ~;
structures which are relatively easy to f'abricate for , achieving unidirectional charge flow with two-phase voltages. In general, each electrode consists not of a single plate but of two plates which overlap. One arrange-,;~ ment shown in FIGURE 9 depends for its operation mainly '' on the geometry of the electrodes and more particularly mainly on the spacing of one electrode of a pair rurthor ' .

., ~ ,. _ .
.~' . ' .. ' ~ :

RCA 63,696 ~8V847 :

1 from the substrate than the other. The second arrangement ` illustrated schematically in FIGURE lO and more realistically in FIGURE 11 depends mainly upon a voltage offset being -~ maintained between the two electr-odes o~ each pair. A third alternatlve is to combine the geometry of FI~URE 9 with the voltage offset of FIGURE 11. An embodiment of this form ~- of the invention is illustrated in FIGURE 12.
In all of the cases ahove, the structure is such as to produce an asymmetrical depletion region beneath an electrode pair in response to a negative potential (OI-potentials) applied thereto. The direction of asymmetry of the depletion region is such that a charge introduced therein will accumulate at the forward or leading edge of ! , the depletion region as the potential well at that region . 15 is substantially deeper than in the remainder of the region.

; FIGURE 9 should now be referred to. Each electrode ,, corresponding to 14-1, 14-2 and so on in FIGUnE 1 consists of two electrodes ~hich overlap. One of the electrodes consists of a metal sucb as aluminum and is shown at 26 ", 26-2 and so on and the other electrode of each pair consists of a p+ polysilicon region as shown at 28-1, 28-2 and so on, which is directly electrically connected to its corresponding aluminum electrode. The term "polysilicon" re~ers to a polycrystalline form of silicon. It is obtained by de- ~ ~
positing the silicon at an elevated temperature or by ~, depositing amorphous silicon, then hea-ting to 900C or more ~or tcn or more minutes to change the amorphous structure to a polycryst.llline structure. (The use oi polysilicon material is in itself known in the MOS technology.) The 3 polysilicon electrode of each pair is spaced closer to the :, ~ ~ , , . . .
, , . .

I~C~ 63>~96

4'~

1 n-type silicon substra-te than the aluminum electlode o~
that pair. Each aluminum electro(1e such as 26-2 overlaps the leading edge of its paired po]Lysilicon elec-trode 28~2 and overlaps also the lagging edge of the polysilicon electrode 28-l o~ the preceding pair.
The overlapping polysilicon aluminum electrocle construction allows very close spacing between each aluminum electrode and the two polysilicon electrodes it overlaps.
Typical dimensions are given later, however, it might be mentioned here that such spacing may be l,OOO A or less.
Moreover, the iabrication techniques employed ~or making the structure, which techniques will be discussed at greater length later, permit sel~-alignment o~ the aluminum electrodes relative to the polysilicon electrodes. The only critical alignment is connected with the etching of the aluminum electrodes above the polysilicon electrodes.
The ~abrication technique also permits the two dif~erent thicknesses of channel oxide (a and b in FIGURE 9) easily to be obtained.
In the operation of the circuit oi FIGURE 9, when a negative voltage pulse ~2' ~or example, is applied to the ~ -electrode pair 26-2, 28-2, the depletion region which is created is asymmetrical as illustrated by the dashed line 30. This region is substantially deeper beneath the electrode 28-2 than beneath its paired aluminum electrode 26-2. There are two reasons. One is that electrode 28-2 is more tightly coupled to the n-type silicon by virtue of its closer spacing to the n-type silicon. This results in a smaller voltage drop across the silicon dioxide under 3 the electrode 28-2 (the region c) than under the electrode -2~-. . .
~ ?

RCA 63,6f3fi ~8~8~
1 26-2 (the region b), causing a deeper poten-tial well ko -~orm under the polys~licon electrode 28-2 than under the aluminum electrode 26-2. The other reason is that the work function for p+ polysilicon used on n-type substrates is lower than that for aluminum by about 1 volt. This implies that ~or a given negative potential applied to a polysilicon electrode it will repel a greater number of electrons from the adjacent region of the substrate than will an aluminum electrode of ~ .
the same size spaced the same distance from the substrate and to which the same voltage is applied.
Since the main function of the aluminum electrode is to provide a barrier for the charge flow when a phase voltage applied to a pair of electrodes is being made more positive (actually less negative), during which period the~
charge is being "spilled" to the potential well under the next electrode pair, the "active region" (the part closest~
to the substrate which bas the dimension k) of this~electrode is made shorter than the corresponding dimensi~on c o~ the polysllicon electrode. Construction ln this way leads to ~o faster trans~fer time and to the possibility of greater packing density. This dimension (which is approximately ~; ~ equal to the spacing k between two adjacent polysilicon - ~`
electrodes) can be made as small as 0.1 mil (2.5 microns) or less with state of the art metal-oxide-semiconductor - 25 fabrication technology.
As discussed above, unidirectional transfer of - ;
charge is obtained in a two phase structure such as shown in FIGURE 9 by providing asymmetrical potential wells under successive electrode pairs in the manner described. To 3 obtain relatively large asymmetry in these wells without ~` -3n-nCA 63,~96 4'7 I having to have very large di~erence~ between the two thicknesses (at b and c respectively) o-f the silicon dioxide layer, it is desirable to employ silicon substrates of relatively lower resistivity as, for example, a resistivity of less than 3 ohm-centimeters, and preerably ln the range of 1 ohm-centimeter. However, a somewhat longer resistivity substrate may be used if' a relatively large substrate bias VN such as ~10 volts or more is employed. A large substrate bias in combination with the two thicknesses o~ oxide pro-duces a deeper potential well beneath the electrode spacedcloser to the substrate surface.
In the operation of the structure shown in FIGURE 9, assume that positive charge accumulates in the deeper portion of the well 30 as indicated at 31 in response to a negative pulse ~2. Toward the trailing edge of this pulse, the negative pulse ~1 is applied to the next electrode pair 26-3, 28-3 (tlme t2 in FIGURE 13). In response to the concurrent presence o~ the last part of pulse ~2 and the first part of pulse ~1~ the charge 31 will tend to flow to the right, the sequence of events being as depicted in FIGURE 13. As the potential well under electrode 28-2 becomes shallower the potential well under electrode pair 26-3, 28-3 becomes deeper and the charge present at 31 spills into this potential well and accumulates under electrode 28-3.

While it is true that concurrently with the appli-cation of the ~1 pulse to electrode pair 26-3, 28-3 this same pulse is applied to the preceding electrode pair 26-1, 28-1, the flow of charge in the reverse direction is pre-vented by the potential barrier present under the aluminum :

': '. : .

-I~C~ 63,696 I electrode 26-2. Just prior to the application of the ~1 pulse, all o~ the charge under the aluminum el.ectrode 26-2 is stored in the deeper well under electrode 28-2 (time t :. in FIGURE 13). Accordingly, when the negative pulse ~1 : 5 goes on and the ~2 pulse starts going o~f (time t2 in FI&URE 13), the charge in this deeper portion 31 o~ the potential well will spill in the forward direction, the direction in which the stored positive charge "sees" the more negative potential, and be presented ~rom moving in the reverse direction by the potential hill (the less negative voltage) it sees in that direction.
It may also be mentioned at this point that i~
the structure of FIGURE 9 is operated with a su~iciently ~ large bias voltage applied to the substrate so that the charge signal can be maintained in the deeper potential : well by the bias signal alone, then the two phase voltaee ~: .
. , ~
pulses do not have to o~erlap. Such operation can lead to simpler signal regeneration circuits as will be described -~: later. ~.:
Typical dimensions by way o~ example ~or the structure o~ FIGURE 9 are:
~ ~ a = 1,000 A
`~ b = 2,000 A
c = 0.4 - 0.5 mils ~ 10-13 microns (~
d = 3,000 - 10,000 A
e = 0.3 - 0.5 mils ~ = 500 ~ 1,000 A

: h = greater than 4 mils - 30 j = 0.2 - 0.3 mils , ~ 32-~C~ 63,6~

V8~

l k = 0.1 - 0.2 mil l = 0.1 mils Dimensions (except ~or b in FIGU~E ll) are similar ~or the structures of FIGURES ll and 12, FI~URE lO illustrates schematically a second method for creating asymmetrical depletion zones. Here again each storage location corresponding to 14-2, 14-3 and so on of FIGURE 1 consists o~ two very closely spaced electrodes such as 30-la and 30-lb with a fixed, direct-voltage o~set, indicated schematically by battery 32, between them. In response to a clock pulse such as a ~1 pulse, the ~irst electrode of each pair, such as 30-1, is not made as negative as the second electrode such as 30-lb of each pair. In practice, the voltage of~set may be achieved in any one of a number o~ conventlonal ways within `~
the multiple-phase power supply. As a simple example, the voltage applied to electrode 30-la may be taken from one point along a volta~e divider and the voltage applied to electrode 30-lb may be taken from another point along the voltage divider. The ef~ect o~ the voltage o~fset is to provide an asymmetrical potential well as indicated by the dashed line 34 which diagramatically shows the situation for the ~l voltage.
A cross-sectional and partially schematic view of a practical implementation of the FIGURE 10 arrangement is shown in FIGURE 11. The structure is very similar to that of FTGuRE 9, however, the aluminum electrodes 30-la, 30-2a and so vn may bc sp;lccd thc same distance from the substratc as the polysilicon electrodes 30~1b, 30-2b and so on, that i.s, a = b.
- .

.~ , . , :

ncA B3 ,696 8~
, I While the asymmetrical depletion region is obtained in a different way in FIGURE 11 then it is in FIG~RE 9, the operation of the structure o~ FIGURE 11 in response to the two phase voltage pulses corresponds very closely to that

- 5 of the FIGURE 9 structure. Thls operation is illustrated in FIGURE 13.
The structure shown in cross-section in FIGU~E 12 combines the features both of FIGURE 9 and FIGURE 11. In view of the previous explanation, FIGURE 12 need not be d~scussed in detail.
; In the various structures discussed above, as already implied, for an empty potential well (one which ; has not yet accumulated charge carriers), for a given -~ voltage drop across the silicon dioxide, the higher the resistivity of the substrate the deeper the well that is formed. As a potential well is being filled with mobile ~- charges, more and more of the voltage provided by the electrode responsible for the well is consumed as a voltage drop across the silicon dioxide. This enhances the asymmetry of the potential well. However, mathematical computations relating to electric fields in charge coupled circuits indicate that the lower the resistivity of the substrate, the smaller the fringing electric field produced at an `~ electrode and as will be discussed later, present theory ~ ~ 25 indicates that the smaller the fringing field, the slower - the charge shi-fting speed which can be obtained. Accord-ingly, there is an advantage to be obtained, in certain applications, in using substrates with higher resistivity.
Ths embodiments of the invention shown in FIGURES 11 and 12, which depend for the poten~ial well asymmetry on the direct ~ : ' . -l~C~ 6~,696 8~
.~
l voltage offiset between the two electrodes of a pair, per~it : this latter type of structure, th~lt is, they permit asymmetrical poten-tial wells -to be ~ormed usin~ higher resistivity substrates. For example, operation appears to : 5 be feasible uslng two phase voltagres and substrates with resistivities of say lO ohm cm ancl higher using the structure of FIGURES ll and 12 with the dimensions already discussed and with a direct voltage offset of' such as 5 volts, as an example.
FIGURE 14 illustrates a portion of a two-dimen~
sional, charge-coupled capacitor array employing pairs of electrodes such as described in the discussion of FIGUR~ 9.
~: (Two-dimensional implies more than the single row of electrodes.) The aluminum electrodes 40-la, 40-2a and so on take a zig-zag path in one sense and the polysilicon : ~ electrodes 40-lb, 40-2b and so on take a zig-zag path in the opposite sense. This means, for example, that in the upper region of the structure the right edge of electrode 40-la is coupled to its paired electrode 40-lb at the right edge of electrode 40-la and at the left edge of electrode 40-lb, whereas at the center of the structure, the left .. . .
edge of electrode 40-la is coupled to the right edge of electrode 40-lb. The reason for arranging the structure in this way is to get the charges to move in one direction (to the right) in the upper thin film region as discussed .
in more detail shortly and to get the charges to move in -~ the opposite direction (to the left) in the next thin film region.
~` ~ The polrsilicon electrodes 40-lb (and the aluminum electrodes) also follow a zig-zag path in the third ''~`: , ~, :
: ,. -. :,.
::
' , , ', ,,:

RCA 63,696 :.
1 dimension, that is, in tbe dimension in and out o~ the paper in FIGURE 14. Thus, at the upper portion o~ the figure, an electrode such as 40-]b is very close and therefore coupled to the substrate. In the following region, the spacing between the electrode 40-lb and the substrate is relatively ~ar, to e-~ective]y decouple the electrode 40-lb from the substrate. The thin ~ilm o~
SiO2 may be e.g. 500-2000 A in depth and the thic~ rilm 10,000 A or more in depth. These di~erent thin ~i]m and thick film regions are indicated by legends at the right o~ FIGURE 14. Each electrode such as 40-la is directly electrically connected to its paired electrode such as 40-lb. These connections are shown schematically in the view of FIGURE 14 by the diagonal, crossed lines.
The structure of the uppermost thin film region~
along 9-9 of FIGURE 14 is similnr to that shown in cross~
section in FIGURE 9 (the reference numerals, however, are different). The zig-zag structure in the third dimenslon~
~in and out oi the paper in FIGURE 14) of the polysilicon~
, and aluminum electrodes and the connection o~ an aluminum electrode to its paired polysilicon electrode are shown in cross-sections taken at 15-15 and 16-16 in FIGURE 14.
These cross sections are shown in FIGURES 15 and 16 re-- ~ spectively. All three figures~may be re~erred to in the ~ ;~
discussion of the operation which ~ollows.
The assumption may be made ~or purposes o~ this discussion that in response to a ~1 pulse, a charge has accumulated at A FIGU~E 14 in the upper shift register beneath electrode 40-lb of pair 40-lb, 4n-la. Note th.lt 3 the structure o~ this electrode pair is similar to th.lt . ~

.
, .
`':", ' . :

RCI~ ~3 ,fi96 1 discussed in connection with EIGVRE 9 such that -the potential well is asymmetrical. In response to the phase-2 pulse ~2~ the charge stored under electrode 40-lb moves to the right and becomes stored at B under the electrode 40-2b of the next electrode pair 40-2a, 40-2b. In response to the next ~1 pulse, this charge continues to move to the right and becomes stored at C under electrode 40-3b of pair 40-3a, 40-3b, and so on. When a charge reaches the end ~f the shift register ~not shown in FIGURE 14) a charge re-generation circuit (shown and discussed later) applies a charge or its complement (depending upon the regeneration ;
circuit employed) to the next shift register. The direc-tion of charge signal flow is indicated by dashed line 42.
For purposes of the present explanation, assume ~; 15 that this charge has arrived during phase 1 time (during the negative pulse ~1) at region E under electrode 40-4b ~ ~ ' of pair 40-4a, 40-4b. It should be clear that now the direction of asymmetry of the potential well is reversed.
~At E, the aluminum electrode 40-4a is to the right of its paired eIectrode 40-4b whereas at D, the aluminum electrode ~ 40-4a is to the left of its paired electrode 40-4b.
: . ;
Accordingly, in response to tbe next ~2 pulse, the charge stored at E will move to the left to F.
It shoulcl be clear from the above that with the ~25 structure of FIGURE 14 it is possible on a single substrate to provide a plurality of shift registers (as illustrated schematically in FIGURE 2) which simulate the operation of one very long shift register. As already mentioned, and as will be discussed shortly, the means connecting the `-output terminal of each shift register to the input terminal .. . .
. ' ' . ' :
: ~ .

RCA 63,696 1 of the following sh~1t register may be integrated onto the same substrate as the registers. With respect to size versus storage capacity, if each storage location occupies an area of say 1 to 2 mils, then it is possible to have a 104 bit register on a substrate 100 mils by 100 mils (0.1 inch x 0.1 inch _ 0.01 in2) in area.
The manufacturing process, which will be dis-cussed later, is similar to that employed in the manufacture of silicon-gate M0~ field-ef~ect transistors and is well known in the art. Each storage location requires only a single element (a single charge-storage capacitor) at each location as contrasted to the requirement, for example, of`
- : `'~ ' .
4 or 6 transistors per location employed in many memories commercially available these days.
"
A second embodiment of a two dimensional structure is shown in FIGURB 17. It includes an n-type silicon sub~
strate 43, a silicon dioxide layer 44 which in some region~s ~-is thick and in others is thin, and p+ type polysilicon lines 65-69 located on the silicon dioxide. The cross~
sectional views of FIGURES 18 and 19 will help the reader -to visualize the structure. The thin film region (section ;~
9'-9') is similar in cross-section to FIGURE 9.
.-~ The final portion of the structure, that which is on the upper surtace of FIGURE 17, includes the aluminum ~
"~ .
lines 50 and 52. These extend to the interdigital structure, in one case tabs 53 through 58, for ex.ample, and in another case tabs 59 through 63~ as a second example. ~ine 50 is connected to the ~1 voltage source and line 52 is connected to the ~2 voltage source. Line 50 is connected to alternate polysilicon electrodes 66 and 68 and line 52 is connected ., ~ ' .... . . . . .
~:: ,, , :: . .. .
..:
:. . . : . .

RC~ 63,~96 3~8~847 1 to alternate polysilicon electl~odes 65, 67 and 69, in both cases in the same way as already discussed in connection witb FIGURE 14.
At a storage location, a pha9e-l pair o~ electrodes would be, as an example, tab 75 and electrode 68; the next electrode pair, a phase 2 pair, comprises tab 56 and electrode 6~; the next pair is a phase 1 pair and comprises tab 74 and electrode 66, and so on.
In the operation o~ the arrangement of FIGURE 17, if a charge initially is stored under electrode pair 75-68 during a phase-l pulse, during the next phase-2 pulse, ttle charge will move to the left to a position under electrode - pair 56-67; during the next phase 1 pulse, the charge will continue to move to the left and will be stored under -electrode pair 74, 66 and so on. Thus, in the shift register along line 9'-9', the stored charge will propa-~ gate to the left. On the other hand, it is clear that for - the next shift register, that defined by tabs 53, 60, 55 - and so on, any stored charge will propagate to the right.
In other words, as 1n the embodiment of FIGURE 9, lf each set of tabs along a-horizontal line is considered to be a ; shift register, the two-phase negative voltage pulses applied to electrode 50 and 52 will cause charges to propagate in opposite directions in successive registers~
A shift register which incorporates the structure of FIGURE 11 or PIGURE 12 is shown in ~IGURE 20. It in-cludes a common conductor 90 connected to interdigital tabs 91, 92, 93, each comprising one electrode of a pair.
.
Polysilicon electrode 94 is the second electrode of the pair 91, 94; polysilicon electrode 95 is the second ~ , .
: -39~

:~ . . . .
. .. . . . .
. . .' ' ' .. .
. ~ .

R~`A 63,696 2a~

1 electrode o~ the pair 92, 95. The polysilicon elec-trodes 94 and 95 are directly connected at 96 and 97 to the aluminum conductor 98. The phase-2 elec-trodes are similar in structure to and symmetrical with the phase l electrodes and are located as shown.
As in previous arrangements already discussed, the portion of the structure of FIGURE 20 at which stored charges propagate contains a thin film silicon dloxide region at ll'-ll'. The cross section along this thin -film region resembles that of FIGURE 11. Alternatively, the cross section may be as shown in FIGURE 12. The operation of the shift register of FIGURE 20 is quite similar to that of embodiments already discussed.
The structure of FIGURE 20 is somewhat inefficient -~ 15 from the point of view of packing density. Extra space is required for the conductors 98 and 98'. Nevertheless, modifications of this structure such as shown in FIGURE 21 are useful and economical. In this figure, in the region lO0 each polysilicon electrode such as l04b t'orm a plurality of storage locations rather then a single such location.
This is illustrated in FIGURE 22 which is a section taken :, :~ along line 22-22 of FIGURE 21.
In the operation of the arrangement shown in FIGURE 21, there are a plurality of source electrode~ (not ~ shown) that introduce into the first "electrode pair'~ a E plurality of charges corresponding to one byte of informa-., .
tion. For example, each polysilicon electrode of a pair may include say eight or more thin silicon dioxide film regions 104 of FIGURE 22 under which 8 bits of information may be stored, respectively. These bits, indicated by the ~ : :

RCA 63 ,69fi l~BSV847 1 presence or absence of charge, for example, are shifted a byte ~t a time from el~ctrode pair to electrode pair.
For example, they (~ bits) may be shifted from electrode pair 104-la, 104-lb to electrode pair 104-2a, 104--2b, where in each case the a electrode is the aluminum electrode -; at the surface and the b electrode is the polysilicon electrode.
If it is attempted to send a signal down a ?
relatively long polysilicon line spaced close to a silicon substrate, there will be a substantial delay in the signal transmission. The reason is that the polysilicon line has a relatively high sheet resistance, of the order of 10 to 20 ohms per squarej so that the line looks like a resistor-capacitor transmission or delay line, where the "capacitor"
is the distributed capacitance between the line and the ~ ~;
~` substrate. The solution to this problem in the arrange- ; ~;
; ments of FIGURES 20 and 21 is to employ a plurality of , relatively short polysilicon lines such as 94 and 95 of FIGURE 20, all connected in parallel to a relativeIy highly conductive line ~uch as aluminum line 98, which is spaced - ~ , relatively far (10,000 A or more) fro~ the substrate.
However, as already mentioned, the price paid is the greater area requlred and this reduces the packing density.
The arrangement of FIGURE 23 solves the problem ~25 above in a different way - one not requiring additional , space. Here, the shift register consists of an inter-digital structure similar to that shown in FIGURE 20 and shown in cross section in FIGURE 11 and the po~ysilicon portion also comprises an interdigital structure. The bus ~30 analogous to 98 of FIGURE 20 comprises a length of .. 41- :
., ,;`: . - -, ' , , , :

RCA 63,fi96 3L(~8~8~L7 1 polysilicon line such as 106 which lies for its entire extent beneath tbe corresponding alumlnum line 108. The spacing f (FIGURE 24) between these two lines may be o~ the order of 500 to lO00 A which may be less than or comparable to the spacing a (FIGURE ll) between the polysilicon line and the substrate in the thin silicon-dioxide region. The spacing between the polysilicon line 106 and the substrate in the thick silicon dioxide region (dimension q, FIGURE
~4~ may be of the order of lO,000 A or more.
The result of the geometry above is to make the capacltance between the polysilicon line and the aluminum electrodes substantially greater than that between the - polysilicon line and the substrate. The reason is that there is a much greater area of polysilicon spaced a small ~-~ 15 distance from the aluminum than there is spaced a comparable distance from the substrate. In addition, as already mentioned, the structure may be such that the closest the polysilicon line comes to the silicon substrate is l,000 to 2,000 A, whereas the dimension f may be 500 A~.
The coupling between an aluminum line and its ~; corresponding polysilicon line may also be increased in - ~ other ways. As one example, the silicon dioxide layer o~
FIGURE 4 can be replaced by a say 500 A thick layer of silicon nitride or other dielectric material which has a 25 ~ higher dielectric constant than silicon dioxide. As another alternative, the silicon dioxide layer may be replaced with a rather thin doped oxide that tend3 to form a PN junction reglon at the surface of the polysilicon, thus avoiding ` ~ ~ direct shosts due to the pin holes that may result ~rom the ~very thin oxide, which may be less than 500 A thick.
.... ~ .

~ -42~
. . ;:

RCA 63,69~
1~3V8at~

1 With the structure arranged as discussed above, the aluminum lines are tightly coupled from an altern~ting voltage viewpoint to the respectivle polysilicon lines.
Accordingly, when, for example, a ~1 pulse is applied to line 108' it is "instantaneously" capacitively coupled to the polysilicon line 106' while at the ~ame time the two lines are offset in voltage relative to one another in the manner already discussed in connection with previous embodiments.
A two dimensional array operating on the prin-ciples discussed in connection with FIGURES 23 and 24 is ~-illustrated in FIGURE 25. This array has substantially the ~ same packing density as the arrangement of FIGURE l7 and~it ; employs a voltage offset as in the structure discussed in ; ~ 15 connection with this figure and FIGURES 11 and 12. As in previous arrangements, there are thin silicon diox~ide film and thick silicon dioxide film regions. Such thin film - regions are present, for example, at 11-11 in FIGURE 25.
The cross section at these regions may be as sbown in FIGURE 11 or as shown in FIGURE 12. The thick film regions are locàted between the thin film regions. Two cross sections, along lines 27-27 and 28-28 respectively, which~
are shown in FIGURES 27 and 28, show both the thick and thin film regions.
one additional feature of interest in FIGURE 25 is the method for conducting the two phase voltages to ~he ~-~ tabs of the array. Taking the phase 1 voltage as an example, it is directly conducted via aluminum conductor 116 to the alternate aluminum lines 118, 120, 124. The more negative phase 1 voltage is conducted via aluminum .~ . .
; ~43~ ~

:

RC~ 6~,696 ~38~84~7 1 conductor 126 to the polysilicon line 128 along the entire extent of this line. This direct connection is shown more clearly in FIGURE 26 which is a section taken ~long line 26-26 of FIGURE 25. The long polysilicon line 128 is connected in parallel to the polysilicon lines 118a, 120a, 124a. Similar structure is employed for the phase-2 voltage.
In the arrangement of FIGURE 25 as in the FIGURE
23 arrangement, the capacitance between each aluminum line such as 118 and its corresponding polysilicon line such as 118a is made much ~reater than that between the polysilicon line and the substrate. The reason is the relatively close spacing between lines 118 and 118a over a relatively large surface area, just as discussed in connection with FIGURE
23.
The operation of the FIGURE 25 arrangement should be clear from what already has been discussed in connection with FIGURE 23. Charge may be introduced into a shi~t register in the manner discussed in connection with the input end of the system. This charge once present in a shift register travels in one direction (to the right) in the uppermost shift register; it travels in the opposite direction (to the left) in the next shift register and so on. The couplings between registers comprise regeneration 2S circuits to be discussed shortly.

Coupling Between Adjacent Shift Registers of the System FlGURE 29 shows in cross section the coupling between the output end of one register and the input end ~, ` =-4-4-~ :

RC.~ 63,69fi aB~

l of a second register. For purposes o~ the present dis-cussion, the plates or electrodes 14-(n-1), 14-n, 16-0 , and so on are shown simply as single elements. Their actual structure may be similar to that a].ready discussed in connection with FIGURES 9, 11 and 12 and will be dis~
~' cussed and shown later. The substrate 10 is a common sub~ , strate and the silicon dioxide layer 12 is also common.
The new structure of FIGURE 29 not previously ~ , -shown comprises a floating region ox junction F and a drain D, both formed ln the substrate. These are highly doped p+ silicon regions similar to the source Sl shown in ;:
FIGURES 4 and 7. The floating junction F and drain D ;' correspond to the source and drain electrodes respectlvely of a metal oxide semiconductor ~ns transistor and the ~e~lec~ ',`J~ ~, ~ 15 trode 14-(n'~l) cor'responds t~ the gate electrode of such~-a~

' '~ transistor. The dr~in ~ is connected to a voltage~su~ly V
which provides a voltage of a v~lue such as -lO volts.
The input end of the next shi'ft register includes~
a source S2 and gate electrode 17 whose function and ~20 ~ structure are similar to that of the source Sl and~gate '~
electrode 14-0, respectively shown in previous figures.
The function of the electrode 17 controlled by the voltage~
pulse Vc is to provide the timing for the transfer of~the~
charge signal from the source,S2 to the potential wel~
25~ beneath the first electrode 16-l. As described previously'~
this potentlal well beneath the first electrode of the~

second shift register can be filled with charge to a known~
in-advance extent such that its surface potential approac~hes~
the voltage o~ the source S2, that is, the voltage of the ~ ~
3, supply Vl which may be a value such as -5 volts.; ~ t "' '~' ' ' ~ ~ ' ,'~: , : `

, .. .... . ..
. ~''. ' .
` :: ~ : `

~1:380i 3~7 I FIGURE 29 shows also some of -the capacitallces in the system. These are det`ined below and their signilicance in the operation of the system will be discussed brie~ly ~ later.
- 5 Ca = the capacitance between electrod~
14-n and ~loating junction F
: Cb = the capacitance between the reset electrode 14-(n-~1) and the junction F
C3 = the capacitance between the junctinn F and the substrate 10 C4 = the capacitance between the gate electrode 16-0 and the substrate 10 C5 = the capacltance between the substrate lO and the conductor 140 joinin~r the junction F to the gate electrode 16-0 CF Ca ~ Cb + C3 + C4 ~ C5 = the total effective capaeitance of the floating junction F.
The operation of the system oi FIGURE 29 will be~
dlscussed first for the case in which the capacitances Ca and Cb are substantially smaller than CF. It is also assumed, ~or purposes of this explanation, that the shi~'t registers are operated with a 3-phase voltage source as this is one o~ the simpler modes~o~ operation. The opera-tion o~ other structures with 4-phase~voltage sources and 2-phase voltage sources will be discussed later.

Tùe waveforms employed in the operation o~ the FIGURE 29 cireuit are shown in FIGURE 31. FIGURE 30 shows -, in a schematic way the potential wells which form and the way in which charge is trans~erred in response to the `~

RC~ 63,ff96 8~7 1 application o~ the wave~orms o-~ ~IGURE 3l.
FIGURE 30(a) illustrates the oper~tion dllrin~
- the ~ pulse (time tl o~ FIGURE 31). A reset pulse V1~
which preferably is more negative than the power supply voltage V4 is concurrent with the negative ~2 pulse.
FIGURE 30(a) shows that a charge 142 has accumulated in ; the potential well beneath electrode 14-(n-1) in resporls~
to the ~ pulse. Concurrentlyg the -15 volt VR pulse applied to the reset electrode 14-(n+l) has created a low impedance channel, illustrated schematically at 144, betwee the source F and drain D electrode which resets the region F to a reference potential close to the value o~ V4 while the charge accumulated in F during the previous cycle is transferred to the drain D.
FIGURE 30(b) illustrates the 1tuation after the pha e-2 pulse is terminated and the phase-3 pulse starts. The time may be t2 of FIGURE 31. The charge ~`
formerly present under electrode 14-(n-1) has spilled into the combined potential well beneath electrode 14-n and the junction F. In the example given, the well benèath eIectrode 14-n is deeper than that beneath electrode F (14-n is at -15 volts and F is at approximately -10 volts) so the .
charge tends to accumulate in the for~er region of the potential well, a~ shown. During this time t2, the reset ~- 25 voltage VR is 0 volts. Accordingly, there is a potential barrier created beneath the reset electrode or, put another way, the channel between the junction ~ and the drain D i9 in its high impedance condition. If one considers F as a source, the electrode 14-(n+l) is a gate and D is a drain, all o~ an ~OS transistor, this transistor ~s cut-off, and "; ':

: , .

RCA 63,69fi 1 and none of the charge pa~ses to D
When the next ~ pulse occurs, the situation i~
as depicted in FIGURE 30(c). This ~lgure illustrates tll.~t a~ter the posltive transition of pulse ~3 (such as at tirrle ~2a in FIGURE 31), the charge, i~ present under an electrode 14-n, will be trans~erred to the floating junction ~l.
Assuming that charge is present at the ~loatlng junction F, the potential o~ this ~loating Junction becomes relatively positive ~actually becomes les~ negative). ~s this ~loating junction i9 directly connected to the control electrode 16-0, it places this control electrode at a relatively positive potential so that the potential well beneath this electrode becomes very shallow. This shallow potential well acts a#
a voltage barrier. During this same period, such as t3 o~
FIGURE 31, the pulse Vc is appl~ed. This pulse cau~es a conductive channel to extend ~rom the source electrode S2, which is at a voltage o~ -5 volts, to a region of the sub-strate beneath electrode 17. However, as the control electrode 16-0 is at a substantially more positive voltage than VT -5 volts, the voltage of the conductive channel, - the charge~ cannot ~low ~rom the source S2 into the ; potential well created beneath electrode 16-1 by the .~ . negative ~ voltage pulse applied to this electrode.

The case in which the last bit stored in the ~irst register is a 0 rather than a l i9 illustrated in FIGURE

30(d). Here, during tbe ¢3 pulse, a 0 is ~tored beneath - electrode 14~n. I'he ~loating junction F there~ore remains negative to the e~tent o~ roughly -10 volts, the voltage to which it was charged during the ~2 pulse. Tbis voltage applied to control electrode 16-0 is in the ~orward ..
-4~-~' ~ ' ' . . , ~`.
.. . . . .

RCA 63,696 4~7 1 direction so that during the pulse Vc a eonduction channel 146 extends from the source S2 to -the region o~ the S~lb strate jus-t beneath eleetrodes 17 and 16-0 to the potential well created under the first electrode 16-1 by the -15 volt ~ pulse. This permits the posltive charge carriers available at tbe source S2 to ~low to the potential well beneath electrode 16-1 until the sur~ace potentlal o~ the well starts to approach the potential o~ the source S2.
Thus, in response to a 0 stored beneatb the last plate 14-n o~ the first shi~t register, a 1 is trans~erred to the ~irst plate 16-1 o~ the next shlft register.
- Summari~ing what has been discussed up to this point, during the ~2 pulse, a charge indicative of the bit 1 may be stored under electrode 14-(n-1). ~uring the ~3 pulse, the bit 1 trans~ers to the potential well beneath electrode 14-n. During the ~1 pulse, the absence of a ;~
charge, indicative o~ the bit 0, becomes stored under the ~irst electrode 16-1 o~ the next shift register. Thus, it is clear that when the last bit in the ~irst register is a 1, its complement 0 is shi~ted into the second shi~t register. The discussion also showed tbat when the last -bit in the first register is a 0, its complement 1 is ~hi~ted into the second shift register.

The circuit o~ FIGURE 32 is the same as tbe one in FIGURE 29, however a 4-pbase voltage source rather than a 3-phase voltage source i9 . employed. The use o~ a 4-pbase rathçr than 3 simpli~ies tbe timing somewhat as the ~2 pulse may be applied to electrode 14-(n+l) rather tban the VR

pulse.

i.

:-:: . : . . .
: ' . ,.

RCA 63, 6,C)fi 8~

1 In the operation o~ the FIGURE 32 embodiment, during the ~ pulse (time tl o~ ~IGURE 33) a charge, i~
present, is moved beneath electrode 14-(n-Z). This same pulse applied to electrode 14-(n+l) causes an inversion layer to ~orm between the floating junction region F and tbe drain electrode D causing region F to discharge the positive charge it may have accumulated in the previous cycle and to assume a negative voltage level of approxl-mately -10 volts. During the ~3 pulse, the charge present under plate 14-(n-2) moves to the region o~ the substrate under plate 14-(n-1~. During the ~ pulse (time t3 o~
FIGURE 33), the charge moves to the region under plate 14-n and may start to accumulate at the ~loating region F.
.
The transfer o~ charge into F is completed by the end o~
the ~4 pulse and this places the control electrode 16-0 a$ a relatively positive value with respect to the potential f S2 if F has accumulated a positive charge representing the bit 1 and at a negative value i~ region F remains negative representing the bit 0. j During the ~ negative pulse applied to electrode 16-1, the control voltage pulse Vc is applied to electrode 17. This occurs at time t4 o~ FIGURE 33. Depending upon whether electrode 16-O is relatively negative or relatively positive, with respect to S2, the conductive channel will or will not be extended ~rom the source S2 to the potential well under electrode 16-1. In other words, the positive carriers available a$ region S2 either will pass or not to the region of ~he potential well beneath electrode 16-1.
In the discussion above, the operation o~ the -~ 30 system with overlapping pulses has been considered. Such .... : . : ' ' .

. ~ , . .

RCA 63,69G
8~

1 operation produces the transfer o~ charge erom one well ~o the next by lowering the surFace potential o~ a follo~ing well while the potential of the well containing the ch.lrgrc to be transferred is being raised, thus ~orcing its charge to spill into tbe ~ollowing potential well. By using a relatively large substrate bias Yn such as a bias of 10-15 volts, it is possible to operate the system with multiple phase pulses which do not overlap. Under such conditions, the control pulse VR can be replaced with an ~ 10 appropriate one o~ the multiple-phase voltage pulses. In : this case whether or not the control pulse Vc may be - eliminated entirely will depend upon how quickly the charge can be trans~erred ~rom under electrode 14-n to the region under floating region F. If this charge transfer is IS suffioiently rapid (takes a shorter interval that the interval between the non-overlapping pulses ~3 and ~1 (FIGURE 29) then proper operation is obtained.
Returning to FIGURE 29, if the capacitances Ca and Cb are more than a small fraction of the value of the total capacitance C~ of the floating F region, the opera-tion o~ the output circuit may be appreciably different ~rom the operation just discussed. Consider ~'irst the ei'~ect o~ the capacitance Cb. If the value of this capacitance is not negligible compared to the total `: 25 capacitances CF, then at the lagging edge of the reset pulse VR applied to electrode 14-(n-~1), where the positive going voltage transition occurs, this positive transition will be capacitively coupled to the region F, resulting in a positive step in the potential of F. The result is that 3 at the end Or this reset pulse V~, the re~lon F wlll be at ~ ' . .' .i . . I
, '-`:,: . , .
.. . . .

RCA ~3,696 1 a higher (more positive) potential than ~4 (the direct voltage at which the drain region D is maintained). As all of the circuits to be considered should have the value f Cb as small as possible, t:he amount of overlap between electrode 14-(n+l) and floating region F should be minimal.
One way to achieve minimum overlap is to employ a "self-aligned polysilicon gate" as shown at 14-(n+l) in FIGURE
37. This may be made by the procedure described later.
~nile the presence of the capacitance Cb should be avoided, the capacitance Ca can be used to advantage to achieve another mode of operation of the output circuit.
The circuit may be schematically represented in exactly the same way as FIGURE 29 for the case of a 3-phase charge coupled shift register, however, the negative timing control voltage pulse Vc may be eliminated~
In operation, the principal difference between -this form of circuit and the one already described in connection with FIGURE 29 is that, due to the relatively large capacitance coupling Ca, the potential o~ the floating `;~
F region tends to follow the voltage swing of the over-lapping electrode 14-n which is driven by the ~3 voltage pulse. Thus, during the ~3 pulse, the F region goes relatively highly negative. It is therefore possible to ` use directly the potentiaL of the floating region F to control the passage of charge from the source S2 to the first potential well ~under electrode 16-1) of the second shift register O In other words, if during the negative pulse there is no charge present beneath electrode 14-n, indicative of storage of the bit 0, the floating `~
region F wi:Ll maintain the gate electrode 16-0 sufficiently - .
.. : ~ .
~:. ;; .

~C~ 63,696 ~8~8~7 1 negative to permlt charge to flow ~rom the source S2 to the region under electrode 16-1 during the time that the leading edge of negative pulse ~1 overlaps the l~gging edge of negative pulse ~3. On the other hand, if during the ~3 pulse there is positive charge representing a 1 present - under plate 14-n, the floating F region becomes su~ficiently positive to prevent the ~low of charge ~rom the source S2 to the region under electrode 16-1 during the next ~1 pulse.
All of this is possible without the need for the additional timing control pulse Vc.
There are a number of other characteristics o~
the circuit operation which can be taken advantage of . . , ~ when there is a substantial capacitance at Ca. At the : termination of the ~3 pulse (time t2a, FIGURE 31), the positive voltage swing o~ ~3 produces a positive voltage step at the F region that tends to modi~y the process of resetting F to the re~erence potential V4. This effect can be used to simpligy the output circuit in two ways.
First the reset pulse VR can be replaced by a direct voltage level such as ground level (since the substrate is at a voltage +Vn) or some more negative potential such as Vl. Secondly, the structure oi the output circuit can be simpli~ied by operating the reset electrode 14-(n~l) as well as the draln D and the source S2 at the same ~25 potential such a~ Vl. Finally, a special control wave~orm Va of FIGURE 35 may be employed to enhance the circuit ,;
operation.

: A circult combining the ~eatures above is shown in FIGURE 34. The common voltage Yl at which the electrodes D and S2 are malntained may be -5 volts, whereas the ' : -53-.:.: :.
~'' .

RCA 63,696 4~

1 substrate 10 may be biased to ~5 volts.
In the description which ~ollows of' $he operation of the circuit o~ FIGURE 34~ FIGUFCES 34, 35 and 36 should be re~erred to. At time tl, there may be a charge present under electrode 14-(n-2). The composite wave~orm Va is at its most positive value which may be ground. In response to this positive pulse, the ~loating region F, which it will be recalled is capacitlvely coupled to electrode 14-n by some substantial value o~ capacitance Ca, also is driven relatively positive. As a result, the region F aets like a relatively highly forward-biased source electrode o~ an MOS transistor and any charge which may previously have been stored there is trans~erred via the channel region - under electrode 14-(n+l) to the drain electrode D. In the-process, electrode F attains a negative value not quite as negative as -5 volts. The actual value is -5 volts + Vt, where Vt is the threshold voltage as already discussed, - The con~iguration of the potential wells at time tl is shown in FIGURE 36(a).
2Q Therea~ter, the ~2 pulse occurs and the charge present under electrode 14-(n-2) transfers to the region ~ -o~ the substrate under electrode 14-(n-1). This part o~
the operation is straighti'orward and i9 not illustrated in FIGURE 36.
At time t2, the control voltage Va ls at its most negative value. The negative pulse ~3 ha~ started and the ~2 pulse is terminating. Assuming that the ~2 pulse hu .~ maximum ne~ative value o~ -15 volts the actual voltage present at electrode 14-(n-1) at this instant is about -8 volts. The potential wells created at this time ~ .

. ''~ '' ~ .

RCA 63,696 84'~

1 are a~ shown in FIGURE 36(b). The charge formerly present in the potential well beneath electrode 14-(n-1) spills into the potential well under electrodes 14-n and into F.
The capacitive coupling between e]ectrode 14-n and region S F has driven region F to a more negative value than electrode l~-n as F initially was negative to the extent of almost -5 volts. Accordingly, the deepest potential well is at region F and if charge initially was stored under electrode 14-(n-2) it eventually accumulates in region F. It may also be observed that drain D is not as negative as region F and moreover, as electrode 14~(n~1) is spaced from the substrate, the surface potential under it is somewhat less negative than that of the drain D.

~, .
During the above period time t2, the ~3 pulse is on. Tbis pulse is applied elsewhere in the system as, for example, to plate 16-3 of FIGURE 34 to propagate a charge . . ,.~
- formerly stored under plate 16-2 to plate 16-3. One could, if desired, rather than employing the control voltage Va, apply the ~3 pulse to the electrode 14-n, as already dis-cussed, however, not as versatile control is obtained of the transfer o~ charge and signal regeneration as will be shown shortly.
At time t3, the ~1 pulse is on. During this same period, the voltage Va is raised to a value intermediate 0 and -15 volts. The actual value employed is a function of such circuit parameters as the amount of capacitance Ca (FI&URE 29) and other distributed circuit capacitances.

The raising of the value of Va to -V makes the potential well under electrode F somewhat shallower but it still remains su~ficiently deep to prevent most of the .

RCA 63,696 4~7 - 1 charge at F ~rom passing to the region D. The value o~ -V
is so chosen that in the case in which there is charge present at F, representing the blt 1, the voltage at 16-0 prevents the passage o~ charge ~rom the source electrode S2 to the region under 16-1. Thi~s set o~ conditions i~
illustrated at (c) in FI&URE 36. The value o~ voltage Vc must also be such that in the absence of charge at F, in-dicative of storage o~ the bit O, a conductive channel region is created beneath electrode 16-O whlch causes charge to trans~er ~rom the source S2 to the region under electrode 16-1. This situation i~ illustrated at (d) in FIGURE 36.
:-~ The circuit of FIGURE 34 is particularly attrac-: tive when implemented with MOS devices (F, 14-(n+l)~D) o~
lS the enhancement type which have low threshold voltages. :
It should al80 be pointed out that other embodiments o~
; the invention already discussed may advantageously employ special waveshapes such as Va of FIGURE 35 ~or control o~
the electrode which overlaps the floating junction region F. This permits better control o~ the timing o~ the potential developed at the ~loating region F and also permits the shi~t o~ the potential at F to a more negative value (when F is receiving a charge ~rom under an electrode such as 14-(n-2) (FIGURE 34)) and to a less negative value -V in FIGURE 35 chosen to provide the desired threshold level ~or signal regeneration when the potential well under the ~irst storage electrode 16 1 o~ the next register is . ready to accept charge. This means that the positive step . ~V at Va (capacitively coupled to F) also is an additional - 30 control to insure that when the region o~ the substrate '.

::
.
: , RCA 63,606 1 adjacent to F is ~illed to the allowable extent with charge, the potential at F (applied to electrode 16-0) will cut-oP~ the flow o~ charge from source electrode S2 to the region under the first storage eIectrode 16-1.
FI&URE 37 illustrates in a more realistic way the actual structure which may be employed ~or the portion of the system shown schematically in FIGURE 29. Note, however, that here and elsewhere the thlcknesses of the electrodes (their vertical dimensions) are not shown to scale and they are drawn in much larger proportion than are the horizontal (length) dimensions o~ the electrodes. This same structure and the alternatives of FIGURES 38, 39 and 40 are also suitable for the structure shown schematically in FIGURES 32 and 34.
., :
FIGURE 37 represents a sllicon gate implementation - ,~
of the 4-phase charge coupled system described previously in connection with FIGURES 32 and 33. FIGURE 38 shows the lower one o~ the two shift registers of FIGURE 37 in a modified version. Here, the signal regeneration i5 accomplished by the coincidence o~ two control pulses Vc and V3. In thi case the voltage pulse Vc provides the timing ~or introducing the charge into the second shii't register. The control pulse V3 determines whether or not or how much charge is to be transferred to the ~irst potential well o~ the second shift register. The selective timing o~ these two control pulses has already been described under the section dealing with the input end of the system.
FIGURE 39 is a generalized showing o~ the input end of a regi~ter similar to that of ~IGURE 38 but intended , .

~: .
: :: , .

RCA 63~696 B'~f7 1 for 2-phase operation. The signal regeneration in a specific, similar 2-phase charge coupled system is described in more detail later in connection with FIGURES
42, 43 and 44.
; 5 Returning to FIGURE 38, here just as in the case oi' the system shown in FIGURES 37, 39 and 40, the floating region F is connected to an aluminum electrode 16-0 which is of the sel~-aligned type and which can be made to have a relatively small amount of capacitance to the substrate 10. While the electrode 16-0 is spaced relatively close to the additional control electrode 17 - a polysilicon electrode, in the region 170, this region 170 is very small, of the order o~ one-half micron. Accordingly, the presence of electrode 17 does not add significantly to the lS capacitance of the electrode 16-0. For the remainder of the overlapped portion, region 171, the silicon dioxide ~;
may be made relatively thick-of the order of several thousand angstroms (the drawing is not to scale). This relatively large spacing over a relatively large distance means that the capacitance in this region is relatlvely small. The polysilicon electrode 17 already mentioned is located between the aluminum electrode 16-0 and the source S2 .
It should be added that in the case of the ~our-phase system, such as described in connection with FIGURE
34, but still made using polysilicon and aluminum electrodes and having an output stage similar to that of FIGURE 40, the floating region F of the first register can be connected to the electrode 17 of the second register shown in FIGURE
37. In this case the ~1 voltage is applied to 16-0, ~2 RCA 63,696 1 to 18~ to 96-2, and ~4 to 16-~3.
All o~ the structures discussed above for the input end o~ the second register may be employed at the input end of the ~irst and all other registers. In other words, the structures schematically shown in FIGURES 4 and 7 may, in practice, be as is shown in one or more of the last three ~igures discussed.
FIGURE 40 illustrates a version of the coupling circuit suitable ~or 2-phase operation in which, just as previously described in connection with FIGURE 34, the overlapping capacitance Ca is a relatively large ~raction of the total capacitance CF ~ the ~loating junction F.
The structure is similar in many respects to that already .
discussed. The waveforms employed in the circuit operation are shown in FIGURE 41.
In operation, during the negative ~1 pulse, the negative voltage pulse VR occurs. This discharges any charge carriers which may have accumulated in the ~loating region F and the floating region F assumes a negative potential close to that o~ the voltage supply V4. During the next ~2 pulse, the charge, if any, accumulated under electrode pair 14-(n-l)a, 14-(n-l)b transfers to the region under electrode 14-n and the floating region F. Shortly a~ter the start o~ the negative ~2 pulseg the negative control pulse Vc occurs and this causes a conduction channel to form under polysilicon electrode 17 effectively extending the source S~ region. Now charge will flow from S2 to the , ~irst potential well under electrode 16-1, or not, depending upon wbether electrode 16-0 is relatively negative (no positive charge at F) or relatively positive (indicative . i ...
~;'' '' RC~ 63,696 ~L~8V847 I of the bit 1 ~tored at 14-n and F) compared to the potential of the source S2.
FIGURE 42 is a plan view of a portlon of a two dimensional, shift-register array a part of which is shown in cross-section in FIGURE 40. To aid the reader to in-terpret FIGURE 42, parts in FIGURE 42 corresponding to - those in FIGURE 40 are identified by the same reference numerals. The economy of layout which is possible with 2-phase operation should be evident from FIGURE 42.
Another form of 2-phase coupling circuit is shown in FIGURE 43. Here, the last electrode of the first shift register comprises an electrode pair 14-na, 14-nb rather tha~ the single electrode of FIGURE 40. In addition, the ~irst electrode 16-1 of the second shift register is driven by a phase 1 pulse rather than a phase 2 pulse. In addi-tion~ the timing waveforms of FIGURE 44 are somewhat different than those employed for the circuit of FIGURE 40.
In the operation of the circuit of FIGURE 43, during the ~1 pulse, the reset pulse VR occurs and the - 2C floating electrode resets to the reference negative voltage level. When the next ~2 pulse occurs, the charge present, ?
if any, under electrode pair 14-(n-l)a, 14-(n-l)b transfers to the potential well under electrode pair 14-na, 14-nb and from there spills into the potential well beneath the floating electrode F if during the ~2 pulse the electrode j F is at a more negative potential than the electrode pair i 14-na, 14-nb.
The transfer of charge from the last potential well of the shift register to the floating region F is completed during the lagging edge of ~2 At this time,

-6~-' ' ` ' ` .

. .

. .

RCA 63,696 lV8V~4~7 1 during the pul8e V (which occurs during the fiIst part of negative pulse ~1' a conduction channel extends from the source S2 to beneath electrode 17. If at the same time the floating electrode F ls relatively negative, charge ~lows from S2 through this channel region ~nd through the channel region formed under electrode 16-0 to the potential well beneath electrode 16-1 created by ~1 If, on the other hand, electrode 16-0 is relatively positive, indicative of the storage of a 1 at floating electrode F, then a barrier is created beneath electrode 16-0 and no charge flows from S2 to the potential well beneath electrode 16-1.
Shortly after the control pulse Vc has terminated and still during the negative pulse ~1' the reset pulse VR occurs to reset the floating electrode F, that is, to place it at its reference potential. No charge can flow from the source S2 at this time, however, as Vc is at ; ground potential, thus forming a barrier for the transfer of charge from the source S2.

FIGURE 45 is a plan view of a portion of a two-dimensional, shi~t-register array such as shown in part in ; FIGURE 43. Again, the economy of layout should be self-evident.
While not illustrated, it is to be appreciated il that various other permutations and combinations of the various arrangements described may be employed. To give i:
but one example, it is clear that the simplified structure of FIGURE 34 may be employed in the 2-phase version of the shift register.

Returning briefly to FIGURE 40, as already 3 mentioned the construction of the signal regeneration stage .. '' ~ .
~ `
: ~ .

RCA 63,696 ~08~

1 can be somewhat simplified, as is evident from the layout in FIGURE 42, if the circuit is designed to operate without the resettlng control voltage pulse VR . This modiflcation of the circult is illustrated schematically by the dashed line connecting the electrode 14-(n~l) to the same power supply V4 as is employed for the drain D. In a pre~erred form o~ the invention, a common power supply is employed ~or D, 14-(n+l) and S2 in the same ~ashion as indicated previously in FIGURE 34 for the case of a 3-phase system.
In the embodiments of the invention illustrated thus far, each shift register receives the complements of the bits stored in the preceding shift register. The circuit shown schematically in FIGURE 46 permits each shift -register to supply the bits themselves to the next shi~t , register. The ~loating electrode F, rather than being directly connected to the gate electrode 1~-0 of the next register, is instead connected thereto through an inverter I. In other respects, the operation is the same as that already discussed. The inverter also may be employed in the various other embodiments of the invention discussed In practice, the inverter may be made of metal-oxide-semiconductor devices which are integrated into the same substrate as the remainder o~ the system or, alternatively, may be a circuit external of the substrate.
In the embodiment of the invention illustrated in FIGURE 21, a plurality of bits are transmitted in parallel in the region 100. It was mentioned in the discussion o~
this -~igure that this plurality of bits may be a byte of in~ormation. Particularly advantageous operation can be achieved if, in addition, the complement o~ the byte is ' , ~;~. : , . . , ~ , " : . . . . , ~, : , f~
nc~ G'~,696 3V~ 7 1 transmitted concurrently. Thus, a system o~ this type comprises n pairs o~ charge-coupled shi~t reglsters (where n is an integer which in the limit:Lng case is 1, which ~; normally is 6 or 8 and which may be a substantially larger number). One shi~t register o~ each pair stores the bits and the other the complements o~ the bits and each such pair may be connected to a balanced detector as shown in FIGURE 47.
An important advantage of operating in this way is that the signal may be detected without requiring that it achieve a definite threshold level. For reliable operation o~ the balanced detector, it is only necessary that there be a su~icient dif~erence in amplitude between the two input s~gnals, one representing the bit 1 and the other the bit O. Another advantage of using a balanced detection arrangement, as will be discussed shortly in connection wi~h FIGURE 49, is the relative ease of entering new information into the storage loop and of obtaining output - in~ormation ~rom the storage loop. The reason is the addi-tional signal gain which is available that allows the balanced detector to be positioned at some distance ~rom the charge coupled shiit-registers.
An embodiment o~ the balanced detection scheme is illustrated in FIGURE 48. It may be assumed that the upper le~t register 14-(n+l), 14-n and so on is storing bits and the upper right-hand~register 14a-(n+l), 14a-n and so on is storing complements of the bits. In practice, these two registers are arranged side-by-side and the bits and their complements travel in the same dlrection, how~
; 30 ever, they are illustrated here as converging simply ~or the sake o~ convenience.

~',, ' RCA 63,696 8~

1 The balanced detector includes two transistors 200~ 201 which are integrated into the same substrate as the remainder o~ the system. It also makes use o~ the output structures o~ the two shi~t registers as the load devices or "resistors" for the two cross coupled transistors 200, 201. Thus, the balanced detector, in e~ect, comprises a four-transistor, flip-~lop~ two o~ the transistors acting as load resistors and being part o~ the output circuit o~
the shift registers.
In the operation of the system o~ FIGURE 48, during the ~ pulse~ VR may be made relatively strongly negative and Vc made equal to V4. As a result, the ~loating regions Fl and F2 discharge any charge either one ... . .
may have accumulated and reset to a value close to -V4.
Thus, terminals 202 and 203 are placed at the same negative potential close to -V4 and when VR is made zero (Vcl re~
maining at -Y4), all four transistors are cut of~ and the ~1 and F2 regions are open-circuited.

The transfer of charge signal to the Fl and F2 establishes the state the ~lip~flop will assume when re-energized or in other words when the four-transistor ~lip-flop is placed in an operative condition. The ~lip-~lop is reenergized by first making Vcl more positive (actually less negative) and then (or concurrently) returning VR
to a negative potential to ef~ectively place the transistor loads (Fl, 14-(n+l),D and E2, 14a-(n+l),D) back in the circuit. More precisely VR may be made somewhat more positive than at the resetting part of the cycle, however, it is still kept at a potential which is suf~iciently ``
negative that the two load transistors still are in '!

~:

~ .. .. . . .

~CA 63,696 8~7 condition to conduct. Control voltage Vcl ls made rela-tively positive with respect to Y4; it may be raised, ~or example, to Vl or a slightly more positive potential (the actual value chosen for Vcl will depend on the voltages desired at 202 and 203).
As mentioned above, the state the flip ~lop assumes will depend upon the values of the bits stored in the two shift registers. For example, if the bit stored under electrode pair 14-n during the ~2 pulse is a 0 (no charge) Fl remains relatively negative. Correspondingly, there will be a charge under electrode pair 14a-n so that - at the end of the ~2 pulse, it will be transferred to F2 and F2 will be relatively positive. The relatively negative voltage at 202 will unbalance the flip-flop and when the flip-flop is reenergized it will result in driving transistor 201 into conduction and correspondingly the relatively positive voltage at 203 will result in driving transistor 200 to cut-off. The difference in voltage between Fl and F2 determines the new state when the flip-flop is re-energized. Thus, terminal 202 w111 be driven relatively negative close to the value of -V4 less the potential drop from D to Fl whereas point 203 will be at a relatively positive value close to the potential of Vcl, which can be the same as Vl.
During the ~1 pulse, the information stored at 202 and 203 which is applied to the gate electrodes 16-0 and 16a-0, respectively, concurrently with a negative pulse VC applled to electrode~ 17 and 17a, will cause a conduction channel to be present under electrode 16-0 and no conduction channel to be present under 16a-0. That is, after the start ~. .. .
`' ~, , :
.

,~ ~

RCA 63,696 I of the ~ pulse when the flip-flo~p is switched to the new state, the control pulse Vc i9 made negative and charge transfers from S2 to the region under storage plate 16-L.
As electrode 16a-0 is relatively positive wlth respect to Yl, no charge transfers from source S2 to the region under storage plate 16a-1.
FIGURE 49 shows in a more schematic way an alternative arrangement. The structure of the upper and lower shift registers is the same as that appearing in FIGURE 48 and only the floating junctions Fl, F2 and electrodes 16-0 and 16a-0 are illustrated. In this em-bodiment, the floating junctions are not employed as load `~ elements for the balanced detector. The transistors 200 and 201 are the same dS those of FIGURE 48. ~owever, in addition, there are separate transistors 204 and 205 whose purpose is to amplify the signals present at F1 and F2 respectively. In addition, there are transistors 207 and 208 that serve the dual purpose of acting as transistor loads for the flip-flop 200, 201 and as a means for intro ducing new information into the flip-flop. It also may be mentioned that new information may be 1ntroduced into the circuit of FIGURE 48 by a pair of transistors such as 207 ~-and 208 shown in FIGURE 49.
In the operation of tbe FIGURE 49 arrangement, , the flip-flop initially may be reset by making transistors 207 and 208 both conductive (EXT = EXT = V while INl =
~1 = some negative value such a~ -V4 of FIGURE 48). Then transistors 207 and 208 are cut o~f, for example by making EXT = ~g-T = ground, while VcI is also equal to -V~ so that transistors 200 and 201 are cut off. Thus points 202 and ; .

:' ` .
- . , RC~ 63,696 ~80847 1 203 are both reset to the same re~erence potential t-V4)-At the time the ~lip-flop is reset and the charge signals are available at Fl and F2, a ~1egative pulse Vc2 which is more negative than Vc iS applied to the drain : 5 electrodes of transistors 204 and 205. If now, for example, IN (the voltage at Fl) is relatively negative and ~-N (the voltage at F2) relatively positive, transistor 204 will conduct more than transistor 205. This unbalances the ' flip-~lop, so that in the same way as described for the circuit of FIGURE 48, when the flip-flop is reenergized (first by returning the voltages IN = ~ to -V4 and then : returning YCl to Vl) it will be set to a new state in which the voltage di~erence between points 202 and 203 will be an amplified version of the voltage dif~erence initially ~:
present between Fl and F2.
:; :
New information can be added to the lower registers via the transistors 207 and 208 in a manner similar to that employed in, for example, a P-MOS memory ~`
array. The EXT and EXT signals perform the function o~ the ?0 word select pulses while the IN and ~ signals perform the function of the bit signals to introduce new in~or~ation.
The external input signals can set the flip-~lop to the desired state in the absence of the control input pulse The external signals also can be made to have sufficient amplltude to override any signals which may be - present at Fl and F2 during Vcl. In other respects, the operation is similar to that described in connection with FIGURE 48. This means that during the process of regenera-3~ tion o~ the information, the transistors 207 and 208 per~orm . ,., . ~

:''' . ' ' RCA 63,696 84'7 1 the function of the load devices in the ~lip-flop which in the circuit o~ EIGURE 48 were part of the output structure of the complementary shift registers.
In addition to the features of FIGURES 48 and 49 discussed above, the flip-flops employed are convenient means for translating the charge-coupled information to static information stored in a flip-flop. In the case, for example, of a byte and its complement being transmitted down to charge coupled shii't register, as in FIGURE 21, at - 10 an output terminal of this system there may be n ~lip flops such as shown in FIGURES 48 and 49, where n is the number of bits in a byte. These n bits easily may be shifted into ~,~
any convenient ~orm of memory desired. For example, the signal regeneratlon flip-flop such as in FIGURE 49 with .
additional trans~stors 204 and 205 to amplify the signal . derived from ~l and F2, may be operated as a semiconductor ~;
memory that may be used as a buffer store between the charge ~.-coupled memory loops and external circuits.
In the systems of FI&URES 48 and 49, input in~
formation is sensed at floating junctions such as Fl and F2. It is to be understood that the system is also .
operative employing floating aluminum electrodes such as 14-n of FIGURE 50 for capacitively coupling signals to the flip flop. The change in capacitance of such floating elec-trodes as a function of the charge signal will become .
apparent from the description shortly to be given of the operation of the FIGURE 50 circuit.
- While FIGURES 47-4g are illustrated for purposes of the present discussion in terms of a 2-phase arrangement, it should be clear that the techniques described are equally ,, :.- .

RCA 63,696 154~

I applicable to 3, 4 and higher phase charge propagating circuits.
In the discussion up to this point, the coupling between two registers has included a~loating junction region such as F, Fl and so on. This ~loating junction region is located in an n-type substrate and consists o~ a p~ region. It iæ also possible to employ as the signal sensing means a ~loating aluminum electrode as illustrated in FIGU~E 50. Here, the ~loating aluminum electrode 14-n at the output end of one shift register is coupled to a gate electrode 16-0 at the input end o~ the next register.
In the operation o~ the FIGURE 50 system, a four-phase system, assume that the electrode 14-n has been reset by the negative control pulse Vc4 to some voltage not quite as negative as V4 and open-circuited (le~t ~loating) by re~
moving the control pulse Vc4. This creates a potential - well beneath electrode 14-n. At ~4 time, charge (or no charge) trans~ers to the region o~ the substrate beneath the last storage electrode 14-(n-1). Assume ~or tne moment that charge is present. During the lagging edge o~ ~g which overlaps the negative ~1 pulse, as the potential well ~ beneath electrode 14-(n-1) is being made shallower, the - charge present there spills into the potential well beneath - ~loating aluminum electrode 14-n. As is well understood in ~ 25 this art, the increase ~n charge in the potential well ; beneath electrode 14-n causes the e~ective capacitance ~ between electrode 14-n and the substrate to increase.
- Since a ~ixed charge previously was established on these iloating electrodes, this causes the voltage present at electrode 14-n and there~ore at 16-0 to decrease.
':
~ -69-:. ' , RCA 63,696 4~7 1 When the ~ pulse has terminated, the charge transfer to the potential well under electrode 14-n becomes completed and at this time the negative control voltage pulse Vc is applied to electrode 17. Now the conditions are correct for charge to ~low ~rom S2 through the con- i duction channel beneath electrode 17 and depending upon whether electrode 16-O is negative or positive relative to the source S2 potantial V1, to flow or not to the po-tential well beneath storage electrode 16-1.
Under ideal conditions assuming a perfect di-electric-silicon dioxide layer, with no'leakage, a ~ixed ~:-' charge could be maintained in the electrode 14-n by :
. . . .
capacitive voltage divider action. For purposes of the present discussion consider a relatively large direct ! ' :- . ` ' voltage source Vc5 and a relatively small capacitor Cp in -the circuit for accomplishing this objective. In practice, however, even a dielectric material as good as silicon~ -.
dioxide has some ~inite resistivity which, in general, tends to make the reference voltage of the electrode 14-n, under these conditions, dependent on the previous state of the sbift register. Moreover, a slow voltage drift will result at the~e ~loating electrodes if the conductivities .. of these two capaci$ors may not be exactly proportional to their respective capacitances and this would introduce ~urther errors. To avoid such problems and also to avoid the need for a relatively high, direct-voltage source, in ; accordance with the present invention, a reset voltage means such as the MOS device F,VC4,Dl is provided for re-: setting electrode 14-n to a reference level. Each time the negative control pulse Vc4 occurs, the floating .'~ ,.

... .

E~CA 63,696 ~8V~

I aluminum electrode 14-n is reset to the voltage of Dl : While, if desired, a negative pulse Vc4 may be applied during each ~2 pulse, actually electrode 14-n need not be reset this often. If desired, it may be reset, for example, in synchronism with a negative ~2 pulseg say every milli-second or so.
One further feature of the circuit of FIGURE 50 ~ is that the voltage of the electrode 16-0 may be modulated by some external voltage source V~5 via a coupling capacitor shown in phantom view at Cp. The control voltage Vc5 may be synchronous with the control voltage Vc. Its purpose is to shift the level of the voltage present at 16~0 to - an appropriate level for, in one case, cutting off com~
pletely the channel beneath electrode 16-0 and, in another case, making it highly conductive. This is, ln effect, similar to what has already been described for the case in which there is substantial overlap capacitance Ca An alternative to the resetting means described above is to maintain the floating electrode 14-n at a fixed re~erence voltage by connecting this electrode via a : reIatively large value o~ resistance, shown in phantom view at Rc, to a power supply terminal. This resistor may take the form of a relatively thin strip of polysilicon film of the same composition as is employed for the poly-silicon electrodes.

Output End o~ the System FIGURE 51 illustrates schematically one form of input-output circuit for the system of the present inven-tion. It also illustrates the use of charge-coupled logic .

' RCA 63,696 ~V~47 1 circuit~. This circuit is designed ~or the 2-phase em-bodiments, however, similar circuits may be employed ~or I the 3, 4 and higher phase embodiments.
The portion of the circuit containing the electrodes 14-(n-2), 14-(n-1) and so on at the upper le~t may be at the end o~ the last reg:ister o~ the system and the circuit which includes electrodes 16-2 and 16-1 and so on may be at the beginning o~ the first register o~
the system. Together they may be part of a closed loop.
Ii' it is desired simply to recirculate the in~ormation, then the pulses VREG have some negative value with respect to source S2 and ~ is relatively positive with respect to source S3, ~or example, the latter may be at ground potential.
; 15 The electrodes 17a, 16a-O, 16a-1, and 16a-2 represent the input end oi a shift register ~or removing the output signal ~rom the system above, which may be a closed loop. Brie~ly, this register of the system operates as ~ollows. The output is obtained only ii' the negative control pulse train VCO (applied to electrode 17a) is present. When VREG pulses are relatively negative and VREG is relatively positive new in~ormation may be intro-duced into the closed loop system under the control input signal Vin. Other~ise, the function o~ the control pulses VREG9 ~ , and Vco is similar to that oi' the timing pulse ; in FIGURE 40.
For the purposes of this description, the ~oltage . . ~
source Vl controlling the potentials o~ S2 9 S3, and S~ will be -5V. The sources S2, S3, and S4 may comprise the same single source region, but to obtain an additional control ~ , .

RCA 63,696 ~0~)8'~7 1 over the operation of the output stage, separate control voltages may be applied to the sources S2, S3 and S4 in a manner such as described, ~or example, in connection with FIGURE 7.
The operation of the closed loop should be clear from previous discussions, for example, such as the dis~
~ cussion of the circuit of FIGURE 40 (with the understanding : that ~2 in FIGURE 40 is ~1 in FIGURE 51). During the negative ~1 pulse, the complement of the bit stored in the last stage o~ the last shi~t register shifts into the ~irst stage (16-1) of the first shift register. During the next ~ ~2 pulse, the bit stored under 16-1 propagates to the le~t -~ to the potential well under electrode pair 16-2.
At the leading edge of this ~2 pulse and the ; 15 lagging edge of the ~1 pulse which is terminating, positive charge which is pre~ent at Fl spills into the potential well being created under 14ma, 14mb. Note that Fl is - spaced a small distance ~rom 14-(n-1), aluminum electrode - 14-n overlapping this distance. Electrode 14-n acts as a gate electrode during the lagging edge of ~1 to prevent any charge at Fl from propagating back to 14-(n=-1). As ~1 is decreasing~, the potential well under electrode 14-n is decreasing and concurrently the potential well ~nder the electrode pair I4-ma and 14-mb is increasing which causes this trans~er of charge to take place. The transfer of charge from Fl to F2 stops when electrode Fl reaches .~! the potential of ~2 less the threshold voltage VT, that is, say (-15 volts ~ YT). This is the reset or reference voltage for Fl.

.

:
. . . . . .

RCA 63,696 1 At the beginning of pulse ~2~ F2 1~ at a negative potential VF2 close to V4 ~ ~2 (assuming strong capacitive coupling of ~2 to F2) having been reset previously in the manner soon to be described. Thus, the positive charge carriers accumulate in the potential well beneath F2, The potential of F2, i~ no charge is trans~erred from Fl, is V4 + ~2~ assuming that the capacitance o~ the electrode ~:~
14-mb is considerably larger than the capacitance of ~
: to the substrate plus the capacitance o~ electrode 16a-0.
OtherwiSe, the potential of F2 will be V4 + ~2~ where A~2 depends upon the relationship of the capacitance ' between the electrode 14-mb and F2, and the total capaci-tance o~ F2.
The above ~low o~ charge, if present, results in . 15 a positive change in potential at F2 and as the latter is ~-connected to 16a-0, a corresponding voltage change at 16a 0. -.
The latter is the gate electrode for another shift register . 16a-1, 16a-2 and so on.
I~, during ~ time, the control voltage VcO is - ~ relatively negative with respect to source S4, charge will ~
; propagate ~rom S4 through the conduction channel beneath ~ ' 17a. Now, depending upon whether l~a-O is relatively negative (no charge at F2) or relatively positive with respect to S2 (charge present at F~) the charge ~rom S
.~ 25 ~ will or will not pass to the ~irst potential well - the one electrode 16a-1. Thereafter, this in~ormation propa- ::
gates to the right. If, on the other hand, VcO is rela-tively positive, say at ground, then no in~ormation can pass irom F2 to the 16a-1, 16a-2 . . . register.

.
~i " ~

RCA 63,696 84~7 :
1 A~ter the termination o~ VCO, the ~2 pulse terminates while the ~1 pulse is on and the second control ` voltage pulse Vc2 occurs. This pulse causes the region o~
the substrate beneath control electrode 14-(n~l) to operate as a conduction channel and any charge at F2 is conducted via this channel to the drain D. A~ter the charges have transferred, the second floating electrodes ~2 is reset to a negative value close to that o-~ V4 by the control pulse Vc2 . V4 may be some value such as -5 volts or so.
- 10 When lt is desired to introduce new in~ormation into the shi~t register, electrode 17 is made relatively positive with respect to S2, that is, it is placed at a potential such as ground and a relatively negative pulse or pulse train VREG is applied to 17-b. The relatively ; positive VREG voltage causes electrode 17 to prevent the passage o~ charge carriers ~rom the source S to the -~ 2 - potential well beneath electrode 16-1 regardless o~ the potential at 16~0. Thus, i~ no in~ormation is inserted -~ at VIN, VRE~ will, in e~ect, insert a O into the ~hift register in response to each ~1 pulse, e~ectively erasing the successive bits stored in the shi~t register system.
New in~ormation may be inserted by applying an appropriate voltage VIN to gate electrode 16b-O in coincidence wlth the pulse ~ applied to 17-b during each negative ~1 pulse. I~ VIN is negative during the ~1 pulse, the source electrode S3 trans~ers charge to the ;~ potential well beneath electrodes 16-1 and 16b-1. These two electrodes are really the same electrode, a common electrode, shown ~eparately ~or the sake o~ drawing con-venience, which is able to receive charge either via the .

.

.,~ :- . , ~ .................................. . .

RCA 63,696 ~8~38~7 1 channel controlled by electrodes 17 and 16-0 or via the channel controlled by the electrodes 17-b and 16b-0. If, on the other hand, VIN is relatively positive as, ~or example, at ground potential, during the negative pulse ~ 5 V~EG, then there is a potential barrier created beneath - electrode 16b-0 and no charge is transferred ~rom S3 to the potential well created by ~1 beneath electrode 16b-1, 16-1.
The purpose o~ the special stage consisting of electrodes 14-ma and 14-mb and the F2 region is to permit an output signal to be obtained which is delayed by one half cycle ~rom the output signal available at the first ; shift register, without any additional capacitive loading of the first output stage. The construction o~ this special output stage can be extended to a multi stage structure, each stage consisting o~ 14-ma, ~4-mb, F2, , successive stages driven by successive phases. This new and improved structure is useful as a so-called "bucket-brigade" circuit such as described in F.L.J. Sangster, ~20 "Integrated MOS and Bipolar Analoy Delay Lines using Bucket-Brigade Capacitor Storage", ISSCC Digest Technical apers, p. 74, 1970. Such bucket brigade circuits are made by a standard p-MOS process. The new structure of FIGURE 51 is made by using self-aligning silicon gate techniques discusssd later and this permits the con-struction of considerably more compact circuits. It also provides a method for making the capacitance of the electrode (electrode 14-mb) overlapping the diffused floating junctions more reproduceable. A further feature ~-o~ this circuit is the virtual elimination o~ the unwanted . ~
: ~, .~.. ..
'~ ' ~. ,' '','" ' RCA 63,696 8~L7 1 feedback capacitanee between th~ stages. The latter is posslble becau~e the ~loating junction regions are di~used with the silicon-gates, such as 14-ma and 14-(n-~1) in the case shown in FIGURE 519 being used as the mask.
The new structures ~or bucket-brigade shi~t ; registers which also can be used as a sel~-scanned photo-sensor array can be made in the same way as two-phase : charge-coupled shift registers, using two thicknesses o~
channel oxide to obtain the asymmetrical potential wells such as shown in FIGURES 14 or 17. However, in the new : bucket-brigade structures, the two di~erent thicknesses of the channel oxide are not essential ~or operation but may be u~ed as an additional control over the relative values o~ the silicon-gate and the aluminum capacitances ~ -in optimizing the design o~ these circuits.
In the operation o~ the bucket-brigade circuit above, charges representing information are trans~erred ;. between reverse-biased floating junctions such as the : region F2 in FIGURE 51 under the control o~ the two-phase ;;
20 clock voltage pulses such as ~2 driving, in parallel, the sel~-aligned polysilicon gates such as 14-ma overlapping the ~loating junetion regions 9uch as F2.
' General Cons~derations in the Design: ~
_ o~ Charge-Coupled Shi~t_Circuits ::
A number o~ ~actor9 to be considered in the design oi the eircuits discussed above have already been ~ : touched on. Taking FIGURE 40 as an example, the power :
,. ~
supply V4 serves to set the ~loating region F to some re~erence potentlal V~EF - V4. The power suppl~ potential "' `'' , '`' ' , ' ` ' :

. `. .

RCA 63,696 1 Vl (combined with V3 (FIGURE 29), if the latter is present) . determines the amount o~ charge to be introduced to the potential well under the ~irst storage electrode 16-1. The potential VF of the floatipg region F is the voltage applied to the gate electrode 16-0. When VF = VREF (no charge signal present at F) then the charge made available at S2 may transfer, at an appropriate -time, to the potential well under 16-1. On the other hand, the value of VF, when charge is present, must be sufficient to prevent the flow of charge from S2 to the well beneath 16-1. This value must be more positive then (-Vl ~ VT), where VT is the threshold associated with S~, 16-0. It may be assumed for .' the present purposes that Vc of FIGURE 40 is sufficiently negative that a highly conductive channel is established under electrode 17.
It is clear from the above that by judicious : choice of the values of V4 and Vl, an appropriate value of VF can be obtained in one case (no charge at F), to permit charge flow to a desired degree from S2 to the potential well beneath 16-1 and? in another case (charge at F), to prevent the flow of charge from S2 to the potential well beneath 16-1. The voltage swing at F - the amount of departure of VF from VREF, can be increased by increaslng - the magnitude of ~2 (in FIGURE 40), causing a deeper potential well to form at F and, when charges are present, causing more such charges to accumulate and thereby causing a greater positive swing of VF.
In the discus~ion of FIGURE 29 the various circuit distributed capacitances were introduced. The total capaci-tive loading CF of the floating region F is:

CF = Ca ~ Cb + C3 ~ C4 ~ C5 ~ . .

RCA 63,696 1 The change in voltage ~V~ produced at F as a result of charge transfer Q to F is:
F = Q
F
For a relatively high resistivity substrate, the major contributors to CT may be Ca and C5. Therefore, in this environment ~VF may be increased substantially for a given Q by reducing Ca and C5 to a minimum. This implies a short dimension LC f FIGURE 40 (assuming that the capaci-tance between 17 and 16-0 is relatively low in FIGURE 40) and minimum overlap between 14-n and F as, ~or example, is shown in FIGURE 43. However3 as discussed in connection with FIGURE 43, somewhat more complex timlng signals are needed and it may sometimes be desirable to ~acri~ice some of the voltage gain in the interest of simpli~ying the timing and other considerations. Tbe effect on the ; circuit operation of increaslng the capacitance at Ca has already been discussed. ~-~

Speed o~ Operation The speed o~ operation which can be achieved with the charge-coupled shift registers described above depends, in part, upon tbe time it takes to transfer a charge ~rom one potential well to the next adjacent potential well.
This eharge trans~er can be accomplished in three di~ferent ;
ways:
1. Diffus~on.
2. By means o~ a self-induced drift field which results from the gradient o~ the suri'ace potential due to an uneven charge distribution in or between the two potential wells, and ,~

~ . , ' : -RCA 63,696 1 3. By an externally induced drift ~ield resulting from the ~ringing ~ield between tbe two electrodes.
Computer calculations relating to 3 above have shown that for a sufficiently high substrate resistivity, the self-aligned electrode structures discussed above which -~ permit the separation between two adjacent electrodes to be equal to or less than the spacing o~ an electrode from the substrate~ can be made to operate so that the complete ~ transfer of charge is accomplished mainly in response to ~ 10 the fringing field and in a time o~ the order of nanoseconds.
On the other hand, mechanism 2 above, which can be considered also as a diffusion mechanism with a diffusion coef~icient . ~ .
proportional to charge density, results in the transfer o~
charge in a manner similar to the discharge o~ a resistor-; ~ 15 capacitor (RC) transmission line. However, as contrasted ~`~ to the latter, with mechanism 2 the charge trans~er becomes - progressively slower than the RC time constant as a ~unction~
of the amount o~ charge which has been removed from the potential well. Accordingly, in the absence o~ 3 above, which is expected ~or widely spaced and/or long electrodes, as the potential well becomes emptler, the transfer of .. , ~ .
charge mechani~m beg~ns to depend entirely upon the diffusion of charge carriers lndependentiy of their concentration with a characteristic time constant of L2 where L = the electrode length and D = the di~u~ion coef~icient in cm2/sec. In cases l and 2, the charge transfer e~iciency ; (the degree o~ complateness of charge transfer) is e~pected to be inversely proportional to the frequency o~ operation.
~ith method 3, howevar, a complete transfer of charge can occur essentially in a single dri~t transit time o~ the ;

, ~'~ ' ,, .

~C~ 63,696 ~OBV~

l charge carrlers and thls implies extremely high speed operation, as well as a complete trans~er o~ charKe.
Therefore, while mechanism 2 may significantly contribute to the initial charge transfer, a complete and rapid charge transfer is possible only in the presence of mechanism 3.
When the depletion depth~ are comparable to or greater than the electrode lengths L, and the separation between electrodes is equal to or smaller than the thick-ness of the silicon dioxide layer, the effective charge transfer time tc due to the fringing field for a substrate of infinite resistivity can be approximated by:
t L2 (L ) (l) :

where the equation above is derived from Emin= 2 a~V (2) : L
tc ~ L (3) min where Emin= the electric field present under the ~2 electrode (see below) 2 = the mobility = 250 cm /volt-seconds for n-type silicon.
~ V represents the difference between the voltages applied to two adjacent charge coupled electrodes. The 25 e~u~ation was derived for a 3-phase charge coupled shift register when the ~2 voltage was decreasing, the ~3 voltage was increasing and the ~l voltage was 0. The charge was being transferred from the potential well under a ~2 electrode to the potential well under the ~3 electrode.
At the instant of time of interest, the values of the :-~
.
~ . , .
' ' '~, .. .

lo~v~ 7 RCA 63,696 1 voltages applied to these two electrodes were ~l - volts, ~2 = -V volts, and ~3 = -2V volts, making ~V = V.
a = the thickness o~ the silicon dioxide, that is, the spacing o~ an electrode ~rom the substrate.
While in the case above the value of Emin was obtained analytically (by precise solution of the potential field equations), when a ~inite resistivity is involved, such analytic methods are not applicable. Here~ computer calculations involving approximations ~the solution of Poisson's equations) are required. Such numerical solutions oi the potential field for charge-coupled structures in which the finite resistlvity o~ the substrate ls taken into account, that is, in which the space charge o~ the depletion region has been considered, have shown tbe following. For a configuration of electrodes in which L = 4 mlcrons (~
.
the spacing f between electrodes = 0.2~, a = 2,000 A, substrate resistivity p = 20 ohm-cm, and voltages present on three adjacent electrodes 2, 7 and 12 volts) respective1y~
the minimum ~ringing field at the silicon substrate surface~
(the field which will assist charge transfer) is 2.5 x 103 volt/cm. This corresponds to a transit time - time ~or :~ charge to travel ~rom one potential well to the next, o~
0.5n.sec. The fringing ~ield ~or L = lO~ with all other ; iactors the same is 4 x lO~ volt/cm. correspondin-g to a~
~ 25 transit time o~ lOn.seo.
;~ ~ The Iringing field drops sharply (and transit time increases correspondingly) as the depletion depth : :~' i;
becomes smaller than the electrode length L. The amount o~ iringing iield is a ~unction, among other things, o~
the electrode voltage (the làrger the voltage between the ;
" ~

~ 82-,~" , : ~

. ~ . .

RCA 63,696 1 electrodes and the larger -their absolute values, the - greater the ~ield) the substrate resistivity p (the greater p, the greater the ~ringing field, for a given electrode voltage) and the dimension a (the smaller a, t~e greater the fringing field ~or a given electrode voltage). It was found that when the depletion depth xd becomes less than 6a, the fringing field starts to decrease very rapidly with decrease in substrate resistivity. The condition at which the depletion depth xd is equal to 6a corresponds to the situation when the effective thickness of the silicon ~ -dioxide (which is equal to about 3a) is equal to 1/2xd, i the effective depletion depth. The above condition corresponds to the situation when the voltage drop across the silicon dioxide is equal to the voltage across the depletion depth of the silicon.
Another method for increasing the fringing ~ield for a ii~ed electrode structure for the case of relatively low resistivity substrate consists oi' operating the two-phase structures with a relatively large substrate bias voltage VN. A large substrate bias voltage, by increasing the depletion depths o~ the potential wells, results in '~
larger fringing fields. For example, the numerical solu-tions of the potential fields show that for substrate doping o~ 5 x 1015 cm (which corresponds to resistivity .
~ 25 of 0.8 ohm-cm for n-type substrate) and 4 micron long - electrodes separated by 0.2 micron spaces on 2,000 A
channel oxide, the minimum fringing ~ield is 300 volts/cm for phase-voltages of 2, 7 and 12 volts. However, for the same structure the minimum fringing field is increased to 1,200 volts/cm for phase voltages o~ 12, 17 and 22 volts.
;' ~ 83-:: -.; . .

RCA 63,696 ~80~3~7 l This means that in this case the minimum ~ringing ~'ield is increased by a factor o~ ~our when the substrate voltage is changed ~rom VN = +2 volts to VN = ~12 volts.
The structures o~ the present invention may be employed to achieve high~speed operation. The overlapping electrode structure permits the adjacent electrodes to be spaced close to one another. The separation between the electrodes f (see FIGURE 9) may be made very small -l,OOO A or less (that is, 0.1~ or less). The length L
10 (FIGUR~ 9) can be small, 13~ or less - perhaps as small as 5~, as can the length k (FIGURE 9) which may be 2-5~.
The small length k is readily achieved by the seli'-aligned ~ silicon gate technique.

-~ The computer analysis discussed brie~ly above indicates that the use of a relatively high resistivity - substrate (10 or more ohm-cm) can provide bit rates o~ the order of 10 bits per second or more. However, high packing density circuits such as are desirable ~or serial memory applications can be best achieved by using two-phase 20 structures ~or the charge coupled circuits. O~ these structures, the one using only the two thicknesses of silicon dioxide and without voltage o~fset (as shown in FIGURE 9) employs a relatively low resistivity substrate such as one having a resistivity oi~ the order o~ three to one ohm-cm. These re~isters are designed to operate in the to the lO bit per second range. To achieve the higher bit rates with these structures, a relatively large sub-~trate bias VN such as +lO volts or more may be used. To achieve bit rates in excess o~ 108, the two phase structures 3 employing the direct o~set voltages (as shown in FIGURE ll) -8~-.' '' '~

RCA 63,696 8~

l are preferred as they can be made with high (as well as low) resistivity substrates.
Another -~actor to be cons~dered in determining the operating speed of the circui1;s discussed above is the response time of the signal regeneration circuits (circuits such as discussed in connection with FIGURES 37-40, for example). Here, the time needed to reset the floating junction F to a re~erence potential must be considered as well as the time required to transfer charge to the floating junction and the time needed to place charge in the ~irst potential well of the next register (the well beneath electrode 16-l) under the control o~ the floating junction.
The transfer of charge into the floating junction, in principle, can be as fast as the time required to transfer charge between two adjacent potential wells. The time required for resetting the floating junction to the refarence potentlal (the potential ~4), is comparable to ; the charge transfer time and can be speeded up by employing a sufficiently large reset pulse VR. The remaining factor, namely the time required to transfer charge to the potentiai well beneath electrode 16-l is the main limitation in the response time of the signal regeneration circuit. However, this is not a serious limitation as it can be shown that $or a voltage o~ two volts or more this charge transfer time can be of the order of several nanoseconds.
.' Methods of Fabrication The discussion which follows of the fabrication techniques which may be employed to construct the charge ; 30 coupled devices described above relates to processes which .'``' ~ ' ~ ' ' ' ' ' ` ' , ' . `

RCA 63,696 1 are in themselves known ln the int;egrated circuit art.
Therefore, the description is somewhat abbreviat~d and such well-known processing steps as cleaning the wa~ers, applications of photore~ist, annealing of the channel oxide, alloying the silicon to aluminum contacts and other common procedures are implied but are not discussed in detail.
FIGURE 52 should now be referred to. As shown in FIGURE 52a, a thick silicon-dioxide layer 240 (about 10,000 A thick) is thermally grown on the silicon sub-. strate 242. Then, as shown in FIGURE 52b, the portion of the silicon dioxide at which the electrodes and the diffused regions D, F and Sl will be ~ormed is et~hed away. Then, as shown in FIGURE 52c, a thin layer 244 o~
silicon dioxide (perhaps 500 A - 2,000 A thick) is ~ ~
thermally grown on the substrate. ~ .
Next as ~hown in FIGURE 52d a polysilicon layer ; ~46 (about 3,000 to 5,000 A thick) is epitaxially deposited over the silicon wafer 242 both over the thin and the thick silicon dioxide regions. Thereafter, a mask is employed : to de~ine the regions o~ the substrate at which the p+
regions will be ~ormed by removing all o~ the polysilicon that is not used for the gates ~r electrodes, In brie~, a photoresist may be deposited through this mask and portions of the polysilicon and silicon dioxide de~ined by . the non-hardened regions on the photoresist etched a~ay to leave the structure shown in FIGURE 52e.~ This exposes certain regions 248-~50 of the substrate. Thereafter, a source of p+ material such as boron is employed to form the PN junctions as illustrated in FIGURE 52f. Note in . -8~-.
.
,. , ~ , ' .

RCA 63,696 47i 1 this operatlon the polysilicon regions and, in other places, the thick silicon dioxide, are used as the diffusion mask.
After the steps above, a second thin silicon dioxide layer ~,000 A - 6,000 A thick may be deposited over the entire sample as shown in FIGURE :52g. The function of this oxide is to serve as the dielectric isolation be~
tween the polysilicon and the aluminum electrodes of di~erent voltage phases. This oxide also may be deposited before the deposition of the sources and drains. Next, another mask may be employed to de~ine the regions etched away in FIGURE 52h. Then, the etching is accomplished to leave behind the polysilicon portions o~ each electrode ` pair as shown at 252-257. In FIGURE 52h, the p~ region in the substrate may be the source Sl, the floating region F
and the drain D. The electrode 258 may be the control electrode which is employed to reset the floating electrode F to the voltage o~ the draln D.
The remaining steps in the process should be self-evident and are not illustrated. First, an additional 20 silicon dioxide layer is thermally grown or deposited to produce the desired thickness of channel oxide under the aluminum electrodes and to iæolate the polysilicon electrodes. Then contact openings are made wlth another mask to the p+ regions in the substra$e and at places on the polysilicon requiring a connection to the aluminum conductors or electrodes to be deposited subsequently.
Then, a continuou layer of aluminum may be deposited over the sample. Then another mask may be employed to define the aluminum electrodes. Then portions of the aluminum may be etched away to de~ine the aluminum electrode ~tructure.

~, , ~ ~ ' ! , . .
'' ' RCA 63,696 8~

1 In the step shown in FIGURE 52h, if desired, a portion o~ the silicon dioxide channel region 244 may be etched away. Whether or not this i9 done depends upon how close it is de3ired that the aluminum electrode be to the substrate. I~ it is desired that the aluminum electrode be as close to the substrate as the polysilicon electrodes, then portions of the layer 244 must be etched away in view of the next layer of silicon dioxide which will be layed down. On the other hand, if the aluminum electrodes are to be spaced ~urther ~rom the silicon substrate then the poly-silicon electrodes, then the etching may stop as shown in : FIGURE 52h.
; In accordance with a second method o~ manu~acture ;~
essentially the same structure, but without sel~-aligned ;~
di~fusion, can be made by modifying the sequence of opera-:: tions. In this case, the p+ regions may be formed in the n-type substrate before the growth o~ the thick silicon . .
~ dioxide (before the step depicted in FIGURE 52a)- Now, .~ as the thick oxide is grown, the p~ regions will be driven ~ 20 deeper into the substrate. In addition 7 with this tecbnique ;~ one o~ the masks may be employed both ~or etching the polysilicon electrodes 252-257 as ~ell as the polysilicon control electrode Z58, While in the main part of the discussion in this application speclfic materials are given to illustrate the invention, it is to be understood that these are examples only. In many cases di~ferent materials than those specified may be used. For example, while it is presently believed that silicon is a pre~erred substrate material other materials such as germanlum or gallium arsenide, as . -88-- ,. . .

RCA 63,696 8~
1 examples, may be used instead. Further, even in the case of silicon, p~type substrates may in some cases be pre-~erred to n-type substrates. In p-type substrates, the charge carriers are electron~ and their mobility ls about twice that o~ holes and this implie~ that ~aster charge coupled structures may be ~abricated in this way. In addition, rather than employing polysilicon and aluminum ~or electrodes, other materials such as polysilicon and one o~ molybdenum, or molybdenum-gold, or platinum-titanium-gold, or tungsten-aluminum, or aluminum silicon alloys or f any one o~ a number o~ such metals may be employed instead.
Substitutions ~or the polysilicon are also possible using the t~o-layer metalization technology. An example ls the use o~ anodized aluminum ~or the ~irst metal layer (aluminum~
oxide, in this case,-would be the insulator or one o~ the insulators bet~een this metal electrode and the second one og the pair). In addition, while silicon dioxide has many advantageous properties, other insulating materials such as aluminum oxide and silicon nitrlde may be employed on silicon substrates and many other high quality dielectrics may be used instead on substrates other t~an silicon.
It i~ to be understood that the dimensions given ~;
by way o~ example above are ~or the case o~ system~ made ~i by integrated clrcuit techniques, such as by using contact or projection printing ~or the development o~ the photo~
resist. The same type o~ structures can be made con~
siderably smaller in dimensions) which means that it can be made $o be capable o~ higher speed performance, by the ;
use oi' a scanning electron beam for the exposure o~ the ~;;
photoreqist or even ~or the direct making o~ the electrodes.

... ,.~ . . .
, ~ ,' " ' ' , . .

RCA 63,696 1 Here, the alignment between di~erent layers o~ the structure can be automated employing ~eedback techniques and a dlgital computer ~or control. Using thl~ manu-~acturing technique, length dimensions o~ electrodes are obtained o~ the order o~ one micron (10 6 meters) or less.

., `; 15 .~

25.

.

:: 3~

~ ' ' '' .. :.

Claims (25)

1. In a two-phase operated, charge-coupled circuit, in combination:
a substrate formed of semiconductor material at which charges may be stored;
a plurality of rows of a relatively thin insulating layer on said substrate, each such row defining a length of the substrate along which charges are to propagate;
a plurality of electrode means adjacent to one another along the length of each row, each such means for creating an asymmetrical potential well in said substrate which is substantially deeper at the portion of the well facing the desired direction of signal propagation along the length of its row than the portion of the well facing opposite to the desired direction of signal propagation; and means for applying one phase of a two-phase shift voltage to alternate electrode means of each row and the second phase of said shift voltage to the other electrode means of each row.

2. In a two-phase operated charge-coupled circuit as set forth in claim 1, each electrode means comprising a pair of electrodes, one closer to the substrate than the other.

3. In a two-phase operated charge-coupled circuit as set forth in claim 1, each electrode means comprising a pair of electrodes, one electrode maintained at a different direct voltage level than the other.

4. In a two-phase operated, charge-coupled circuit as set forth in claim 1, further including relatively thick insulation on said substrate separating said rows from one another; and in which each electrode means of a row includes a conductive layer which is spaced from the substrate by said relatively thin insulation layer, the corresponding electrode means in at least two adjacent rows being formed as a continuous conductive layer which passes from one row, over the thick insulation between that row and the next row, to said next row.

5. In a two-phase operated, charge-coupled circuit as set forth in claim 4, each electrode means including, in addition to said conductive layer, a conductive line which passes from at least one row to the next adjacent row, being spaced from the substrate by said relatively thin insulation in said two adjacent rows and by relatively thick insulation between said two rows.

6. In a two-phase operated, charge-coupled circuit as set forth in claim 5, each conductive line forming with each conductive layer an electrode pair at least two adjacent rows, the conductive layer spaced from and overlapping one side of the line in one of said rows and spaced from and over-lapping the other side of the line in the other of said rows.

7. In a two-phase operated, charge-coupled circuit as set forth in claim 6, each conductive layer being in direct contact with the conductive line it overlaps at a place located over said relatively thick insulation layer.

8. In a two-phase operated, charge-coupled circuit as set forth in claim 6, each conductive layer being maintained at a different direct voltage level than the conductive line it overlaps such that a deeper potential well forms under the line than under the conductive layer at each relatively thin film region.

9. In a two-phase operated, charge-coupled circuit as set forth in claim 7, in each row having a relatively thin insulation layer, said layer being substantially thinner between said line and said substrate than between said conductive layer and said substrate, whereby in response to a given voltage applied to a line and the layer overlapping that line, a deeper potential well forms beneath the line than the layer.

10. In a two-phase operated, charge-coupled circuit as set forth in claim 6, each conductive layer overlapping a given conductive line at a plurality of pairs of adjacent rows, and further including, over the thick insulation layer between each pair of rows, a direct, conductive connection between the conductive layer and said given conductive line.

11. In a two-phase operated, charge-coupled circuit as set forth in claim 5, each conductive layer comprising an undulating line extending in the column direction and each conductive line comprising also an undulating line which extends in the column direction, which passes under a conductive layer at spaced points, over said thick insulation, along the length of said line, and which between these spaced points, undulates in an opposite sense to the undulating layer it passes under.

12. In a two-phase operated, charge-coupled circuit as set forth in claim 5, each conductive layer comprising an interdigital structure having a main trunk extending over the thick insulation between a pair of rows and tabs extending in opposite directions from the main trunk over the thin insulation layer of said pair of rows, a tab extending in one direction spaced from and overlapping one edge of a given conductive line and an adjacent tab extending in the opposite direction spaced from and overlapping the opposite edge of the same conductive line.

13. In a two-phase operated, charge-coupled circuit as set forth in claim 12, each conductive line also comprising an interdigital structure having a main trunk which lies beneath and is closely capacitively coupled to the main trunk of a corresponding conductive layer.

14. In a two-phase operated, charge-coupled circuit as set forth in claim 5, each conductive line comprising a highly doped semiconductor.

15. In a two-phase operated, charge-coupled circuit as set forth in claim 14, further including a first highly conductive metal bus extending over a relatively thick insulation region in physical conductive contact with alter-nate ones of said lines, and a second highly conductive metal bus extending over a relatively thick insulation region and in physical conductive contact with the remaining lines.

16. A semiconductor shift register array comprising:
(a) a semiconductor body;
(b) means for injecting charges in the body, said means for injecting charges in the body comprising a diode biased to inject minority carriers into the body and a gate to control the flow of charges from the diode into the body;
(c) a pair of electrode systems capacitively coupled to the body;
(d) means for impressing voltages varying with time to each of said pair of electrode systems for producing stepped depletion regions in the body and sequentially transferring the accumulation of charges through the body; and (e) means for sensing the transferred charges.

17. The array of claim 16 wherein said electrode system comprises a series of conductive lines formed over an insulating layer formed on the surface of the body.

18. The array of claim 16 wherein said voltages are between 90 degrees and 180 degrees out of phase with one another.

19. The array of claim 16 wherein said sensing means comprises a biased semiconductor device coupled between the body and a power source.

20. The array of claim 16 wherein said sensing means is also coupled to said injecting means for regenerating the transferred charges and reinjecting said charges in the body.

21. A semiconductor device comprising a body of semiconductor material of one conductivity type, an ununiform insulating layer on the surface and a pair of electrodes on said layer arranged to create in said body a plurality of ununiform depletion regions upon the imposition of a time varying voltage to each of said electrodes, said voltages being equal in magnitude and out of phase, and wherein each of said depletion regions has at least four layers with each layer having a greater field intensity therein than the preceding layer.

22. A semiconductor device which utilizes the generation and mobility of charges in depletion regions created at the surface of a semiconductor body to transmit information as collected charges comprising a semiconductor body, an ununiform insulating layer on the surface of the body, said layer having a plurality of depressed, inter-connected parallel, elongated troughs therein, said troughs serially interconnected to form a serpentine pattern, said troughs being offset in their elongated direction, an inter-digitated pair of electrodes formed on the surface of the layer and crossing said troughs substantially perpendicular to said elongated direction, and means for impressing pulsed, out of phase, overlapping voltages on said electrodes to alternately create and extinguish depletion regions in said body beneath the troughs to transport charges through the body.

23. A semiconductor device utilizing the generation and mobility of minority type charge carriers in depletion regions in a semiconductor body to transmit information which comprises a semiconductor body and first and second electrode structures formed on a surface of the body, each of said structures having a plurality of parallel strips connected at one end thereof to a common point, one of said strips being disposed parallel and adjacent to two of said strips of said other electrode structure and insulation means between said structures and said body for creating in said body progressively increasing depletion regions, and wherein said insulation means comprises a layer of insulating material formed on a surface of said body, said layer having a series of parallel ridges perpendicular to said strips, said ridges defining between them a depressed, serpentine pattern, the insulating layer in said pattern arranged to modify any effect in said body by the said imposition of voltages on said strips.

24. An integrated semiconductor device comprising a semiconductor body of uniform conductivity type, an insulating layer on a surface of the body, means for injecting charges in the body, interdigitated electrodes formed on the layer, means for impressing a first time varying voltage signal on first of said electrodes, means for impressing a second time voltage signal on the second of said electrodes, said first and second voltage signals being equal in magnitude and frequency and overlapping and out of phase, said layer being adapted to vary the effect of the impressed voltages in said body to create under the electrodes a series of contiguous depletion regions, each depletion region having levels of lesser and greater electrical field intensities therein, the injected charges migrating within the depletion regions from the level of lesser field intensity to the level of greater field intensity, said depletion regions being alternately created and extinguished in the body by said time varying signals to continually expose the injected charges to a greater field intensity causing said charges to flow through the body in a predetermined direction and means for detecting the presence of said charges in said body.

25. A semiconductor device which utilizes the mobility of minority charge carriers in depletion regions in a semiconductor body to transmit information which comprises a semiconductor body, an insulating layer disposed on a surface of said body, said insulating layer arranged to define a serpentine track under which said charge carriers can be transmitted and monolayer electrode array disposed on said layer and across said track to selectively create and extinguish depletion regions under said track when alternately applied time varying signals are impressed on said array.