CA1078921A - Inverter control system - Google Patents
Inverter control systemInfo
- Publication number
- CA1078921A CA1078921A CA260,273A CA260273A CA1078921A CA 1078921 A CA1078921 A CA 1078921A CA 260273 A CA260273 A CA 260273A CA 1078921 A CA1078921 A CA 1078921A
- Authority
- CA
- Canada
- Prior art keywords
- inverter
- voltage
- voltages
- phase
- commutation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
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Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/66—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output with possibility of reversal
- H02M7/68—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output with possibility of reversal by static converters
- H02M7/72—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output with possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/75—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output with possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a thyratron or thyristor type requiring extinguishing means
- H02M7/757—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output with possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a thyratron or thyristor type requiring extinguishing means using semiconductor devices only
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/02—Conversion of ac power input into dc power output without possibility of reversal
- H02M7/04—Conversion of ac power input into dc power output without possibility of reversal by static converters
- H02M7/12—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/145—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a thyratron or thyristor type requiring extinguishing means
- H02M7/155—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a thyratron or thyristor type requiring extinguishing means using semiconductor devices only
- H02M7/162—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a thyratron or thyristor type requiring extinguishing means using semiconductor devices only in a bridge configuration
- H02M7/1623—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a thyratron or thyristor type requiring extinguishing means using semiconductor devices only in a bridge configuration with control circuit
- H02M7/1626—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a thyratron or thyristor type requiring extinguishing means using semiconductor devices only in a bridge configuration with control circuit with automatic control of the output voltage or current
Abstract
INVERTER CONTROL SYSTEM
Abstract of the Disclosure An inverter in a D.C. power transmission system is controlled by gate pulses which are synchronized with voltages of an A.C. system and whose interval is constant for respective arms of the inverter. To prevent the inverter from causing a commutation failure upon occurrence of a fault in the A.C. system, a control voltage for the gate pulses is corrected by use of the magnitude of the unbalance of the phase difference between the voltages of the A.C. system.
The control voltage becomes greater, as the phase voltage or the line to line voltage falls from the rated voltage.
When the control voltage increases, the gate pulses are provided at a timing having a larger advanced control angle so as to maintain the extinction angle constant.
Abstract of the Disclosure An inverter in a D.C. power transmission system is controlled by gate pulses which are synchronized with voltages of an A.C. system and whose interval is constant for respective arms of the inverter. To prevent the inverter from causing a commutation failure upon occurrence of a fault in the A.C. system, a control voltage for the gate pulses is corrected by use of the magnitude of the unbalance of the phase difference between the voltages of the A.C. system.
The control voltage becomes greater, as the phase voltage or the line to line voltage falls from the rated voltage.
When the control voltage increases, the gate pulses are provided at a timing having a larger advanced control angle so as to maintain the extinction angle constant.
Description
)789Z~
Back~round of_the Invention This invention relates to an inverter control system for use in D.C. power transmission, and more particu-larly to a control system for maintaining the gate pulse interval constant.
The so-called individual-phase control system has hitherto been adopted as a phase control system for the gate pulses of an inverter in D.C. power transmission. This system determines the phases of the gate pulses of the respective arms of the inverter, gate pulse phase shifters, which employ the commutation voltages of the respective arms for their synchronizing power sources, being disposed to correspond with thyristor valves of the arms. In order to perform a stable operation without any commutation failure, even when an unbalanced fault occurs on the A.C. side of the ..
inverter when using such an individual-phase control system, the control may be made to be such as to attain a prescribed extinction angle by detecting a drop of the commutation voltage and increasing the advanced control angle by the amount of an increment of the overlapping angle ascribable to the drop of the commutation voltage.
This method of increasing the advanced control angle B
in dependence on the drop of the commutation voltage cannot, however, always achieve stable operation when using a gate pulse phase shifter-, as proposed in United States patent no. 3,891,912 issued June 24, 1975 to Hitachi Ltd. by which phase variations of the synchronizing power sources are average by means of a voltage-controlled oscillator so as to render the gate pulse interval constant. Even if the phase of one commutation voltage leads, that of another commutation voltage will lag by the same amount, so
Back~round of_the Invention This invention relates to an inverter control system for use in D.C. power transmission, and more particu-larly to a control system for maintaining the gate pulse interval constant.
The so-called individual-phase control system has hitherto been adopted as a phase control system for the gate pulses of an inverter in D.C. power transmission. This system determines the phases of the gate pulses of the respective arms of the inverter, gate pulse phase shifters, which employ the commutation voltages of the respective arms for their synchronizing power sources, being disposed to correspond with thyristor valves of the arms. In order to perform a stable operation without any commutation failure, even when an unbalanced fault occurs on the A.C. side of the ..
inverter when using such an individual-phase control system, the control may be made to be such as to attain a prescribed extinction angle by detecting a drop of the commutation voltage and increasing the advanced control angle by the amount of an increment of the overlapping angle ascribable to the drop of the commutation voltage.
This method of increasing the advanced control angle B
in dependence on the drop of the commutation voltage cannot, however, always achieve stable operation when using a gate pulse phase shifter-, as proposed in United States patent no. 3,891,912 issued June 24, 1975 to Hitachi Ltd. by which phase variations of the synchronizing power sources are average by means of a voltage-controlled oscillator so as to render the gate pulse interval constant. Even if the phase of one commutation voltage leads, that of another commutation voltage will lag by the same amount, so
- 2 -1078~2~
that the averaged phase variation i9 zero. This method of increasing the advanced control angle ~ according to the drop of the commutation voltage cannot cope with changes vf the phases of the commutation voltages. As a result, the arm in which the phase of ~he commutation voltage~leads falls to an insufficient extinction angle and can cause commutation failure.
To avoid this problem, we have proposed in U.S. Patent No. 4,028,607 issued June 7, 1977 to Hitachi Ltd., that the control voltage for the gate pulse be corrected by the use of the lowest one of the phase voltages or line to line voltages of the A.C. system.
Thls proposed system, however, is not always fully satisfactory, because the extinction angles obtained in case of faults in the A.C. system are sometimes larger than those suitable for the faults. This is attributed to the fact that the relation of amplitude and/or phase angle between the phase voltage and the commutation voltage varies according to the kind of the fault in the A.C. system or the connection of a transformer. Extinction angle~ larger than necessary place limits on the transmission power of the inverter.
Summary of the Invention It is accordingly an object of this invention to provide an inverter control system which is so contrived that, when a fault takes place in the A.C. system, the phase of a gate pulse can be instantly and suitably controlled in the direction of stabilizing the operation of an inverter.
Generally speaking, this invention accomplishes this object by providing means to output the gate pulses accurately at a fixed interval, and means to shift the phases of the gate pulses to be applied to the inverter, depending on the state of its operation, by introducing into the phase ~ .
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shifting means a signal corresponding to the condition of phase variation of the commutation voltages of the inverter.
More specifically, the invention consists of an in-verter control system for an inverter connected between one side of an inverter transformer and a D.C. system, the other side of said transformer being connected to an A.C. system, said system comprising (a) first means for deriving a signal corresponding to an advanced control angle of said inverter in accordance with voltages of said A.C. system applied to sald inverter and current in said D.C. system, (b) second means for deriving a phase correction signal in response to an unbalance of said A.C. voltages applied to said inverter, said phase correction signal corresponding to the magnitude of the unbalance of phase differences among respective phases of commutation voltages applied to said inverter, (c) third means to synthesize the outputs of said first and second means, and (d) fourth means for generating firing pulses whose phases are determined in accordance with the output of said third means.
Brief Descri~tion of the Drawings FIG. 1 is an overall connection diagram showing the arrangement of an inverter in D.C. power transmission;
FIG. 2 is a waveform diagram for explaining phase changes of commutation voltages;
FIG. 3 is a block diagram showing the essential portions of an embodiment of this invention;
FIGS. 4a-c, 5a-c and 6a and b are vector diagrams for explaining voltages in case of various faults in the A.C.
system (FIGS. 6 are with FIGS. 4 on a sheet);
FIG. 7 is a graph for explaining the phase variation of the commutation voltage for the inverter in case of faults in the A.C. system;
~ - 4 -B
~.0'78~21 FIG. 8a and b are vector diagrams for explaining the phase variation and the amplitude of the cu~mutation voltage for the inverter in case of faults in the A.C. system;
..
- 4a -1078~,~2~, FIGS. 9, 10, 11, 12, 13 and 13' are connection diagrams showing examples of specific circuits to be used in the embodiment of FIG. 3;
FIGS. 13", 14 and 15 are diagrams showing characteristics of circuits to be used in the embodiment of FIGS. 13 and 3;
FIGS. 16 and 17 are block diagrams for explaining examples of specific circuits of equidistant pulse phase control devices which can be employed in this invention; and FIG. 18 is a waveform diagram for explaining the ~ !
operation of the circuit in FIG. 17.
Detailed Description of the Preferred Embodiments As previously stated, this invention realizes control of the gate pulse interval, and prevents an inverter from failing in commutation, even when faults occur in the A.C. system. Hereunder, the invention will be explained in conjunction with an embodiment thereof. A description will first be given of what influences faults in the A.C. system have on the inverter.
An example of a D.C. power transmission system is shown in FIG. 1. Referring to the figure, T designates a transformer, Vl - V6 are the arms of an inverter constructed of thyristor or mercury valves, and LDC is a D.C. reactor.
The D.C. input side of the inverter is connected through D.C.
lines to other terminals. On the A.C. side the terminals of the transformer T are connected to an A.C. system, the respective phases of which have voltages Va, Vb and Vc.
These line to ground voltages are detected through potential transformers PTa, PTb and PTc and are delivered to a control circuit (not shown) including a gate pulse phase shifter.
DCCT denotes a D.C. current transformer, while IV indicates a current - voltage converter with an output terminal kid.
Normally, the three voltages Va, Vb and Vc are balanced, as shown by the solid-line waveforms in FIG. 2.
Consider the case where a one-line grounding fault occurs in the A.C. system and the voltage Va drops as shown at Va'.
Where the transformer connection is a star-star connection, as in FIG. 1, the commutation voltages are equal to the line to line voltages, and their zero points are the inter-section points of the phase voltages, e.g. the point to.
Accordingly, when the voltage Va drops to Va', the phase of the intersection point to' and hence that of the commutation voltage leads phase-b by ~ and lags phase-c by ~ as illustrated in FIG. 2. Namely, the intersection points of the phase voltages Va and Vb transfer from to to to'. Therefore, to avoid commutation failure in all the arms Vl, V2,.... V6, the advanced control angle has to be made larger by ~ than the normal one.
As is well known, the relation among the commutation voltage, the extinction angle y and the advanced control angle ~ is expressed by the following equation:
c O s r - c O s ~ = Ea (1) where r denotes the extinction angle, ~ the advanced control angle, Ea the commutation voltage, Id the D.C. current, and x the commutation reactance. The reference point for the phases of the angles r and ~ is the zero point of the commutation voltage.
According to the embodiments of the present invention, the advanced control angle ~ for obtaining the prescribed extinction angle depending on the magnitude of the commutation voltage and the magnitude of the D.C. current, 107892~.
is evaluated on the basis of Eq. (1), the change ~ of the phase of the commutation voltage being evaluated from the magnitude of unbalance of the A.C. voltages. A control voltage corresponding to ~AP = ~ + ~ is then applied to the gate pulse phase shifter, whereby stable operation is made possible at the minimum required extinction angle for any fault in the A.C. system.
FIG. 3 shows such an embodiment of the invention.
In this figure, the same symbols as in FIG. 1 indicate the same parts. APT represents an auxiliary potential transformer.
Recl - Rec3 represents rectifier circuits for converting A.C.
voltages to D.C. voltages. HVCl and HVC2 designate high value circuits which select the maximum input from among a plurality of inputs, while LVCl - LVC5 designate low value circuits which select the minimum input from among a plurality of inputs. DVCl and DVC2 denote divider circuits, FGl and FG'l denote gate pulse phase calculating circuits, FG2 and FG3 denote gate pulse phase correction calculating circuits, AD
denotes an adder, and AP denotes an automatic gate pulse phase shifter.
Before explaining the operation of the embodiment in FIG. 3, the magnitudes and phases of commutation voltages in cases where various faults occur in the A.C. system will be described with reference to FIGS. 4 to 8.
FIGS. 4(a) to 4(c) illustrate the situations of the commutation voltages in a case where the transformer of the inverter is star-star connected. In this case, the line to line voltage becomes the commutation voltage. FIG. 4(a) corresponds to a one-line grounding fault, FIG. 4(b) to a two-line grounding fault, and FIG. 4(c) to a three-line grounding fault. In the figures, the phase voltage at the ~07892~
fault is represented by p, and the phase change of the commutation voltage is represented by ~1.
FIGS. 5(a) to 5tc) illustrate the situations in a case where the transformer of the inverter is of star-delta connected. FIG. 5(a) corresponds to a one-line grounding fault, FIG. 5(b) to a two-line grounding fault, and FIG. 5(c) to a three-line grounding fault. In each of these figures, the left han~ diagram depicts the phase voltages on the A.C.
side of the ~ ansformer, while the right hand diagram depicts those v ~ es that become the commutation voltages on the D.C. side As in the case of FIG. 4, p denotes the magnitude of the ph se voltage at the fault as based on the normal value, and ~2 an ~3 denote the changes of the phases of the commutation voltages.
FIGS. 6(a) and 6(b) illustrate the drops of the phase voltages and the phase changes ~4 and ~5 of the commutation voltages in the case of a two-line short-circuit whether the transformer of the inverter is of the star-star connection or the star-delta connection. FIG. 6(b) illustrates the commutation voltages when the transformer connection is star-delta, when the primary sidç of the transformer becomes as shown in the vector diagram of FIG. 6(a). The situation for a three-line short-circuit is the same as for the three-line grounding fault.
In any of the examples of FIGS. 4 to 6, the vertices of the voltage vectors of the respective phases when the A.C.
system is normal are represented by A, B and C, and those at the occurrence of the fault by A', B' and C'. The commutation voltages for the inverter are the voltages between the vertices, i.e., the line to line voltages of the secondary windings.
When these changes of magnitudes of the commutation voltages and of their phases under fault conditions are collectively studied, the following can be said.
Firstly, study will be made of the commutation voltages in the cases of the star-star connection illustrated in FIG. 4. In the one-line grounding fault of FIG. 4(a), the commutation voltages VAB and VCA (voltages between the vertices A and B and between the vertices C and A) change to VA'B and VCA'. As the result, the phases also change by ~1. At this time, VA'B and VCA' have equal magnitudes.
In the two-line grounding fault of FIG. 4(b), all the commutation voltages change in magnitude, although VA'B' does not change in phase with respect to VAB. In contrast, VB'C and VCA' change in phase with respect to VBC and VCA, respectively, the magnitudes of the commutation voltages VB'C and VCA' being equal. In the three-line grounding fault of FIG. 4(c), all the commutation voltages change only in magnitude and undergo no phase change. It is thus apparent that the number of commutation voltages undergoing phase changes is two in any case in which any phase change occurs, and that the magnitudes of the commutation voltages that do change phase are equal in any of the faults.
Secondly, study will be made of the commutation voltages in the cases of the star-delta connection illustrated in FIG. 5. The commutation voltages to be applied to the inverter are shown in the vector diagrams on the right hand sides of FIGS. 5(a), 5(b) and 5(c). In the one-line grounding fault of FIG. 5(a), VB'C and VCA' differ in both magnitude and phase from VBC and VCA, respectively, but VA'B' differs only in magnitude from VAB and does not differ in phase.
In the two-line grounding fault of FIG. 5(b), VA'B' and VB'C
differ in both magnitude and phase from VAB and VBC, respectively, 107892~
but VCA' differs only in magnitude from VCA. In the three-line grounding fault of FIG. 5(c), all the commutation voltages change only in magnitude and do not change in phase. In FIGS. 5(a) and tb) a vector indicated by Vo designates a zero-phase-sequence voltage which develops on the primary side with the unbalanced faults. The potential of the neutral point of the transformer changes by this zero-phase-sequence voltage, and the neutral point moves from 0 to 0' on the vector diagram. It is apparent that, also in the case of the star-delta connection, the number of commutation voltages undergoing phase changes is two in any case in which any phase change occurs, and that these two voltages have equal magni-tudes.
Study will now be made of the two-line short-circuit illustrated in FIG. 6. FIG. 6(a) illustrates the example in which, in the case of the star-star connection, the short-circuit takes place between the lines of phase-a and the phase-b. The commutation voltage VAB changes to VA'B', the commutation voltage VBC to VB'C and the commutation voltage VCA to VCA'. VB'C and VCA' undergo changes in phase as well as in magnitude. FIG. 6(b) is the vector diagram of the commutation voltages when the fault of FIG. 6(a) occurs on the A.C. side in the case of a star-delta connection. In this case, VAB changes to VA'B', VBC changes to VB'C, and VCA
changes to VCA'. VCA' changes only in magnitude, and VA'B' and VB'C change in phase as well as in magnitude. Also in the cases of FIG. 6, the number of commutation voltages changing in phase is two, and the magnitudes of these voltages are equal. In balanced faults, no phase change arises in any case.
It is accordingly noted that, whichever connection of the transformer may be used, i.e. star-star or star-delta, and whatever the kind of the fault may be, in those faults in which the commutation voltages change not only in magni-tude but also in phase, there are always two commutation voltages undergoing phase changes and these two commutation voltages have equal magnitudes. It will therefore be under-stood that, when the advanced control angle is to be determined by using those commutation voltages whose phases change with a fault, it needs to be made larger by the --magnitude of the phase changes.
In recognition of this fact, the phase changes in the present circuits are derived from the relationship of the magnitudes of the three commutation voltages. The advanced control angle ~ obtained by the known equation (1) above is corrected by the use of the magnitude of the phase changes, and the optimum operation of the inverter is realized.
FIG. 7 is a diagram in which the abscissa represents the magnitude of the phase voltage p with the rated value being 1 (one), while the ordinate represents the change of phase in degrees. Here, ~ 5 indicate the phase changes in the various cases illustrated in FIGS. 4 to 6.
FIGS. 8(a) and 8(b) are diagrams in which the relations of the phases and magnitudes of the commutation voltages are summarized as to the cases of FIGS. 4 - 6. As previously stated, the two commutation voltages whose phases have changed are equal. The circumstances of the commutation voltages can be summarized as shown in FIG . 8(a), wherein the triangle formed of the vectors of the commutation voltages becomes a'bc in such a form that the vertex a of the triangle abc shifts to a'; or as shown in FIG. 8(b), wherein the 1078921;
triangle formed of the vectors of the commutation voltages becomes ab'c' in such a form that the base bc of the triangle abc shortens. Let Q denote the length of the equal sides of the triangle, and m denote the length of the remaining side.
Then the angle ~ is represented by the following equations.
The triangle abc is an equilateral triangle. Therefore, in the case of FIG. 8(a), 30 + ~ = ~
(2) = sin~l Q
-1 m .. ~ = sin 1 2Q ~ 30 and in case of FIG. 8(b), + ~ = 30 ~ + sin 1 2Q = 300 ~ ~ = 30 - sin~l Accordingly, correction signals for the advanced control angle can be obtained by providing circuits for calculating (2) and (3).
Referring again to FIG. 3, the phase voltages Va, Vb and Vc of the A.C. system as derived from the potential transformers PTa, PTb and PTc are applied to the three auxiliary potential transformers APT in delta connection.
On the secondary sides of the three transformers APT, accordingly, the line to line voltages of the A.C. system or the commutation voltages of the inverter are obtained.
107892~
These commutation voltages are applied to the rectifiers Recl, Rec2 and Rec3, and are converted into D.C. voltages.
The high value circuit HVCl receives the outputs of all the rectifiers as inputs, and delivers the greatest one of the inputs as an output. Thus, the greatest voltage in the form summarized in FIG. 8 can be obtained. The low value circuits LVCl, LVC2 and LVC3 each receives two different ones of the outputs of the rectifiers Recl, Rec2 and Rec3 as inputs, and selects and delivers a smaller one of its two inputs as an output. The outputs of the three low value circuits are applied to the high value circuit HVC2. As apparent by referring to FIG. 8, accordingly, the magnitude (Q in FIG. 8) of the two commutation voltages whose phases change due to the fault and whose magnitudes are equal are obtained from the circuit HVC2. The low value circuit LVC4 receives all the outputs of the three rectifiers as inputs, and delivers the smallest one of these inputs as an output.
Thus, the smallest voltage of the form summarized in FIG. 8 can be obtained. Both circuits FGl and FGl' are function generators, which serve to derive voltages necessary for obtaining the foregoing advanced control angle ~ given by the relation of Eq. (1). Accordingly, these circuits receive as inputs a voltage corresponding to the commutation voltage of the inverter and a voltage corresponding to the D.C.
current, and they deliver as an output a voltage corresponding to the advanced control angle ~. As the voltage corresponding to the commutation voltage, the output of the high value circuit HVC2 is introduced into the function generator FGl, and the output of the low value circuit LVC4 into the function generator FGl'. As the voltage corresponding to the D.C.
current, the output of the current - voltage converter 107892~
circuit IV is introduced into both the function generators.
In this way, the function generator FGl provides the voltage for obtaining the advanced control angle necessary for the commutation angles whose phases have changed, as shown in FIG. 8, and the function generator FGl' provides the voltage for obtaining the advanced control angle necessary for the least one of the commutation voltages shown in FIG. 8.
The divider circuits DVCl and DVC2 receive the outputs of the circuits HVCl and HVC2 and the outputs of the circuits HVC2 and LVC4 as inputs, respectively. Letting el, e2 and e3 denote the outputs of the respective circuits HVCl, HVC2 and LVC4, the divider circuit DVCl provides an output of 2el2 and the divider circuit DVC2 provides an output of 2e32. The inputs and outputs of the divider circuits will now be studied in correspondence with FIG. 8.
In the case where the commutation voltages are as in FIG. 8(a) due to the fault in the A.C. system, the output of HVCl, el = m, the output of HVC2, e2 = Q and the output of LVC4, e3 = Q. Accordingly, the output of DVCl becomes 2el2 = 2Q~
and the output of DVC2 becomes 2e32 = -2-Q- = 2 On the other hand, in the case where the commutation voltages are as in FIG. 8(b), el = Q, e2 = Q and e3 -- m, so that the output of DVCl becomes 2el2 = 2Q = 2- and that the output of DVC2 e3 m becomes 2 2 = 2Q.
FG2 and FG3 designate function generators, which receive the outputs of the divider circuits DVCl and DVC2, respectively, and which provide the absolute values of voltages corresponding to the phase changes ~ in Eqs. (2) and (3), respectively.
The adder AD is a circuit which executes an operation in such form that the outputs of FG2 and FG3 are subtracted ``. 1~)7~g2~
from the output of FGl. Accordingly, the output of the adder AD becomes the voltage necessary for obtaining the advanced control angle as derived from the commutation voltages whose phases have changed due to the fault, the first-mentioned voltage having been corrected by the component of the phase changes. The reason why the outputs of FG2 and FG3 are added with negative sign is that the actual gate pulse phase shifter AP is usually adapted to control the retarded control angle ~ and that, in the present embodiment, the gate pulse phase shifter AP is constructed and operated so as to make the retarded control angle ~ greater as the input voltage Ec is greater. Needless to say, the relation between ~ and i S 0~ + ~ = 7T .
The outputs of FG2 and FG3 will now be further explained. As previously stated, in the case of FIG. 8(a), the voltage corresponding to 2Qm is obtained from DVCl, and the voltage corresponding to 2 is obtained from DVC2. In consequence, the function generator FG2 having received the former voltage provides the absolute value of the voltage corresponding to ~ = sin 1 2Q ~ 30 in conformity with Eq. (2), and function generator FG3 having received the latter voltage provides the output voltage of zero corres-ponding to ~ = 30 - sin 1 2 = 30 ~ 30 = 0 in conformity with Eq. (3). On the other hand, in the case of FIG. 8(b), the voltage corresponding to 1 is obtained from DVCl, and the voltage corresponding to 2Q is obtained from DVC2. In consequence, the function generator FG2 provides the zero voltage corresponding to ~ = 30 - sin 1 = 0 in conformity with Eq. (2), and the function generator FG3 provides the absolute value of the voltage corresponding to ~ = 30 - sin 2Q in conformity with Eq. (3).
It is FIG. 7 that illustrates these phase changes as calculated in correspondence with the various faults of the A.C. system, ~ 5 in FIG. 7 corresponding to ~ 5 illustrated in FIGS. 4 - 6.
Shown at LVC5 in FIG. 3 is a low value circuit, which allows the smaller one of the output of the adder AD
and the output of the function generator FGl' to pass through.
Irrespective of which of the cases of FIGS. 8(a) and 8(b) the fault can be ascribed to, accordingly, the voltage is obtained in such a way that the voltage corresponding to the advanced control angle derived from the commutation voltages having the phase changes is corrected by the voltage corresponding to the phase changes, and the voltage which corresponds to the advanced control angle derived from the least commutation voltage is selected and emitted from the low value circuit - LVC5.
In order to understand the operation of the circuit of PIG. 3 more concretely, the cases when a two-line grounding fault and a three-line grounding fault occur, are considered hereinafter, wherein the ~ ~ connection inverter transformer is used and the commutation reactance, the extinction angle and the D.C. current equal 0.2 p.u., 20 degrees and 1.0 p.u.
respectively, are considered. The commutation voltages under the two-line grounding fault are shown in FIG. 4b.
When p drops down to 0.6 p,u., the voltage Vab equals 0.6 p.u. and the voltages Vbc and Vca equal 0.808 p.u. According to Eq.(l), the outputs of the function generators FGl and FGl' are known to be the voltages corresponding to ~ = 133.8 degrees and ~ = 127.3 degrees respectiv~ly. According to Eq.(2) and
that the averaged phase variation i9 zero. This method of increasing the advanced control angle ~ according to the drop of the commutation voltage cannot cope with changes vf the phases of the commutation voltages. As a result, the arm in which the phase of ~he commutation voltage~leads falls to an insufficient extinction angle and can cause commutation failure.
To avoid this problem, we have proposed in U.S. Patent No. 4,028,607 issued June 7, 1977 to Hitachi Ltd., that the control voltage for the gate pulse be corrected by the use of the lowest one of the phase voltages or line to line voltages of the A.C. system.
Thls proposed system, however, is not always fully satisfactory, because the extinction angles obtained in case of faults in the A.C. system are sometimes larger than those suitable for the faults. This is attributed to the fact that the relation of amplitude and/or phase angle between the phase voltage and the commutation voltage varies according to the kind of the fault in the A.C. system or the connection of a transformer. Extinction angle~ larger than necessary place limits on the transmission power of the inverter.
Summary of the Invention It is accordingly an object of this invention to provide an inverter control system which is so contrived that, when a fault takes place in the A.C. system, the phase of a gate pulse can be instantly and suitably controlled in the direction of stabilizing the operation of an inverter.
Generally speaking, this invention accomplishes this object by providing means to output the gate pulses accurately at a fixed interval, and means to shift the phases of the gate pulses to be applied to the inverter, depending on the state of its operation, by introducing into the phase ~ .
~)78g2~
shifting means a signal corresponding to the condition of phase variation of the commutation voltages of the inverter.
More specifically, the invention consists of an in-verter control system for an inverter connected between one side of an inverter transformer and a D.C. system, the other side of said transformer being connected to an A.C. system, said system comprising (a) first means for deriving a signal corresponding to an advanced control angle of said inverter in accordance with voltages of said A.C. system applied to sald inverter and current in said D.C. system, (b) second means for deriving a phase correction signal in response to an unbalance of said A.C. voltages applied to said inverter, said phase correction signal corresponding to the magnitude of the unbalance of phase differences among respective phases of commutation voltages applied to said inverter, (c) third means to synthesize the outputs of said first and second means, and (d) fourth means for generating firing pulses whose phases are determined in accordance with the output of said third means.
Brief Descri~tion of the Drawings FIG. 1 is an overall connection diagram showing the arrangement of an inverter in D.C. power transmission;
FIG. 2 is a waveform diagram for explaining phase changes of commutation voltages;
FIG. 3 is a block diagram showing the essential portions of an embodiment of this invention;
FIGS. 4a-c, 5a-c and 6a and b are vector diagrams for explaining voltages in case of various faults in the A.C.
system (FIGS. 6 are with FIGS. 4 on a sheet);
FIG. 7 is a graph for explaining the phase variation of the commutation voltage for the inverter in case of faults in the A.C. system;
~ - 4 -B
~.0'78~21 FIG. 8a and b are vector diagrams for explaining the phase variation and the amplitude of the cu~mutation voltage for the inverter in case of faults in the A.C. system;
..
- 4a -1078~,~2~, FIGS. 9, 10, 11, 12, 13 and 13' are connection diagrams showing examples of specific circuits to be used in the embodiment of FIG. 3;
FIGS. 13", 14 and 15 are diagrams showing characteristics of circuits to be used in the embodiment of FIGS. 13 and 3;
FIGS. 16 and 17 are block diagrams for explaining examples of specific circuits of equidistant pulse phase control devices which can be employed in this invention; and FIG. 18 is a waveform diagram for explaining the ~ !
operation of the circuit in FIG. 17.
Detailed Description of the Preferred Embodiments As previously stated, this invention realizes control of the gate pulse interval, and prevents an inverter from failing in commutation, even when faults occur in the A.C. system. Hereunder, the invention will be explained in conjunction with an embodiment thereof. A description will first be given of what influences faults in the A.C. system have on the inverter.
An example of a D.C. power transmission system is shown in FIG. 1. Referring to the figure, T designates a transformer, Vl - V6 are the arms of an inverter constructed of thyristor or mercury valves, and LDC is a D.C. reactor.
The D.C. input side of the inverter is connected through D.C.
lines to other terminals. On the A.C. side the terminals of the transformer T are connected to an A.C. system, the respective phases of which have voltages Va, Vb and Vc.
These line to ground voltages are detected through potential transformers PTa, PTb and PTc and are delivered to a control circuit (not shown) including a gate pulse phase shifter.
DCCT denotes a D.C. current transformer, while IV indicates a current - voltage converter with an output terminal kid.
Normally, the three voltages Va, Vb and Vc are balanced, as shown by the solid-line waveforms in FIG. 2.
Consider the case where a one-line grounding fault occurs in the A.C. system and the voltage Va drops as shown at Va'.
Where the transformer connection is a star-star connection, as in FIG. 1, the commutation voltages are equal to the line to line voltages, and their zero points are the inter-section points of the phase voltages, e.g. the point to.
Accordingly, when the voltage Va drops to Va', the phase of the intersection point to' and hence that of the commutation voltage leads phase-b by ~ and lags phase-c by ~ as illustrated in FIG. 2. Namely, the intersection points of the phase voltages Va and Vb transfer from to to to'. Therefore, to avoid commutation failure in all the arms Vl, V2,.... V6, the advanced control angle has to be made larger by ~ than the normal one.
As is well known, the relation among the commutation voltage, the extinction angle y and the advanced control angle ~ is expressed by the following equation:
c O s r - c O s ~ = Ea (1) where r denotes the extinction angle, ~ the advanced control angle, Ea the commutation voltage, Id the D.C. current, and x the commutation reactance. The reference point for the phases of the angles r and ~ is the zero point of the commutation voltage.
According to the embodiments of the present invention, the advanced control angle ~ for obtaining the prescribed extinction angle depending on the magnitude of the commutation voltage and the magnitude of the D.C. current, 107892~.
is evaluated on the basis of Eq. (1), the change ~ of the phase of the commutation voltage being evaluated from the magnitude of unbalance of the A.C. voltages. A control voltage corresponding to ~AP = ~ + ~ is then applied to the gate pulse phase shifter, whereby stable operation is made possible at the minimum required extinction angle for any fault in the A.C. system.
FIG. 3 shows such an embodiment of the invention.
In this figure, the same symbols as in FIG. 1 indicate the same parts. APT represents an auxiliary potential transformer.
Recl - Rec3 represents rectifier circuits for converting A.C.
voltages to D.C. voltages. HVCl and HVC2 designate high value circuits which select the maximum input from among a plurality of inputs, while LVCl - LVC5 designate low value circuits which select the minimum input from among a plurality of inputs. DVCl and DVC2 denote divider circuits, FGl and FG'l denote gate pulse phase calculating circuits, FG2 and FG3 denote gate pulse phase correction calculating circuits, AD
denotes an adder, and AP denotes an automatic gate pulse phase shifter.
Before explaining the operation of the embodiment in FIG. 3, the magnitudes and phases of commutation voltages in cases where various faults occur in the A.C. system will be described with reference to FIGS. 4 to 8.
FIGS. 4(a) to 4(c) illustrate the situations of the commutation voltages in a case where the transformer of the inverter is star-star connected. In this case, the line to line voltage becomes the commutation voltage. FIG. 4(a) corresponds to a one-line grounding fault, FIG. 4(b) to a two-line grounding fault, and FIG. 4(c) to a three-line grounding fault. In the figures, the phase voltage at the ~07892~
fault is represented by p, and the phase change of the commutation voltage is represented by ~1.
FIGS. 5(a) to 5tc) illustrate the situations in a case where the transformer of the inverter is of star-delta connected. FIG. 5(a) corresponds to a one-line grounding fault, FIG. 5(b) to a two-line grounding fault, and FIG. 5(c) to a three-line grounding fault. In each of these figures, the left han~ diagram depicts the phase voltages on the A.C.
side of the ~ ansformer, while the right hand diagram depicts those v ~ es that become the commutation voltages on the D.C. side As in the case of FIG. 4, p denotes the magnitude of the ph se voltage at the fault as based on the normal value, and ~2 an ~3 denote the changes of the phases of the commutation voltages.
FIGS. 6(a) and 6(b) illustrate the drops of the phase voltages and the phase changes ~4 and ~5 of the commutation voltages in the case of a two-line short-circuit whether the transformer of the inverter is of the star-star connection or the star-delta connection. FIG. 6(b) illustrates the commutation voltages when the transformer connection is star-delta, when the primary sidç of the transformer becomes as shown in the vector diagram of FIG. 6(a). The situation for a three-line short-circuit is the same as for the three-line grounding fault.
In any of the examples of FIGS. 4 to 6, the vertices of the voltage vectors of the respective phases when the A.C.
system is normal are represented by A, B and C, and those at the occurrence of the fault by A', B' and C'. The commutation voltages for the inverter are the voltages between the vertices, i.e., the line to line voltages of the secondary windings.
When these changes of magnitudes of the commutation voltages and of their phases under fault conditions are collectively studied, the following can be said.
Firstly, study will be made of the commutation voltages in the cases of the star-star connection illustrated in FIG. 4. In the one-line grounding fault of FIG. 4(a), the commutation voltages VAB and VCA (voltages between the vertices A and B and between the vertices C and A) change to VA'B and VCA'. As the result, the phases also change by ~1. At this time, VA'B and VCA' have equal magnitudes.
In the two-line grounding fault of FIG. 4(b), all the commutation voltages change in magnitude, although VA'B' does not change in phase with respect to VAB. In contrast, VB'C and VCA' change in phase with respect to VBC and VCA, respectively, the magnitudes of the commutation voltages VB'C and VCA' being equal. In the three-line grounding fault of FIG. 4(c), all the commutation voltages change only in magnitude and undergo no phase change. It is thus apparent that the number of commutation voltages undergoing phase changes is two in any case in which any phase change occurs, and that the magnitudes of the commutation voltages that do change phase are equal in any of the faults.
Secondly, study will be made of the commutation voltages in the cases of the star-delta connection illustrated in FIG. 5. The commutation voltages to be applied to the inverter are shown in the vector diagrams on the right hand sides of FIGS. 5(a), 5(b) and 5(c). In the one-line grounding fault of FIG. 5(a), VB'C and VCA' differ in both magnitude and phase from VBC and VCA, respectively, but VA'B' differs only in magnitude from VAB and does not differ in phase.
In the two-line grounding fault of FIG. 5(b), VA'B' and VB'C
differ in both magnitude and phase from VAB and VBC, respectively, 107892~
but VCA' differs only in magnitude from VCA. In the three-line grounding fault of FIG. 5(c), all the commutation voltages change only in magnitude and do not change in phase. In FIGS. 5(a) and tb) a vector indicated by Vo designates a zero-phase-sequence voltage which develops on the primary side with the unbalanced faults. The potential of the neutral point of the transformer changes by this zero-phase-sequence voltage, and the neutral point moves from 0 to 0' on the vector diagram. It is apparent that, also in the case of the star-delta connection, the number of commutation voltages undergoing phase changes is two in any case in which any phase change occurs, and that these two voltages have equal magni-tudes.
Study will now be made of the two-line short-circuit illustrated in FIG. 6. FIG. 6(a) illustrates the example in which, in the case of the star-star connection, the short-circuit takes place between the lines of phase-a and the phase-b. The commutation voltage VAB changes to VA'B', the commutation voltage VBC to VB'C and the commutation voltage VCA to VCA'. VB'C and VCA' undergo changes in phase as well as in magnitude. FIG. 6(b) is the vector diagram of the commutation voltages when the fault of FIG. 6(a) occurs on the A.C. side in the case of a star-delta connection. In this case, VAB changes to VA'B', VBC changes to VB'C, and VCA
changes to VCA'. VCA' changes only in magnitude, and VA'B' and VB'C change in phase as well as in magnitude. Also in the cases of FIG. 6, the number of commutation voltages changing in phase is two, and the magnitudes of these voltages are equal. In balanced faults, no phase change arises in any case.
It is accordingly noted that, whichever connection of the transformer may be used, i.e. star-star or star-delta, and whatever the kind of the fault may be, in those faults in which the commutation voltages change not only in magni-tude but also in phase, there are always two commutation voltages undergoing phase changes and these two commutation voltages have equal magnitudes. It will therefore be under-stood that, when the advanced control angle is to be determined by using those commutation voltages whose phases change with a fault, it needs to be made larger by the --magnitude of the phase changes.
In recognition of this fact, the phase changes in the present circuits are derived from the relationship of the magnitudes of the three commutation voltages. The advanced control angle ~ obtained by the known equation (1) above is corrected by the use of the magnitude of the phase changes, and the optimum operation of the inverter is realized.
FIG. 7 is a diagram in which the abscissa represents the magnitude of the phase voltage p with the rated value being 1 (one), while the ordinate represents the change of phase in degrees. Here, ~ 5 indicate the phase changes in the various cases illustrated in FIGS. 4 to 6.
FIGS. 8(a) and 8(b) are diagrams in which the relations of the phases and magnitudes of the commutation voltages are summarized as to the cases of FIGS. 4 - 6. As previously stated, the two commutation voltages whose phases have changed are equal. The circumstances of the commutation voltages can be summarized as shown in FIG . 8(a), wherein the triangle formed of the vectors of the commutation voltages becomes a'bc in such a form that the vertex a of the triangle abc shifts to a'; or as shown in FIG. 8(b), wherein the 1078921;
triangle formed of the vectors of the commutation voltages becomes ab'c' in such a form that the base bc of the triangle abc shortens. Let Q denote the length of the equal sides of the triangle, and m denote the length of the remaining side.
Then the angle ~ is represented by the following equations.
The triangle abc is an equilateral triangle. Therefore, in the case of FIG. 8(a), 30 + ~ = ~
(2) = sin~l Q
-1 m .. ~ = sin 1 2Q ~ 30 and in case of FIG. 8(b), + ~ = 30 ~ + sin 1 2Q = 300 ~ ~ = 30 - sin~l Accordingly, correction signals for the advanced control angle can be obtained by providing circuits for calculating (2) and (3).
Referring again to FIG. 3, the phase voltages Va, Vb and Vc of the A.C. system as derived from the potential transformers PTa, PTb and PTc are applied to the three auxiliary potential transformers APT in delta connection.
On the secondary sides of the three transformers APT, accordingly, the line to line voltages of the A.C. system or the commutation voltages of the inverter are obtained.
107892~
These commutation voltages are applied to the rectifiers Recl, Rec2 and Rec3, and are converted into D.C. voltages.
The high value circuit HVCl receives the outputs of all the rectifiers as inputs, and delivers the greatest one of the inputs as an output. Thus, the greatest voltage in the form summarized in FIG. 8 can be obtained. The low value circuits LVCl, LVC2 and LVC3 each receives two different ones of the outputs of the rectifiers Recl, Rec2 and Rec3 as inputs, and selects and delivers a smaller one of its two inputs as an output. The outputs of the three low value circuits are applied to the high value circuit HVC2. As apparent by referring to FIG. 8, accordingly, the magnitude (Q in FIG. 8) of the two commutation voltages whose phases change due to the fault and whose magnitudes are equal are obtained from the circuit HVC2. The low value circuit LVC4 receives all the outputs of the three rectifiers as inputs, and delivers the smallest one of these inputs as an output.
Thus, the smallest voltage of the form summarized in FIG. 8 can be obtained. Both circuits FGl and FGl' are function generators, which serve to derive voltages necessary for obtaining the foregoing advanced control angle ~ given by the relation of Eq. (1). Accordingly, these circuits receive as inputs a voltage corresponding to the commutation voltage of the inverter and a voltage corresponding to the D.C.
current, and they deliver as an output a voltage corresponding to the advanced control angle ~. As the voltage corresponding to the commutation voltage, the output of the high value circuit HVC2 is introduced into the function generator FGl, and the output of the low value circuit LVC4 into the function generator FGl'. As the voltage corresponding to the D.C.
current, the output of the current - voltage converter 107892~
circuit IV is introduced into both the function generators.
In this way, the function generator FGl provides the voltage for obtaining the advanced control angle necessary for the commutation angles whose phases have changed, as shown in FIG. 8, and the function generator FGl' provides the voltage for obtaining the advanced control angle necessary for the least one of the commutation voltages shown in FIG. 8.
The divider circuits DVCl and DVC2 receive the outputs of the circuits HVCl and HVC2 and the outputs of the circuits HVC2 and LVC4 as inputs, respectively. Letting el, e2 and e3 denote the outputs of the respective circuits HVCl, HVC2 and LVC4, the divider circuit DVCl provides an output of 2el2 and the divider circuit DVC2 provides an output of 2e32. The inputs and outputs of the divider circuits will now be studied in correspondence with FIG. 8.
In the case where the commutation voltages are as in FIG. 8(a) due to the fault in the A.C. system, the output of HVCl, el = m, the output of HVC2, e2 = Q and the output of LVC4, e3 = Q. Accordingly, the output of DVCl becomes 2el2 = 2Q~
and the output of DVC2 becomes 2e32 = -2-Q- = 2 On the other hand, in the case where the commutation voltages are as in FIG. 8(b), el = Q, e2 = Q and e3 -- m, so that the output of DVCl becomes 2el2 = 2Q = 2- and that the output of DVC2 e3 m becomes 2 2 = 2Q.
FG2 and FG3 designate function generators, which receive the outputs of the divider circuits DVCl and DVC2, respectively, and which provide the absolute values of voltages corresponding to the phase changes ~ in Eqs. (2) and (3), respectively.
The adder AD is a circuit which executes an operation in such form that the outputs of FG2 and FG3 are subtracted ``. 1~)7~g2~
from the output of FGl. Accordingly, the output of the adder AD becomes the voltage necessary for obtaining the advanced control angle as derived from the commutation voltages whose phases have changed due to the fault, the first-mentioned voltage having been corrected by the component of the phase changes. The reason why the outputs of FG2 and FG3 are added with negative sign is that the actual gate pulse phase shifter AP is usually adapted to control the retarded control angle ~ and that, in the present embodiment, the gate pulse phase shifter AP is constructed and operated so as to make the retarded control angle ~ greater as the input voltage Ec is greater. Needless to say, the relation between ~ and i S 0~ + ~ = 7T .
The outputs of FG2 and FG3 will now be further explained. As previously stated, in the case of FIG. 8(a), the voltage corresponding to 2Qm is obtained from DVCl, and the voltage corresponding to 2 is obtained from DVC2. In consequence, the function generator FG2 having received the former voltage provides the absolute value of the voltage corresponding to ~ = sin 1 2Q ~ 30 in conformity with Eq. (2), and function generator FG3 having received the latter voltage provides the output voltage of zero corres-ponding to ~ = 30 - sin 1 2 = 30 ~ 30 = 0 in conformity with Eq. (3). On the other hand, in the case of FIG. 8(b), the voltage corresponding to 1 is obtained from DVCl, and the voltage corresponding to 2Q is obtained from DVC2. In consequence, the function generator FG2 provides the zero voltage corresponding to ~ = 30 - sin 1 = 0 in conformity with Eq. (2), and the function generator FG3 provides the absolute value of the voltage corresponding to ~ = 30 - sin 2Q in conformity with Eq. (3).
It is FIG. 7 that illustrates these phase changes as calculated in correspondence with the various faults of the A.C. system, ~ 5 in FIG. 7 corresponding to ~ 5 illustrated in FIGS. 4 - 6.
Shown at LVC5 in FIG. 3 is a low value circuit, which allows the smaller one of the output of the adder AD
and the output of the function generator FGl' to pass through.
Irrespective of which of the cases of FIGS. 8(a) and 8(b) the fault can be ascribed to, accordingly, the voltage is obtained in such a way that the voltage corresponding to the advanced control angle derived from the commutation voltages having the phase changes is corrected by the voltage corresponding to the phase changes, and the voltage which corresponds to the advanced control angle derived from the least commutation voltage is selected and emitted from the low value circuit - LVC5.
In order to understand the operation of the circuit of PIG. 3 more concretely, the cases when a two-line grounding fault and a three-line grounding fault occur, are considered hereinafter, wherein the ~ ~ connection inverter transformer is used and the commutation reactance, the extinction angle and the D.C. current equal 0.2 p.u., 20 degrees and 1.0 p.u.
respectively, are considered. The commutation voltages under the two-line grounding fault are shown in FIG. 4b.
When p drops down to 0.6 p,u., the voltage Vab equals 0.6 p.u. and the voltages Vbc and Vca equal 0.808 p.u. According to Eq.(l), the outputs of the function generators FGl and FGl' are known to be the voltages corresponding to ~ = 133.8 degrees and ~ = 127.3 degrees respectiv~ly. According to Eq.(2) and
(3), the outputs of the function generators FG2 and FG3 are known to be the voltages corresponding to 0 degree and 8.2 ~ - 16 -.. ,~
10789Zl degrees. The output of the adder AD becomes the voltage correspon-ding to 125.6 degrees, which equal the difference between the outputs of the function generators FGl and FG3. The low value circuit LVC5, therefore, selects the output of the adder AD and the retarded control angle ~ is determined at 125.6 degrees.
When a three-line grounding .ault occurs and p drops to 0.6 p.u-., the following outputs of the function generators FGl, FGlt, FG2 and FG3 and the adder AD are obtained in the same manner.
FGl: voltage corresponding to 127.3 degrees.
FGl': voltage corresponding to 127.3 degrees.
FG2: voltage corresponding to 0 degrees.
FG3: voltage corresponding to 0 degrees.
~ D: voltage corresponding to 127.3 degrees.
In this case, the outputs of the function generator FGl' and the adder AD are equal to each other. The low value circuit LVC5, therefore, selects one of them and the retarded control angle is determined at 127.3 degrees.
As mentioned above, the suitable retarded control angle is selected automatically according to the fault conditions.
The automatic gate pulse phase shifter AP provides a gate pulse as an output at a timing which corresponds to the retarded control angle ~ corresponding to the input voltage Ec.
In short, this arrangement obtains the optimum advanced control angle, in consideration of the phase changes resulting from faults by which the commutation voltages become unbalanced, thus realizing stable operation.
FIGS. 9 to 12 show examples of various circuits for FIG. 3. In these figures, R designates a resistance OP an operational amplifier, D a diode, T a terminal,and VR a variable resistance, with appropriate numerical suffixes to ~ - 16a -~4 107~
discrlmlnaLe betwccn thc components. Needless to say, theresistance values will be calculated by well-known methods.
~ES or -ES signifies that a voltage of the given polarity and at a certain magnitude will be applied to the terminal concerned.
- 16b -107892~.
FIG. 9 shows an example of a circuit which can be used for the low value circuits LVCl - LVC5. The smallest one of input voltages applied to terminals Tl - T3 is obtained at terminal T4. FIG. lO shows an example of a circuit which can be used for the high value circuits HVCl -HVC2. The greatest one of voltages applied to terminals Tl - T3 is obtained at terminal TS. FIG. ll shows an example of a circuit which can be used for the adder circuit AD. With this circuit, a voltage which corresponds to the difference between the sum of the voltages applied to terminals Tl and T2 and the voltage applied to the terminal T3 is obtained at terminal T4. FIG. 12 shows an example of a circuit which can be used for the function generators FG2 - FG3. With this circuit, when a positive voltage is applied to terminal T2, a voltage proportional to the difference between the positive voltage and a negative voltage given by variable resistance VR is obtained at terminal T3. When the output of the divider circuit DVCl - DVC2, i.e., the voltage Q is applied to the terminal T2 and a voltage corresponding to 30 is given by the variable resistance VR, the absolute value of the fore-going ~ is obtained at the terminal T3. In the illustrated example, sin Qm is approximated by a straight line. In general, however, the operating range of the inverter is p > 0.2 - 0.3 for the one-line grounding fault, p _ 0.5 - 0.6 for the two-line grounding fault and p _ 0.6 for the two-line short-circuit. Therefore, even when sin 2Q is approximated by a straight line, the error is at most 0.5, and this linear approximation can therefore be satisfactorily put into practical use. The phase change in the range of p is at most about 30, as seen from FIG. 7. FIG. 13 shows an example of a circuit which can be used for the function generators 1078g2~
FGl - FGl'. When a positive voltage ei is applied to the terminal Tl, a positive voltage e ls obtained at the terminal T7, FIG. 14 showing the characteristic curve by a solid line.
In this example, the circuit selects a smaller one of two voltages indicated by the straight line s - t and the straight line u - v for the input ei. Further, by adding circults corresponding to OP2 and OP3, a circuit which selects the smallest one of three voltages, including also a voltage indicated by the stralght line x - y, can be slmply constructed.
As known by Eq.Cl~, the advanced control angle ~ is determined by two variables, namely the commutation voltage Ea and the D.C. current Id. The function generators FGl and FGl', therefore, are concretely modified as the circuit shown in ~-FIG. 13', which is made by addlng a terminal T8 and resistances R13 and R14 to the circuit shown in FIG. 13. The terminals Tl and T8 are added with the commutation voltage Ea and the D.C.
current Id respectively.
As is well known, for example, from the textboo~.
"High Voltage Dlrect Current Power Transmisslon" by C. Adamson and N.G. Hlngoranl (Garroway Ltd., London 1960) from page 24 to 37, especially FIGs. 3.6 and 3.7, a relation between the retarded control angle ~, whlch equals ~ - ~, and the commutation voltage Ea is shown by curves A and B shown in FIG. 13", in which the D.C. curre~t Id is taken as a parameter. The cur-ves-A and B also represent the relation among advanced control angle~ , commutation voltage Ea and the D.C.
current Id under Eq.(l). The curves A and B are analogized by a combination of straight lines a-b, b-c and a'-b', b'-c' respectively. The circuit shown in FIG. 13', therefore, is used as function generators FGl and FGl'. Gradients of the line a-b or a'-b' and of the line b-c or b'-c' are determined by the ~ ~ .
107892~ -ratios of the resistances R6/R5 and R10/R9 respectively. The difference between points a' and a,b' and b or c' and c i9 determined by the ratio of the resistance R6/R13 which equals the ratio of the resistance R10/R14.
FIG. 15 shows an example of the characteristic curve of the automatic gate pulse phase shifter whose circuit arrange-ment will be exemplified below. The circuits shown in FIGS. 9 to 13 are known and need not be explained further. Moreover, for the divider circuits in FIG. 3, commercially available circuits, for example circuits known by the trade names MODEL 4452 - 4455 made by TELEDYNE* PHILBRICK Inc., can be used.
Referring now to FIG. 16, an example of the automatic gate pulse phase shifter will be described.
FIG. 16 is a block diagram which shows the example of the automatic pulse phase shifter AP. In this figure, PTa; PTb and PTc designate the potential transformers shown in FIG. 1, Ec designates a terminal for introducing the output of the low value circuit LVC5 shown in FIG. 3, and Pl; P2 ... and P6 designate the gate pulses to be applied to the respective arms consisting of the thyristor valves Vl;
V2 ....V6.
In the example of FIG. 16, the synchronizing power sources (the llne to line voltages of the A.C. system in the illustrated example) are subjected to waveform conversion into square waves in a wave shaping portion 1. The square * Trade Mark - 18a -A
waves are not directly impressed on a gate pulse phase portion 2. A synchronous oscillator which is synchronized with the synchronizing power sources and which has a frequency six times higher, is employed. The output of the oscillator is applied by a ring counter into six parts, which are used as synchronous inputs of the automatic gate pulse phase shifting portion 2. According to this example, the change of the output gate pulse phase responsive to the change of the control voltage is very fast as in the general gate pulse phase shifter circuits. Moreover, the gate pulse interval is constant, because it is determined by the single oscillator.
The synchronization ~ay be put into a phase relation fixed with the voltages of the A.C. system, and requires only to follow a gentle fluctuation of the frequency of the voltages of the A.C. system. It is therefore not feared that the system will pull out of synchronism.
Outputs corresponding to the positive and negative half waves of the respective line to line voltages of the A.C. system are obtained by the potential transformers PTl -PT3 and waveform converter circuits Fl - F6. The outputs from the circuits Fl, F2 ... and F6 are respectively applied to corresponding differentiation circuits Dl, D2 ... and D6.
From the differentiation circuits Dl, D2 ... and D6, only positive pulses are derived. They are impressed on set terminals S of flip-flop circuits FFl, FF2 ....and FF6 at the next stage, and serve to set these flip-flop circuits. These flip-flop circuits are reset in such a way that outputs from flip-flop circuits RCl, RC2 ... and RC6 constituting the ring counter RC are impressed on the reset terminals R
thereof. The width of the outputs of the six flip-flop circuits FFl - FF6 or the magnitude of a voltage corresponding 1(~7892~.
thereto indicates the phase difCerence between the phase of the synchronizing power sources and that of tlle ring counter outputs. An adder AD' produces a voltage corresponding to the period during which the outputs of the six flip-flop circuits FFl - FF6 continue. A differential amplifier DF
evaluates the voltage difference between the output of the adder AD' and a phase setpoint given at a terminal PH. The output of the differential amplifier DF is smoothed by a filter FL, amplified by a D.C. amplifier A', and applied to a voltage-controlled oscillator VCO. The oscillator VCO
oscillates at a frequency which is proportional to the input voltage. The output of the oscillator VCO is applied to the ring counter RC. The flip-flop circuits RCl - RC6 constitut-ing the ring counter RC have the output of the oscillator VCO
impressed on their reset terminals R and have output change signals of the different ones of the flip-flop circuits RCl -RC6 impressed on their set terminals S. Only one of the flip-flop circuits RCl - RC6 is normally set at "1". Each time a pulse is applied from the oscillator VCO, the position of the state "1" shifts in the order of the suffixes of the flip-flop circuits RCl - RC6.
Flip-flop circuits FOl - F06 have set terminals S
and reset terminals R. The flip-flop circuit FOl is set by the output of the flip-flop circuit RCl, while it is reset by the output of the flip-flop circuit RC4. The flip-flop circuit F02 is set by the output of the flip-flop circuit RC2, while it is reset by the output of the flip-flop circuit RCS. The others are similarly operated.
The outputs of the flip-flop circuits FOl - F06 are respectively applied to integrators Il - I6.
The operation of the circuit in FIG. 16 will now 107~92~
be explained.
The mean value of the output of the adder AD' is proportional to the difference in phase between the synchroniz-ing power sources and the outputs of the ring counter RC.
The terminal PH is set according to this phase difference.
When the ring counter outputs lag behind the synchronizing power sources by an amount exceeding this setting, the output of the adder AD' becomes greater than the voltage of the terminal PH. The output of the D.C. amplifier A' increases, the frequency of the voltage-controlled oscillator VC0 rises, and the phase difference decreases. When the phase of the ring counter outputs lead the setting, the frequency of the oscillator VC0 lowers and the phase is retarded. Accordingly, the phase of the outputs of the ring counter RC becomes a value equal to the setting given to the terminal PH and is fixed. If the frequency of the synchronizing power sources varies, the ring counter outputs will gradually deviate with respect to the synchronizing power sources, if the frequency of the oscillator VCO is fixed. Consequently, the frequency of the oscillator VC0 varies for the reason as stated above, and the same phase relation as that before the frequency variation is established.
Assuming now that the phases are set at 60 degrees, the output of the flip-flop RC2 is at a position to lag 60 degrees behind the output of the waveform converter circuit Fl in FIG. 16. Accordingly, the output of the flip-flop RCl leads by 60 degrees that of the flip-flop RC2 and is in phase with the output of the waveform conve}ter circuit Fl.
Since the flip-flop F01 is set by the flip-flop RCl and is reset by the flip-flop RC4, it has an output width of 180 degrees, as the waveform converter circuit Fl, and is in 1078g21 pha4e with the circuit Fl. Likewise, where the synchronizing power sources are balanced, the outputs of the flip-flops F02 - FO6 have the same phases and waveforms as those of the waveform converter circuits F2 - F6. Where the synchronizing power sources become unbalanced, the widths of the outputs of the flip-flops FFl - FF6 become respectively different.
However, they are smoothed by the filter FL, and the oscillator VC0 continues the constant oscillation. Therefore, the outputs of the flip-flops RCl - RC6 and accordingly those of the flip-flops F01 - F06 are provided accurately at the interval of 60 degrees and continue by 180 degrees. The characteristic as in FIG. 15 is therefore fulfilled by introducing the outputs of the flip-flops F01 - F06 into the integration circuits Il - I6, comparing the outputs of the integration circuits Il - I6 with the control voltage Ec by respective comparators Cl - C6 and producing the pulse outputs in places where they coincide.
When the control voltage Ec is corrected according to the least one of the phase voltages and the line voltages as in FIG. 14, the gate pulse interval-fixing control is satisfied and stable running of the inverter is possible.
FIG. 17 is a block diagram showing a further example of gate pulse phase shifter which can be used for this invention. FIG. 18 is a waveform diagram for explaining the operation of the circuit in FIG. 17. This circuit has been published in IEEE Summer Power Meeting Paper N0 TP 640-PWR, and is mentioned herein as an example of an automatic gate pulse phase shifter which can be employed.
The operation of the pulse generator PG in FIG. 17 will now be described. In the figure, VCC represents a voltage-controlled current source which provides a current 92~
of magnitude proportional to an input voltage Vc2. CON
denotes a capacitor, and VCOM a comparator. The comparator operates and generates a pulse Vp when the terminal voltage Vc of the capacitor CON becomes larger by ~V/2 than a phase control signal Vcl. The pulse Vp drives a capacitor dis-charging circuit CD, to keep the capacitor CON discharged until the terminal voltage Vc becomes smaller by ~V/2 than the phase control signal Vcl. The appearance of this operation can be readily appreciated from the waveform diagram in FIG. 18. The velocity ~ at which the terminal voltage Vc rises is proportional to the output current of the current source VCC and accordingly to the input voltage Vc2. While-the phase control signal Vcl is constant, the pulses Vp are generated at intervals of 60 degrees. When the voltage Vcl increases as shown at ~Vcl.l in the figure, the phase of the pulse Vp changes by ~1 in the lagging direction. In contrast, when the voltage Vcl decreases, as shown at ~Vc1.2, the phase of the pulse Vp instantly leads by ~2. The magnitudes of ~1 and ~2 are proportional to Vcl.l and Vc1.2, respectively.
Shown at SR is a shift register. This is a circuit that .-:
distributes the pulses Vp as gate pulses to the respective arms of the inverter constituted by the thyristor valves Vl - V6. The outputs Pl - P6 of the circuit SR are the gate pulses of the respective arms of the inverter. The other part of the circuit arrangement in FIG. 17 is a circuit for establishing synchronization with the voltages of the A.C.
system. AM indicates a circuit for measuring the actual retarded control angle ~ of the inverter. FLl and FL2 designate filters. The output ~ref of the filter FLl is equal to the phase control signal Vcl. Accordingly, this value is made a reference value, and an ~ control circu t AC operates to 1~)78g2~
control the gradient ~ of the terminal volrage Vc in order that the output ~act of the filter FL2 may become equal to the output ~ref of the filter FLl. The pulse generator PG
thus operates in synchronism with the A.C. system to which the inverter is connected. Vc21 denotes a voltage proportional to the frequency of the A.C. system. It controls the gradient of the voltage Vc through an adder ADF according to a change of the frequency, so as always to maintain the retarded control angle ~ equal to an electrical angle determined by the phase control signal Vcl. Since the time constant of the filter FL2 is set at a large value, the pulse phase shifter in FIG. 17 has the same function as the circuit in FIG. 16. Of course, the control voltage Ec in FIG. 3 is introduced as the control voltage indicated by Vcl in FIG. 17.
As described above, in accordance with this con-struction, stable running can be ensured when employing the automatic pulse phase shifter of the gate pulse interval-fixing control system, and even when the voltage of the A.C.
system drops due to any fault arising in the A.C. system.
While the connection of the transformer for the inverter has been explained above as being a star - star connection, this invention is applicable without any substantial change to a case where the transformer uses the star - delta connection.
When the transformer for the inverter uses the star - delta connection, the voltage transformers PTa, PTb and PTc in FIG. 3 and FIG. 16 may be changed to the star - delta connection to form voltages corresponding to the commutation voltages, and the voltage transformers APT and PTl, PT2 and PT3 may be changed to the delta - star connection to apply the commutation voltages to the waveform converter circuits Fl - F6.
Since the voltage transformers PTa, PTb and PTc are not always used exclusively for the gate pulse phase shifter, they cannot always be brought to the star - delta connection.
In such cases, a method to be stated below can be relied on.
This invention relates to a system in which the voltage phase of the A.C. system under normal conditions is referred to as the phase of the synchronizing power sources. Therefore, it is not necessary to employ the commutation voltages as the synchronizing power sources of the automatic gate pulse phase shifter. Where the transformer uses the star - delta connection, the phase voltages Va, Vb and Vc on the A.C. side of the transformer for the inverter which are in phase with the commutation voltages in the normal operation of the A.C. system may be used as the synchronizing power sources without change.
In this case, both the voltage transformers PTa, PTb and PTc and the voltage transformers APT and PTl, PT2 and PT3 in FIG. 3 and FIG. 17 can use the star - star connection.
10789Zl degrees. The output of the adder AD becomes the voltage correspon-ding to 125.6 degrees, which equal the difference between the outputs of the function generators FGl and FG3. The low value circuit LVC5, therefore, selects the output of the adder AD and the retarded control angle ~ is determined at 125.6 degrees.
When a three-line grounding .ault occurs and p drops to 0.6 p.u-., the following outputs of the function generators FGl, FGlt, FG2 and FG3 and the adder AD are obtained in the same manner.
FGl: voltage corresponding to 127.3 degrees.
FGl': voltage corresponding to 127.3 degrees.
FG2: voltage corresponding to 0 degrees.
FG3: voltage corresponding to 0 degrees.
~ D: voltage corresponding to 127.3 degrees.
In this case, the outputs of the function generator FGl' and the adder AD are equal to each other. The low value circuit LVC5, therefore, selects one of them and the retarded control angle is determined at 127.3 degrees.
As mentioned above, the suitable retarded control angle is selected automatically according to the fault conditions.
The automatic gate pulse phase shifter AP provides a gate pulse as an output at a timing which corresponds to the retarded control angle ~ corresponding to the input voltage Ec.
In short, this arrangement obtains the optimum advanced control angle, in consideration of the phase changes resulting from faults by which the commutation voltages become unbalanced, thus realizing stable operation.
FIGS. 9 to 12 show examples of various circuits for FIG. 3. In these figures, R designates a resistance OP an operational amplifier, D a diode, T a terminal,and VR a variable resistance, with appropriate numerical suffixes to ~ - 16a -~4 107~
discrlmlnaLe betwccn thc components. Needless to say, theresistance values will be calculated by well-known methods.
~ES or -ES signifies that a voltage of the given polarity and at a certain magnitude will be applied to the terminal concerned.
- 16b -107892~.
FIG. 9 shows an example of a circuit which can be used for the low value circuits LVCl - LVC5. The smallest one of input voltages applied to terminals Tl - T3 is obtained at terminal T4. FIG. lO shows an example of a circuit which can be used for the high value circuits HVCl -HVC2. The greatest one of voltages applied to terminals Tl - T3 is obtained at terminal TS. FIG. ll shows an example of a circuit which can be used for the adder circuit AD. With this circuit, a voltage which corresponds to the difference between the sum of the voltages applied to terminals Tl and T2 and the voltage applied to the terminal T3 is obtained at terminal T4. FIG. 12 shows an example of a circuit which can be used for the function generators FG2 - FG3. With this circuit, when a positive voltage is applied to terminal T2, a voltage proportional to the difference between the positive voltage and a negative voltage given by variable resistance VR is obtained at terminal T3. When the output of the divider circuit DVCl - DVC2, i.e., the voltage Q is applied to the terminal T2 and a voltage corresponding to 30 is given by the variable resistance VR, the absolute value of the fore-going ~ is obtained at the terminal T3. In the illustrated example, sin Qm is approximated by a straight line. In general, however, the operating range of the inverter is p > 0.2 - 0.3 for the one-line grounding fault, p _ 0.5 - 0.6 for the two-line grounding fault and p _ 0.6 for the two-line short-circuit. Therefore, even when sin 2Q is approximated by a straight line, the error is at most 0.5, and this linear approximation can therefore be satisfactorily put into practical use. The phase change in the range of p is at most about 30, as seen from FIG. 7. FIG. 13 shows an example of a circuit which can be used for the function generators 1078g2~
FGl - FGl'. When a positive voltage ei is applied to the terminal Tl, a positive voltage e ls obtained at the terminal T7, FIG. 14 showing the characteristic curve by a solid line.
In this example, the circuit selects a smaller one of two voltages indicated by the straight line s - t and the straight line u - v for the input ei. Further, by adding circults corresponding to OP2 and OP3, a circuit which selects the smallest one of three voltages, including also a voltage indicated by the stralght line x - y, can be slmply constructed.
As known by Eq.Cl~, the advanced control angle ~ is determined by two variables, namely the commutation voltage Ea and the D.C. current Id. The function generators FGl and FGl', therefore, are concretely modified as the circuit shown in ~-FIG. 13', which is made by addlng a terminal T8 and resistances R13 and R14 to the circuit shown in FIG. 13. The terminals Tl and T8 are added with the commutation voltage Ea and the D.C.
current Id respectively.
As is well known, for example, from the textboo~.
"High Voltage Dlrect Current Power Transmisslon" by C. Adamson and N.G. Hlngoranl (Garroway Ltd., London 1960) from page 24 to 37, especially FIGs. 3.6 and 3.7, a relation between the retarded control angle ~, whlch equals ~ - ~, and the commutation voltage Ea is shown by curves A and B shown in FIG. 13", in which the D.C. curre~t Id is taken as a parameter. The cur-ves-A and B also represent the relation among advanced control angle~ , commutation voltage Ea and the D.C.
current Id under Eq.(l). The curves A and B are analogized by a combination of straight lines a-b, b-c and a'-b', b'-c' respectively. The circuit shown in FIG. 13', therefore, is used as function generators FGl and FGl'. Gradients of the line a-b or a'-b' and of the line b-c or b'-c' are determined by the ~ ~ .
107892~ -ratios of the resistances R6/R5 and R10/R9 respectively. The difference between points a' and a,b' and b or c' and c i9 determined by the ratio of the resistance R6/R13 which equals the ratio of the resistance R10/R14.
FIG. 15 shows an example of the characteristic curve of the automatic gate pulse phase shifter whose circuit arrange-ment will be exemplified below. The circuits shown in FIGS. 9 to 13 are known and need not be explained further. Moreover, for the divider circuits in FIG. 3, commercially available circuits, for example circuits known by the trade names MODEL 4452 - 4455 made by TELEDYNE* PHILBRICK Inc., can be used.
Referring now to FIG. 16, an example of the automatic gate pulse phase shifter will be described.
FIG. 16 is a block diagram which shows the example of the automatic pulse phase shifter AP. In this figure, PTa; PTb and PTc designate the potential transformers shown in FIG. 1, Ec designates a terminal for introducing the output of the low value circuit LVC5 shown in FIG. 3, and Pl; P2 ... and P6 designate the gate pulses to be applied to the respective arms consisting of the thyristor valves Vl;
V2 ....V6.
In the example of FIG. 16, the synchronizing power sources (the llne to line voltages of the A.C. system in the illustrated example) are subjected to waveform conversion into square waves in a wave shaping portion 1. The square * Trade Mark - 18a -A
waves are not directly impressed on a gate pulse phase portion 2. A synchronous oscillator which is synchronized with the synchronizing power sources and which has a frequency six times higher, is employed. The output of the oscillator is applied by a ring counter into six parts, which are used as synchronous inputs of the automatic gate pulse phase shifting portion 2. According to this example, the change of the output gate pulse phase responsive to the change of the control voltage is very fast as in the general gate pulse phase shifter circuits. Moreover, the gate pulse interval is constant, because it is determined by the single oscillator.
The synchronization ~ay be put into a phase relation fixed with the voltages of the A.C. system, and requires only to follow a gentle fluctuation of the frequency of the voltages of the A.C. system. It is therefore not feared that the system will pull out of synchronism.
Outputs corresponding to the positive and negative half waves of the respective line to line voltages of the A.C. system are obtained by the potential transformers PTl -PT3 and waveform converter circuits Fl - F6. The outputs from the circuits Fl, F2 ... and F6 are respectively applied to corresponding differentiation circuits Dl, D2 ... and D6.
From the differentiation circuits Dl, D2 ... and D6, only positive pulses are derived. They are impressed on set terminals S of flip-flop circuits FFl, FF2 ....and FF6 at the next stage, and serve to set these flip-flop circuits. These flip-flop circuits are reset in such a way that outputs from flip-flop circuits RCl, RC2 ... and RC6 constituting the ring counter RC are impressed on the reset terminals R
thereof. The width of the outputs of the six flip-flop circuits FFl - FF6 or the magnitude of a voltage corresponding 1(~7892~.
thereto indicates the phase difCerence between the phase of the synchronizing power sources and that of tlle ring counter outputs. An adder AD' produces a voltage corresponding to the period during which the outputs of the six flip-flop circuits FFl - FF6 continue. A differential amplifier DF
evaluates the voltage difference between the output of the adder AD' and a phase setpoint given at a terminal PH. The output of the differential amplifier DF is smoothed by a filter FL, amplified by a D.C. amplifier A', and applied to a voltage-controlled oscillator VCO. The oscillator VCO
oscillates at a frequency which is proportional to the input voltage. The output of the oscillator VCO is applied to the ring counter RC. The flip-flop circuits RCl - RC6 constitut-ing the ring counter RC have the output of the oscillator VCO
impressed on their reset terminals R and have output change signals of the different ones of the flip-flop circuits RCl -RC6 impressed on their set terminals S. Only one of the flip-flop circuits RCl - RC6 is normally set at "1". Each time a pulse is applied from the oscillator VCO, the position of the state "1" shifts in the order of the suffixes of the flip-flop circuits RCl - RC6.
Flip-flop circuits FOl - F06 have set terminals S
and reset terminals R. The flip-flop circuit FOl is set by the output of the flip-flop circuit RCl, while it is reset by the output of the flip-flop circuit RC4. The flip-flop circuit F02 is set by the output of the flip-flop circuit RC2, while it is reset by the output of the flip-flop circuit RCS. The others are similarly operated.
The outputs of the flip-flop circuits FOl - F06 are respectively applied to integrators Il - I6.
The operation of the circuit in FIG. 16 will now 107~92~
be explained.
The mean value of the output of the adder AD' is proportional to the difference in phase between the synchroniz-ing power sources and the outputs of the ring counter RC.
The terminal PH is set according to this phase difference.
When the ring counter outputs lag behind the synchronizing power sources by an amount exceeding this setting, the output of the adder AD' becomes greater than the voltage of the terminal PH. The output of the D.C. amplifier A' increases, the frequency of the voltage-controlled oscillator VC0 rises, and the phase difference decreases. When the phase of the ring counter outputs lead the setting, the frequency of the oscillator VC0 lowers and the phase is retarded. Accordingly, the phase of the outputs of the ring counter RC becomes a value equal to the setting given to the terminal PH and is fixed. If the frequency of the synchronizing power sources varies, the ring counter outputs will gradually deviate with respect to the synchronizing power sources, if the frequency of the oscillator VCO is fixed. Consequently, the frequency of the oscillator VC0 varies for the reason as stated above, and the same phase relation as that before the frequency variation is established.
Assuming now that the phases are set at 60 degrees, the output of the flip-flop RC2 is at a position to lag 60 degrees behind the output of the waveform converter circuit Fl in FIG. 16. Accordingly, the output of the flip-flop RCl leads by 60 degrees that of the flip-flop RC2 and is in phase with the output of the waveform conve}ter circuit Fl.
Since the flip-flop F01 is set by the flip-flop RCl and is reset by the flip-flop RC4, it has an output width of 180 degrees, as the waveform converter circuit Fl, and is in 1078g21 pha4e with the circuit Fl. Likewise, where the synchronizing power sources are balanced, the outputs of the flip-flops F02 - FO6 have the same phases and waveforms as those of the waveform converter circuits F2 - F6. Where the synchronizing power sources become unbalanced, the widths of the outputs of the flip-flops FFl - FF6 become respectively different.
However, they are smoothed by the filter FL, and the oscillator VC0 continues the constant oscillation. Therefore, the outputs of the flip-flops RCl - RC6 and accordingly those of the flip-flops F01 - F06 are provided accurately at the interval of 60 degrees and continue by 180 degrees. The characteristic as in FIG. 15 is therefore fulfilled by introducing the outputs of the flip-flops F01 - F06 into the integration circuits Il - I6, comparing the outputs of the integration circuits Il - I6 with the control voltage Ec by respective comparators Cl - C6 and producing the pulse outputs in places where they coincide.
When the control voltage Ec is corrected according to the least one of the phase voltages and the line voltages as in FIG. 14, the gate pulse interval-fixing control is satisfied and stable running of the inverter is possible.
FIG. 17 is a block diagram showing a further example of gate pulse phase shifter which can be used for this invention. FIG. 18 is a waveform diagram for explaining the operation of the circuit in FIG. 17. This circuit has been published in IEEE Summer Power Meeting Paper N0 TP 640-PWR, and is mentioned herein as an example of an automatic gate pulse phase shifter which can be employed.
The operation of the pulse generator PG in FIG. 17 will now be described. In the figure, VCC represents a voltage-controlled current source which provides a current 92~
of magnitude proportional to an input voltage Vc2. CON
denotes a capacitor, and VCOM a comparator. The comparator operates and generates a pulse Vp when the terminal voltage Vc of the capacitor CON becomes larger by ~V/2 than a phase control signal Vcl. The pulse Vp drives a capacitor dis-charging circuit CD, to keep the capacitor CON discharged until the terminal voltage Vc becomes smaller by ~V/2 than the phase control signal Vcl. The appearance of this operation can be readily appreciated from the waveform diagram in FIG. 18. The velocity ~ at which the terminal voltage Vc rises is proportional to the output current of the current source VCC and accordingly to the input voltage Vc2. While-the phase control signal Vcl is constant, the pulses Vp are generated at intervals of 60 degrees. When the voltage Vcl increases as shown at ~Vcl.l in the figure, the phase of the pulse Vp changes by ~1 in the lagging direction. In contrast, when the voltage Vcl decreases, as shown at ~Vc1.2, the phase of the pulse Vp instantly leads by ~2. The magnitudes of ~1 and ~2 are proportional to Vcl.l and Vc1.2, respectively.
Shown at SR is a shift register. This is a circuit that .-:
distributes the pulses Vp as gate pulses to the respective arms of the inverter constituted by the thyristor valves Vl - V6. The outputs Pl - P6 of the circuit SR are the gate pulses of the respective arms of the inverter. The other part of the circuit arrangement in FIG. 17 is a circuit for establishing synchronization with the voltages of the A.C.
system. AM indicates a circuit for measuring the actual retarded control angle ~ of the inverter. FLl and FL2 designate filters. The output ~ref of the filter FLl is equal to the phase control signal Vcl. Accordingly, this value is made a reference value, and an ~ control circu t AC operates to 1~)78g2~
control the gradient ~ of the terminal volrage Vc in order that the output ~act of the filter FL2 may become equal to the output ~ref of the filter FLl. The pulse generator PG
thus operates in synchronism with the A.C. system to which the inverter is connected. Vc21 denotes a voltage proportional to the frequency of the A.C. system. It controls the gradient of the voltage Vc through an adder ADF according to a change of the frequency, so as always to maintain the retarded control angle ~ equal to an electrical angle determined by the phase control signal Vcl. Since the time constant of the filter FL2 is set at a large value, the pulse phase shifter in FIG. 17 has the same function as the circuit in FIG. 16. Of course, the control voltage Ec in FIG. 3 is introduced as the control voltage indicated by Vcl in FIG. 17.
As described above, in accordance with this con-struction, stable running can be ensured when employing the automatic pulse phase shifter of the gate pulse interval-fixing control system, and even when the voltage of the A.C.
system drops due to any fault arising in the A.C. system.
While the connection of the transformer for the inverter has been explained above as being a star - star connection, this invention is applicable without any substantial change to a case where the transformer uses the star - delta connection.
When the transformer for the inverter uses the star - delta connection, the voltage transformers PTa, PTb and PTc in FIG. 3 and FIG. 16 may be changed to the star - delta connection to form voltages corresponding to the commutation voltages, and the voltage transformers APT and PTl, PT2 and PT3 may be changed to the delta - star connection to apply the commutation voltages to the waveform converter circuits Fl - F6.
Since the voltage transformers PTa, PTb and PTc are not always used exclusively for the gate pulse phase shifter, they cannot always be brought to the star - delta connection.
In such cases, a method to be stated below can be relied on.
This invention relates to a system in which the voltage phase of the A.C. system under normal conditions is referred to as the phase of the synchronizing power sources. Therefore, it is not necessary to employ the commutation voltages as the synchronizing power sources of the automatic gate pulse phase shifter. Where the transformer uses the star - delta connection, the phase voltages Va, Vb and Vc on the A.C. side of the transformer for the inverter which are in phase with the commutation voltages in the normal operation of the A.C. system may be used as the synchronizing power sources without change.
In this case, both the voltage transformers PTa, PTb and PTc and the voltage transformers APT and PTl, PT2 and PT3 in FIG. 3 and FIG. 17 can use the star - star connection.
Claims (8)
1. An inverter control system for an inverter connected between one side of an inverter transformer and a D.C. system, the other side of said transformer being connected to an A.C. system, said system comprising:
(a) first means for deriving a signal corresponding to an advanced control angle of said inverter in accordance with voltages of said A.C. system applied to said inverter and current in said D.C. system, (b) second means for deriving a phase correction signal in response to an unbalance of said A.C. voltages applied to said inverter, said phase correction signal corresponding to the magnitude of the unbalance of phase differences among respective phases of commutation voltages applied to said inverter, (c) third means to synthesize the outputs of said first and second means, and (d) fourth means for generating firing pulses whose phases are determined in accordance with the output of said third means.
(a) first means for deriving a signal corresponding to an advanced control angle of said inverter in accordance with voltages of said A.C. system applied to said inverter and current in said D.C. system, (b) second means for deriving a phase correction signal in response to an unbalance of said A.C. voltages applied to said inverter, said phase correction signal corresponding to the magnitude of the unbalance of phase differences among respective phases of commutation voltages applied to said inverter, (c) third means to synthesize the outputs of said first and second means, and (d) fourth means for generating firing pulses whose phases are determined in accordance with the output of said third means.
2. The inverter control system according to claim 1, wherein said phase correction signal is formed on the basis of commutation voltages applied to said inverter.
3. The inverter control system according to claim 1, wherein said fourth means comprises:
an oscillator which outputs an oscillation frequency responsive to an input voltage fifth means to divide the outputs frequency of said oscillator, sixth means to derive a phase of voltages in phase with commutation voltages being applied to said inverter in the normalcy of said A.C. system, seventh means to derive a difference in phase between an output of said fifth means and an output of said sixth means, eighth means to convert an output of said seventh means into a voltage and to add thereto a signal for regulating into a predetermined relation with the output phase of said oscillator and said phase of said voltages in phase with said commutation voltages, thus to bring a sum voltage to said input voltage of said oscillator.
an oscillator which outputs an oscillation frequency responsive to an input voltage fifth means to divide the outputs frequency of said oscillator, sixth means to derive a phase of voltages in phase with commutation voltages being applied to said inverter in the normalcy of said A.C. system, seventh means to derive a difference in phase between an output of said fifth means and an output of said sixth means, eighth means to convert an output of said seventh means into a voltage and to add thereto a signal for regulating into a predetermined relation with the output phase of said oscillator and said phase of said voltages in phase with said commutation voltages, thus to bring a sum voltage to said input voltage of said oscillator.
4. The inverter control system according to claim 3, wherein the phase correction signal is a signal obtained from the commutation voltages, said signal being a signal which corresponds to the magnitude of the unbalance of phase differences among respective phases of commutation voltages applied to said inverter.
5. The inverter control system according to claim 4, further comprising:
(a) fifth means to derive the smallest commutation voltage, and (b) sixth means to select either of the output of said fifth means and the control voltage corrected by said correction signal and to make the selected voltage the control voltage.
(a) fifth means to derive the smallest commutation voltage, and (b) sixth means to select either of the output of said fifth means and the control voltage corrected by said correction signal and to make the selected voltage the control voltage.
6. The inverter control system according to claim 1, wherein said fourth means comprises a capacitor whose charging speed is controlled by a current dependent upon a voltage corresponding to a frequency of said A.C. system and a retarded control angle of said inverter, and a circuit which, when a charging voltage of said capacitor and a control voltage are compared and are in a predetermined relation, outputs gate pulse and controls discharg-ing of said capacitor.
7. The inverter control system according to claim 6, wherein the phase correction signal is a signal obtained from the commutation voltages, said signal being a signal which corresponds to the magnitude of the unbalance of phase differences among respective phases of commutation voltages applied to said inverter.
8. A system comprising:
(a) An inverter connected between on side of an inverter transformer and a D.C. system, the other side of said inverter transformer being connected to an A.C. system, (b) first means to derive voltages corresponding to three commutation voltages of said inverter, (c) a first high value circuit for deriving the largest one of said voltages corresponding to said three commutation voltages, (d) first, second and third low value circuits each for deriving a smaller voltage from a combination of two of said voltages corresponding to said three commutation voltages, (e) a fourth low value circuit for deriving the smallest one of said voltages corresponding to said three commutation voltages, (f) a second high value circuit for deriving the largest one of the outputs of said first, second and third low value circuits, (g) second means for deriving a voltage correspond-ing to a current flowing through said D.C. system, (h) a first function generator for obtaining a voltage corresponding to a necessary advanced control angle of said inverter from the respective outputs of said second means and said second high value circuit, (i) a second function generator for obtaining a voltage corresponding to a necessary advanced control angle of said inverter from the respective outputs of said second means and said fourth low value circuit, (j) a first divider circuit for calculating a ratio between the outputs of said first and second high value circuits, (k) a second divider circuit for calculating a ratio between the output of said second high value circuit and the output of said fourth low value circuit, (l) third and fourth function generators for deriving phase correction signals from the outputs of said first and second divider circuits, respectively, (m) third means for synthesizing the output of said first function generator and the output of each of said third and fourth function generators, (n) a fifth low value circuit for selecting one of the outputs of said third means and said second function generator, and (o) a gate pulse phase shifter whose control voltage is the output of said fifth low value circuit, whose synchronizing power sources are said commutation voltages, for outputing gate pulses at times corresponding to the advanced control angle.
(a) An inverter connected between on side of an inverter transformer and a D.C. system, the other side of said inverter transformer being connected to an A.C. system, (b) first means to derive voltages corresponding to three commutation voltages of said inverter, (c) a first high value circuit for deriving the largest one of said voltages corresponding to said three commutation voltages, (d) first, second and third low value circuits each for deriving a smaller voltage from a combination of two of said voltages corresponding to said three commutation voltages, (e) a fourth low value circuit for deriving the smallest one of said voltages corresponding to said three commutation voltages, (f) a second high value circuit for deriving the largest one of the outputs of said first, second and third low value circuits, (g) second means for deriving a voltage correspond-ing to a current flowing through said D.C. system, (h) a first function generator for obtaining a voltage corresponding to a necessary advanced control angle of said inverter from the respective outputs of said second means and said second high value circuit, (i) a second function generator for obtaining a voltage corresponding to a necessary advanced control angle of said inverter from the respective outputs of said second means and said fourth low value circuit, (j) a first divider circuit for calculating a ratio between the outputs of said first and second high value circuits, (k) a second divider circuit for calculating a ratio between the output of said second high value circuit and the output of said fourth low value circuit, (l) third and fourth function generators for deriving phase correction signals from the outputs of said first and second divider circuits, respectively, (m) third means for synthesizing the output of said first function generator and the output of each of said third and fourth function generators, (n) a fifth low value circuit for selecting one of the outputs of said third means and said second function generator, and (o) a gate pulse phase shifter whose control voltage is the output of said fifth low value circuit, whose synchronizing power sources are said commutation voltages, for outputing gate pulses at times corresponding to the advanced control angle.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP50111635A JPS5235830A (en) | 1975-09-17 | 1975-09-17 | Control system for reverse converter |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1078921A true CA1078921A (en) | 1980-06-03 |
Family
ID=14566297
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA260,273A Expired CA1078921A (en) | 1975-09-17 | 1976-08-31 | Inverter control system |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JPS5235830A (en) |
| CA (1) | CA1078921A (en) |
| DE (1) | DE2641963A1 (en) |
| SE (1) | SE437201B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109557491A (en) * | 2018-12-17 | 2019-04-02 | 江苏固德威电源科技股份有限公司 | A kind of its inverter of three-phase voltage sampling correcting methods and applications |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57148594A (en) * | 1981-03-10 | 1982-09-13 | Toshiba Corp | Automatic operation control system for hydraulic power plant |
| JP3338159B2 (en) * | 1994-02-10 | 2002-10-28 | 三菱電機株式会社 | Amplitude / phase detector |
| CN113541153B (en) * | 2021-06-11 | 2023-05-26 | 南瑞集团有限公司 | Camera adjustment control method and system for resisting overvoltage of commutation failure sending end wind power plant |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5451B2 (en) * | 1974-04-22 | 1979-01-05 |
-
1975
- 1975-09-17 JP JP50111635A patent/JPS5235830A/en active Granted
-
1976
- 1976-08-17 SE SE7609145A patent/SE437201B/en unknown
- 1976-08-31 CA CA260,273A patent/CA1078921A/en not_active Expired
- 1976-09-17 DE DE19762641963 patent/DE2641963A1/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109557491A (en) * | 2018-12-17 | 2019-04-02 | 江苏固德威电源科技股份有限公司 | A kind of its inverter of three-phase voltage sampling correcting methods and applications |
Also Published As
| Publication number | Publication date |
|---|---|
| SE437201B (en) | 1985-02-11 |
| DE2641963A1 (en) | 1977-03-24 |
| JPS5235830A (en) | 1977-03-18 |
| JPS5628469B2 (en) | 1981-07-02 |
| DE2641963C2 (en) | 1989-07-13 |
| SE7609145L (en) | 1977-03-18 |
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| MKEX | Expiry | ||
| MKEX | Expiry |
Effective date: 19970603 |