CA1072231A - Slow rise time write pulse for gas discharge device - Google Patents

Abstract

TITLE
SLOW RISE TIME WRITE PULSE FOR GAS DISCHARGE DEVICE
ABSTRACT
A gas discharge device having at least one dielectric charge storage member the gaseous medium contacting surface of which consists of a low operating voltage material. The material is used in an amount sufficient to increase the operating life span of the device and/or stabilize the operating voltages of the device. An interface and addressing means is connected to a pair of opposed electrode arrays to energize a plurality of discharge cells, each cell including proximate electrode portions of at least one electrode in each opposed array, said dielectric charge storage member insulating at least one of said proximate electrode portions from said gas. A cell presents a capacitive impedance to a voltage pulse applied by the interface and addressing means to the electrode portions to generate a relatively slow rise time leading edge on said voltage pulse for improved addressing of said cell.
In an alternate embodiment, a write voltage pulse having a relatively fast rise time is superimposed on a sloped pedestal to generate a relatively slow rise time portion of said voltage pulse for improved addressing of a cell.

Description

7~

BACKGROUND OF THE IN~ENTION
l. Field Of The Invention This inventlon relates to wave forms for controlling gas discharge devices, especially multiple gas discharge display/memory devlces which have an electrical memory and which are capable of producing a visual display or representation of data.

2. Description Of The Prior Art Heretofore, multiple gas discharge display andlor memory panels have been proposed in the form of a pair of dielectric charge storage members which are backed by electrodes, the electrodes being so formed and oriented with respect to an ionizable gaseous medium as to define a plurality of discrete gas discharge units or cells. The cells ha~e been defined by a surrounding or confining physical structure such as the walls of apertures in a perforated glass plate sandwiched between glass surfaces and ~hey have been defined in an open space between glass or other dielectric backed with conductive electrode surfaces by appropriate choices of the gaseous medium, its pressure and the electrode geometry. In either structure9 charges ~electrons and ions) produced upon ionization of the gas volume of a select d discharge cell, when proper alternating operating voltages are applied between the opposed electrodes, are collected upon the surface of the dielectric at specifically defined locations. These charges constitute an electrical ield opposing the electrical field which created them so as to reduce the voltage and .
terminate the discharge for the remainder of the cycle portion during i .
~ which the discharge producing polarity remains applied. These collected charges aid an applied voltage of the polarity opposite that which created them in the initiation of a discharge by imposing a total voltage across the gas sufficient to again initiate a discharge and a collection of charges. This repetitive and alternating charge collection and ionization discharge constitutes an electrical memory.
~" .
.' ~ .

~' .

' .

~7;~39~

~n example of a panel structure containing non-physically isolated or open discharge cells is disclosed in U.S. Patent No. 3,499,167 issued to Theodore C. Baker, et al. Physically isolated cells have been disclosed in the article by D.L. Bitzer and H.G. Slottow entitled "The Plasma Display Panel - A Digitally Addressable Display With Inherent Memory" Proceeding of the Fall Joint Computer Conference, I E E E , San Francisco, Cal., November 1966, pp 541 -547 and in U.S.
Patent No. 3,559,190.
One construction of a memory/display panel includes a continuous volume of ionizable gas confined between a pair of dielectric surfaces backed by conduc~or arrays, typically in parallel lines with the arrays of lines orthogonally related, to define, in the region of the proJected intersections as viewed along the common perpendicular to each array, a plurality of opposed pairs of charge storage areas on the surfaces of the dielectric bounding or confining the gas. Many variations of the individual conductor form9 the array form, their relationship to each other and to the dielectric and gas are available , hence the orthogonally related, parallel llne arrays which are discussed herein are merely illustrative. -In prior art, a wide variety of gases and gas mixtures have been utilized as the ionizable gaseous medium, it being desirable that the gas provide a copious supply of charges during discharge, be inert to the materials with which it came in contac~, and,where a visual display is desired, be one which produces a vlsible light or radiation which stimulates a phosphor. Preferred embodiments of the display panel have utilized at least one rare gas, more preferable at least two, selected from helium, ;
neon, argon, krypton or xenon.
In the operation of the display/memory device an alternating voltage is applied, typicalLy, by applying a first periodic voltaee wave ~ ~

-3- -223~

form to one array and applying a cooperating second wave form,frequently identical to and shifted on the time axis with respect to the first wave form, to the opposed array to impose a voltage across the cells formed by the opposed arrays of electrodes which is the algebraic sum of the first and second wave forms. The cells have a voltage at which a discharge is initiated~ That voltage can be derived from an externally applied voltage or a combination of wall charge poten~ial and an externally applied ~;
voltage. Ordinarily, the entire cell array is excited by an alternating voltage which, by itself, is of insufficient magnitude to ignite gas discharges in any of the elements. When the walls are appropriately ~ charged, as by means of a previous discharge, the voltage applied across ; the element will be augmented, and a new discharge will be ignited.
Electrons and ions again flow to the dielectric walls extinguishing the discharge; however9 on the following half cycle, their resultant wall charges again augment the applied external voltage and cause a discharge in the opposite direction. The sequence of electrical discharges is sustained by an alternating voltage sig~nal that, by itself, could not initiate that sequence. The half amplltude of this sustaining voltage has been designated Ys/20 - 20 In addition to the sustaining voltage there are manipulating voltages or addressing voltages imposed on the opposed electrodes of a selected cell or cells to alter the state of those cells selectively.
One such voltage, termed a "wrlting voltage", transfers a cell or discharge site from the quiescent to the discharging state by virtue of a total applied voltage across the cell sufficient to make it probable that on subsequent sustaining vol~age half cycles the cell will be in the "on state".
A cell in the "on state~' can be manipulated by an addressing voltage, termed an "erase voltage", which transfers it to the "off state" by .

4--: : . .. . . : .. . . .

imposing æufficient voltage to draw off the surface or wall charges on the cell walls and cause them to discharge without being collected on the opposite cell walls in an amount such that succeeding sustainer voltage transitions are not augmented sufficiently by wall charges to ignite discharges.
A common method of producing writing voltages is to superimpose -voltage pulses on a sustainer wave form in an aiding direction and cumulatively with the sustainer voltage, the combination having a potential ~ ~
of enough magnitude to fire an "off state" cell lnto the "on state". Erase ;
voltages are produced by superimposing voltage pulses on a sustainer wave form in opposition to the sustainer voltage to develop a potential sufficient to cause a discharge in an "on state" cell and draw the charges from the dielectric surfaces such tha~ the cell will be in the "off state".
The wall voltage of a discharged cell is termed an "off state wall voltage"
lS and frequently is midway between the extreme magnitude limits of the sustainer voltage Vs.
, The stability characteristics and non-linear switching properties of these bistable cells are such tha~, in the case of a cell which has not fired in the preceding half cycle of sustainlng voltage, the state of such cell in the cell array can be changed by selective application of ., , an external voltage which exceeds the firing or discharge igniting potential.
In the case of a cell which has been fired in the preceding half cycle and has accumulated charges which can aid the sustaining voltage, the cell can be ~urned off by applying a voltage which discharges the cell.
These manipulating sign;l6 are applied in a tlmed relationship with the alternating sustaining voltage, and through control of discharge intensity, . .
accomplish selective state transitions by changing the wall voltage of only the cell being addressed.
Cells are transferred to the "on state" by applying a portion of ~he manipulating signal superimpoeed on the sustaining voltage, termed ~: .'. ' ': ' .. ,. , ,, ., . -,' ., '' "~, ~,.,' '. ' ' . ' ', . .,: ,' ' ' ~7223~
.
a "select signal", on each of two opposed electrode portions which are proximate the cell. Conventionally, like sustaining signals are imposed on each electrode array so that half the sustaining voltage is imposed on each array and half the select signal is imposed on the addressed cell electrode in each electrode array at a time when the sum of the applied voltages is sufficient to ignite a discharge. Further, the partial select signals on each electrode are limited to a value which will not impose a firing potential across other cells defined by that electrode and not selected~ A typical write signal for a cell is developed by applying half select voltages to the addressed electrodes of the cell to be placed in the "on state" at a time the sustaining voltages are developing a pedestal potential somewhat below the maximum sustaining voltage. Typically, a write signal is imposed on each opposed electrode portion of the cell during the terminal portion of a susta:Ln voltage half cycle when any wall charging which may result from the prior sustainer transient is substantially completed. The manipulating signal thus ignites a single, and unique, cell at the intersection of the selected two opposed electrodes. ~-This ignited discharge thus establishes the cell in the "on state" since a quanitiy of charge is stored in the cell such that9 on each succeeding half cycle of the sustaining voltage, a gaseous dlscharge will be produced.
~; In order to erase a cell or transfer it to the "off state", the charge stored in the cell is discharged at a time when the sustaining voltage is imposing a voltage in opposition to the wall charge voltage. As for writing, the erase manipulation is facilitated if the sustaining voltage ZS is at a pedestal level below the level providing the maximum applied voltage so that the erase half select voltages are at a convenient level. Typically, an erase signal is imposed on each opposed electrode portlon of the cell during the terminal portion of a sustain voltage half ; ~ :
cycle, when the wall charglng from the prior sustainer discharge is :; , ~72~3~ ~:

substantially completed, but preceeding the next half cycle alternation by enough time so that the wall discharge of the selected cell is substantially stabilized.
Circuitry for sustaining voltages, and where employed, their pedestal, and for the manipulating voltages for writing and erasing individual cel~s can be quite extensive.
Transformer coupling of manipulating signals to the electrodes ~ of multiple gas discharge display/memory devices has been disclosed in ; William E. Johnson et al. U.S. Patent ~o. 3,618,071 for "Interfacing Circuitry and Method for Multiple-Discharge Gasous Display and/or Memory Panels" which issued NovO 29 1971. ~he coupling of individual electrodes in large arrays involvlng substantial numbers of electrodes is cumbersome and expensive. Accordingly, solid-state pulser circuits capable of feeding through the sustaining voltage were proposed as exemplified in William E.
Johnson U.S. Patent No. 3~611,296 of Oct. 5~ 1971 for "Driving Circuitry For Gas ~ischarge Panel". Multiplexing of the signals to the electrodes in an array has ~een utilized employing combinations of diode and resistor pulsers to manipulate cell potentials as shown in U.SO Patent No. 3,864,918 issued Aug. 15, 1972 to Larry J. Schmersal for "~as Discharge Display/
Memory Panel6 and Selection and Addressing Circuits Therefore".
It previously had been discovered that the operating characterist~cs uniformity and operating life span of a multiple cell gaseous discharge display~memory de~ice can be increased by utilizing a charge storage member wqth a gas medium contact surface consisting of at least one member selected from oxides of Be, Mg, Ca, Sr, Ba, or Ra. As used herein the gas medium contacting surface is that portion of the dielectric charge storage member which is in direct contact with the ionizable gas medium. -i Although it is not known whether the charges are stored on the gas contacting surface or sub-surface of the dielectric, the charges at least originate at such surface.
: ' ' :" .

~ ' . .

~7~:Z3~L
In one em~odiment, the entire dielectric body consists of a Group IIA oxide. In another embodiment, a continuous or discontinous layer of film of a Group IIA oxide is applied to the gaseous medium contacting surface portion of the dielectric body.
In such latter embodiment, the oxlde layer may be formed in situ on the dielectric surface, e.g., by applying the elemental Group IIA (or a source thereof) to the dielectric surface followed by oxidation. One such in situ process comprises applying a melt to the dieleGtric followed by oxidation of the melt during the cooling thereof so as to form the oxide layer. Another in situ process comprises applying an oxidizable source of the Group IIA element to the surface. -~
Typical oxidi~able sources include minerals and/or compounds containing the appropriate Group IIA element, especially organic compounds which are readily heat decomposed or pyrolyzed. ~-Typically, the Group IIA oxide layer (or a source thereof) is applied directly to the dielectric surface by any convenient means including not by way of limitation: vapor deposition; vacuum deposition;
chemical vapor deposition; wet spraying upon the surface a mixture of solution of the oxide suspended or dissolved in a l~quid followed by evaporatlon of the liquid; dry spraylng oE the oxide upon the surface;
electron beam evaporation; plasma flame and/or arc spraying and/or - deposition; and sputtering target techniques.
The Group IIA oxide is appliad to (or formed in situ on) the dielectric surface as 2 very ~hin continuous or discountinous film or ; 25 layer, tXe thickness and amount of the oxide layer being suff~cient to increase the operating characteristics uniformity ~such as stabili~ation . .
of operating voltages) and/or operating life span of the device. In ; -the usual practice hereof, the oxide layer is applied to or formed on .
, .

~72~3:~

the dielectric materi~l surface to a thickness of at least about 200 angstrom uni-ts with a range of about 200 angstrom units up to about 1 microm (10,000 angstrom units). When the en-tire di-electric consists of a Group IIA oxide, the dielectric Group IIA
oxide thickness may range up to 25 microns or more. As used herein, the terms "film" or "layer" are intended to be all in-clusive of other similar terms such as deposit, coating, finish, spread, covering, etc.
In the fabrication of a gaseous discharge panel, the dielectric material is typically applied to and cured on the surface of a supporting glass substrate or base to which the .
electrode or conductor elements have been previously applied.
The glass substrate may be of any suitable composition. In a Baker et al device two glass substrates containing electrodes and cured dielec~ric are then appropriately heat sealed together so as to form a panel.
In order to achieve maximum results, the Group IIA
oxide layer is continuously or discontinuously applied to the gaseous m~dium contacting surface o the dielectric. In other words, the applied Group IIA oxide layer must be directly ex-posed to the gaseous medium in order to achieve the desired results.
Other metal or metalloid oxide layers may exist below that of the Group IIA oxide layer. Such sub-layers may be of any suitable oxide of the periodic table, especially alumlnum oxide, silicon oxide and the rare earth oxides. Also, as already noted hereinbefore, another embodiment of this invention com~
prises using a dielectric which consists of Group IIA oxide.
According to the present invention there is provided a method of manipulating the discharge state of individual cells of a gas discharge display/memory device which comprises apply-g ~.

.

~72;~3~

ing a periodic alternating polarity sustainer voltage to the cells having a magnitude and duration sufficient to maintain a discharge in any cell which is in the "on state"; turning a cell in the "off state" to the "on state" by applying a write pulse having a relatively slow rise time portion; and turning a cell in the "on state" to the "off state" by applying an erase pulse having a relatively fast rise time leading edge.
The present invention also provides, in an operating system for a multicelled gas discharge display/memory device, the device including a pair of opposed electrode arrays with proxi-mate electrode portions of at least one electrode in each array defining the cells; an ioniæable gas volume between the spaced electrode portions of each cell; a dielectric charge storage member in contact with the gas insulaking at least one electrode portion of each cell from the gas; a sustainer voltage source connected across each cell to cyclically impose an alternating . , .
voltage having a period; pulser means for generating write and erase voltage pulses to manipulate the discharge state of in-dividual cells between an '~on state" and an "off state", the improvement comprising: said dielectric charge storage member formed from a low~operating voltage material and means for generating said write voltage pulses with a relatively slow rise time portion whereby cro~stalk between adjacent cells is reduced.
Preferred embodiments of the invention relate to a ~ ;
multicelled gas discharge display/memory device having a~ least one dielectric charge storage member with a low~operating voltage gaseous medium contacting surface, The surface is typically formed of at least one Group IIA oxide used in an amount suffi- ~-cient to increase the operating life span of the device and/or stabilize the operating voltages of the device. An interface and addressing circuit i9 connected to a pair of opposed elec-. . ' .

Z3~L

trode arrays to energize a plurality of discharge cells, eachcell including proximate electrode portions of at least one electrode in each opposed arrayO the dielectric charge storage member insulating one of the proximate electrode portions from the gas.
The interface and addressing circuit includes sustainer vol~age sources for maintaining a series of discharges in a cell and a pulser-resistor-diode matrix for writing and erasing selected cells. Since the cells present a capacitive impedance to the interface and addressing circuit, keyerpulsers are in-cluded to generate a steeply rising leading edge on the write and erase pulses. However, where the low voltage dielectric surface is utilized, the steeply rising wrife pulses tend to generate crosstalk, that is turn on cells adjacent to the selected cell.
The keyer pulsers are turned off when the write pulses are generated. The write pulses are then subjected to ~he capaci tive impedance of the cells to generate a slow rise time leading edge. Such write pulses tend to decrease or eliminate crosstalk in the device. In addition, the slow rise time write pulses increase the size of the window, the pulse-sustainer voltage -~
combinations which result in satisfactory operation of the deviceO
An increase in the duration of the write pul~e in conjunction with the slow rise time of that pulse may also be utilized to further improve the relia~ility of the selective manipulation of ~ -the charge state of individual cells~
When the pulser circuits utilize integrated circuits, the low output impedance reduces the charging time constant of `~
the cells. Therefore, the keyer pulsers can be eliminated from ~he interface and addressing cixcuit. However, when the low voltage dielectric surface is utilizedO the steeply rising write ~ .

~7;~23~L

pulses tend to generate "crosstalk" that is turn on cells ad-jacent to the selected cell.
Although the pulsers could be designed to generate a write pulse with a slow rise time leading edge, that would drastically limit their usefullness and flexibility. In accord-ance with an alternate embodiment of the present invention, the interface and addressing circuit ~enerates a sustainer voltage having a sloped pedestal. When the fast rise time write pulse is added to the sloped pedestal, a relatively slow rise time portion is created on the write pulse. Such write pulses tend to de-crease or eliminate "crosstalk" in the device. In addition, the slow rise time portion write pulses increase the size of the window, the pulse-sustainer voltage combinations which result in -satisfactory operation of the device.~ An increase in the dura-tion of the write pulse in conjunction with the slow rise time portion of that pulse may be utili~ed to further improve the reliability of the selective manipulation of the charge state of individual c~lls.
An o~ject of he present invention is to facilitate the control of a multiple gas discharge display/memory device for the manipulation of cell states.
Fig. 1 is a generalized prior art sustaining voltage wave form and write pulse plotted against time; -~
Fig. 2 is a generalized sustaining voltage wave form and a write pulse according to the present invention plotted against time;
Fig. 3 is a partially cut-away plan view o a gaseous discharge display/memory panel of the Baker et al type, disclosed in U.S. Patent 3,499,167, connected to a diagrammatically illus-30 trated source of operating potentials; -;

Fig. 4 is a cross-sectional view (enlarged, but not to ,,~,,,~

: . . . . ~ ~ -:, .. .

~7;~:;Z3~

proportional scale since the thickness of the gas volume, di-electric members and electrode arrays have been enlarged for purposes of illustration) taken on line 4-4 of Fig. 3;
Fig. 5 is an explanatory partial cross-sectional view similar to Fig. 4 (enlarged, but not to proportional scale);
Fig. 6 is an isometric view of a gas discharge display/
memory panel;
Fig. 7 is a schematic representation of the interface and addressing circuit of Fig. 3;
10 Fig. 8 (which appears on the same sheet as Figs. 1 and 2) is a modified sustaining voltage wave form and an extended write pulse according to an embodiment of the present invention plotted against the time scale of FigsO 1 and 2;
Fig. 9 is a plot of the window data for a typical ~-gaseous discharge panel;
Fig. 10 is a modified sust:aining voltage wave form -with a sloped pedestal and a write pulse according to the al-ternate embodiment of the present invention plotted against time;
Fig. 11 is a schematic representation of the interface and addressing circuit according to the alternat~ embodiment of - ;
the present in~ention;
Fig. 12 is a modified sustaining voltage wave form and an extended write pulse according to the alternate embodiment of the present invention plotted against the time scale of ~igs. 1 and 10;
Fig. 13 is a schematic representation of an alternate to the circuit of Fig. 11; and Fig. 14 is a schematic representation of a second alternate to the circuit of Fig. 11.

~ - .

~ 13 . , ~

-. .~ : ., , : . . :. : :.

~Z;Z3~L

DESCRIPTION OF THE PRE~ERRED EMB~DIMENT
There is shown in Fig. 1 the prior art wave forms associated with the bistable operation of a gas discharge cell. The applied voltage wave form shows a sustaining voltage Vs which is continuously applied to all cells or sites on a panel. The magnitude of the sustaining voltage is insufficient to cause any discharge sites to turn on (i.e. to initiate ; -a stable sequence of discharges), but is sufficient to sustain a discharge sequence once the sequence has been initiated by a "write" pulse applied to the selected site. The magnitude of the "write" pulse must exceed the firing potential of the site and can be applied between the alternate ; half cycles of the sustaining voltage, superimposed on a half cycle or superimposed on a pedestal as shown in Fig. 1. The utilization of the -pedestal with the sustaining voltage wa~e form allows the use of a smaller magnitude write pulse which can be generated by less expensive electronics.
Because the conducting electrodes are separated from the discharge by a thin layer of insulating dielectric material, the gas discharges occur as short pulses. As the dlscharge current flows, the electrons and ions accumulate on the insulating surfaces producing an electric field which opposes the field whlch caused breakdown. The voltage due to these charges on the walls is called the wall voltage. ;
~;~ When the polarity of the applied voltage changes, the wall voltage adds to the applled voltage thus produc~ng another discharge pulse. This process repeats every half cycle producing a sequence of discharges which continues indeflnitely.
A slte may be turned off by applying an appropriate "erase"
pulse (not sho~m) which has the efect of reducing the wall voltage to a level insufficient to relnforce the reversed sustaining voltage to produce a dlscharge pulse. The sequence of discharge pulses is accompanied by '.`' `, ' ':

. ~'' ~97~ZZ3~

a sequence of light pulses (also not shown)~ The repetition rate of the light pulses is fast enough so that the light appears steady to the human eye. A typical sustaining voltage fre~uency is in the range 30-50 ~Hæ. The magnitude of the sustaining voltage must be kept within a certain range, the bistable range. If the sustaining voltage is too low, the discharge sequence will not be maintained. If the sustaining voltage ls too high, the discharge sites will be turned on by the sustaining voltage alone, thus negating the ability to address selected points on the x-y matrix by the appllcation of a write pulse. The memory of the panel is a consequence of the charges stored on the insulating surface.
For a given display panel, the limits of the bistable range depend on many parameters such as the composition of the fill gas, the gas pressure, the panel geometry and panel ma~erials.
Typically, a periodic sustaining voltage sufficient to operate the panel is applied to the opposing e:Lectrode arrays, the wave form - being rectangular, square, sinusoidal, trapezoidal, triangular~ or of `
any other periodic geometric form or shape. As described in U.S. Patent No. 3,727,102 issued to William E. Johnson on April 10, 1973, one half ~ -of the sustaining voltage can be applied to one electrode array and the other half can be applled at lôO phase or opposite polarl~y to the opposing electrode array, the two applied sustaining voltages being algebraically added across the unit. Likewise, all of the sustaining voltage can be applied to only one electrode array.
In the operatlon of a multiple gas discharge display/memory device which contains opposing electrode arrays, the writing of a ;j ; particular unit or cell is usually effec~ed by applying a writing voltage to j one electrode of the cell and a similar writing voltage to the opposing electrode of the cell. The phase of each writing voltage is such that "-'.
' '~

:
. , .,, :
- ~ ' . .

~17223~L

the two voltages are algebraically added to form a write pulse of sufficient magnitude to turn on the cell. The write voltages are known as partial select voltages~ If the writing voltages are derived from the same source, each is equal to the other in magnitude and therefore represents one half of the write pulse.
Such write voltages are known as half select voltages. U. S. -Patent No. 3,618,071 issued to William E. Johnson and Larry J.
Schersal on November 2, 1971 discloses a circuit and method for generating partial select voltages to form write pulses.
U. S. Patent NoO 3,801,861 issued to William D. Petty and David E. Liddle on April 2, 1974 discloses wave forms for operating a multiple gaseous discharge panel so as to minimize or eliminate the writing of not-to-be-written cells. One partial select voltage is applied to one electrode of a cell and another partial select voltage is applied to the opposing electrode wherein only they are algebraically added across the cell from a near zero slope pedestal. The magnitude of the pedestal is substantially less than the maximum magnitude achieved by the total applied sustaining voltage in one period,!and the magnitude of the partial select voltage applied to either opposing electrode alone is insufficient to write any cell in the panel. -It is desirous to increase the operating characteristics uniformity and operating life span of a yaseous discharge device.
It has been found that such results can be obtained by utilizing a charge storage member with a low operating voltage gas medium contact surface consisting of at least one member selected from the oxides of Be, Mg, Ca, Sr, Ba or Ra as disclosed in U. S.
Paten~ No. 3,846,171 issued to Bernard W. Byrum, Jr. et al on November 5, 1974 and U. S. Patent No. 3/863~098 issued to 30 Roger E. Ernsthausen on January 28, 1975~
~ .

;, ~ .. . .

. .
.: . , :
, . . , :. ', :'- ~ ' ' ' ~7223 ~ :

One reason for the increase in the operating life span is a substantial reduction in ~he magnitudes of the operating voltages required to drive the panel. ~owever, it has been found that use of a Group IIA
oxide as the gas medium contact surface has a tendency to generate "crosstalk" when a selected cell is being turned on. Crosstalk refers to the turning on of cells adjacent the selected cell when only the selected cell is subjected to the write pulse. The present invention is directed to eliminating crosstalk by utilizing a slow rise time write pulse in place of the sharply defined write pulse of Fig. 1.
~.
There is shown in Fig. 2 the wave forms associated with the operating voltage applied to a gas discharge cell having at least one j gaseous medium contacting surface which consists of a Group IIA oxide.
The general shape of the sustaining voltage wave form is similar ~o the sustalning voltage shown in Fig. 1, but the magnitude is substantially less. The write pulse has a slow rise time designed to elimina~e crosstalk. The circuitry for generating the slow rise time write pulse is well known in the art and can use the natural capacitive impedance of the cells to advantage. This circuLt will be discussed subsequently after a general discussion of the panel construction and operation.
As illustrated in Figs. 3 through 6, the saker et aI. device utili~es a pair of dielectric films 31 and 32 separated by a thin layer or volume of a gaseous discharge medium 33. The medium 33 . . . .
produces a copious supply of charges (ions and elec~rons) which are alternately collectable on the surfaces of the dielectrlc members at opposed or facing elemental or discrete areas X and Y defined by the ; electrode matrix on non-gas-contacting sides of the dlelectric members, each dielectric member presenting large open surface areas and a plurality of pairs of elemental X and Y areas. While the electrically operative structural members such as the dielectric members 31 and 32 -and a pair of electrode matrixes 34 and 35 are all relatively thin :: : . ................................. . .
.. . . ' , ' ' .. ' ; ' : . ~.. ': ' ' ': ' .

~722~1 ~being exaggerated in thickness in the drawings); they are formed on and supported by a pair of rigid nonconductive support members 36 and 37 respectively.
Preferably, one or both of the nonconductive support members 36 and 37 pass light produced by discharge in the elemental gas volumes.
Typically, they are transparent glass members and these members essentially define the overall thickness and strength of the panel. For example, the thickness of the gas layer 33 as determined by a spacer 38 is usually under 10 mils for operation in the memory mode, the dielectric layers 31 and 32 (over the electrodes at the elemental or discrete X and Y
areas) are usually between 1 and 2 mils thick, and the electrodes 31 and 32 about ~,000 angstro~s thicko Eowever, the support members 36 and 37 are much thicker (particularly in larger panels) so as to provide as much ruggedness as may be desired to compensate for stresses in the panel. The support members 36 and 37 also serve as heat sinks `~
for heat generated by d~scharges and thus minimize the effect of temperature on operation of the device.
~xcept for being nonconductive or good insulators, the electrical properties of the support members 36 and 37 are not critical.
2~ ~ The main function of the support members 36 and 37 is to provide mechanical support and strength for the entire panel, particularly with respect -to pressure differential acting on the panel and thermal shock. It is noted that they should have thermal expansion characteristics ; substantally matching the thermal expansion characteristics of the dielectric layers 31 and 32. Ordinary 1/4" commerical grade soda lime plate glasses have been used for this purpose. Other glasses such as .. ~ , :,.:: -:
low expansion glasses or transparent devitrified glasses can be used provided they can withstand processing and have expansion characteristics substantially matching expansion characterlstics of the dielectric -: .' .
'': ".

-., ..... . ,. . ...... ., ..... ~ . : ~

. : , . .

~L~;972~

coatings 31 and 32. For given pressure differentials and thickness of plates, the stress and deflection of plates maybe determined by following standard stress and strain formulas (see R.J. Roark, Formulas for Stress and Strain9 McGraw-~lill, 1954).
The spacer 38 may be made of the same glass material as the dielectric films 31 and 32 and may be an integral rib formed on one of the dielectric members and fused to the other members to form a bakeable hermetic seal enclosing and confining the ioni~able gas volume 33. ~owever, a separate final hermetic seal may be effected by a high strength devitrified glass sealant 39. A tubulation 41 is provided for exhausting the space between the dielectric members 31 and 32 and filling that space with the volume of ionizable gas, For large panels, small beadlike solder glass spacers, such as shown at 42, may be located between conductor intersections and ~used to the dielectric members 31 and 32 to aid in withstandlng stress on the panel and maintain uniformity o~ thickness of the gas volume 33.
The electrode arrays 34 and 35 may be formed on the support members 36 and 37 by a number of well-known processes, such as photoetching , ~acuum deposition, stencil screeningS etc. In the panel shown in Fig. 6, the center-to-center spacing of the electrodes in the respective arrays is about 17 mils. Transparent or semi-transparent conductive material ~ such as tin oxide, gold, or aluminum can be used to form the electrode ; arrays and should have a resistance less than 3000 ohms per line.
Narrow opaque electrodes may alternately be used so that discharge light passes around the edges of the electrodes to the viewer. It is important to select an electrode material that is not attacked during processing by the dielectric material.
; It will be appreciated that the elec~rode arrays 34 and 35 may be wires or filaments of copper, gold, silver or aluminum or any "..':
'-' ',"

,~ 19 2Z3~

other conductive metal or material. For example, 1 mil wire filaments are commerically available and may be used in the invention~ However, formed in situ electrode arrays are perferred since they may be more easily and uniformly placed on and adhered to the support plates 36 and 37.
The dielectric layer members 31 and 32 are formed of an inorganic material and are prefereaby formed in situ as an adherent film or coating which is no~ chemically or physically affected during bake-out of the panelO One such material is a solder glass such as Kimble SG~68 - 10 manufactured by and commercially available from the asslgnee of the present invention.
This glass has thermal expansion characteristics substantially matching the thermal expansion characteristics of certain soda-lime glasses, and can be used as the dielectric layer when the support members 36 and 37 are soda-lime glass plates. The dielectric layers 31 and 32 must be smooth and have a dielectric breakdown voltage of about 100Qv. and be electrically homogeneous on a microscopic scale (e.g., no cracks, bubbles, crystalsl dirt, surface films, etc.) .
In addition, the surfaces of the dielectric layers 31 and 32 should be good photoemitters of electrons ~n a baked out condition. Alternatively, the dielectric layers 31 and 32 may be overcoated with materials designed to produce good electron emission, as in U.S. Patent No. 3,634,7193 issued to Roger E. Ernsthausen. Of course, for an optical display at least one of ~he dielectric layers 31 and 32 should pass light generated on discharge and be transparent or translucent and, preferably, both layers are optically transparent.
Ths pre~erred spacing between surfaces of the dielectric films is about 4 to 8 mils with the electrode arrays 34 and 35 having center-', ,' '' ' ' "

23~L

to-center spacing of about 17 mils. The ends of the electrodes 35-1 through 35-4 and the support member 37 extend beyond the enclosed gas volume 33 and are exposed Eor the purpose of making electrical connection to an interface and addressing circuit 43. Likewise, the ends of the electrodes 34-1 through 34-4 on the support member 36 extend beyond the enclosed gas volume 33 and are exposed for the purpose of making electrical connection to interface and addressing circuit 43.
The bistable mode of initiating operation of the panel will be described with reference to Fig. 5, which illustrates the condition of one elemental gas volume 44 having an elemental cross-sectional area and volume which is quite small relative to the entire volume. The area is defined by the overlapping common elemental areas of the electrode arrays and the volume is equal to the product of the distance between - the dielectric surfaces and the elemental area. It is apparent that if the electrode arrays are uniform and lLnear and are orthogonally (at ;~
right angles to each other) related, each of elemental areas X and Y
will be squares and if the electrodes of one electrode array are wider than the electrodes of the other electrode array, said areas will be rectangles. If the electrode arrays are at transverse angles relative to each other, other than 90, the areas will be diamond shaped so that the cross-sectional shape of each volume is determined solely in the first instance by the shape of the common area of overlap between the electrodes in the electrode arrays 3~ and 35. The dotted lines 44~ are imaginary lines to show a boundary of one elemental volume about the center of which each elemental discharge takes place. As described earlier herein, ; it i5 known that the cross-sectional area of the discharge in a gas is affected by, inter alia, the pressure of the gas, such that, if desired, ~; the discharge may even be constricted to within an area smaller than ~ ~ 7 ~ ~Q~

the area of electrode overlap. By utili2ation of this phenomenon, the light production may be confined or resolved substantially to the area of the elemental cross-sectional area defined by the electrode overlap.
Moreover, by operating at such pressure, charges (ions and electrons) produced on discharge are laterally confined so as not materially to affect operation of adjacent elemental discharge volumes.
In the instant shown in Fig. 5, a conditioning discharge about the center of the elemental volume 44 has been initiated by application ~;
to the electrode 34-1 and the electrode 35-1 firing potential Vx~
as derived from a source 45 of variable phase, for exampleg and source 46 of sustaining potential Vs (which may be a sine wave, for example).
The potential Vx~ is added to the sustaining potential Vs as the sustaining potential Vs increases in magnitude to intitate the conditioning discharge about the center of the elemental volume 44 shown in Fig. 4. -~
There, the phase of the source 45 of potential Vx~ has been adjusted into adding relation to ~he alternating voltage from the source 46 of the sustaining voltage Vs to provide a voltage Vf', when a swltch 47 has been closed, to the electrodes 34-1 ancl 35-1 defining the elemental gas volume 44 sufficient (in time and/or magnitude) to produce a light ;~ ;
generating d~scharge centered about the discrete elemental gas volume 44. -:: :
At the instant shown, since electrode 34-1 is at a positive potential, a plurality of electrons 48 have collected on and are moving to an elemental area of the dielectric member 31 substantially corresponding to the area of the elemental gas volume 44 and a plurality of the less mobile positive ions 49 are beginning to collect on the opposed elemental ~; ar~a of the dielectric member 32 since it is at a negative pot~ntial.
.
~ As these charges build up, they constitute a back voltage opposed to ! . ' . ' the voltage applied to the electrodes 34-1 and 35-1 and serve to terminate the discharge in the elemental gas volume 44 for the remainder of a - , . ~ ,. .
half cycle.

':

. . ,- , , . , :

3~L

During the discharge about the center of the elemental gas volume 44, photons are produced which are free to move or pass through the gas medium 33 as indicated by a plurality of arrows 51, to strike or impact remote surface areas of the photoemissive dielectric members 31 and 32, causing such remote areas to release a plurality of electrons ~; 52. The electrons 52 are, in effect~ free electrons in the gas medium 33 and condition other discrete elemental gas volumes for operation at a lower firing potential Vf which is lower in magnitude than the firing potential Vf' for the initial discharge about the center of the elemental volume 44. This voltage is substantially uniform for each other elemental gas volume.
Thus, elimination of the physical obstructions or barriers between discrete elemental volumes permits photons to travel via the space occupied by the gas medium 33 to impact remote surface areas of the dielectric members 31 and 32 and provides a mechanism for supplying free electrons to all elemental gas volumes. These free electrons condition all discrete elemental gas volumes for subsequent discharges~ respectively, at a uniform lower applied potential. While ln Fig. 5 a single elemental volume 44 is shown, it will be appreciated that an entire row (or column) of elemental -~ gas volumes may be maintained in a "fired" condition during normal operation of the device with the light produced thereby being masked ~ ;
or klocked off from the normal viewing area and not used for display purposes. It can be expected that in some applications there will always be at least one elemental volume in a "fired" condition and producing light in a panel, and in such applications it is not necessary to provide separate dlscharge or generation of photons for purposes described earlier.

~ ~ .

. ' '. ~ ' ~ ' . :

~7~

The prlor art has taught that the entire gas volume ~an be conditioned for operation at uniform firing potentials by use of external or internal radiatlon so that there will be no need for a separate source of higher potential for initiating an initial dischargeO Thus, by irradiating the panel with ultraviolet radiation or by inclusion of a radioactive material within the glass materials or gas space, all discharge volumes can be operated at uniform potentials from the addressing and interface circuit 43~
Since each discharge is texminated upon a build up or storage of charges at opposed pairs of elemental areas, the light produced is likewise terminated~ In fact, light production lasts for only a s~all fraction of a half cycle of applied alternating potential and depending on design parameters, is in the microsecond ~
range. - `
~ .
After the inltial firing or discharge of the discrete elemental gas volume 44 by a fir~ng potential Vf', the switch 47 may be opened so that onl~ the sustaining voltage Vs from t~e source 46 is applied to the electrodes 34-1 and 35-1. Due to the storage of the charges (e.g., the memory) at the opposed elemental area X and Y~
the elemental gas volume 44 will discharge again at or near the peak of the negatlve half cycles of the sustaining voltage Vs to again produce a momentary pulse of light. At this time, due to the reversal ; of field dixection, the electxons 4~ will collect on and be stored on the elemental surface area Y of the dielectric member 32 and the positive `` ~ "
ions 49 will collect and be stored on the elemental surface area X
of the dielectric member 31. ~fter a few cycles of the sustaining voltage Vs, the times of discharges become symmetrically located with respect to the wave foxm of the sustaining voltage. At the remote :~
.~ ` . .
.

~7'~3~

elemental volumes, as for example, the elemental volumes defined by the electrode 35-1 with the electrodes 34-2 and 34-3, a uniform -magnitude or potential Vx from a source 53 is selectively added by one or both of a pair of switches 54 or 55 to the sustaining voltage Vs, generated by a voltage source 56, to fire one or both of these elemental discharge volumes. Due to the presence of free electrons produced as a result of the discharge centered about the elemental volume 44, each of these remote discrete elemental volumes has been conditioned for operation at uniform firing potential Vf.
It is apparent that the plates 36 and 37 need not be flat but may be curved, the curvature of facing surfaces of each plate being complementary to each other. While the preferred conductor arrangement is of the crossed grid type as shown herein9 it is likewise apparent that where an infinite variety of two dimensional display patterns --are not necessary, as where specific standarized visual shapes te.g.
numerals, le~ters, words, etc.) are to be formed and image resolution is not critical9 the conductors may be shaped accordingly.
The device shown in Fig. 6 is a panel having a large number o~ elemen~al volumes similar to the elemental volumie ~4 of Fig. 5. In this case more room is provided to make electrical connection to the electrode arrays 34' and 35~, respe~tively, by extending the surfaces of the support members 36' and 37' beyond the seal 39', alternate ~-electrodes being extended on alternate sidesD ~he electrode arrays 34' and 35' as well as the support members 36' and 37' are transparent.
The diélectric coatings are not shown in Fig. 6 but aire likewlse transparent so that the panel may be viewed from either side. The panel can include red, green and blue phosphors associated with .

-~5- i -~: :

.
. . : .

~7;~:23~ :

individual discharge cells as disclosed in U. S. Patent No.
3,878,422 issued to F. H. Brown et al, and U. S. Patent No.
3,909,657 issued to F. H. Brown. The panel can be of monolithic design as disclosed in U. S. Patent No. 3,896,327 issued to J. S. Schermerhorn.
The support members, the dielectric members, and the dielectric coatings on one side or half of the panel may be dark and/or opaque in order to improve the viewing light contrast on the opposite side of the panel. Reference is made to U. S.
P~tent No. 3,686,686 issued to M. S. Hall. b A wide variet~ of gases and gas mixtures have been utilized as the gaseous medium in a gas discharge device. Typical of such yases include CO; CO2; halogens; nitrogen; NH3; oxygen;
water vapor; hydrogen; hydrocarbons; P2O5; boron fluoride; acid fumes; TiCL4; air; H2O2; vapors of sodium, mercury thallium, cadmium, rubiduem, and cesium; carbon disulfide; H2S;
deoxygenated air; phosphorus vapors; C2H2; CH4; naphthalene vapor; anthracene; freon; ethyl alcohol; methoy~ene bromide;
heavy hydrogen; electron attaching gases; surfer hexafluoride;
tritium; radioactive gases; the rare or inert gases; and mixtures thereof.
It is known in the art that the interface and addressing circuit 43 of Fig. 3 may be the relatively inexpens1ve line scan~
systems or the somewhat more expensive high speed random access systems. In either case, it is to be noted that a lower magnitude of operating potentials helps to reduce problems associated with the interface circuitry between the addressing ; system and the display/memory panel. Thus, by providing a panel .i . . .
having a greater uniformity in the discharge characteristics 30 throughout the panel, tolerances and operating characteristics of the panel with which the inter~ace circuitry cooperates, are made less rigid.

' "' ' .. .: : , . ., : . . .
: . . . . : . : .

~7;~Z31 The interface and addressing circuit 43 of Fig. 3 is represented schematically in Fig. 7 as a circuit for driving a single column electrode 34-1 and a single row electrode 35-4 whose intersection defines a single cell or discharge site. The electrodes are connected to a diode-resistor matrix for selecting individual column electrodes and individual row electrodes to write and erase selected cells. A pair of sustainer voltage sources are connected between the electrode arrays and the circuit ground potential to supply the sustainer voltage to the cell.
A row sustainer voltage source 61 is connected to the row electrode 35-4 and all other row electrodes (not shown) through a plurality oE diodes such as a feed through diode 62 haing an anode connected to the voltage source 61 and a cathode connected to the electrode 35-4. A column sustainer voltage source 63 is connected to the column electrode 34-1 and all other column electrodes (not sho~m) ~ through ~ plurality of diodes such as a feed through diode 64 having `` a cathode connected to the voltage source 63 and an anode connected to the electrode 34-1.
A plurality o~ pulser voltage ~enerators are utilized to address ~he indiv1dual electrodes. A row diode pulser P(RD) 65 and a row resistor pulser P(RR) 66 are connected in parallel with the diode 62 between the row sustainer voltage source 61 and the row electrode 35-4. A row diode 67 has an anode connected to the electrode 35-4 and a cathode connected to the pulser 65. A row resistor 68 is connected between the pulser 66 and the electrode 35-4. The pulser-diode-resistor circuit ~or the column electrode 34-1 is similar. A
column diode pulser P(CDI 69 and a column resistor pulser P(CR) 71 are connected in parallel with the diode 64 between the column sustainer ~ ~
~ ' ,~

, :
. .. ... . : ..... .. . . .. : . . . :: :
.. .. : j : :: :- ,; .: .:,,,: .,. . , : . .

-~72'~3~

voltage source 63 and the column electrode 34-1. A column diode 72 has an anode connected to the pulser 69 and a cathode connected to the electrode 34-1. A column resistor 73 is connected between the pulser 71 and the electrode 34-1. Since the pulsers are connected in series with the sustainer voltage sources between the electrodes and a ground connection 7~, the pulser voltage wave forms will float on the sustainer voltage wave forms and will be referenced from the composite sustainer wave form Vs of Figs. 1 and 2.
There is also shown in Fig. 7 a pair of pulsers, a row keyer pulser 75 P(RK) common to all row electrodes and a column keyer pulser 76 P(CK) common to all column electrodes. The row keyer pulser 75 is connected in series with a resistor 77 between the ground connection 74 and the row diode pulser 65. The column keyer pulser 76 is connected in series with a resistor 78 between the ground connection 74 and the column diode pulser 69. The row keyer pulser 75 is connected through a plurality o~ resistors to the row diode pulsers for each of the other row electrodes and the column keyer pulser 76 is connected ` in a similar manner to all of the other column electrodes.
; The sustainer voltage sources 61 and 63 generate voltages which are 180 out of phase so that each source need supply only one half of the sustainer voltage Vs required to sustain discharges at a selected cell. The voltage sources 61 and 63 continuously generate the Vs/2 and ~s (180)/2 voltages to the row and column electrodes.
These voltages are periodic and can be for example sinusoidal, trapezo~idal~
2S square wave ( as shown in Figs. 1 and 2) or triangular. The sustainer ; wave forms can also be asymmetric as disclosed in U.S. Patent No.
; 3,840,779 issued to Jerry D. Schermerhorn on October 8, 1974. The sustainer voltage is passed through the diode pulsers 65 and 69 such '. ':.' ~72~3~

that the diodes 62 and 64 provide a current path for one polarity of the sustainer voltage and the diodes 67 and 72 provide a current path for the other polarity of the susta:Lner voltage such that the sustainer voltage is applied across the cell.
S As disclosed in the previously referenced U.S. Patent No.
39727,102, the pulsers 65, 66, 69 and 71 are utilized to generate the write and erase pulses for turning on and off respectively the cell defined at the intersection of the electrodes 3~-1 and 35-~
If the sustaining voltage source 61 is generating a positive polarity wave form with respect to the circuit ground potential and the source 63 is generating a negative potential wave form, the charging current for the cell is flowing through the diodes 62 and 64. The pulsers 65 and 66 generate a negative polarity wave form with respect to the circuit ground potential and the pulsers 69 and 71 generate a positive polarity wave form to generate an erase pulse which has a polarity opposite that of the sustaining voltage. If the sources 61 and 63 are generating negative and positive polarity wave forms respectively, then the pulse generated by the pulsers will be a write pulse since it has the same polarity as the sustaining voltage.
~: 20 The natural capacitance ~f ~he discharge cells tends to ;
soften the leading edge of the write and erase pulses. This effect is undesirable where a relatively rapid succession of writing and erasing operations must be performed. Therefore, the row keyer pulser 75 -and the column keyer pulser 76 were added to the resistor-diode matrix to improve the rise time of the leading edge of the write and erase pulses. These pulsers are relatively high voltage, high current circuits ; and therefore tend to be more expensive than the standard pulsers ;~
previously described~ Thus, they are connected in parallel to all the row electrodes and column electrodes so that only one pair is required~
': . ~: "

.. : . . ' : ~ , ' ' . .:: ': . .
. . : , , .:. : . , . ., . , . : : .

~7~:3~

- Where the panel includes a relatively large number of electrodes, more than one pair of keyer pulsers may be required with each one -connected to a separate group of electrodes. The keyer pulsers are turned on at the same time that the other pulsers are turned on to generate the steeply rising leading edge shown in the write pulse of Fig. 1. The keyer pulsers are then turned off and when the other pulsers are turned off, the cell rapidly discharges through the diodes to generate the steeply falling trailing edge of the write and erase pulses.
10Where a Group IIA oxide gas has been utilized as the gaseous medium contacting surface to lower the operating potentials required, it has been found that the steeply rising leading edge of the write pulse of Fig. 1 generates "crosstalk"~ That is, the write pulse not only turns on the selected cell, but also -frequently turns on one or more adjacent cellsr In accordance with the present invention, the keyer pulsers 75 and 76 are turned off during the generation of the write pulses but not during the generation of the erase pulses. Such operations of the inter-face and addressing circuit 43 and the capacitance of the ~elected cell generate a slow rise time write pulse as shown in ; Fig. 2. The slow rise time write pulse reduces crosstalk and rasults in improved operation of the panel.
The operation of the panel can be further improved by increasing the duration of the write pulse thereby decreasing the slope of the leadlng edge. Thus, there has previously been proposed a method and apparatus for altering the substainer voltage wave form during addressing to provide longer intervals for the transfer of addressed cells between an "on state" and an "off state" of dischargeO Sustainer wave forms allow more time for 30 "turn on" and "turn of" partial select signals to be effective - ~
~ .

_ 30 _ - ~
.

i ~ .
., , ~ .

~L~7~3~L

by e~tending the sustainer wave form pedestals on which the partial selects are imposed. These sustainer alternations can be performed by extending the sustainer periods in which addressing is per~ormed or by maintaining the sustainer periods and shortening those portions of the period which are not utili~ed for addressing as by employlng only a "write'l pedestal or only an "erase" pedestal. This latter technique is illustrated in Figo 8 which shows a shortened non-addressing erase pedestal and an increased duration slow rlse time write pulse superimposed on a lengthened write pedestal.
Fig~ 9 shows the window data for a typical gaseous discharge panel plotted as write and erase pulse voltage Vp against sustainer voltage Vs. A first hyperbolic-like curve 81 defines the range of pulse voltages versus sustainer voltages for writlng the cells in the panel. The area to the left of the curve represents the combinations of write pulse voltage and sustainer voltage for which at least one cell in the panel will fail to write (not turn on) while the area ~o the right of the curve represents combinations for which all cells will write. If a combinat~on falls in the area to the lower left of the curve 819 the magnitude of the write pulse for a given sustainer voltage is insufficient to initiate a discharge ln one or more of the cell~0 Therefore, the magnitude of the write pulse voltage must be . .
increased to generate a comblnation to the right of the fail to write curve 81. ~f the combination falls in the area to the upper left of the curve 81, the magnitude of the write pulse ~or a given sustainer voltage is sufficient to turn on one or more cells so hard that the wall charge which is fo~led is unstable and the cell turns itself off.
Therefore, the magnitude of the write pulse voltage must be decreased to generate a combination to the right of the fail to write curve ~1.
''' '"

~ - . , ............ : :

~7~23~

A second hyperbolic-like curve 82 defines the range of pulse voltages versus sustainer voltages for erasing the cells in the panel.
The area to the right of the curve represents the combinations of erase pulse v~ltage and sustainer voltage for which at least one cell in the panel will fail to erase (not turn off) while the area to the curve represents combinations for which all the cells will erase. If a combination falls in the area to the lower right of the curve 82, the magnitude of the erase pulse for a given sustainer voltage is insufficient to discharge the wall charge to turn off one or more of the cells. Therefore, the magnitude of the erase pulse must be increased - to generate a combination to the left of the fail to erase curve 820 If a combination falls in the area to the upper right of the curve 82, the magnitude of the erase pulse for a given sustainer voltage is ~ sufficient not only to discharge the wall charge but develop an opposite -- 15 wall charge to maintain one or more cells in the on state. Therefore, the magnitude of the erase pulse must be decreased to generate a combination to the left of the fail to erase curve 82.
Also shown in Fig. 9 is a partial select erase line 83 and -a partial select wrlte line 84. The partial select erase line 83 defines combinations of a partial select erase pulse and a sustainer voltage which will turn off at leas~ one cell in the panel to ~;
which only the one partial select erase pulse has been applied.
Similarly, the partial select wri~e line 84 defines combina~ions of a partial select write pulse and a sustainer voltage which will ~urn on at least one cell in the panel to which only the one partlal . . .
select write pulse has been applied. A maximum pulse voltage line 85 defines the upper voltage limit of the electronlcs which generate the write and erase pulses. The reIative positions of the curves 81 ., ' 3~

and 82 and the lines 83, 84 and 85 form a window which contains all the permissible com~inations of pulse voltage and sustainer voltage which will operate all the cells of the panel. The maximum vertical and horizontal dimensions of the window are an indication of the tolerance of the panel to variations from the desired optimum operating - pulse and sustainer voltages.
As shown in Fig. 9 for a typical panel, the maximum vertical dimension Vp~ is defined by the maximum pulse voltage line 85 and the intersection of the fail to write curve 81 and the fail to erase curve 82. The maximum horizontal dimension Vs~ is defined by the fail to erase curve 82 and the intersection of the fail to write curve 81 and the partial select erase line 83. It is desirable to have a relatively large window so that less expensive, wider tolerance electronics can be utilized to generate the pulse and sustainer voltages.
However, the useful window is reduced by crosstalk shown as a line 86.
When the write pulse of Fig. 1 is used, only that portion of the window to the left of the line 86 can be utilized without generating crosstalk in cells adjacent to the selected cell.
When the slow rise time write pulse of ~ig. 8 is used however, the cross~alk line 86 is shif~ed to the right as shown in Fig. 9 by a dashed line 86'. This shift increases the size of the useful portion of the ~indow. The slow rise time pulse also generates an additional benefit. The upper portion of the write curve 81 is modified to be more nearly vertical (shown as dashed line 81') and the curve is shifted to the left to increase the size of the window. The partial select write line 8~ is also shifted to the left but does not enter into the definltion of the boundaries of the window unless it crosses ~-the fail to erase curve 82. In a test of seven panels having a MgO
' ~, .: '.

.

~7;~:Z3~L

gaseous medium contacting surface, the Vs' dimension was increased an average of 33% and the Vp' dimension was increased an average of 62%.
The interface and addressing circuit 43 includes a sustalner voltage source control means 91~ a keyer pulsers control means 92, a diode and resistor pulser control means 93 and an addressing means -94 shown in Fig. 7. The sustainer control means 92 enables the sustainer voltage sources 61 and 63 to apply the sustainer voltage to all of the cells in the panel. The addressing means 94 receives information from an external source which can be for example, a computer, a tape reader or keyboard. The addressing means 94 then determines which - cells are to be written or erased and sends control signals to the ~; keyer pulser control means 92 and the diode and resistor pulser control means 93. If the cell defined by the crossing of the electrodes 34 and 35-4 is to be turned on, the control means 92 and 93 sense the timing of the sus~ainer control means for generating a write pulse. The control means 92 turns off the keyer pulsers 75 and 76 and the control means 93 turns on the pulsers 65, 66, 69 and 71. If the cell is to be turned off, the control means 92 turns on the keyer pulsers and the ;
control means 93 turns on the resistor and diode pulsers to genera~e an `
erase pulse.
~` In summary, the present invention concerns a method and apparatus for generating a write pulse having a relatively slow rise time leading edge. The write pulse is applled to a multicelled gas discharge dlsplay memory device having a dielectric charge storage member formed from a low operating voltage material for improved operation of the device.
The device includes a pair of opposed electrode arrays with proximate electrode portions of at least one electrode in each .
~' 1, , ,, , ., . , , ,, . ., ' ' 3~

array defining the cells. An ionizable gas volume is contained between the spaced electrode arrays and a dielectric charge storage member in contact with the gas insulates at least one electrode portion of each cell from the gas. The dielectric charge storage member is formed from a low operating voltage material such as an oxide of a Group IIA element.
A sustainer voltage source is connected across each cell to impose an alternating voltage having a period. During a period the susta~ner wave form has a first voltage of a first polarity and a second voltage of a second polarity with a magnitude and duration ; sufficient to maintain a discharge in any ce]l which is in the "on state".
Also included is pulser means for generating write and erase voltage pulses to manipulate the discharge state of individual cells between the "on state" and an "off state"~ -The write pulse has a relatively slow rise time leading edge and the erase pulse has a relatively fast rise time leading edge. The sustainer voltage source generates a third sustainer voltage of the first polarity between the first and second voltages of the same period having a magnitude and duration, when added to the write pulse~ sufficient to turn any cell in the "off state" to the "on state".
Typically, the duration of the first sustainer voltage i9 greater than ~he dura~ion of the third sustainer voltage and the duration of the leading edge of the write pulse approaches the duration of the third sustainer voltage. The sustainer source also generates a fourth sustainer voltage of the second polarity between the second and first voltages of succeeding periods having a magnitude and duration, when added to the erase voltage pulse, sufficient to turn -~
any cell in the "on state" to the "off state".

35_ .

. . ..... .... . .. . . .. . .. . . .

~L~7Z;~:3~ ~
.~ ,. . .
A keyer pulser means is connected to the pulser means. An interface and addressing circuit controls the operation o~ the sustainer voltage source, the pulser means and the keyer pulser means. When an addressing means determines that a cell is to be written, it sends control signals to a keyer pulser control means and a diode and resistor pulser control means. The control means sense the timing of a sustainer voltage source control means for generating a write pulse during the generation of the same polarity sustainer voltage~
The keyer pulser means is turned off and the diode and resistor pulser ;~
means is turned on to generate the write pulse with a relatively slow rise time leading edge across a selected cell. When the addressing -means determines that a cell is to be erased, it sends control signals to the control means for generating an erase pulse during the generation of the opposite polarity sustainer voltage. The keyer pulser means and the diode and resistor pulser means are turned on to generate the erase pulse with a relatively fast rise time leading edge across a selected cell.
Therefore, the method of the present invention concerns manipulating the discharge state of individual cells of a gas discharge 2~ display memory device. A periodic alternating polarity sustainer voltage is applied to a cell having a magnitude and duration sufficent to maintain a discharge if the cell is in the "on state". If the cell is in the "off state", it can be turned to the "on state" by turning on a pulser means connected across the cell and turning o~f a keyer pulser means connected across the cell to generate a write pulse having a relat~vely slow rise time leading edge. If the cell is in the "on state", it can be turned to the "off state" by turning on the -~
pulser means and the keyer pulser means ~o generate an erase pulse having a relatively fast rise time leading edge.
"" ' ,. ':

. ~',.

. .

lL~72;~3~

The sustainer wave form can be altered to allow more time for the i'turn on" partial select signal by extending the write pedestal.
This may be accomplished by extending the sustainer perlods or by maintaining the sustainer periods and lengthening the write pedestal while shortening the erase pedestal. Thus the duration of the third ~ -sustainer voltage is increased as can be the duration of the leading edge of the write voltage pulse while the duration of the fourth sustainer voltage is decreased~
The slow rise time leading edge write pulses tend to decrease or eliminate crosstalk in the device. However, if integrated circuits are utilized in the address circuitry, the write pulse will have a relatively fast rise time unless the circuits are specifically redesigned for a slow rise time. Since redesigning would significantly reduce the usefullness of the integrated circuit, a sloped pedestal is generated to modify the relatively East r~se time write pulse into a relatlvely slow rise time pulse at the magnitude required ~o turn on a cell. The wave form is shown in Fig. 10 and will be discussed ~ ;
in connection with the clrcuit of Fig. 11.
An alternate embodiment of the interface and addressing circuit of Fig. 7 is shown in Fig. 11 as a circuit 100 for driving a single column electrode 101 and a single row electrode 102 similar ,, ~. .: .
to the electrodes 34-1 and 35-1 respectively of Fig. 7; whose intersection defines a single cell or discharge site. The electrode are connected to a diode-resistor matrix for selecting individual colu~n electrodes and individual row electrodes to write and erase selected cells.
pair of sustainer voltage sources are connected between the electrode ~ -arrays and the circuit ground potential to supply the sustainer ~` -~` voltage to the cell.

~37~
'.'' ~

.. : . . : . : - ~ . .. :: . .:, : . .. : . .

~C}7ZZ3~

A row sustainer voltage sou~ce 103 ~s connected to the row ~.
electrode 102 and all other row electrodes (not shown) through a plurality of diodes such as a feed through diode 104 having an anode connected to the voltage source 103 and a cathode connected to the electrode 102. A column sustainer voltage source 105 is connected to the column electrode 101 and all other column electrodes (not shown) through a plurality of diodes such as a feed through diode 106 having a cathode connected to the voltage source 105 and an anode connected to the electrode 101.
A plurality of pulser voltage generators are utilized to address the individual electrodes. A row diode pulser P(RD) 107 and a row resistor pulser P(PR) 108 are connected in parallel with the ; diode 104 between the row sustainer voltage source 103 and the row electrode 102. A row diode 109 has an anode connected to the electrode 102 and a cathode connected to the pulser 107. A row resistor 111 :.
is connected between the pulser 108 and the electrode 102. The pulser-diode-resistor circuit for the column electrode 101 is similar. A
column diode pulser P(CD) 112 and a column resistor pulser P~DR) 113 are co~nec~ed in parallel with the diode 106 between the column sustainer voltage source 105 and the column electrode 101. ~ column diode 114 has an anode connected to the pulser 112 and a cathode connected to the electrode 101. A column resistor 115 is connected between the ~ -pulser 113 and the electrode 101. Since the pulsers are connected in ~:
; series with the sustainer voltage sources between the electrodes and : 25 a ground connection 116, the pulser wave forms will float on the sustainer wave forms and will be referenced from the composite sustainer . ;: wave form Vs of Figs. 1 and 10.

~ ~ ' : :
. .' : , '.. ': ' .

,. . . . . .
.
, . . .

~7ZZ31 The sustainer voltage sources 103 and 105 generate voltages which are 180 out of phase so that each source need supply only one half of the sustainer voltage Vs required to sustain discharges at a selected cell. The sustainer voltage is passed through the diode pulsers 107 and 112 such that the diodes 104 and 106 provide a current path for one polarity of the sustainer voltage and the diodes 109 and 114 provide a current path for the other polarity of the sustainer voltage such that the sustainer voltage is applied across the cell.
The interface and addressing circuit 100 includes a sustainer voltage source control means 117, a diode and resistor pulser control means 118 and an addressing means 119 shown in Figo 11. The sustainer control means 117 enables the sustainer voltage sources 103 and 105 to apply the sustainer voltage to all of the cells in the panel. The addressing means 119 receives information from an external source which can be, for example, a computer~ a tape reader or a keyboard. ~ ;
The addressing means 11~ then determines which cells are to be written ~
or erased and sends control signals to the sustainer voltage source -control means 117 and the diode and resistor pulser control means 118.
If the cell defined by the crossing of the electrodes 101 and 102 ~-~`: 20 is to be turned on, the control means 118 senses the timing of the ..... :,:
sustainer control means for genera~ing a write pulse. The control means 117 generates a sloped pedestal and the control means 118 turns ~-on the pulsers 107, 108, 112 and 113. If the cell is to be turned off, the con~rol means 117 generates a zero slope pedestal and the ; -control means 118 turns on the resistor and diode pulsers to generate - ;an erase pulse. ;~-There is shown in Fig. 7 an interface and addressing circuit 43 including a pair of keyer pulsers means 75 and 76. Where the pulsers -~

,: '.~:- -''-39- ~

. ~ ', ' - .

, .. , , , . , , ., , , ~ , ~L~7Z~3~ ::

65, 66, 69 and 71 have circuits formed from discrete components, the natural capacitance of the discharge cells and circultry tends to soften the leading edge of the write and erase pulses. This effect is undersirable where a relatively rapid succession of writing and erasing operations must be performed. Therefore9 the row keyer pulser 75 and the column keyer pulser 76 were added to the resistor-dlode matrix to improve the rise time of the leading edge of ~he write and erase pulses. These pulsers are relatively high voltage, high current circuits and therefore tend to be ~ore expensive than the standard pulsers previously described. Thus, they are connected in parallel to all the row electrodes and column electrodes so that only one pair is required. Where the panel includes a relatively large number of electrodes, more than one pair of keyer pulsers -may be required with each one connected to a separate group of electrodes.
The keyer pulsers are turned on at the same time that the other pulers are turned on to generate the steeply rising leading edge shown in the write pulse o~ F~g. 1. The keyer pulsers are then turned off ~
and when the other pulsers are turned ofE, the cell rapidly ~`
discharges through the dlodes to generate the steeply falling trailing edge of the write and erase pulses.
Subsequently, higher voltage, higher power integrated circuits were manufactured which made it possible to economically ~ replace the discrete components in the pulsers with "chips". It `- was soon discovered that the keyer pulsers were no longer required to form the steeply rising leading edges on the write and erase pulses since they were a function of the operating characteristics of the lntegrated circuits. Specifically, the low output impedance reduced the charging time constant for the cell. Therefore, Fig. 11 of the '; ' 7'~;23~

present application represents an interface and addressing circuit 100 having pulsers including integrated circuits for generating the write pulse shown in Fig. 1.
Where a Group IIA oxide has been utili~ed as the gaseous medium contacting surface to lower the operating potentials required, it has been found that the steeply rising leading edge of the write pulse of Fig. 1 generates "crosstalk". That is the write pulse not only turns on the selected cell, but also frequently turns on one or more adjacent cells. Although the mechanism which produces the phenomenon is not fully understood, it is believed that there is a tendency for a steeply rising leading edge write pulse to generate a large amount of wall charge which is transferred to ad~acent cells.
Even through the inte~rated circuits could be redesigned to generate ~
a slow rise time write pulse, to do so would drastically limit the ~ -usefullness and flexibility of the circuit. In accordance with the alternate embodiment of the present invention, the control means 117 ~ -and the voltage sources 103 and 105 generate a sloped pedestal during the generation of the fast rise ~ime write pulse but not during the generation of the erase pulses. Such operations of the interface and addressing circuit 100 generate a relatively slow rise time portion of the wrlte pulse as shown in Fig. 10. This slow rise time ~;
portion reduces crosstalk and results in improved operation of the panel.
The operation of the panel can be further improved by increasing the duration of the write pulse and the sloped pedestal thereby decreasing the slope of the slow rise time portion. Sustainer wave forms allow more time for "turn on" and "turn off" partial select signals to be effective by extending the sustainer wave form pedestals ','' : . . .

.
. .
- , ,. ~ , . . . .

~L~7'~23~L

on which the partial selects are imposed. These sustainer alternations can be performed by extending the sustainer periods in which addressing is performed or by maintaining the sustainer periods and shortening those portions of the period which are not utilized for addressing as by employing only a "write" pedestal or only an "erase"
pedestal. This latter technique is illustrated in Fig. 12 which shows a shortened non-addressing portion and an increased duration slow rise time portion write pulse.
When the slow rise time portion write pulse o~ Fig. 12 is used~ the ~'crosstalk~ line 86 is shifted to the right as shown in Fig. 9 by a dashed line 86~. This shift increases the size of the ~ -useful portion of the window. The slow rise time portion pulse also generates an additlonal benefit. The upper portion of the write curve 81 is modified to be more nearly vertical (shown as dashed ; 15 line 81') and the curve is shifted to the left to increase the size of the window. The partial select write line 84 is also shifted to the left but does not enter into the definition of the boundaries of the window unless it crosses the fail to erase curve 82. In a test of seven panels having a MgO gaseous medium contacting sur~ace, the Vs~ dimension was increased an average of 33% and the Vp~ dimenslon was increased an average of 62~.
There is shown in Figs. 13 and 149 two alternate embodiments of the pulser circuits for driving the single column electrode 101 and the single row electrode 102 of Fig. 11. In Fig. 13, the resistors 111 and 115 associated with the row resistor pulser P(RR) 108 and the column resistor pulser P(CR) 113 respectively have been eliminated.
In Fig. 14, the diodes 104 and 106 and the diodes 109 and 114 associated with the row diode pulser P(RD) 107 and the column diode pulser .

~7223~

P(CD) 112 respectively have also been eliminated along with the diode pulsers.
~- In a typical multicell display panel, the resistor pulsers and the diode pulsers are connected to resistors and diodes associatsd wqth a plurality of electrodes. For example, in Fig. 11 the row ; resistor pulser P(RR) 108 may be connected to several electrodes through resistors similar to the resistor 111. Each of those electrodes is also connected through a diode to a separate diode pulser similar to the row diode pulser P(RD) 107. These diode pulsers form a diode switch matrix for multiplexing write and erase pulses onto the selected electrodes. If the row resistor pulser P(RR) 103 is turned on, a pulse voltage is applied to all ~he resistors connected thereto.
The diode pulsers ~or all the electrodes which are not selected , are turned on to provide a current path back to the resistor pulser. If the electrode 102 is one of those not selected, the row diode -pulser P(RD) 107 is turned on to provide a current path back to the row resistor pulser P(RR) 108 through the resistor 111 and and the diode 109. Therefore, the pulse voltage is dissipated across the resistor 111 and does not reach the electrode 102. ;
If the electrode 102 is the selected electrode, the row diode pulser P(RD) 107 is not turned on. The pulse voltage is blocked from returning through the pulser 107 and i9 applied to the electrode 102. If the electrode 101 is also selected, the pulse ;~
' : ,.... .
voltage is applied across the discharge cell as a write or erase pulse.
Where integrated circuits are utilized, the resistors ;
may be eliminated as shown in Fig. 13. Each of the row and column . . " . .
electrodes are connected to separate "resistor" pulsers. The diode pulsers are still connected to a plurality of electrodes. A pulser --~3-. ,.. i :,. , : ~ .

~7~

control 121 turns on one of the row pulsers associated with each of the diode pulsers~ The diode pulsers connected with the unselected electrodes are turned on and the diode pulser connected to the selected electrode is turned off. For example, if a row pulser P(R) 122 is turned on and a row diode pulser P(RD) 123 is turned off, a pulse voltage is applied to an electrode 124. If a column pulser P(C) 125 is turned on and a column diode pulser P(CD) 126 is turned off, a pulse voltage is applied to an electrode 127 and across the discharge cell defined by the electrodes 124 and 127.
Fig. 14 shows a circuit wherein each electrode has an associated "resistor" pulser which is separately actuated by a pulser control 131. Therefore, the diodes and diode pulsers shown in Figs. 11 and 13 can be eliminated. A row pulser P(R) 132 is connected to a Y axis electrode 133 and a column pulser P(C3 134 is connected to a X axis electrode 135. I~ both pulsers are turned on, a pulse .~ , . .
voltage is applied across the discharge cell defined by the electrodes 133 and 135.
~; In summary, the alternate embodiment of the present invention concerns a method and apparatus for generating a write voltage ` 20 pulse having a relatively fast rise time leading edge ~ollowed by a relatively slow rise time portion. The write pulse is applied to a multicelled gas discharge display/memory device having a dielectric charge storage member formed from a low operating voltage material for improved operation of the device.
25 ~ The device includes a pair of opposed electrode arrays with proximate electrode portions of at least one electrode ln each :~ .

~ ~44-.~ .

1~72~3~ ~
array defining the cells. An ionizable gas volume is contained between the spaced electrode arrays and a dielectric charge storage member in contact with the gas insulates at least one electrode portion of each cell from the gas. The dielectric charge storage member is formed from a low operating voltage material such as an oxide of a Group IIA element.
A sustainer voltage source is connected across each cell to impose an alternating voltage having a period. During a period, the sustainer wave form has a first voltage of a first polarity with a magnitude and duration sufficient to maintain a discharge in ` any cell which is in the "on state". Also included is a pulser -- ;~
means for genarating write and erase voltage pulses to manipulate the discharge state of individual cells between the ~on state" and ~ ~`
an "off state".
; 15 Both the write and erase pu3ses have a generally square wave shape with relatively fast rise time leading and trailing edges due to ~he integrated circuits utilized in the interface and addressing ~` circuit. The sustainer voltage source generates a third sustainer ~' voltage of the first polarity between the first and second voltages ~1 20 of the same period having a magnitude and duration9 when added to ` the write pulse, sufficient to turn any cell in the "off sta~e7' to -the "on state". This third voltage has a lower magnitude than the first vol~age and a sawtoo~h wave form to define a sloped pedestal upon whlch the write pulse is superimposed. The sloped pedestal generates a relatively slow rlse time portion of the write pulse for improved addressing of the cell~ The sustainer source also ~ -generates a fourth sustainer voltage of the second polarity bet~een the second and first voltages of succeeding periods having a zero " . ' .

~:972;~3~

slope portion of a magnitude and duration5 when added to the erase voltage pulse, sufficient to turn any cell in the "on state" to the "off state".
Therefore, the method of the present invention concerns ~anipulating the discharge state of individual cells of a gas discharge display memory device. A periodic alternating polarity sustainer voltage is applied to a cell having a magnitude and duration sufficient to maintian a discharge if the cell is in the "on state".
If the cell is in the "off state"9 it can be turned to the "on state"
by superimposing a generally square wave write voltage pulse on a sloped pedestal of the sustainer voltage to generate a write pulse having a relatively slow rise time portion. If the cell is in the "on state", it can be turned to the "off state" by superimposing an erase pulse having a relatively fast rise time leading edge on a ~ero slope pedestal of the sustainer voltage.
In accordance with the provislons of the patent statutes, the principle and mode of operation of the present invention has been explained and what are considered to be its best embodi~ents have been illustrated and described. However9 it is to be understood that ~; 20 the invention may be practiced otherwise than as specifically illustrated and described wlthout departing from its spirit or scope.
.

, ~' ' ' .

-46- ~
.. :
' '"' ~ ~'''''' ''.

.

Claims (21)

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. A method of manipulating the discharge state of individual cells of a gas discharge display/memory device which comprises:
applying a periodic alternating polarity sustainer voltage to the cells having a magnitude and duration sufficient to maintain a discharge in any cell which is in the "on state";
turning a cell in the "off state" to the "on state" by applying a write pulse having a relatively slow rise time portion; and turning a cell in the "on state" to the "off state" by applying an erase pulse having a relatively fast rise time leading edge.

2. A method according to claim 1 wherein said relatively slow rise time portion is the leading edge of said write pulse.

3. A method according to claim 2 wherein said step of turning a cell to the "on state" is performed by turning on a pulser means connected across said cell.

4. A method according to claim 2 wherein said step of turning a cell to the "off state" is performed by turning on a pulser means and a keyer pulser means connected across said cell.

5. A method according to claim 1 wherein said write pulse has a relatively fast rise time leading edge followed by said relatively slow rise time portion.

6. A method according to claim 5 wherein said step of turning a cell to the "on state" is performed by generating said sustainer voltage with a sloped pedestal, generating said write voltage pulse with a square wave form and superimposing said write voltage pulse on said sloped pedestal to generate said relatively slow rise time portion of said write voltage pulse.

7. A method according to claim 6 wherein the step of turning a cell to the "off state" is performed by generating said sustainer voltage with a zero slope pedestal, generating said erase voltage pulse with a square wave form and superimposing said erase voltage pulse on said zero slope pedestal to generate said relatively fast rise time leading edge of said erase voltage pulse.

8. In an operating system for a multicelled gas discharge display/memory device, the device including a pair of opposed electrode arrays with proximate electrode portions of at least one electrode in each array defining the cells; an ionizable gas volume between the spaced electrode portions of each cell; a dielectric charge storage member in contact with the gas insulating at least one electrode portion of each cell from the gas; a sustainer voltage source connected across each cell to cyclically impose an alternating voltage having a period; pulser means for generating write and erase voltage pulses to manipulate the discharge state of individual cells between an "on state" and an "off state", the improvement comprising: said dielectric charge storage member formed from a low operating voltage material and means for generating said write voltage pulses with a relatively slow rise time portion whereby crosstalk between adjacent cells is reduced.

9. A system according to claim 8 wherein said low operating voltage material is an oxide selected from the oxides of Group IIA
elements.

10. A system according to claim 9 wherein said low operating voltage material is magnesium oxide.

11. A system according to claim 8 wherein said device includes keyer pulser means for generating a steeply rising leading edge on said write and erase voltage pulses and wherein said means for generating said write voltage pulses includes means for turning off said keyer pulser means during the generation of said write voltage pulses to form a relatively slow rise time leading edge on said write voltage pulses.

12. A system according to claim 11 including capacitor means connected to the junction between said pulser means and said spaced electrode portions.

13. A system according to claim 11 wherein said sustainer voltage source generates a first sustainer voltage of a first polarity and a second sustainer voltage of a second polarity having a magnitude and duration during each sustainer period sufficient to maintain a discharge in any cell which is in the "on state" and generates a third sustainer voltage of said first polarity between said first and second voltages of the same period having a magnitude and duration, when added to said write voltage pulse, sufficient to turn any cell in the "off state" to the "on state".

14. A system according to claim 13 wherein said sustainer voltage source generates a fourth sustainer voltage of said second polarity between said second and first voltages of succeeding periods having a magnitude and duration, when added to said erase voltage pulse, sufficient to turn any cell in the "on state" to the "off state".

15. A system according to claim 14 wherein the duration of said fourth sustainer voltage is less than the duration of said third sustainer voltage.

16. A system according to claim 15 wherein the duration of the leading edge of said write voltage pulse approaches the duration of said third sustainer voltage.

17. A system according to claim 8 wherein said means for generating said write voltage pulses include said pulser means having means for generating said write voltage pulses with relatively fast rise time leading edges, said sustainer voltage source generating a sloped pedestal portion of said alternating sustainer voltage and control means for enabling said pulser means to superimpose said relatively fast rise time leading edge write voltage pulse on said sloped pedestal portion of said alternating sustainer voltage to generate said write voltage pulse with said relatively slow rise time portion.

13. A system according to claim 17 wherein said sustainer voltage source generates a first sustainer voltage of a first polarity and a second sustainer voltage of a second polarity having a magnitude and duration during each sustainer period sufficient to maintain a discharge in any cell which is in the "on state" and generates a third sustainer voltage of said first polarity between said first and second voltages of the same period having a sloped portion with a magnitude and duration, when added to said write voltage pulse, sufficient to turn any cell in the "off state" to the "on state".

19. A system according to claim 18 wherein said sustainer voltage source generates a fourth sustainer voltage of said second polarity between said second and first voltages of succeeding periods having a magnitude and duration, when added to said erase voltage pulse, sufficient to turn any cell in the "on state"
to the "off state".

20. A system according to claim is wherein the duration of said fourth sustainer voltage is less than the duration of said third sustainer voltage.

21. A system according to claim 20 wherein the duration of said write voltage pulse approaches the duration of said third sustainer voltage.