CA1068795A

CA1068795A - Offset adjustment circuit

Info

Publication number: CA1068795A
Application number: CA245,377A
Authority: CA
Inventors: Ronald W. Russell
Original assignee: National Semiconductor Corp
Current assignee: National Semiconductor Corp
Priority date: 1975-02-12
Filing date: 1976-02-10
Publication date: 1979-12-25

Abstract

Application for Patent of Ronald W. Russell for OFFSET ADJUSTMENT CIRCUIT
ABSTRACT OF THE DISCLOSURE
An offset adjustment circuit for a differential am-plifier includes a current source connected in series with a resistor for establishing a biasing voltage for a pair of field effect transistors (FET) having variable resistors in their biasing circuits. These FET's are connected to intro-duce currents respective connections between an input stage and a second stage of the differential amplifier. The dif-ference of the currents supplied by the FET's divided by the transconductance of the input stage of the differential amplifier corresponds to an offset which remains fixed with changes in temperature. The offset introduced by the FET's, as determined by the adjusted values of the resistors in their biasing circuits, may be in opposition to the offset of the differential amplifier to either reduce it partially or com-pletely, or it may be additive to the offset of the differ-ential amplifier, as desired.

Description

~ 10 B795 ~ ~

1 BACKGROUND OP T~IE I.WE~TION

2 P ~ LD OF TME INVENTIO~
4 ~his invention relates generally to amplifier circuits, and more particularly to an offset adjustable differential 6 amplifier.

9 The offset voltage of a differential amplifier is one of the errors of that amplifier. The offset error voltage 11 of a differe~tial amplifier can be defined as the output 12 voltage of the amplifier divided by its gain when the inputs 13 of the amplifier are connected together. The offset of a 14 differential amplifier is an imbalanced condition and may lS be the resul; of one or more of a variety of factors, such lS as mismatch of the input dif.erential pair, mismatch of the 17 current loads for the input differential pair, or unequal 18 loading of .he input stage, for example. Regardless of the 19 cause of the offset voltage of a differential amplifier, however, its effect will produce a difference in the currents 21 between the input s.age and the second stage thereof, whic::
22 difference will be proportional to the offset error voltage.
23 Although it may be possible to analyze individual 24 differential amplifiers to determine the specific cause of its offset error voltage and to malce a special offset adjusting 26 circuit for each, this approach is not practical for mono-27 lithic circuits in which the specific cause of the offset 28 error voltage of each circuit cannot be determined. Further-29 more, problems may arise, as will be discussed below, when attempting to employ circuitry which is external to a mono-31 lithic circuit for adjusting tlle offset voltage of that mono-32 lithic circui~. Also, once a specific circuit has been designed ... ... . ~,. . . .

~ ' 1068795 `J

1 I as a large production monolithic circuit, it is desirable 2 ¦ to include as many.components of that circuit as possible

3 ¦ within the monolithic circuit as internal components, rather

4 ¦ than as external components.

5 ¦ Although a differential amplifier may have an offset 61 error voltage, it may be desirable in some applications to 7 ¦ adjust that offset voltage to a predetermined level, rather 8 ¦ than to completely eliminate it. In the past, the offset `9 ¦ voltage o a monolithic differential amplificr has been cor-10 ¦ rected by employing external circuitry to alter the difference 11 ¦ in the currents in the differential amplifier in a direction 12 ¦ and by an amount to provide the desired corrected offset vol-13 ¦tage. If it is desired to reduce the offset voltage of a .
14 ¦ differential amplifier to zero, the difference in the currents 15 1 in that differential amplifier are altered by sucn additional 16 i circuitry in a direction and by an amount sufficient to can-17~ cel the effect of the offse. voltage. Generally,the temperature 181 coefficient of such additionâl, external circuitry is dif^
19l ferent from the temperature coefficient of ;he internal com-20 i ponents of the monolithic amplifier.
21 I The offset error voltage of a differential amplifier ?2 i is subject to drift with the changes in temperature. Prior 23 ¦known circuitry for adjusting the offset voltage of a dif-24 ¦ ferential amplifier is also subject to drift wi~h the changes 25 ¦ in temperature. The known prior art circuitry for adjusting 26 ¦ the drift in a monolithic differential amplifier produces 27 1 a drift of the amplifier output with changes in temperature 28 ¦ which is substantially ~reater than the drift which would 29 1 occur solely as a result of the original, unadjus~ed offset 301 error voltage of that amplifier without the additional, ex-31 ¦ te~nal offset adjusting circuitry connected thereto. The 32 ~drift produc~d as a res lt of :h- a~ditiona1, extorra1 c~rcuitry .. .... . . . ,.. , . , ....... . . .. . .

1068~95 1 ¦ for adjusting the offset voltage results from the fact that 21 the tempcrature coefficient of the external components is 31 substantially different from the temperature coefficient 4 ¦ of the internal components of the monolithic circuit being 51 adjusted. That is, if a gross mismatch of the temperature 61 coefficients of the internal and external components exists, 7¦ a relatively large drift will result with changes in temperature.
8 1 An example of the above mentioned teclmique for cor-9 ¦ recting the offset error voltage of a differential amplificr 10 1 includes the connection of a potentiometer between the dif-11 1 ferential input pair which can be varied to adjust the dif-12 ¦ ference in currents between the input stage and the second 13 ¦ stage thereof by an amount and i3 a direction to produce 14 ¦ the desired amount of adjusted offset voltage. If desired, 15 1 this potentiometer can be adjusted such that the difference 16 ¦ in these currents will be equal to zero, thereby providing 17 1 a zero offset voltage for the differential amplifier. In 18 ¦ a monolithic circuit, such a poter.tiometer must be external 19 ¦to the amplifier circuit. Generally, the temperature coef-20 ¦ ficient of such a potentiometer is different than the tem-21 ¦perature coefficient of the internal components of the mono-22 lithic differential amplifier, thereby resulting in drift 23 of the adjusted offse~ voltage wi,h changes in temperature.
24 Another example of offseL error voltage adjustment circuitry for a differential amplifier includes an external 26 circuit which is employed for forcing a change in one branch 27 of a current mirror connected to the input dif,ferential pair 28 of the amplifier. With changes in temperature, however, 29 the adjusted offset voltage will drift, since the temperature coefficient of the external components is different from 31 the temperature coefficient of the internal components.
32 Accordingly, it can be appreciated that a need exists ,.. .. . . . .... . ... .... . . . . .

~0687~5 for an offset adjustment circuit for a differential amplifier which will produce either no drift or a relatively low drift of the offset adjustment with temperature change.
SUMMARY OF THE INVENTION
The present invention provides, in combination with a differential amplifier having an offset error voltage, an offset voltage adjusting circuit, comprising: a current source; means connected in series with the current source for developing a voltage drop thereacross, and a pair of transistors, each having their biasing circuits connected in parallel with said means and having their outputs connected to respective connections between an input stage and a second stage of the differential amplifier.
It is an object of the present invention to further provide a differential amplifier with a circuit for adjusting the offset error voltage thereof, which circuit does not contribute any drift in that offset voltage as a result of a temperature change.
Another object of the present invention is to provide an offset adjusting circuit for a monolithic differential amplifier in which the temperature coefficients of the external components thereof are equal and the temperature coefficientæ
of the internal components of the adjusting circuitry and the internal components of the differential amplifier are equal, such that temperature changes will not produce any greater drift in the output of the amplifier than that pro-duced by the original offset voltage.
These and other objects of the present invention are attained by the provision of a circuit which is connected to the outputs of the input differential pair of a differ-ential amplifier and produces currents, wi h the difference of such currents corresponding to an offse when reflected ~k - S -jvb/rw to the inputs of the differential amplifier. The difference between the currents supplied by the offset adjustment cir-cuitry divided by the transconductance of the input stage of the differential amplifier is equivalent to an offset which may be either in opposition to the offset of the differential amplifier or may be additive therewith. This quotient of the difference between the currents supplied by the offset 8 correction circuit and the transconductance of the differential - 5a -jvb/rw 1 ampli~ier remains fixed with changes of temperature.
2 Accordingly, it can be appreciated that the offset 3 correction circuit of the present invention not only adjusts 4 the original offset voltage of the differential a~plifier, but does not contribute any drift in that original offset

6 voltage due to a temperature change.

7 The invention, however, as well as othor objects,

8 features and advantages thereof will be more fully realized

9 and understood from the following detailed description, when taken in conjunction with the accompanying drawing, wherein:
Il BRIEF DESCRIPTIO~ OF T~E DRAWING
12 _ -13 The single figure is a schematic diagram of an off-14 se~ corrected differential amplif er constructed in accordance 15S with the principles of the present invention.

17 DETAILED DESCRIPTIO~ 0~ THE PREFER~ED E~IBODI~IE~T
18 With reference to the drawing in detail, there is 19 ¦shown a differential amplifier having an input stage which 20 ¦ is generally designated with the reference numeral lO, a 21 ¦second and output stage which is generally designated wieh 22 ¦ the reference numeral 12, and an offset correction circuit 23 ¦ which is contained within the dot~ed line outline whic11 is 24 ¦designed with the reference numeral 14. Although the off-25 ¦ set correction circuit 14 is illustrated as being connected 26 ¦to a particular differential amplifier, it is to be under 27 ¦ stood that the offset correction circuit 14 may be employed 28 ¦ with any differential amplifier if the character.stics of 29 ¦the components thereof are matched to the charac;eristics 30¦ of the differential amplifier.
31 ¦ The input stage io of the differential amplifier in-32 ¦cludes a current source 16 connected betwèen a positive supply . I
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~ 1068 795 (-' ~

1 ¦ voltage and a differential pair of field effect transistors 2 ¦ ~FET) 18 and 20, The gate electrodes of the FET's 18 and 20 3 ¦ fo~m the inputs of the amplifier stage 10, FET current source 4 ¦ loads 22 and 24 are connected between a respective one of 5 ¦ the FET's 18 and Z0 and the negative supply voltage. The ¦ outputs of the input amplifier stage 10 are connected to 7 ¦ respective inputs of the output stage 12 ~hich includes a 8 ¦ differential pair of transistors 26 and 27. A capacitor 28 9 ¦ is connected between the base of the transistor 27 and an lO ¦ output terminal 29 of the differential amplifier and provides ll ¦ asymmetric frequency compensation therefor.
12 ¦ If the input terminals 30 and 32 are connected together, 13 ¦ any offset voltage of the input stage 10 or any loading there-14 ¦ of will produce differential drain currents on output lines 15 ¦ 34 and 36. If the base drive currents required to produce 16 ¦ a zero output on ~he terminal 29 are subtracted from the 17 ¦ drain currents into the bases of the transistors 26 and 27, 18 ¦ the difference of the resulting current magnitudes will be l9 I equal to the product of the of,set voltage of the differen~ial 20 ¦ amplifier and the transconductance of the input stage 10.
21 The offset correctio.. circui; 14 includes an FET 38 22 having its gate and source conne~-ted together and through 23 a resistor 40 to the positive supply voltage, thereby fornling 24 a current source. Accordingly, the voltage developed across ~he resistor 4Q is proportional to the current through the 26 FET 38.
27 The source of the FET 3S is connected to the gates 28 of a pair of FET's 42 and 44 having their sources connected 29 through variable resistors 46 and 48, respectively to the positive supply voltage. The drain of the FET 44 is connected 31 to the output line 34 and the drain of the FET 42 is connected 32 to the output line 36. The su~ of the voltage drop across .
.... . . . . . . . , . ~, . _ ~ .. . . . . .... .

~068795 1 the resistor 46 and the source to gate voltage on the FET
2 42 is equal to the voltaze drop developed across the resistor 3 40. In a like manner, the sum of the voltage drop across 4 the resistor 48 and the source to gate voltage on tlle FET
44 is equal to the voltage drop developed acToss the resistor 6 40. Therefore, the current supplied to the output lines 7 34 and 36 from the offset correction circuit 14 can be con-8 trolled by adjusting the variable resistors 46 and 48.
9 The difference between the currents through the FET's 42 and 44 divided by the transconductance of the input stage 11 10 corresponds to an adjusting offset voltae. Accordingly, 12 the currents through the PET's ~2 and 44 can be adjusted 13 by the variable resistors 46 and 48 to be either in opposition 14 to the differential currents produced by the original offset 15 voltage of the different al amplifier or can be adjusted 16 to be additive to the di''erential currents produced by the 17 I original offset of tlle d..ferential amplifier. If desired, 18 I the currents through the FET's 42 and 44 can be adjusted 19 I to cancel the effect of the differential currents produced 20 I by tlle original offset of the differential amplifier at its 21 ¦ output 29. The sum of the adjus.ing offset voltage produoed 22 I by the circuit 14 and the original offset voltage of the 23 ¦ differential amplifier is equal to the total offset voltage 24 1 of tlle entire circuit illustrated in the drawing. Accordingly, 25 ¦ if the adjusting offset voltage is equal to the original 26 I offset voltage, but of opposite polarity thereto, the total 27 ¦ offset voltage of the en,ire circuit will be equal to zero.
28 ¦ The temperature change wllich occurs àfter the resistors 29 ¦ 46 and 48 are set, will change the transconductance of the 30 ¦ input stage 10. Such a change in temperature will also change 31 ¦ the conduction level of the FET 3~. A change in the conduction 32 ¦ level of the FET 38 will alter the bias on the FET's 4~ and I . -8-. I ..... . . . .. . ..... ~,.. ..

~068~95 1 ¦ 44, such that the amplitude of ;heir drain currents will 21 also change. Any temperature change which tends to increase 31 the transconductance of the input s~age lO also tends to 4 ¦ increase the drain currents of the FE~'s 42 and 44 by an 5¦ equal amount. Therefore, the adjusting offset voltage pro-6¦ vided by the circuit 14 remains fixed with changes in tem-7I perature.
8 ¦ If the differential amplifier illustrated in the 9 ¦ drawing is to be made as a monolithic circuit, the FET's

10 ¦ 38, 42 and 44 wouid be included in that monolithic circuit I and the resistors 40, 46 and 48 would be connected as external 12 ¦ components to that monolithic circuit. Since the resistors 13 ¦ 40, 46 and 48 can be easily obtained with the same tempera-14 ¦ ture coefficient, there will b.~ no drift due to a change 15 I in temperature if the resistors 40, 46 and 48 are matched 16 ¦ components. Since the FET 38 is an internal component, its 17 ¦ temperature coefficient will be matched with the temperature 18 ¦ coefficient of the other internal FET's illustrated in the 19 ¦ drawing and, therefore, there will be no drift as a result 20 ¦ of a temperature change effectir.g the characteristics of the 21 ¦ internal components of the monolithic circuit. It can be 22 ¦ appreciated, therefore, that the only drift which will result 23 ¦ in the circuit illustrated in the drawing is that which would 24 ¦ occur for the original offset voltage without the circuit 25 ¦ 14 connected to the differential amplifier. As previously 26 I mentioned, the drift resulting from the original offset voltage 27 ¦ of a differential amplifier is considerably less than that 28 ¦ which is produced by prior known offset correcting circui~s.
29 ¦ Also, if it is desired to establish a predetermined amount of 30 ¦ offset voltage for the differential ampliier by adjusting 31 ¦ tlle variable resistors 46 and 4~, the drift of the amplifier 32 ¦ with changes in temperature will be only that amount of drift 1(1168'~95 - ' 1 which would have resulted from the original offset voltage 2 of the differential amplifier without the circuit 14 connected 7 ¦~bure o.

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2l ol ` 32 . .,..... ~ .............. ~1-.

Claims

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:

1. In combination with a differential amplifier having an offset error voltage, an offset voltage adjusting circuit, comprising (a) a current source (b) means connected in series with said current source for developing a voltage drop thereacross, and (c) a pair of transistors, each having their biasing circuits connected in parallel with said means and having their outputs connected to respective connections between an input stage and a second stage of said differential amplifier.

2. The offset voltage adjusting circuit of claim 1, wherein the temperature coefficient of said current source is equal to the temperature coefficient of the components of said input stage.

3. The offset adjusting circuit o. claim 1, further comprising means connected to said transistors for altering the current through each.

4. The offset adjusting circuit of claim 1, wherein said transistors are field effect transistors.

5. The offset adjusting circuit of claim 4, wherein said means includes a first resistor connected from a positive

Claim 5 cont'd.
supply voltage to said current source and to the gate of each of said FET's, and further comprising a pair of variable resistors each connected from the positive supply voltage to the source of a respective one of said FET's.