CA1054737A - Multi-channel data color display apparatus - Google Patents

Abstract

Abstract of the Disclosure A multi-channel television display includes a computer having a random access memory means for storing start and stop line data for a plurality of color beam drivers for generating vertical scan lines on a television tube. Each driver is preset to produce a predetermined color. Alphanumeric data is generated by a separate character generator connected to an auxiliary decoder selecting the color beam driver. A computer processor and a display controller are operated through an interlocking control with processing stopped during character display and line segment generation interrupted during processing. Buffer and latch registers for each line in each channel are connected to a digital comparator which sequentially reads the registers and activates the drivers.

Description

~o54737 Background of the Invention The present invention relates to a multi-channel color display apparatus with individual unique color per channel.
A continuous, visual presentation of changes in various functions and processes, may employ video devices. Black and white video is employed but a color device is shown in U.S.
Patent 3,642,634, in which each point or line is individually color coded. They are generally complicated, expensive and of somewhat limited use. Data has been transmitted and stored in shift registers with the information sequentially transferred to a display unit, for example, as shown in U.S. Patent 3,745,407.
Summary of the Present Invention The present invention is particularly directed to a multi-channel data display color display apparatus including a computer having a random access memory means for storing continuous monitored data and driving a multiple channel display means, with each channel identified by a selected unique color. In one embodiment, a commercial television receiver is reoriented to present vertical scan lines. The computer stores the definition of a line segment for each scan line to activate a color driver means which is preset to produce a predetermined color presentation in each channel and thereby provide a color-coded presentation. The display apparatus may, in accordance with another aspect of this invention, also include means to display alphanumeric data in selected channels. In this aspect of the invention, a character memory 'Dank is provided having means to output to a character generator having an internal sequence system to readout the selected character and channel location with an auxiliary decoder to select the color and channel identification.
A graphical display may include buffer and latch registers connected to control registers for each line in each channel to be displayed and a pair of digital logic comparing units driven from a single coordinate count unit, which is reset at the beginning of each scan line.
The character display processing system includes a suitable readout with its own internal sequence to produce predetermined characters in response to a coded binary input, with the output coupled through a channel decoder.
The color interfacing includes individual preset channels for properly shaping and transmitting of the channel control signals, with the output being interrelated to a suitable position and condition control interlock. The channel output may generate three-gun control signals of a predetermined relationship and thereby establish a pre-determined color signal uniquely related to that particular channel. The television sync signals are derived from the same sync signal generator as the timing signals for the transfer or interface with the memory unit such that the coordinate signal is predetermined and merely the assignment of its position for the related channel is controlled by the signal processing. Coordinate information processing is minimized while maintaining the highly desirable color separation control.
The channels can be located on the display screen in separate or superimposed locations and related graphical and character channels can be displayed in corresponding colors by suitable logic circuitry.
Further, to ensure a continuous appearing color graph, the initial coordinate is emphasized by generating of a pulse signal in response to each channel signal. The pulse signal is applied to the color driver circuits in synchronism with the initial turn-on of the channel~
An alarm control can change channel color.
The present invention provides a highly simplified basic concept in producing of a preset color channel with means for sequentially coupling of the data to the color drivers of an associated channel at an appropriate time to produce the multi-channel display on a conventional television unit or the like. The present invention provides a relatively simple reliable means of collecting and visually displaying various interrelated or separate data on a single drive or display unit in a relatively simple and inexpensive construction.
Brief Description of Drawin~
In the drawing:
Fig. 1 is a block diagram of a display system;
Fig. 2 is a detail of Fig. 1.
Description of the Illustrated Embodiments In Fig. 1, a conventional color television set 1 is diagrammatically illustrated on a screen 2 such as industrial processes or controls, operating apparatus data, phsiological data of a patient or the like. Simultaneous presentation of information in graphical form on display channels, shown diagrammatically by four separate channel lines 3. A beam-on control 4 is wired to establish individual colors for each of the several channels 3. Color is employed as the basically distinguishing feature and the channels may be superimposed or displaced in any desired manner within the present invention.
The television beam is interlaced with the conventional odd and even scan lines 5 and 6 driven through the conventional suitable synchronizing control. A small expanded portion of line 5 is shown and only the starting portion of line 6 for simplicity of illustration. Screen 2 is reoriented by 90 with the horizontal scan lines 5 and 6, which, in fact, are vertically oriented. Graphical displays are generated by line segments 7 (heavy portions on lines 5 and 6) with only determined starting coordinate 8 and final coordinate 9 determined. For example, the invention may be applied to the monitoring of a plurality of body functions of a patient.
Electrodes 10 may be attached to a patient and leads 11 connected to suitable voltage transducer 12. The log signals are coupled through a special computer 13 and an interlocking and interfacing system 14 to drive and produce a visual presentation of the information on a particular interrelated channel 4.
Generally, signals are sequentially sampled and stored in a shared random access memory 15 via a multiplexer 16 under the control of a computer processing unit 17 and computer program unit 18. The stored data is sequentially updated and fed to control the television beam-on control 4 by suitable operation of a processing unit 19 for time spaced and computer controlled operation.
The computer 13 may be a small digital minicomputer for sampling, storing and processing of the sampled data.
A multiple channel analog-to-digital (A/D) converter 20 is connected to transducers 12 and produces corresponding digital outputs to the unit 17.-Although shown with only four channels, a greater number will normally be used. In a practical construction aneight channel unit has been made and it may be readily expanded to thirty-two channels by provision of an appropriate sized memory. Program unit 19 continuously and sequentially sample the data and stores such data in the shared memory 15, automatically keeping track of the particular channel 3 and the horizontal line interlacing. The mul~iplexer 16 is coupled to the interfacing processing unit 19 which includes a sequence controller operated in synchronism with the scan line 5 and 6 to sequentially load the graphical data for each line segment 7 and having an output which sequentially activates the beam-on control 4 to generate the line segments 7 which a predetermined color for each channel.
A second channel or system 22 is provided for producing selected alphanumerics display on preselected channels 3. System 22 includes a character shared memory bank 23 coupled to unit 17 via a multiplexer 24 and to a character generator 25.
A logic unit 26 provides an ANDED output to the beam-on control 4 for the selected channels of the same color.
Fig. 2 illustrates a preferred apparatus for the graphical display channel 14 with channel 22 briefly discussed.

In Fig. 2, a detailed block diagram illustrates a preferred apparatus for implementing the color coded multiple-channel display in accordance with the teaching of this inven-tion, with a detailed illustration and description given for the graphical display channel 14. The character generator channel 22 is briefly discussed and references to channel 14 for a complete understanding of the system.
In Fig. 2, unit 17 is connected via a data input bus 27 to sample the data from the A/D converter 20 on a time basis and to transmit the converted information via a data output bus 22 to memory 15 for storage. The usual interrupt unit 28 provides the control logic and signals the unit 17 for coupling of the A/D converter 20 and detecting termination of the cycle. A teletypewriter 29 may also be coupled to the unit 17 for communication under the control of the interrupt unit 28. Bus 22 is also connected to the program unit 17 to provide the necessary information interchange, as well as to a peripheral data processor 23, such, for example, as a video character generator which is, of course, controlled from the processing unit 17 in accordance with a conventional control, as shown by signal lines 31 and 32.
The information relative to the position of the lines and channels of display means 2 is coupled between the processor 19 and the program unit 17 via a memory data input bus 33 and a memory address bus 34. The several memory buses 33 and 34 are also coupled by the multiplexer 16 to corresponding shared memory address buses 35 and shared memory information data bus 36 of the memory unit 15 and to the graphic address bus 37 and graphic data bus 34 of the interfacing processing unit 19.
Unit 17 is adapted to provide an overriding control lOS4737 to obtain communication with the shared memory at will. An interlocking status monitor control unit 39 is interconnected to signal the unit 17 and anticipates the demand of the com-puter 13 to produce a signal to multiplexe 16 of that demand.
The multiplexer 16 then signals the graphical display interface 19 to hold momentarily until the computer has completed the communication or fetch cycle.
The interface unit 19 is normally activated and is controlled by the output of a television sync signal driver or generating unit 40, as hereinafter described, to transmit the shared memory data to the display processing system via bus 36 and 38 in response to input address information via buses 37 and 35.
The memory storage unit 15 provides the data for each channel 3 and the processing unit 19 includes separate signal processing channels with selected common sequencing elements.
Each of the channels is similarly constructed to drive the beam-on control to properly illuminate the line segment 7 on the screen and correspondingly generate a preselected color trace in accordance with the sampled data. Because each of the signal channels is similarly constructed, a single one of the channels is shown and described in detail.
The interfacing system 19 of the shared memory 15 to the display means 1 is controlled by a sequence controller means 41 which selectively and sequentially establishes the transfer of the information on a line by line basis.
Controller 41 includes a channel selector 42 and addressing memory 43 to select the channels in a repetitive manner, and to effect transfer of the data from memory 15 to an appropriate storage stage 44, which includes a pair of storage registers 45 and 46 for each channel and which re-ceives and stores points 8 and 9 for each line s-gment 7. A
comparing or reading stage 47 sequentially reads the stored information and activates a three gun color driver stage 48 to produce the preselected color display for the channel read.
The television sync signal driver or generator 40 is included to generate the necessary synchronizing signals for the several stages 42, 43, 47 and 48 and establish the proper timing of the data transfer and processing with the generation of scan lines 5 and 6.
Character system 24 employs a separate character generator 25 which receives the character information and through a separate internal sequence generates the driving signals for turn-on and turn-off of the beam. Sequence control may be similar to that of the graphical display.
Bank 43 is diagrammatically illustrated including a first address selector unit 49 and an address increment or stepping unit 50. Unit 49 is illustrated as a preset, hard-wired input to the address memory ban~ 43 and is coupled to the television sync driver 40 by an odd-line sync signal line 51 and an even-line sync signal line 52 to initiate each dis-play scan of the screen from a preselected starting address.
Unit 49 may be a presettable,~

latch unit driven from the computer for further automatic movement of the display across the screen, positioning on the screen and the like.
A data for points 8 and 9 and "F" and "N"
buffer registers 53 and ;4 are loaded during a scan line drive under the control of the sequence controller 41. The coordination and synchronism between the display and the memory is controlled by providing channel and register selection output synchronism in response to signals from the television synchroniz-ing signal generator 33. Controller 41 includes the channel load counter 42 connected to a register select unit 55, the output of which is coupled by a bus 56 to sequentially activate the buffer registers 53 and 54 during the loading cycle to temporarily store the data for subsequent transfer to the registers 45 and 46. The channel selector 42 sequentially activates the F registers 53 to insert each "O" address. The F/N
register select unit 55 is then toggled with the output connected by line 57 to activate the address increment driver 50 to the next or "1" address in memory 43.
The channel counter 42 recycles and loads all the N
registers 54.
Driver 50 is thus driven to sequence the address memory for each scan line 5 and 6 for transfer of data in proper sequence to the registers 45 and 46, from the even frame output of the register selector 53 - r (~:

via line 54 to properly switch fro~ the one set o buffer registers 45 to the second set of N buffer registers dur-ing the loading thereof from the shared memory. ~he in-crement unit 50 is enabled from channel select sync signal line 58 which also is connected by line 58a to activate or cycle the channel selector 42. The increment address unit 5D is urther driven from an odd frame sync signal line 58b tapped to line 52 to properly step the address at the bo--ginning of each odd line scan. -The channel load counter 42 provides sequential channel selections with the memory address 43 transmitted via a cable 37 to the multiplexer 16. The memory is thus addressed via bus 35 and the related data is transerred from memory via the graphical data output bus 36 to a tri-state buffer 59 of the multiplexer 16. The tri-state buffer 59 is a well-known device and is connected to directly trans-mit the data to the F and N buffer registers 53 and 54 through an 8 or 9 bit adder 60 which is selectively set by a latch unit 61 coupled to the computer processing bus data bus line 22 and controlled by a control line 62 from the compu~er processing unit.
The adder 60 is employed to provide a split screen presentation on the screen. Thus, the adder is a convention-al logic element which, when activated, proportionately con-verts all the data information by a given percentage andshifts the presentation to the upper or lower half of the screen.
The channel selection counter 42 thus sequentially counts or steps from channel 0 through channel 3 with the initial address for each channel. The selection toggle unit -~0-55 is activated by the termination of the first channel selection sequence to select the alternate or N register .
buffers 54, and simultaneously to toggle the address bank 50 to read the next address.
The channel selector 42 is driven from a clock 63 wh~ch is coupled thereto through a suitable on-off control gate 64. The normal state of the gate 64 is to transmit the clock pulse and thereby sequence ~he channel selector 42 whenever the latter has been enabled. The gate 64 has a stop-input connected by a defeat line 64a to an-output of the multiplexer 16 which activates the shared memory or communication with the computer processing unit 17.
As previously discussed, the computer means 13 has priority and can couple the memory banks 15 and 23 at any time. The character generator unit 25 is directly disabled or defeated any time with the particular display points blanked. This is acceptable as the character information is only presented every second or so and will not create any adverse flickering.
The graphical display is synchronized and the addressing and channels are held in step with the display means, and the processing is desirably interrupted at the énd o~ a line readout.
In the illustrated embodiment, the moni~or 39 anti-cipates the computer demand for memory and holds the pro-cessing system 41 inactivated at the end of a line readout cycle for a selected period which is sufficiently great to permit the computer fetch cycle, after which the processing - system is again xeleased and will proceed with the next line.
Thus the computer time requirement is always sufficiently short, and the anticipatory time is sufficiently great to permit the desired sequencing with the display means momentarily held in an interrupted state. The computer will complete a "fetch~' or communication readily within the line retrace time o~ the beam. Registers 45 and 46 are coupled to re-gisters 53 and 54 via buses 65 and 65a and the data or in-formation is simultaneously transferred for all graphicaL
display channels 3 at the end of each scan line 5 or 6.
In the illustrated embodiment a "one-shot" circuit ~0 unit 66 of any suitable construction is connected to the blanking signal output line 66a o the television sync generator unit 40 and activates the registers 45 and 46-to ~etting of registers 53 and 54.
The actual information transfer to the beam-on control 4 is controlled by detecting the digital output of register 45 to turn-on the scanning beam and detecting the output of register 46 to turn-off the beam and thereby generate one line segment 7. Afte~ the outputs of the several registers 45 and 46 for each channel have been se-quentially detected and have activated the beam, all theline segments 7 of one scan line 5 are completed. The registers 45 and ~6 are then updated for the next scan line 5 during the blanks and retrace time and the cycle is re-peated. During each line generating cycle, the bu~fer registers 53 and 54 are updated.
More particularly, the setting of the registers 45 and 46, and therefore the point to turn-on and turn-off of the display beam, is determined by driving of a counter 67 to the setting of the registers 45 and 46. Thus the counter 67 is any suitable digital output counter and in the illus trated ellibodiment of the invention is shown driven from the television synchronizing circuit clock 68.
, The signal generator 40 is driven from a suitabLe clock 68 with a vertical sync and blank signal lines 66a and 66b connected to the television sync circuit 68a. The generator 40 further dQvelops the various keying signals at the lines 51, 52 and 58 for operating of the interacing means to load the registers 53 and 54 in proper sequence.
The counter 67 is reset at the beginning of each scanning line, for example, as a result,of the horizontal blanking signal appearing,at line 66a and shown by the connecting input reset line. The output of the counter 67 and the outputs of registers 45 and 46 are compared in a continuous manner through related digital signal comparators lS 69 and 70. Thus the comparator 69 includes a first input connected via a bus 71 to the output of-the registers 45.
second input is connected via a bus 72 to .the outpu~ of the counter 67. The output of the comparators 69 and 70 are combined in a separate logic unit 73 for each pair of registers and thus for each individual channel 3 ana forms ;a'control signal line 74 to~-one of a plurality of color-level control units 48 to activate three color gun drivers 75 for producing the selected color for that channel. Thus, at the very initial start of a scan line 5, the counter 67 is reset. Consequently, its input is at reference or zero ' '' level. The related'output o register 45 creates a beam-off signal from comparator 69 to logic u~it 73 via a channel bus 76 and the beam is held off or deenergized. The counter 67 begins to count in synchronism with the movement of the scan line 5. When the count of the counter 67 equals'the setting of the register 45 the comparator 69 will detect the coinci-dence and provide a beam-on signal via line 74. Further, for each particular channel the level controls are uniquely related to produce a predetermined color for the line segment 7. Thus the corresponding line segment 7 is generated and continues until the comparator 70 produces a turn-of~ of the beam.
The turn-off point 9 is set by the output of the comparator 70 which has one-input connected to the output of counter 67 by ..
a bus ?7 and the second input connected via a bus 78 to the registers 46. An output bus 79 is connected to the logic unit 73 and when the comparator 70 registers coincidence, the beam unit 48 turns off or deenergizes the beam.
More particularly, the logic unit 73 is shown fQr one channel and includes a pair of two input NOR gates 80 each -15 having a pair of inputs connected one each to each of the com-parators 69 and 70. The outputs o the NOR gates 80 are connect-ed to a third NOR gate 81, the output of which is.connected to the channel driver line 74. The first comparison creates an enable signal on channel driver line 74 which is coupled through a suitable buffer inverter unit 82 for that channel; The other channels are driven from separate comparator outputs which a~e -combined by similar logic units to develop control signals on related channel driver lines 74, not shown. . - ..
Thus, illustrated line 74 may be coupled through t~e buffer 82 to a selected color control input line 83 or through the NAND gate 26 to a di~ferent color control input line 84.
Thus-, the color control unit 48 includes a plurality of individual stages, each of which is similarly constructed - to produce three output signals coupled one to each of three input lines 85 to the color gun driver 75. Each stage is (- ( .

~ imilarly constructed and one is described. The stage includes .
three individual potentiometers 86 having individually adjust-able output taps 87. The setting of the taps 87 determines the output voltage and, therefore, the percentage o the color com-bined with the other two similarly set colors. The taps ~7are connected to the dri~Jers by suitable diode means 88 or other suitable means to isolate the several signals. By pro-viding of a continuous or infinite type control such as pro-duced by a potentiometer of the three primary colors, a cor-responding continuous range of colors are obtained for each of the channels. -Thus, the wiring of each channel driver line 74 to a particular color control input line 83 sets one stage of the unit 48 and presets the color for that channel. In Fig. 2, the cable input illustration to buffer ~2 and ~A~D gate 2~ indicates the multiple line connections with each channel driver line 74 connected to only one of the input lines.
The apparatus is preferably constructed with the color control taps 87 coupled to exposed adjustment elements for ad-~0 ~ustment of the channel colors as desired.
Further, by employing suitable automatic color signaladjustment means, the channel color may be programmed, remotely controlled or the like. --In development of the line segments 7, the initial tuxn-on will not with the conventional colored television nor-mally be with full intensity. Thus, a slight delay is generally encountered while t~e intensity of the beam builds to the level set by the color driver stages 48. In the illustrated embodi-- ment, an auxiliary momentary drive-on signal is applied to the intensity control of the television set to emphasize the starting point and thereby develop a continuous, even line intensity.
~ Thus, in the illustrated embodiment, a NAND-~OR
logic unit 89 is connected to all of the color stage input lines 83. The output of unit 89 is connected through a pulL-up variable resistor 90 to a positive voltage supply. Thetap 91 o~ the resistor 90 is connected directly to a base line unit 92 of the television set 1 via a wave shaping capacitor-resistor circuit 93. The output of the circu t 93 is connected via the lead 94 to the unit of the television set ~ to increase the intensity during the initial turn-on. - -The wave shaping circuit may, of course, be employedto also control the terminal point of the line segment for optimum visual graphical illustration. For example, the wave shaping may thus be selected to produce a slow start and gradual termination to develop a smooth, visual pleasing line graph in each of the graphical display channels. Further, a suitable circuit means may be introduced in ~ny part of the output cir-cuit, for exam~le, in the individual color driver circuits.
The character generating channel, as previously noted, is constructed with the character generator 25 which includes the necessary sequencing to generate selected alphanumeric characters. The generator 25 includes an addressing bus 95 coupled to the shared memory 23 by multiplexer 24 and includes a character select input bus 96 forming a part of the data in-put from memory. ~ decoder 97 coup~es the output of thecharacter generator 25 to the several drivers through an output channel bus 98. The decoder 97 is coupled to bus 96 and re-ceives simultaneous color channel encoded data which selects the channel driver line of bus 98 in accordance with the memory data to receive the character. Thus, the memory unit 23 includes -~6-the necessary encoded information as to the partic~lar character to be displayed, the channel and channel location, with the de-coder function to apply the character to the appropriate channel color wire or line of bus 96. This is in contrast to the gra-phical display where the controller provides sequencing of theseveral channel outputs.
As previously noted, the character channel is other-wi~e similarlv interfaced with the computer means. As the character generator is operating at a ~ery rapid cycle, the generator 25 is defeated or blanked upon receipt of a signal that the computer is about to establish correspondence with . . . .
the memory unit. Thus, the high speed of the character genera-tor makes a system to hold the unit in a standby mode while the computer is coupled to the memory impractical.
lS Further, the present invention may, of course, be expanded to provide any number of channels with the time capability of the system, and may be further expanded by em-ploying duplicate display and sequence controller-means coupled to the one memory.

Claims (28)

The embodiments of the invention in which an exclu-sive property or privilege is claimed are defined as follows:

1. A multiple channel data display apparatus for individual display of a plurality of monitored data as separate single line function graphs on a separate data channel, com-prising a computer means having input means to receive the data and processing means for analyzing the monitored data and storing such data in a graphical memory means in accordance with a segment of the related single line function, a color display means having a variable driver means, one driver means for each of said channels, said display means being connected to said memory means and including a controller means for sequentially withdrawing of said information and applying said information to said individual color driver means to actuate the color drivers in accordance with the line segment data of the related channel, whereby said multiple channels are displayed with preset identifying color for each of said channels.

2. The apparatus of claim 1 wherein each of said plurality of color driver means includes adjustment means for adjusting the color related presentation established for said channel.

3. In the data display apparatus of claim 1, said computer processing means selectively monitors the data and transmits the data to the memory means, said display means having means responsive to said processing means to hold the display means in standby with the computer means communicating with the memory means and thereafter releasing the display means.

4. The apparatus of claim 1 including a multiplexer means coupled between the computer processing means and the graphical memory means, said multiplexer means having an output coupled to the display means and said controller means including inhibit means responsive to a computer demand signal decoupling the shared memory means from the display means and coupling the shared memory means to the computer processing means, said computer means generating an anticipatory signal prior to the actual demand time whereby said controller means completes a line segment and then holds till the terminal end of the computer-memory cycle.
5. The apparatus of claim 1 wherein said graphical shared memory includes data identifying the initiating and terminal points in each line segment for each channel, register means for storing of such point data, said controller means including a sequence means including a channel select means and a memory address means coupled to the memory means to activate transfer of data from the memory means, a clock means for driving said channel select means, a display sync signal generator coupled to activate the channel select means and the memory address means in timed relation to activation of the display means, a register select means coupled to be driven from the channel select means and coupled to selectively activate said register means to sequence the output of the channels to said display means, a comparing means having a first input connected to said register means and a second input connected to a reference input source means to provide a selective comparison between the output of the register means and the reference means and thereby generate an output in accordance with the comparison

Claim 5 continued....

therebetween, and logic means selectively connecting the comparing means to said channel color driver means to correspondingly activate one of the color driver means to thereby provide visual display of the related channel.

6. The apparatus of claim 5 including an adder means connected between the memory means and the register means, said adder means including a control input connected to the computer processing means for selective actuation of the adder means for shifting of selected channels.

7. The apparatus of claim 1 including a character generator means, a separate character memory means, means coupling the character memory means and the character genera-tor means to the computer processing means to selectively trans-mit a character to said channels for character display.

8. The display apparatus of claim 7 including output combining means connected to said character generator means and to said controller means to receive data signals and connected to said color driver means whereby selected graphical display channels and character channels are pre-sented in corresponding identifying color.

9. The apparatus of claim 1 including a character generator means having an internal sequencing means to produce an output related to a selected character for display in any one of said channels, said computing means including a shared character memory means, means connecting said character generator means to said shared character memory means for preselected presentation of characters in predtermined channels.

10. The apparatus of claim 9 wherein said computer processing means includes a memory demand means generating an anticipatory demand signal for selection of the graphical or character memory means, said controller having hold means operable to hold the graphical display means in an intermediate hold position, said memory demand means being coupled to the controller means and to the character generator means to selectively effectively decouple the graphical memory means to the computer means and to simultaneously activate said hold means and being coupled to defeat the operation of the character generator for a given channel.

11. The apparatus of claim 1 including shift means to shift the position of at least one of said channels.
12. A multiple channel data color display apparatus having a television display means including a vertically oriented scan line and interrelated beam control means to generate vertically extended line segments for presentation of a plurality of monitored data in graphical form in a related plurality of presentation channels as separate single line function graphs, comprising a computing apparatus includ-ing a processing means for manipulation of data and memory means including a graphical shared memory means for storing of said line segment data for each channel means to monitor the data, a multiplexing means connecting the processing means to said graphical shared memory means, a line generator comparing means connected to said multiplexing means to receive the graphical shared memory means, a beam control means connected to the line generator comparing means including individual pre-settable color channel driver means for each channel, said line generator comparing means including a sequence controller for

Claim 12 continued....

actuating said driver means to present each channel on the television display means in accordance with a preselected color and the stored memory under the control of the computer processing means.

13. The apparatus of claim 12 wherein said line generator comparing means includes a plurality of pairs of registers for storing the beginning and end information for each of the line segments of each channel for each scan line, means connecting said registers to the graphical multiplexing means for sequential loading of the line segment information, a sequence controller including a channel selection means and a memory address means connected to the multiplexing means for sequential loading of the data regarding the line segments into said register means, a register select means driven from said channel select means and connected to the register means to selectively activate the pairs of registers, and a synchron-izing signal generator connected to the channel select means and to the memory address means to sequentially and cyclically operate said sequence controller and the display means in synchronism.

14. The apparatus of claim 13 wherein said line generator comparing means further includes a digital comparator connected to the output of said register means and having a clock driven input means, and means connected to said synchronizing signal generator to activate, reset and drive said comparator to sequentially establish outputs related to the data information in said registers and thereby sequentially activate said channel driver means.

15. The color display apparatus of claim 12 wherein said color driver means include a plurality of presettable color driver circuits having dual adjustment means for individually and separately establishing pre-selected colors, logic means connected to said presettable color driver circuits and to the output of said comparator for energizing a corresponding color driver circuit for the preselected channel, said comparator establishing the position of the display of the color segment on the display means with said presettable color providing distinguishing characteristics between channels.

16. The color display apparatus of claim 12 wherein said display means includes means connected to the output of said comparator to shape the signal generating a line segment to thereby present an improved visual color graphical presenta-tion in each channel.

17. The apparatus of claim 16 wherein said means emphasizes the initial turn-on of a line segment.

18. The display apparatus of claim 12 having a character generator, a character shared memory means, a character multiplexing means connecting the character shared memory means to the processing unit and to the character generator, means connecting the character generator to the beam control means.
19. The display apparatus of claim 18 wherein said character generator includes an integrated character generator circuit element adapted to establish predetermined output characters, and decoder means connected between the character generator means and the color driver means to selectively connect the output of the character generator

Claim 19 continued....

including a coupling bus to the character generator multiplexing means, and a defeat means connected to said computer processing unit to terminate the operating of the character generator and reset the character generator to the next starting position.

20. The color display apparatus of claim 12 wherein said television display means includes multiple line interleaving.

21. The apparatus of claim 12 wherein said multi-plexing means is biased to connect the shared memory to the display means, said computer processing means establishes a memory demand signal a predetermined time prior to actual demand, and said sequence controller including a hold means connected to receive said memory demand signal and responsive to complete a line segment sequence cycle and then establish a hold on the sequence controller.
22. A multiple channel data color display apparatus having a television display means including vertically orien-ted even and odd scan lines for individual display of a plur-ality of monitored data as separate line function graphs on a separate data channel, comprising a plurality of different color drivers each of which produces a preselected color display, a computing apparatus including a processing means for manipulation of data and having a graphical shared memory means and a character shared memory means, means to monitor the data, an analog-to-digital conversion means coupled to the monitoring means and to the processing means, said pro-cessing means generate vertically extended line segment data for presentation of the monitored data in graphical form and to generate related alpha numerized presentations in separate Claim 22 continued....

channels, a graphical multiplexing means connecting the processing means to the graphical shared memory means, a character multiplexing means connecting the processing means to the character shared memory means, a character generator connected to the character shared memory means and to said color drivers to establish selected alpha numeric information channels, pairs of registers for stor-ing the beginning and end information for each of the line segments of each of said channels, sequence controller connecting said registers to the multiplexing means for the graphical shared memory means for sequential loading of the line segment information into said registers, said sequence controller including a channel selection means and a memory address means connected to the graphical memory multiplexing means for sequential withdrawal of the data regarding the line segments, incrementing means for se-quentially increasing of the address of the memory address means for sequential withdrawal of information from such memory, a register select means driven from said channel select means and connected to the registers to selectively activate the registers, a synchronizing signal generator connected to the channel select means and to the memory address means and to the address incrementing means to sequentially and to cyclically operate said sequence con-troller and the display means to operate the display means in synchronism with the sequence controller, a digital com-paring means connected to the output of said pairs of re-gisters and having a clock driven input means, means to activate said comparing means to establish a plurality of

Claim 22 continued....

outputs to said color drivers for selectively establishing colors in accordance with preselected preset outputs, said comparing means establishing the position of the display of the line segments on the display means with said channel colors providing distinguishing characteristics from other channels.

23. The apparatus of claim 21 wherein said plurality of color drivers each include presettable color level controls for individually and separately establishing preselected colors, said display means including means connected to all of the outputs of said comparing means to emphasize the initial turn-on of each line segment to thereby present a continuous appearing color graphical presentation.

24. The apparatus of claim 22 wherein said character generator means includes an integrated character generator circuit element adapted to establish predetermined output characters, a decoder means connected between the character circuit element and the logic means to selectively connect the character generator output to said several channel drivers.

25. The apparatus of claim 23 wherein said computer processing means controlling said character memory means to introduce channel select coding means into said decoder means to select the color channel.
26. The apparatus of claim 22 wherein said computer processing means includes a memory demand signal means-a predetermined time before actual coupling to the memory means, said demand signal means being connected to activate such sequence controller to complete a readout

Claim 26 continued....

sequence for a given line segment and then to remain in stand-by position until the computer completes its pro-cessing to the shared memory.

27. The apparatus of claim 26 wherein said demand signal means of said computer processing means is connected to the character generator to terminate and reset the character generator.

28. The color display apparatus of claim 2 includ-ing a binary adder connected between the register means and the graphical shared memory means, said adder having an input means connected to the computer processing means and selectively actuated to shift the presentation of said channels.