CA1053375A - Computer system - Google Patents

Computer system

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Publication number
CA1053375A
CA1053375A CA241,963A CA241963A CA1053375A CA 1053375 A CA1053375 A CA 1053375A CA 241963 A CA241963 A CA 241963A CA 1053375 A CA1053375 A CA 1053375A
Authority
CA
Canada
Prior art keywords
storage
address signals
store
address
unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
CA241,963A
Other languages
French (fr)
Inventor
Hans Cramwinckel
Adrianus M.J. De Bijl
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Philips Gloeilampenfabrieken NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Gloeilampenfabrieken NV filed Critical Philips Gloeilampenfabrieken NV
Application granted granted Critical
Publication of CA1053375A publication Critical patent/CA1053375A/en
Expired legal-status Critical Current

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Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10Address translation

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)

Abstract

ABSTRACT

The invention relates to a computer system, comprising a central data processor, a peripheral appa-ratus which acts as a background store (secondary storage) and wherein binary information elements can be stored in storage positions which are each time conse-cutively arranged within a storage sector, the said storage sectors being each time rigidly spaced and being addressable by a group of address portions, a number of storage positions being sequentially accessible under the control of the said address portions, furthermore comprising a control unit for controlling the generating of universal, logic address signals for the storage unit in the central processor, governed by program signals, on the basis of user address signals received by the central processor. As a result, only quantitative para-meters must be adapted in the conversion unit when the storage unit is replaced.

Description

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P~N 7856 MUNS/EI/ST~Y
01,12.75 .

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"Cornputer system".
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'rhe invention relates to a computer system, comprising a central data processor, a peripheral appa-ratus which acts as a background s-tore (secondary storage) C l:h n b e s~o r e~
~ and wherein binary information elements ~ ~e~ in storage positions which are each time consecutively situat-ed within a storage sector, storage sectors being each time rigidly spaced and being addressable by a group of addreQs portions, a number of storage portions being sequentially ;
accessible under the control of the said address portions, furthermore comprising a control unit for controlling the generating in the central proces~or of universal, logic address signals for the storage unit, governed by program signals, on the basis of user address signals received by the central processor.
~ Systems of this kind are often wsed. The control ~~ unit may comprise, for example, a storage unit (control - store) wherein a machine program is stored. ~le user address signals can be generated under the control of a ~ user program (application ~rogram~. On the other hand, they .? 20 can alternatively be externally generated, for example, by . , .
means of a keyboard. The program signals may relate to the updating of a data file. The logic address signals gene-rated by the control unit must subsequently be converted into pnyslcal address signals. Logio address signals are to be understood to mean herein address signals wherein the hierarchically arranged address elements differ from each other only o~l~as regards their position in the
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``~ 01~ 12.75 ~3533 hierarchical sequencc~ without the electrical or mechanical properties of the storage unit having an effect; the logic address is notably independent of the -~ ~ access process of the store, The logic address thus corresponds as if it were to a counter position. The user address, how-ever, need not contain any indication as reg~rds a sequence, but may conslst of an identification of a file and an object within a file, so for example9 "customer Peter". This user address is converted, by means of, for example, a table which is stored for the data control, into two addresses which indicate the starting address of the file "customer"
and the relative address in the sequence of the customers, respectively. The logic address can thus be readily formed and gives a relative address in the sequence of storage positions, taken from the first storage position. The storage unit is thus addressed in the same manner as a ~ random access store, the most obvious example thereof ~~ being a store composed o~ storage matrices. The physical addresses, h~wever, comprise port~ions which are directly g ~ \ O~
related to the cp~ti~l or ~ and hence to -the con-struction of the storage unitO Portions thereof may thus concern address portions which are accessible at random, periodically accessible, accessible in a delayed manner, conditionally accassible, etc. Examples thereof are the Z5 address portion which selects from the dlsks of a disk store, the address portion which relates to the angular shift of a disk store, the address portion which relates _3_ Mt~N~ L/ST~
01 . 12.75 1~53375 to the position on a magnetic tape or the position of a movable magnetic head of a disk store, and an address portion which relates to information stored ln a buffsred storage section, so that first the buff`er must be avail~
able, respectively. The physical address is i~portant notably if a number of storage positions are sequentially accessible, because the exchange of information with tlle storage Ullit must then satisfy severe requirements as regards s~rnchronization. On the other hand, storage units of this kind are comparatively cheap and hence v0ry at-trac- -tive. For converting logic addresses into physical addresses, it is known to use a conversion unit which controls the data file and which is controlled, for example, by a speci-fic machine program which is stored in a control store.
Notably if the data file is also controlled by the said machine program, this program must contain a substantial amount of information as regards the organization of the data storage in the storage unit. Unlted States ~br~M~
Specification 3,366,928 describes such a computer system comprising tape stores as a background sto-re. A provided --- "main" or principal store contains -a display table, so that a number of hierarchical address portions can be derived. To this end, the principal store contains per d~ta ~Q~ y ~c~
file an identification of a tape store, ~ a physical sub-~
address, and also a sequence of logic block numbers with a~
length indication for each block, ~hus,block numbers are neither logic nor phygical address portions, bscause they .

' I'llN 7856 MUNS/I~I/sr~Y
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have a significance only on account of the accumulated length o~ the preceding blocks. In accordance with the known state of the art, the physical addresses are derived from the said data. For a designer who in-ter alia has to determine the contents of the said principal store, it has been found that the fact that the said contents must also include e~tensive information as regards the physical properties of the data storage in background storage unit represents an additional burden. Therefore, the invention has for its object to reduce this burden, so that it is sufficien-t to apply exclusively logic address signals to an adapter. If the storag~ unit in the ~nown systems is modlfied, the adapter program, ~i.e. the contents of the said principal store) must also be modified. This modifi-cation may concern the capacity, with the re3ult that the upper limit of a physical sub-address is modified. It may also concern the organlzation of the storage unit, so that, for example, an address-portion whi-h was accessible in a delayed manner thus far then becomes accessible at random.
For example, a magnetic disc store is provided with a mag-netic head for each storaga track. The contents of the said pricipal store must also be changed if the organization of the data file in the storage unit is changed~ This can already occur when the number of information units in a file grows, so that more s-torage space is required. Further-more, according to the present state of the art the contents of the said pricipal store can be used only for a given .

~ ~533~5 configuration, or in other words it cannot be universally used. The same is applicable if the operations must be executed in specific devices in -accordance with the contents of the said principal store: in the case of modifications in the storage unit, these devices would also have to be modified. The invention has for its object to have a storage unit addressed by the machine program as if it were a random access store. The invention furthermore has for its object to realize a storage unit which can be addressed by the machine program regardless of the physical prope~ties of the storage unit. The invention also has for its object to realize a simple and fast exchangeability of storage units o~ different properties, in that no modification is required in the central processor.
According to the present invention, there is provided a computer system comprising a central data processor, a conversion unit, and a peripheral device operative as a background store for secondary storage, said central data processor having a control unit for receiving user address signals and for generating on the basis of said user address signals universal logic address signals under program signal control, said background store comprising a plurality of storage sectors of uniform length each accommodating binary information elements in storage positions which are ~ ;
each time consecutively arranged within a storage sector, wherein each storage sector has a predetermined relative position and is separately addressable by a complement of respective physical address signals, each of said storage sectors forms part of a storage block which comprises a first predetermined number of storage sectors which number is specific to the said background store, and wherein each storage sector within a storage block is addressable by a first partial physical address signal, said background store comprising a second predetermined number of storage blocks each of which is addressable by a second partial physical address signal, said conversion unit comprising means for receiving said universal logic address signals, means -for storing a ~epresentation of said first predetermined number as a para-meter signal, means for generating by means of a calculating member, on the , .

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basis o~ said universal logic address signals and said first predetermined number, flrst and second partial physical address signals, and means for forwarding said partial physical address signals to said background store.
Due to the introduction of storage sectors of constant length in storage blocks of constant lengthJ a major simplification is achieved, because the length of the storage sector and the storage block now only appear as two parameters in the said conversion unit: a high degree of modularity is thus achieved. In the case of modifications in the storage unit, only parameter signals must be modified. The universal logic addresses can thus remain -the same. Due to the absence of an extensive mapping table, re-programming can be dispensed with. A conversion unit having an unchange-able logic structure is to be understood to mean herein a device which can perform only a number of predetermined data operations each time when it is addressed, without the nature of the said operations depending on information which can be fetched from a storage uni~.
Each of the said storage blocks preferably forms part o~ storage regions which contain a uniform number of storage blocks specific to the said storage unit, with the result that the said storage sectors can be addressed in a three-dimensional address space. Each physical address then comprises three address portions, whilst for each address portion a modular construction is realized, so that the conversion unit can have a simple structure. Using a three-dimensional address space, a very large storage capacity can also be realized.

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The storage unit preferably comprises a number of magnstizable disc surfaces whereon the three address portions identify the cylinder surface; mag~netic head and track sector, respect;vely. There are many possibilities ' for tlle design of a magnetic'disc store, ,o it is particular-ly advantageous that the program which performs the address conversion on the basis o-f the user addre'sses is not aware of the characteristics of the disc store, such as the n~u~-ber of discs or tracks, and that the said program is lirni-ted to the generating of logic addresses. '' The storage unit'preferably contains information in the form of magnetic domains. A physical address can then consist of a number of address portions, the sub-division being dependent of the selected type of magnetic domain store.
As far as the logic address portions are con-cerned, such a store can be addressed in exactly the - same manner as the said disc store. Similarly, the storage - unit can also comprise a device including shift register elements or even be composed of storage matrices; in -that -' case the invention can be attractively utilized if a number of storage words are sequentially addressed; in this case there is no distinction be-tween storage units having rand-om access or not as far as the logic addresses are concer-ned.
~he said calculating member preferably forms part of the central processor. Due to the dual use of the _ ~ , .

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said calculating member ~for adclress calculation as we]l ~ C~ntq~ S
-~ as for the "own" operations), a ~FI~n~saving~is reallzed.
The calculating member is then t~mporarily contralled by the conversion unit situated outside th~ central processor.
On the other hand, it is advantageous for the said conversion unit and the saicl storage un:lt to b~
constructed with common terminals for the said logic address signals and coIllmon connection termina]s for data -transport.
As a result, thc exchanging of connections is already sufficient for effecting the replacement of the storage unit ~plug~to-plug compatibility).
The invention will be described in detail hereinafter with reference to a number of figures. Figure 1 shows a computer system according to the present state of the art. Figure 2 shows a computer system according the invention. Figure 3 shows the invention. ~ig. 4 shows a ` detailed circuit in ac-cordance with the Inven-tion. Fig. 5 -- illustrates the organi~ation of a magnetic domain store.
Fig. 1 shows a computer system according to the - 20 present state of the art, notably as shown~in Fig. 1 of the said United States Pat-~nt Specification 3,366,928. The sy~tem comprises an input terminal 1 for program signals.
S
is a progIam which is referred to herein as a user program and which relates, for example, to the updating of a data file. An instruction in that case contains, for ex-ample9 an identification of the file, an identification of a section of the said file, for e~ample, a number, and a ,.- . ~ . ' D
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.~g~ information. The latter information will not be' considered herein, because the invention does not specifi-cally relate thereto. In accordance with the present state of the art, the principal store 2 contains a display table which when addressed by the iden-t'ification o~ the file, can provide an identification Or one O:r the magnetic tape apparatus 10, 11, 12, an identification of one or more blocks thereon, and the lengths of the relevant blocks. The pricipal store thus implicitly contains the entire organiza-tion of the contents of the tape apparatus, which is thus co-determined by the physical proper-ties thereof, for example, the block length per tape, the number of tapes, and the capacity per tape. Under the control of the clock 5, the block access test unit 3 and the sector (record) access test unït 4 select a given sector, inter alia by comparison of the number within the file, the block lengths stored in the principal store 2, and the positions of the block counter -- (7, 8, 9) of the selected tape unit. When the desired sec-tor has been selected, the gate 6 is opened, with the result that the information read is applied to the central proces-. sor via the line 13. Similarly, information is written in a f tape unit; in the case of a magnetic tape, a systematic po-.. . .
sition error almost always occurs when information is re-written, so that a read/write cycle can be performed only : a few times in succession before an un desired interac-tion between the stored information of successive sectors is liable to occur. When, for example, a tape apparatus is - -1Q- ~ .

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01 12.75 ~n533~5 replaced by an apparatus of a dlfferent type, the inf`orma-tion in the principal. store 2.must be completely updated.
This requires an extensive updati.ng operation, both as regards the reference table in the principal store and the control program which is also stored in the princi.pal store and on the basis of WhiCIl the reference -table is drafted.

The said change can al.so occur if the informa-tion stored in the tape units i.s replaced by i.nformation which is organized in a different manner. Changes of this kind are usually quite comp].ex. The known device has a further drawback in that, given the rank of an address in a file, all block leng-ths within the ~ile must be successi-vely subtracted from the rank number until the remainder is smaller than the block leng-th. A large number of sub-tractions may be required for this purpose, each subtractioninvolving:a diffent minuend~ so that the principal store . : 2~must be interrogated a corresponding number of times.~
Figure 2 shows a computer system according to the invention, comprising a peripheral apparatus 14, a first conversion unit 15, a central processor 16, a second conversion unit - 18, an arm control device 20, a disc (angular) position de~ection unlt 19, a disc drive unit 21, a gate unit 17, and four discs 22,..25 with assoc`iated magnetic heads 26...29. The peripheral apparatus 14 may be of a known type, for example, a peripheral appara-tus of the kind referred to as "intelligent" which comprises an input element for data, .for example, a keyboard,.an output element for data, .

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PIIN ~856 M~NS/EL/STRY
01,12.75 ~S33~i for example, an alpha nulnerical d~splay apparatus with a TV monitor, a control store, for example, a number of registers for instruc-tions, and a processing store. Simi-larly, the unit 14 may be a store wherein a user program ls storedO When information is to be requested from the disc store, this information is identified and applied to the unit 15. This ldentiflcation is, for example, "customer~
Peter". A store is adclressed by this identification as if it were a random access store. The uni-t 15 comprises a conventional store wherein the word "customer" ~the repre-sentation thereof being a glven blnary coded number, for example, "01") fetches a given word which gives the basis of the file, i.e. the first address thereof and also the length of the said file. In the diagram of Fig. 3, the column 32 indicat~s the address of the word assigned to a file; the column 33 indicates the basic address of the - said file; the column 34 indicates the length of the file.
Whenthe address 0 1 is addressed, therefore, the basic address 0 0 1 0 and the file length 0 1 0 0 appear on the outputs of the relevant store. The unit 15 comprises a second store (which may be cons~ructed to form one physical unit together with the former store) wherein a given word is also fetched by the name "customer Peter"~ The name "cus+omer Peter" is represented, for example, by the 25 ~ elght-bit binary numher (columni~) 0 1 0 0 0 1 0 1, the two most significant bits thereof originating, as stated, from the indication "customer", At the sLorage position of , .
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the addressed word, the relative rank number within the customer file (shown in column 36j and the length O:r the information concernlng the said customer (shown in column 37? are stored. Thus, the rànk number of "customer Peter"
5 - is, for example, 0 0 1 1 . 1 0 0 0 . 0 1 0 1 (901 in decimal notation) and the ]ength is 0, which means that a single storage sector is assigned to the relevant customer.
In accordance with the embodiment shown, at the most two sectors are assigned to the same customer. The advantage of the separate storage of the base of the file and the rank numbe~r within the file i5 embodied in the fact that a storage region can now be readily assigned to newly ariving information by a simple modification of the first store (columns 32, 33, 3l~), The addresses and the lengths in the columns 33, 34, moreover, can identify merely the most significan-t address porti~ons~ so that an "address" can con-tain a large number of information units. For example, if the eight least-significant address bits are not stored, the length will be 4 x 2 = 1024, 50 that the actually last address is 0 1 0 1. 1 1 1 1 1 1 1 1. The file 11 is empty in Fig. 3, and the remaining space can be filled by a file of arbitrary length (provided it, is smaller than 0 1 1 0).
- If a new file is to be stored~ first all ~ddresses of the column 33 are examined and~ when an empty part of storage space is found, it is checked whether the file fits there-in, Operatlons of t~is kind are commonly performed, se they - will not be elaborated herein. The customer number found in , 13- , .

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accordance with Figure 3~ or possibly supplied directly, is added to the basic address until a logic address is `
formed which does not contain information as regards the physical position in the background store or the physical ~ -properties of the background store. This address does not offer more than the rank of the addressed storage position within the disc store. If all addresses comprise twelve ~: .... ... ..
bits, the logic address of "customer Peter" is then `
0 0 1 0. 0 0 0 0.0 0 0 0~ increased by 0 0 1 lol O O 0-0 1 0 1 '.
¦901), so as to form the sum 0 1 0 1.1 0 0 0 0 1 0 1 ~ - ~
(1413). This is because the customer "901" means the 902 ;
in rank, because the first custcmer has the ~Irank~ 0.
In this example the store can thus indicate 4096 sectors from the conversion unit 15 (additional address bits which are not shown can possibly be present in the said store for later extension of the background store (22... 25). ;~
Figure 4 shows an elaboration of a circuit for use in a storage system in accordance with the in-vention. The unit 15 comprises an input address register 153 wherein the input information ("customer Peter") arrives. ~`
via the lines 157. In accordance with the foregoing3 the two most-significant bits of the input information select the information 0 0 1 0 in the store 152. Furthermore, as a whole the input information selects the information 0 0 1 1.1 0 0 0.
.
0 1 0 1 (901) in the store 1510 These two data appear in `~
the output registers 154 and 155. If the user program directly generates the customer number already, this infor-'' '' ~(~S;~3~
mation can be applied directly to the register 154~ but this is not sho~n for the sake of simplicity.
The outputs of the registers 154 and 155 are connected via the lines 156, 158, to twelve and four, respectively, most-significant bit positions of the twelve bit positions of the adding member 160 of the central processor 16. In the accumulator register 161 the sum of `~
the two data of the unit 15 is formed in accordance with the previously described principles. The adder 160 can pos-sibly also perform other operations for the benefit of ;
the other tasks of the central processor, and to this end it is also shown to be connected to outputs of the data register 163 which is not involved in the described processO
~tput information lines from the register 161 to, for example, the processing store of the central processor have been omitted. This is also applicable to the device which controls the operations of the units 15 and 16 in a synchronized manner~ and to the-protection against the indication of an ~'excessively high~' customer number. Pro-tection devices of this kind are known per se, for example, from Canadian Patent 967~287 which issued on May 6, 1975 in the name of ApplicantO
The storage disc 22-25 shown in Figure 2 (one disc can have one or two surfaces which are active for informa-tion storage) all comprise the same number of tracks for information storage, for example 20 tracks~and each track comprises the sa~e number of sectors, for example, 50 P~-IN 785~) - MUNS/EI~Sll~Y
01.12.75 .
~S33~5 ' sectors. The organlzation may alternatively be 100 tracks of 10 sectors each per disc. Each sector can accomrnodate the same quantity of informa-tion, for example, 2~6 by-tes (2 bits~. The discs are rotatecI together by the disc drive unit 21 by way of the sha~t 30 wnich is denoted by a stroke-do-t line. Rotation is at a uniform speed and the disc posltion detection unl-t 19 continuously applies a signal to the conversion unit 18 to indicate the lnstan-taneous ro-tation position. The rnagnetic heads 26..~29 can be simultaneously radlally moved across the cliscs 22...25 by means of the arrn control device 20 by way of the arms denoted by a broken line. As a result, always~four tracks are addressed at the same radial position relative to each other. Obviously, the organization of the heads may be different, for example, a stationary head ~or each track or multIpIe, movable heads per disc surface.
An attraotive organization conslsts in that the sectors of a track have successive sector numbers, for example, frorn 0-9, all sectors "O" then being situated in the same tangential position, etc. The disc surfaces are numbered, for example, from O to 3j and the cylind~rs are numbered from O to 99, going inwards from t~e outside.
~ The logic address thus generated is applied, via the line 38 in Fig~ 2 and via the line 165 in Fig. 4, to the conversion unit 18 so as to derive the physical address therefrom~ i.e. the crlinder number, the disc number and the sector numbeF. Per cylinder there are , . -16-.,. '. ' ' ".

~ 1'TIN '7856 MUNS/~?,L/S'rR~' 01.l2.75 ~ ~5337Si sectors a so that the logic address is divided by forty (0 0 0 0.0 0 1 0.1 0 0 0), the quotient determining the cylinder number and the remainder bei.ng sa-ved. ln the present e~ample 1413 : 40 = 35 (0 0 0 0~.0 0 1 0.0 0 1 1) 5 wi-th the rcmainder 13 (0 0 0 0.0 0 0 0.1 1 0 1), the rirst six bits of the remainder always being identical to zero.
Under the control of the number 35, the arm control. uni.t 20 is activated and the magne-tic heads 26...2~ are posi-tioned opposite the track 35 (which is the thirty~sixth track because the'track number 0 also exists). Simulta-neously, tlle remainder 13 (...0 0 1.1 0 1) is divided by 10 (...0 0 1 0 1 0) by the conversion.~unit 18. The quo-tient 1 (..0 1) gives the disc number, i.e. in this case that of the second disc 23, the remainder 2 (..0 1 0) gi~ing_ the sector number, i.~.in this case the third sector'.'because the sector number zero also exis-ts.
~ As is shown in Fig. 4~ -the information of the accumulator register 161 is applied, via the li.nes 165, to the register for the numerator in the con~ersion unit 18. The output of this regis-ter 183 is connected to the arithmetic unit 184. The regis-ter 185 for the 11an~.mi.-nator is filled from the static carry circuit 186 containing the information 1 0 1 0..., which is the representation of the ~umber of sectors per cylinder ~40). The subtrac-ting member 184 subtracts the contents of the register 185 from the conten-ts of the register 183, and returns the remainder to the register 183. If the numerator . -17-I'l-IN 785(, MUNS~¢L~S'I~Y
01,12.75 .

(remainder) ~as larger -than the denominator, this is detected by the control unit 188 and, via the connection denoted by a dotted line, a binary "I" is applied to the quotient register 182. If the numerator (remainder) was smaller than the denominator, the denominator is added again to the remainder wh:Lch ;s now negative. In both cases -the registels 183 and 182 recei~e a sh:ift pulse over one bit position from the control unit 1~8 (to -the left in the Figure). In this case the cylinder number will be known a~t~r se~en subtractions. The register 185 for the denominator is then filled with the information 1010 from the static carry circuit 187; this is the representa-tion of the number of sectors per track. In the present example, the number of discs is a power of 2 (22~? and as a result the information of the static carry circuits 186, 187 is the same in this case, but this need not neces--- sarily be so. The static carry circuits can be formed, for exampl~, by the posltions of a number of switches which are set, f~r example, when a background disc s-tore of a given type is installed. After two further subtractions;
the track number is also known in this case. The cylinder number is applied from the register 182 to the register 190 and is ~ompared with the position of the track countar ~ 192 by:the comparator 191. l'he result of the comparison is used for controlling the unit via the line 193.
When a track is passed, the position of the track counter is each time increased or decreased by one unit by means :!'TIN 7856 MUNS/I~L/SI`RY
C)1,12.75 ~S3~a'5 .
of` a track detector (not shown~. The two next-lower bits in the register 182 are decodecl in the decoder 171 so as to form a 1-out-of-4 cod-e 9 SO -tha-t only one o~ the four gates 172...175 is unblocked. These~ gates form part o~ the gate unit 17 in order to conduct only the information of one of the magnetic heads 26...2~. The r~mainder in -the regis-ter 183 indicates the sector number and is compared ~i.n a manner not shown) with the sector position detected by the unit 19. If the comparison device 191 supplies -the signal "correspondence", a central control unit actuate3 - the gates 172... 175 (with resu~t that only one thereof is opened) during the relevant sector (sector number corresponding~ to desired number), wi.th the result that the information can proceed to the central processor via the li.ne 162. In the case of a write operation, the re-levant magnetic head is actuated in the ~ame manner as the gat~s 172...175. The control units 1~9 and 164 may in--- eract so as to determine a priority between ~he devices 15 and 16 as regards the adding unit 160. The invention - does not speclfically relate thereto, so this will not be elaborated..herein. Instead of the arithmetic unit . 184, use can possibly made of an calculating member of the central processor 16. The central processor 16 can com-prise a processlng~ store wherein the information of one ~5 or more sectors can be temporarily stored. The disc store is then active as a background store, whilst neither the central processor 16, nor the units 14, 15 need contaln~ -. .

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mapping table of the background store so as to calculate addresses.
The described example~related to four discs .; .
comprising ten sectors per track. If these numbers are changed, only the information in the static carry elements 186, 187 need be changed. For the remainder everything remains the same in as far as the input signals of the ": ", , sector counter are not concerned. If the number of tracks is increased from 100 to, for example 200 per disc~
the comparison in the unit 191 changes: in that case another bit of highest significance must be taken into account. If the number of discs is changed~ the decoder `~
171 changes~ together with the denominator in the register 185. The unit 15, however, can remain unchanged~ provided that the value of the highest possible address fits in the said unit. In the foregoing the line 38 thus serves for the transport of addresses~ and the l1nes 39~ 40 serve fore the transport of information signals (Figure 2).
Within the scope of the invention Figure 5 shows the organization of ~hbackground store wherein the information elements are embodied in the presence or ab sence of magnetic domains.. Storage units of this kind are known f~o~ the previous Netherlands Patent Application 7316107 in the name of Applicant laid open to public inspection `
on ~a~ 28,1975 unit comprises domain guide structures which are composed of discrete elements in the form of~ for example T-bars or chevrons and which consist of permalloy which is vapour- -.,:,~, ..

~ 3~
deposited on the plate or plates of magnetic material ~garnet or orthoferritc), it being possible to -form and sustain domains in the said plates by means of a main magnetic field which is directed transversely thereto.
The stores are composed in accordance with the principle of main loops and auxiliary loops. In accordance with the simple diagram of Figure 5) the bac~ground store comprises two separate storage units 98, 99 only the functional , elements thereof being shown, which may be accom~odated on one and the same or on two different plates of magnetic material, and also the conversion unit 61. Under the con-trol of a sequence of a rotary magnetic field in the plane of the plate, the domains are driven along the domain guide structures, the shape thereof not being shown in detail for the sake of simplicity. If the rotary magnetic field rotates in the positive sense (counter-clockwise) the ;
sources 43, 63 produce a domain in each period. These domains are normally deflected at the diverging switches 44, 64 and are subsequently destroyed in the elements 61A~81. Under the control of a specific rotary field sequence ~comprising for example, a rotation of 7/4 periods in the negative sense) the domains can proceed in the for-" :
ward direc~ion. The distances 43/44 and 63/64 are unequal, so that the diverging switches can be separately controlled, in that synchronization occurs or does not occur between ; ~-the specific rotary ~ield synchronization for the straight -forward travel and the local presence of a domain. The de-'', '''~ ~
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responding position are introduced together into the main ;-loop~ so for example the domains 6~ 7 8. These domains successively reach the detector after irogressively in-creasing delay times of, for example, 8~ 10, 12~o periods of the rotary field. Only thè information of one detector is applied to the central processor. Assume that there :
are sixteen domain positions per auxiliary loop; the counter 100 then algebraically counts the number of periods of the rotary field sequence which is controlled by rotary lQ ~ield control unit 42. The actual rotary field generator is not shown for the sake of simplicity. The counter 100 is capable of counting periods in the positive as well as in the negatiYe sense and is therefore connected to +) and -) outputs of the device 420 If a given domain posi-tion is to be addressed~ the logic address thereof appears on the terminals 105, 114, 118, that is to say the most- -~
significant bit on the terminal 118~ the four next-lower bits on the terminals 105~ and the least-significant bits on the terminals 114. Obviously~ the registers 104~ 113 .0 117 can be combined to form a single register. The logic address ~ se does not contain information as regards the organization of the physical addresses in the storage.
unit>because this information is given only by the inter-nal structure of the conversion unit 61. This is applicable ~-inter alia regardless of ~he number of main loops, etc.
Simultaneously with the arrival of the logic address, the termina1 102 receives a positive pulse which sets thP

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~53375 vic~ can furtherlllore colllprise diverging swit~.h6s in series connection so as to form a specific inpu-t cod~ comprising at least two levels. Via converging switches L~5, 65, the conducted domains arrive in the ma:Ln loop.s 96, 97. V1a diverging s~Y.itches ~6, 48, 50, 66, 68, 7Q and converging switches 55, 57, 59, 75, 77, 79, th~se domains arrive, :if desi:red, in the auxiliary loops 90...95. Via the di-vergin~ switches 56, 58, 60, 76, 78, 80 and the converging sw:itches 47, 49, 51, 67~ 69, 71, they arrive in the main l~ops again and can be detected in the detectors 52, 72.
When they are deflected by the divergi.ng s~it~hes 53, 73, they can be destroyed in the elements 54, 74. The diver-gin~ switches 53, 73 are arranged to be shifted relative to each other, so that by the presence or absence of synchronization between the specific ~otary field sequence .
for the st~aight forward travel and the local presence of a~domain information can be selectively erased.
. . ~ :
If a given informatlon bit is to be addressed, the physical address is given by the identity of the de- . . .
tector or of the corresponding one of the main loops .~! .
96, 97, by the identity of the auxiliary loop whereln .- the said bit is stored, and by the position in the sequence of the domain positions in the relevant auxiIiary loop. . .
The detail A oY Fig. 5 shows the corresponding logic addres-~5 ses for three auxiliary loops, (for example, 93, 94, 95)~
domains present being represented by a dot and void domain positiions being represented by a circle. Domains of cor-, .
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flip~lop 101 to the "1"-position, thus activatirlg the com-parison unit 103. If the position of the coun-ter .100 cor-- responds to the information in the regis~er 104, an ou-tput signal of the comparison device 103 sets the flipflop 106 to the "1"~posi.tion~ and re~ets the f`lip:~lop 101 to the "0"-position. The output signal of the comparison clevice 103 a].so acti.vates the rotary fielcl control clevlce ~2 and counts to eight. The carry output signal of the counter 108 sets the fl.ipflop 109 to the "1"~position, and resets the flipflop 106 to the "0"-position. As a result, the coun-ter 108 remains in the position ~ero. These eight periods of the rotary field constitu1;e the delay incurred by the domai.n between the output of, for example, the auxiliary loop 95 and the detector 72. Subsequently, the counter 111 counts the next periods of the rotary .field sequence.
This counter comprises three stages, so it counts from 0 ~ ~ to 7. The positions of the hlgher two stages are compared - --- with the information in the register 113. The comparison ~ - - .
device 112 is activated by the output signal of the flip-flop 109, When correspo~dence occurs, the comparison de-vice 112 supplies a signal whereby the decoder 115 is ac-tlvated, the flipflop 109 is set to "0'l-position, and -the counter 111 is reset to the position zero. The delay~of .
: 89 10i 12, 14 periods in the arrival of the bits is thus implementéd (it is assumed that in this case there are four auxlliary loops per main loop). The decoder 115 decodes the posltion of the (one-bit) register 117 and supplies . .
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a pulse on one of the lines 116, so that the inL`orm~t:ion on one of the lines 119, 120 can be applied to the central processor (not shown) ~ria gates which correspond to the gates 172...175 of Fig. Il. After the read operation, the in-format;ion can be destroyed. The ;nI`ormation can alterna-ti-vely be rew~itten in the previous location. This i~ pos-sible because the counter 108 has a higher maximurn counting posit:ion, for example~ 6ll; the first output carry is used as in Fig. 5; the total output carry -then sets the f:Lip-`10 flop 106 to the "0"-position, and is also applied to the `
rotary field sequence control unit 42 which activates~ in the manner already described for unit 103, the diverging switches l~6, 48, 50, 66, 68, 70. D~ing the said 64 pe-riods, the information passes through the main loop once and four times through the auxiliary loops, so that the re-written information returns to the original posi~i~n. Li~e the organization of the storage unit shown in Fig~ 5, this organizatlon has no effect on~the logic address, but possibly only on the highest permissible logic address.
~ However, all other quantities relating -to the p~l~sical address, ~such as a number of detec-tors, the number of auxiliary loops, the numbe^ of bi-ts per auxiliary loop, and the initial delay (counter 108) can be changed, together with a di~ferent organization within the unit 61.
~ The conversion unit 61 can be connected to the central processor in the same manner as the unit 1g shown in Figs. 2, 4~ so that plug-to plug compatibility .

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exists. On the other hand, the device 6l can also comprise a calcula-ting member having a more ge~eral structure, so that a numher o~ divisions can be directly performed in-stead o~ by means o~ counters like ~n Fig. 5. However, these counters also represent calculating members of a special constructiorl. Ir the nwnber of auxiliary loops i9 increas~d, the comparison unit 112 must receive a ' plurality of bits, ~or example, 3; this can be realized by connecting the relevant register, for example 113, to the output of a multip]exer which recei~es the logic address and wh~ch can be read~lly set by an external spe-cial command. In this case the bits f`or the register .
sections 104, 117 must also be shifted over one position in the input address.
.:
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.

Claims (6)

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. A computer system comprising a central data processor, a conver-sion unit, and a peripheral device operative as a background store for secondary storage, said central data processor having a control unit for receiving user address signals and for generating on the basis of said user address signals universal logic address signals under program signal control, said background store comprising a plurality of storage sectors of uniform length each accommodating binary information elements in storage positions which are each time consecutively arranged within a storage sector, wherein each storage sector has a predetermined relative position and is separately addressable by a complement of respective physical address signals, each of said storage sectors forms part of a storage block which comprises a first predetermined number of storage sectors which number is specific to the said background store, and wherein each storage sector within a storage block is addressable by a first partial physical address signal, said background store comprising a second predetermined number of storage blocks each of which is addressable by a second partial physical address signals, said conversion unit comprising means for receiving said universal logic address signals, means for storing a representation of said first predetermined number as a para-meter signal, means for generating by means of a calculating member, on the basis of said universal logic address signals and said first predetermined number, first and second partial physical address signals, and means for forwarding said partial physical address signals to said background store.
2. A computer system as claimed in claim 1, in which each of said storage blocks forms part of a storage region which comprises a third pre-determined number of storage blocks which number is specific to the said background store, and wherein each storage block within a storage region is addressable by a third partial physical address signal and said background store comprises a fourth predetermined number of storage regions each of which is addressable by a fourth partial physical address signal, said conversion unit comprising means for storing a representation of said third predetermined number as a parameter signal, means for generating by means of calculating member, on the basis of said universal logic address signals and said first and third predetermined numbers, first, third and fourth partial physical address signals, the latter two together constituting second partial physical address signals, to said background store.
3. A computer system as claimed in claim 2, characterized in that the background store comprises a number of magnetizable disc surfaces where-on three address partial physical addresses identify the cylinder surface, the magnetic head and the track sector, respectively.
4. A computer system as claimed in claim 1 or 2, characterized in that the background store contains information in the form of magnetic domains.
5. A computer system as claimed in claim 1 or claim 2, characterized in that the said calculating member forms part of the central processor.
6. A computer system as claimed in claim 1 or claim 2, characterized in that the said conversion unit and the said background store are construc-ted to have common input terminals for the said logic address signals and common connection terminals for data transport.
CA241,963A 1974-12-20 1975-12-17 Computer system Expired CA1053375A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
NL7416631A NL7416631A (en) 1974-12-20 1974-12-20 CALCULATOR SYSTEM.

Publications (1)

Publication Number Publication Date
CA1053375A true CA1053375A (en) 1979-04-24

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ID=19822697

Family Applications (1)

Application Number Title Priority Date Filing Date
CA241,963A Expired CA1053375A (en) 1974-12-20 1975-12-17 Computer system

Country Status (8)

Country Link
JP (1) JPS566579B2 (en)
CA (1) CA1053375A (en)
DE (1) DE2555434C2 (en)
FR (1) FR2295480A1 (en)
GB (1) GB1536159A (en)
IT (1) IT1051173B (en)
NL (1) NL7416631A (en)
SE (1) SE417761B (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4156932A (en) * 1977-07-05 1979-05-29 Honeywell Information Systems Inc. Programmable communications controller
JPS6053763U (en) * 1983-09-22 1985-04-16 日鐵溶接工業株式会社 Welding wire charges

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1077985A (en) * 1964-06-08 1967-08-02 Farrington Electronics Inc Apparatus for reading
US3525081A (en) * 1968-06-14 1970-08-18 Massachusetts Inst Technology Auxiliary store access control for a data processing system
US3564513A (en) * 1969-01-31 1971-02-16 Burroughs Corp Address translator
US3562719A (en) * 1969-05-23 1971-02-09 Burroughs Corp Address translator
GB1447297A (en) * 1972-12-06 1976-08-25 Amdahl Corp Data processing system

Also Published As

Publication number Publication date
JPS5188142A (en) 1976-08-02
FR2295480A1 (en) 1976-07-16
JPS566579B2 (en) 1981-02-12
SE7514235L (en) 1976-06-21
GB1536159A (en) 1978-12-20
SE417761B (en) 1981-04-06
DE2555434C2 (en) 1986-07-24
IT1051173B (en) 1981-04-21
FR2295480B1 (en) 1981-08-07
NL7416631A (en) 1976-06-22
DE2555434A1 (en) 1976-06-24

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