CA1053359A - Protective relaying apparatus of the unblock type - Google Patents

Abstract

PROTECTIVE RELAYING APPARATUS
OF THE UNBLOCK TYPE

ABSTRACT OF THE DISCLOSURE
Protective relaying apparatus for power trans-mission lines of the unblocking type which utilizes a fault signal from a remote portion of the protected line to initiate a normal transient blocking timer which in the absence of a local fault signal (within its timing period) will initiate a desensitizing operation and pre-vent the tripping of the local breaker due to the presence of transient and an additional timer arranged to be ener-gized in response to a local fault signal and effective when timed out to initiate the normal transient blocking timer in the absence of the remote fault signal. In a modified form of the apparatus, the concurrent reception of the received and local signals (indicative of a fault in the line section protected thereby) deactivates the normal timer and prevents its further timing operation to increase the margin of coordination when transient blocking should not occur.

Description

BRIEF SUMMARY OF THE INVENTION
The inventlon is especially usef`ul ln protective relaying apparatus used to protect parall~l~ arranged trans-mission lines and consists in the use of a sc~cond timer actuable under certain ~ault conditions to determine the time interval that the normal transient bloc~.ing timer is i~nserted. It is especially desirable when the time req~ired for the signals which are transmitted between the remote and local end portions of the lines is relatively long and the breaker opening tlme is short.
-1- ~ , .

~s~3ss Fig. 1 is a s~ngle line diagram showing a palr o~ substakions interconrlected by a palr o~ transmlss~on lines;
Flgæ. 2A and 2B when placed sid~-by-side show, ~n bloc~ diagram form, a i~ault responding network embodying the lnve~tlon;
~lgs, 3, 4 and 5 are time chart~ u~e~ul in ::
expla~ning the 3nYention;
Fig. 6 ls a series o~ curves show~ng maxim~un and ~ -mlnimum tlme ~values of the transient blocklng t~mer and ls us~ful in under~tandirlg the operation o~ the invention; and Fig. 7 ~s a schems,tic dlagram sho~ing a modi~led ~orm o~ the trip output board (shown on the same sheet ~s Fig. 1).
BRIEF DESCRIP~IO~ OF THE PREFERRED ~O I~S~
Re~erring to the draw~n~s by characters o~ re~e-rence, the numeral 1 deæignates a first substation havlng -a bus Bl which m~y be Pnergized from any suitable ~ource and to which a transmission line Ll is conne~ted through a ~reaker lA and to whlch transmisæion line L2 is connected through breaker 2C. A second subs~tlon 2 ha~ing a s~cond bus B2 iæ suitably energized f.rom one ox more sources. The llne Ll is connected to bus B2 through breaker lB. Th~ :
l~ne L2 18 connected to bus B? through breaker 2D.
F~g. 2 illustrates a ~ault responding ne~wor~ 10 associated with a typical breaker 18 whlch connects a -typical line ~ to a typical bus Bo As lllustrated therein, th~ ~ault responding network ~ncludes f~rst ~nd second ~ault detector~ FDl ~nd FD2 which ~re ~upplied with current and voltage ~ignals ~rom the usual current and ~oltage ..

~05;~35~
transformers CT and PT~ The detector~ may take the ~orm o~ distance relays which ar~ actua~ed in response to a flaw o~ ~aul~ pow~r outwardl~ o~ th~ buæ B lnto the line ~.
The detector FD2 responds only to faults o~ very high cur-rent and d1rectly actuates the bre~ker trip circuit 12 to provlde an immediate trip signal over ~he cir~uit 14 to energize the trlp coil 16 and open the contacts 20 in ~he shortest pos~ible tlme. The breaker 18 also includes the usual 52b contacts and which when the breaker is ln a conditlon to con~ect the l~ne L to the bus B i~ open cir-culted ana which clo~e whan the brea~er 18 disconrlect~ the line L i~rom the buæ B~ The ~ault detector FDl responds not onl~ to the high poWer ~aults but to f~ult power o~ les~er magnitude and consequently will be actuated whenever fault occur~ within its reach.
The networ~c 10 further inclu~es ~ intelligence haJndllng network 22 which includes a tran~mitting portion 24 and a rec~v~g portion 26. When the ~ault detector FD1 detects a fault it provides ln output signal which i~ sup-plied to ~he first in~ut's connec~on 28 of an OR device 01 whleh ~n turn pro~ideæ an ener~izin~ nal to the trans-mltting portion 24 of the ~ntelligence ha~dling nekwork 22 which then pro~des an unblocking signal at lts output con-nection 30. The ~ntelllgence networks 22 o~ the fault re-sponding ne~work~ FRA and ~RC are ~nterconnected with the ~ault respond~ng networks F~B and FR~ respect~vely through sultable 81gn~l carrying channels illustrated ~n F~g. ~ a~
the power line carrier type but which could be o~ the micro-waYe or leased line type as well.
The output connection o~ khe ~ault detector FDl --3- ~:

5~
'-- 18 al~o connected to the lnput Or a ~lrst tlmer TDl and to tho lnput t~rminal 3a 0~ an a~ming board 33. The ~nput connection 32 18 connect~d through an OR n~twork 02 ~n~ ~n ANl~ n~twork Al to the lnput termin~l 34 o~ ~ tr~p output board 35 whlch includes a breaker tripping network 35B
compri~lng network~ A2 and A5. As w~ll be apparent ~rom the drawings a loglcal 1 output slgnal o~ the ~aul~ det~ctor }?Dl wlll appear a~ a oglcal 1 input ~lgnal at the lnput termlnal 34 and the Input term~nal o~ an AND n~twork A2 o~
the trip out~ut board 35.
The output of the tlm~ d~l&~ TDl lg conn~ct~ to an input termin~l 36 o~ the arrnlng bo~rd 33 whlch lnput term~nal i, 36 1~ conn~et~d to ~ne i~lpUt t~rminal o~ ~ DRIV~ R nctw~r}c 03; the output term~nal of ~h~hh ~ -onnect~d through ~ tlm~r Tl to on~ input te~mlnal of ~ .~4I~ network A3. The output termlnal o~ thB AND network A3 1~ connected to one ir~u~
ter~nal 37 o~ the tr~p output board 35 which ln turn 1~
conne~ted to one ~nput o:P an OP~ ne~work 0~. l'h~ output o~ ..the OR n~twork O4 13 e~nnected tc~ c~ne input of an AND network ;
A4. The output t~rm~nal o~ the ANI3 n~twQrk A4 18 connecte~ .
to th~ inp~ terminal of a translent~ blockln~ tlm~r TD2 The output o~ the tran~i~nt bl~klng timer 'rD2 i8 ~Upp~
through an OR network 05 to a ~ t lnput terminal 42 o~ the break~r tripplng natwork 35B wh~h i~ aormected to ~ ~irRt .~;.
- ln~ut ~rmlnal o~ ~he ~ network A~. Prlor to tlming out o~ the translent blocklng timer TD2 the OR network 05 supplle~
log~cal 1 ~ignal to tha AND network A2. Th~r~ or~ when the log~cal ~ sign~ 18 ~uppll~d by the ~ault d~t~ctor FDl to ~-.
a second input terminal 43 o~ the br~a~er trlI)plng n~twork 35B~
the other inpul; ~ermlnal th~ AND network A2 wlll provld~
log~cal 1 lnput clrcult to one l~lput terminal o~ a ~econd AND n~twor~ A5. Th~ o.ther lnput t~rm~n~l ofi the AND network A5 iB conn~ted through the th~rd ~put terminal 45 o:~ th~
breaksr trl~p~ng nettlork 35B and an OP~ n~twork o6 and a timer TD3 ~0 . . ~, - ~ , - . . , ,, .. :

another lnput terminal 38 o~ the trip output board 35, Unless a logical 1 signal is concurrently supplled by the ~ault detector FDl and by the receiving portio~ 26, the AND
network A6 of the arming board 33 cannot supply a logical 1 signal to the input terminal 38 to cau~e the timer TD3 to time out and supply a logical 1 signal to the AND device A5.
In the absence of this logical 1 ~ignal~ t~le A~rD devlce A5 i8 prevented ~rom supplying a logical 1 sign~l ~rom it~
output to an input terminal 39 o~ the breaker trip circuit 12 and no tripping o~ the breaker 18 will occur.
Assuming a condition in which the receiving por-tion does not supply a logical 1 signal to the input termi-nal 40 o~ the channel trlp board 41 but the ~ault deteckor ~Dl is actuated, the time delay TDl wlll time out and s~lpply a logical 1 signal to the DRIVER-OR 03, the timer ~1, and network A3, OR network 04 to the AND device A4. This ini-tiates the timing out o~ the transient blocking network timer TD2. At the expiration o~ its timing period, the logical 1 signal will be removed ~rom the upper input ter~

2~ minal of the AND networ~ device A2 to c~use the AND device A2 to remove the logical 1 input 3ignal supplied to the upper input o~ the AND network A5. Thi~ disables the AND
de~ice A5 and it no longer is abl~ to supply a logical 1 signal to the breaker trlp circuit 12 irrespecti~e of any trip signal or logical I signal supplied by the arming bvard 33 to the input terminal 38 of the trip output board. The time delay networkg TDl and TD2 as well TD3 resek ko their initial condition substantlally instantaneou~l~ with the remoYal of the logical 1 signal supplied thereto.

. . . . . . . ~ .. ~ . . . ~.. , . : . . . . .. .

41,086 - ~53359 Therefore, when the fault detector FDl no longer detects .a fault and supplies a logical O output signal, the time .~ :
delays TDl and TD2 will be substantially instantaneously '' reset. ' In modern day equipment, the fault detector FDl ~' does not immedlately become actuated or:does not immediately ; ~
reset upon the occurrrence o~ or a termination of the fault ::.
power flowing from bus B to line L. The interval reqùired to actuate the detector may vary from a low interval of one . ' 10 or two milliseconds to as much as 8 milliseconds or more '.
depending in the most part on the instant in~the sine wave that the ~ault occurs. Some change in delay may arise be- ~
cause o~ the fault current magnitude but normally the fault . ~.
current will.be sufficient so that the delay ls for all intents and purposes constant with respect to'fault current magnitude.. The resetting time is genèrally less and espe~
cially so when the fault power reverses. ' .
The re]~.ying apparatus wlthout the inclusion of ~.
the time delay TDl has been on sale since at leas'~ as ~arly '^' ..
.i . ~
as January 1, 1970 and is substant'ially that shown and des-cribed in a publication of Westinghouse Electrlc Corporation and identified as the "Type STU Unblock Relay" IL 41-959.4A
available from Relay-Instrument Divlsion, Westinghouse Electric Corporation, 95 Orange Street, Newark~ NJ 07101. `'~
While the apparatus without the timer TDl will performg the ~ .
addition of this timer TDl enhances its performance and ~ ~.
permits a more accurate control of the transient blocking - function when for example two substations are interconnected '.'.

by two separate power transmitting lines or networks, the .
. 30 breaker operating time is short and the channel time '' '' :.

3~5~
lnt~rconnectin~; the r~layin~s app~ratu~ at the tw~ sub-stations .
For pl~pO~e8 0~ ~xplanation, it w~l b~ a~ d that a fault F OCCUl'8 on the llne Ll. At tha ln~tant th~
~ault o~ ll o~ th~ breal~ers A, B, C and D will be clo~ed and fault powcr wlll ~low ~rom bu~ Bl through breakar A to the ~aul~ F~, irom the bu~ B2 throu~3h breal~er 13 an~ line Ll to th~ f~ F, ir~m~5Qu~ Ps2 ~hro~h breab:~r D, l1rle L2g breaker C" bus Bl ~d br~zker A to the ~au~t E'~ Assumln~s tha~ bre~k~r A open~ bs:~or~ braak~r B, the openîng o:f breaksr A în~rrupt~ ~atllt pouler ~rom the bu~ Bl to the ~au~t F.
~e ~ault ~ r form~rly ~lowlng throu~h ~h~ llne JJ2 now rev~rs~ and :~10W~ ~rom bu~ Bl through br~ r C9 llne ~2, breaker D~ bu2~ B2J break@r B ana line Ll ~o the ~ault F.
Wh~3N br~aXer B ~p~n~ the line Ll 1~ co~plete~y cut o~
:~rom the bu~ nd B2 and co~plsteîy interrupts all rault power.
Under th~ d~crlbe~ ~ault conditlong the lîne L2 ~;
~ not ~aultc~ and neîther breaker C nor breaker D should ~.
be act;uated to open clrcuit cond~tion. When the ~ault de-.
tector FDl a~oclated wlth ~ault responding network FRD con-troll~rig break~r D i~ actuated beca~e of' ~he P~ult p~Yer ~lowing th~oueh l~ne ~2 ~rom th~ bus B2, the receiving por- ;
tion 26 o~ the fault re~p~ndin~ net,work F`RC a~6~ciated with ~.
the br~aXer C receives ~n unblocking ~lgnal. The ~Qult~, deteetor FD~ o~ the network FRC w~ll nok.be actu~t~d ln re- -:
~ponse to ~ult p~wer fla~Y~ng ~rom the llne L2 ln~o the bu~
Bl ~nd bre~ker C wlll remain clo~dO During th~ inter~a~
wh~n th~ ~ault p~wer i~ ~l~ing ~Lnto the bu~ Bl its tr~n- .
~lent blocking t~m~r ~D2 1~ per~ormirlg it;B tim~ng ~unct~on ~`

-7- : .

~ (~S:~3S~3 as indicated in Fig. 3. This timer TD2 must time out and disable the AND device before the time instant t30 to insure that the network FRC will not trip the breaker C in response to the re~ersal of ~ault power flow through the line L2 which occurs when the breaker A opens prior to the brea~er B which is the assumed condition.
If the fault detector FDl of network FRD had no time delay in resetting and i~ there was no delay between the termination of the si~nal to the transmitting portion 24 of network FR~ and the termination o~ t~e output signal o~
the receiving portion 26 o~ nekwork FRC so that the logical 1 signal was immediately removed khere would be no possibllity that the network FRC would be concurrently energized from lts fault detector FD1 and ~rom its receiving portion 26 for a time interval sufficient to time out the security timer TD3 and no possibility o~ an unnecessary tripping of th b k C
e rea er During the lnitial fault period, the fault detec-tor FDl of network FRD will be actuated and not only cause its associated transmitting portion 24 to transmit the unblock signal to network FRC but will al~o suppl~ a logical 1 signal at the lower input terminal o~ AND network ~2 so that network A2 will suppl~ a logical liarmlng signal to the upper input terminal o~ AND network A5.
When the breaker A opens and the ~ault po~er in line L2 reverses in direction, the ~ault detector FDl of the network FRD will not immediately reset ko remove the arming logical 1 signal. If the fault detector FDl of network FRC
is fast acting and the fault detector FDl of network FRD is .~.
ælow in resetting and/or the channel time of the power ' ~

3~~5335g handling network No, 2 (Fig~ 1) is longer than 4 milli-seconds, the AND network A6 o~ network FRD could be actuated to provide a logical 1 output signal to its associated timer TD3 for a time interval greater than lts 4 millisecond timing period and cau3e an undesired tripping o~ the breake~ D.
In the prior art apparatus as disclosed in the qaid We~tinghou~e Electric Corporation publlcation wherein the tlmcr TD~l i5 not used, tha fault detector FDl directl~ r 10 inltiat~s the t1ming operation o~ the transient blocking timer TD2 æo that the .AND network A2 of network ~RC may under certaln condit1on~, not be disabled by th~ termina~
tion o~ the unblocking signal ~rom network FRD be*ore the ~ecurity timer ~D~ at FRC times out resulting in an unde-sired opening o~ the breaker C, Since the ~a~lt F might occur ~n either line ~1 or L2 and in ~uch a manner that the fault power in the un~aulted line could initially flow in elthe~ direction and either o~ the breakers of the f~u}ted ~ ~
lin~ could open ~irstJ each o~ the fault responding networks . ::
20 must be adapted toqperate in any o~ tha described po~itlons. ~:
It will be apparent ~rom th~ ~oregoing discus~ion and with . :
reference to the time chart of Fig, 3, which illustrates one possible ~ault combination, and as~uming 8 millisecond chan-nels between ~tation ~ 1 and station ~ 2 and the fault F at the loeation shown in Fig. i and ~urth~r assuming that ~or some rea~on or other FD2 failed to opera~e and initlate the tripping o~ breaker A, the earliest time that the breaker ~;
trip circuit 12 for breaker A could be actuated w~uld be ~:~
at time t20 when the timer TD~ times vut. m is requlres a .. ~ ~ .
~0 timing interval ~or timer TD2 o~ 21 m.s. so ~hat the transient _ g _ :

blocklng cannot occur untll after the Q~D networ~ A5 has energized the breaker trip circuit. mis interval of 21 milliseconds is long enough ~or the trip circuit 12 at location B to be energized.
Suppose9 however, khat the fault cletector d~d actuate to ener~izc the breaker trlp c1rcui~ at locatlon Ag the breaker A would open at time t25 and the :~ault currant ~lowing through line L2 to the fault ~ woul~ re-vcrseO Assu~ing the fault detector DFl at location C
responded with minimum delay also at time t25~ the assoc-~atcd timer TD~ would tim~ out at time t29, As illustrated ~n Fig. 3 thi~ is much sooner than tran~lent blocking can occur (t~7) and ~ince the AND network A5 of the ~ault re-sponding network 10 at C is now satis~ied it will energiæe its associated breaker trip circuit 12 and breaker C will be ~alsely oparated.
With the lower transmisslon ~oltages on the older line~, the brea~er~ operated much slower in ~rom 3 to 4 cy~les of a 60 Hz wave ~hich ln the ~rms o~ time would be -.
~rom 50 to 67 milliseconds. With such br~akers the percen-tage dif~erence in ~he optimum time intervals of the tlmers TD2 in the networks FRC and FRD was small and a comproml~e setting which would delay the disabling of the AND networkæ .
A2 as long as possibl~ to permit the networ~s ~RC and FRD
to be e~ective to reæpond to a subse~uent ~ault in line L2 and ye~ insure the disabling of the AND networks A2 be~ore the time in whlch the networks FRC and/or FRD could undesi-rably open the breakeræ C ~nd~or D.
t~ith the modern trend to higher and hi~her trans-mi~sion voltages and the consequent increase in fa~lt power 41,0~6 , ~, 335~3 when~a fault occurs, ~aster ~pening breakers became neces-sary and as a consequence modern breakers of guaranteed 2 cycle opening time have been developed and faster brea-kers are being developed. Because of manufacturing tole-rances some of these modern breakers open in as short a ~ :
time as 25 milliseconds or less. The time chart of Fig. 3 also illustrates the timing when the breaker opens at 25 milliseconds after the occurrence of the fault F, it~being assumed that with the closeness of ~ to the breaker lA
that a sufficlent magnitude of fault power existed to cause ~, `
the ~ault detector FD2 to:actuate the breaker trip circuit : ' 12 of network FRA directly and that- the line'Ll,is long ~. . ' enough so that only the fault detector ~D2 of the network ,;
..
FRB was not actuated by the fault.
When the breaker A'opened as illustrated in Fig. 3 . ~.;
by the lekter A within the c1rcle3` the directi.on of the ji~
fault power reversèd and assuming a fast.acting fault detec- '~
. ~ tor FDl at location C, the,s~curity timer TD3 at location C ',`. ~
will commence to time as indicated by the letter ~ within `,' :
20 the circle. Even assumlng that the fault detector FDl at ''.'~: :
location D immediately reset,.it would take an additional ,i ,~
8 milliseconds for the receiver 26 at location C to reset ~.~" , '' the timer TD3 and prevent the actuation of the AND network ,~ :
A5 at location C to prevent energizatior. of the breaker trip circuit 12 which would occur prior to the timing out .~ .
of the transient blocking network ~D2; which as stated above ,~ .
in connection with fault F~and TD2 of the network 10 at ,;

location A is the minimum setting to permit response of network 10 at location C to a nearby faulk in line L2. Under '~ `
these'conditions break~r C would be falsely actuated.
--11-- . .

. ~
`

~5335~ ~
With appllcant~s arr~ngement wherein an aadi- -tional timer TDl is provided~ the timer TD2 is delayed in its timing operatlon whenever such operation is ini-tlated by the associated fault detector FDl so that the minimum time delay afforded by the timer TD~ ma~ be re-duc~d sufficiently to permit the timing out o~ the timer TD2 at C to disable the AND network A2 prior to the tim-ing out o~ the securlty timer TD3 whereby false tripping of breaker C is prevented~ As will be discussed morQ
~ully below, the optimum time interval Por the timer TDl is the sum o~ the channel times in each direction and ~ince the channel times in each ~irection are u~ual~y equal TDl is tw~ce the channel time ~formulas ~10), (11), ~14) and (17)). me optimum intervalR of the timers TD2 may be determlned as set out below~formulas (~), (8), :.
(12) and (16)).
An examination of the Fig. 4 time chart which illu trates within an 8 millisecond channel time one set o~ possible operating times of the fault detectors FDl at .
the variou~ locations reveal~ that the security timer TD~
at location B causes a trip slgnal to be æupplied to the brea~er B at 12 milliseconds so that as far as network FRB
is concerned, the transient blocking timer TD2 o~ network FRB could time out at anytime after 13 milliseconds and pro~ide a margin time MB of 1 millisecondO
me transient blocklng in network FRC should occur be~ore and preferably not until 28 mill~seconds after the fault ~allowing a 1 milli~econd marginJ MC). It i9 assumed that the fau7t detector FDl of network FRD operated :: , at the tim~ 8 milliseconds. With a channel time of 8 .

'~ - ~
~o5i3359 milli~econd~ the rec~iver and tlmer ~D2 at FRC will be actuated at 16 millissconds~ The tlmlng out of ~he ~imer TD2 at C ls not later than 28 milliseconds wlth its opti-mum setting o~ 12 milliseconds. The optimum time ~or di~-abling the AND network A2 o~ network FRD is 36 milliseconds (assuming the same tlme margln MD o~ 1 mi~lisècond), Referring to Flg~ 4, whlch showæ the relative opera~ion of the networks FRC and FRD, it can be seen that the rel~tionships at C ma~ be expressed by two simultaneou~
e~uations as follows:
tD ~ Chnl (D~ C) ~ T~2C ~ MC = 30 (1) ~KA ~ tC + TD3C = 30 (~) wherein tD represents ths tlme at which the fault detector o~ the network FRD operat0s;
Chnl (D~ C) indica~es the channel time; which is the tim~ re~uired ~or the input signal to the trans~
mltter o~ ~he network FRD appear at the output of the recelver o~ the network FRC; -`
TD2C represent~ the time delay of the timer TD2 of the network FRC, MC represents the margin o~ coordination of the network FRC; :
BKA represents the tlme a~ter the fault occurs that the breaker A intsrrupts the currant therethrough;
tC represents the time that the fault detector FDl o~ the network ~C operates; and~ :
TD3C is the time interval timed out by the tlmer TD3 ~`~
o~ the network FRC.
These simultaneou~ e~uations ma~ be solved to determine ~he 30 required maximum magnitude o~ time delay o~ the timers TD2~ :

~, .
,' ~, ' .
- . - .. -..... ; - . ... . , ~ . , .:

~6)533S9 TD2(max) = BKA tD ~ tC - Chnl (D~ ~) ~ TD3C = MC (3~
Similarly the ~ollowing two ~imultaneou~ equations (4) and (5) ~or the timer relationsh~ps of network FRD may be established.
tD + TDlD ~ TD2D = ~D = 3~ (4) BKA ~ tC + Chnl (C-D) ~ TD~D - 34 (5) Equations (4) and (5) ~or the maximum value o~ TDl ~ TD2 reduce to TDlD ~ TDQD = BKA ~ tC - tD ~ TD3D ~ MD (6 10 As set out abo-re, a ~ult responding network 10 may be called on to per:Borm any of` the various ~unctions recited f`or the locations A, B, C and D dependin~ upon the location Or the ~ault F. It is therefore desirable to provide the same timlng interval ~or all of the timers TDl as well as the same timing interval f`or all the timers TD2. There-fore, the fQrlllula ~or TD2C may be combined with a :~ormula f`or TDlD ~ TD2D to provide the formula for the optimum maximum value o~ ~Dl.
TDl = Chnl (D-D~ ~ Chnl (~C)-~ 1 (7) 20 Normally the same equipment will be used ~or the fault re-sponding networks at the opposite ends o~ the protected line :
and the time ~ormula reduces to TDl = 2 Chnl.
The maximum opt~mum value o~ the time interval o~
.
the tlmer TDl is independe~ of the system components with the exception o~ channel time ~hile the maximum o-~ timing value o~ TD2 1~ dependent upon the relative tlmes at which -the fault dekectors FDl o~ the networks FRG and FRD operate and the ~ctual curren~ interrupting time o~ the breaker A~ `.
The minimum optimum values oP TD2 may be ascer~
30 tained ~rom the time re~ationships shown in Fig. 3 ~or the .: '.
`:

. .

~ ~ 5 33 S~
natwork~ FRA and ~RB, Similarly, as describad above equations may be derived for the times TDl ~ ~D2 o~
ne~work FRA and timer TD2 o~ network ~RB, ::
TD2 (mln.) - MB ~ TD3B ~ tb = tA - Chnl (A-B) (8) CTDl ~ TD2] (m~n.) = MA ~ TD~A ~ Chnl (B-A) + tB-tA ~9) Subtracting T~2 ~rom TDl ~ TD2 providcs the ~ormuJ.a for TDl TDl (min.) 3 Chnl (B;A) ~ Chnl (A-B) ~10) If the channel time A to B ls the same as B to A the formula ~-for TDl (min.) - 2 Chnl~
TDl (min.) - 2 Chnl. (11 With eight millisecond channel~ between networks FRA and FRB, it will be apparent that a tA-tB - 8 milliseconds, the minimum value of TD2 is determined to be 5 mllliseconds with a 1 millisecond margin ~ith a u5ual 4 millisecond time delay TD~ at all values of tA - tB which are positive or between ~ and -8 milliseconds. At negative values of tA-tB
greater than -8, it will be seen that the minimum value of TD2 in~reases until at a magnituds tA-tB equal to -15, 12 milliseconds iB the minimum value of TD2 to prev9nt tlming `~
out of the timer TD2 o~ network FRB so that it will not time our prior to the timing out of the corresponding network TD3 .:
of network FRB.
With a decreased channol time~ as *or example 4 . -millisecond~, the minimum value o~ TD2 occurs at tA-tB of

4 and the minimum value increase~ as the ~alue of tA-tB
: . . .
decreases to -15 to 16 milliseconds. It will also be appa-rent ~rom Fig. 6 that the maximum mill~second value of TD2 o~ networ~s FRC and FRD ~ncrease~ 1 millisecond with each increa~e o~ milliseconds in channel time and wlth aach ln-crease o~ 1 millisecond in the current interrupting tlme ,:

~53359 of breaker A~ Fig, 6 also shows an increase of 1 milli-sccond of minimum values of TD2 o~ n~twork~ FRA ~nd FRB
with each 1 millisecond of channel tim~, If it ls desired to determine the value of T~2 ::
in terms o~ the time t~KR that is required ~or the breaker to open af~er inl~iation o~ the breaker trip circuit and with the ~ub~crlpts following the TD'~ d~noting the loca-tion o~ the TDJ (See Fig, 5) the formula may be rewritten as follow~: :
kA + t~KR(~) ~ tC + TD~C) = ~D + Chnl (D-~C) ~ TD2(C) ~ MC
or TD2(C)-tBKR(A?~TD3(C)~tA~tC-tD ~ MC-Chnl (~ C) (12) tA ~ tBKR + tC + Chnl(C-D) + TD3~D~ - tD + TDl(D)+TD2tD)~MD
or MD+[tD-(tA~tC)~ = t~KR(A)~Chnl(C D)+TD3(D~-TDl(D) TDl(D) TD2tD) - tB~R(A)~TD3(D)~tA-tC-tD-MD + Chnl ~C~ D) tl3) by ~ubtracting (12~ ~rom (13) and a~suming TD2C= TD2D
TDl(D) = Chnl (C~ D) + Chnl (D~ C) + MC-MD tl4) tA+TDl(A) ~ TD2~A) = tB-Chnl (B-~A) -~ TD3~A~ + MA
or TDl(A)+TD2(A) 5 MA + tB-tA+TD3(A~ ~ Chnl (B~ A) (15 tA + Chnl~A-B~ + TD2~B) - tB + TD3(B) ~ MB
20 or TD2(B) - MB ~ TD~(B) -tA+tB - Chnl (A~ B) ~16) by subtracting 16 ~rom 15 and assuming TD2A = TD2B
TDl(A) = Chnl (A ~ B) ~ Chnl (B-~A) + MA ~ MB (17) ;~
I~ it is assumed that MA = MB and MC = MD, equatlons ~14) and (17) reduce to TDl(C) = TDl(D) - 2 Chnl (C-3D) (18) :
TDl(A) - TDl(B) ~ 2 Chnl (A~ B) (19) I~ it is also assumed that all o~ the channel :~-tim~s are equal then .
TDltA) a TDl(B) = TDl(C) D T~l(D~ ;
~0 Again i~ it is assumed that tD - tB+tC and TD2(B3 =

~0~ 9 ~:
TD2(C) and addin~ equations (12) and (13) TD2 = ~ TD3 Chnl mis simpli:eied value o~ TD2 will increase the margin time at locations A and B but since both of these ~ ;
breakers are to be opened, a~y delay in the timlng ou-t oP : :
TD2 beyond the timing out o~ TD3 is ~nnmater~al; it being the tim~ng out o~ TD2 be~ore the tlming out o~ TD3 at loca ~ions C and D which i9 important, Fi~, 7 show~ a modi~ied ~orm o~ trip output board 35A wherein like alements to those in the ~ip board 35 are re~erred to by the same characters o~ re~erence, The trip board output board 35A lncludes an AND device A15 which has ~t~ lower input t~rminal connected to the boar~ input ter- ~ :
minal 38 and has its input term~nal connected to the output terminal o~ the transient blocking timer TD2. The ou~put :
terminal of the AND device A15 i~ connected to one input -:
terminal o~ an OR devlce 015 ~hich has its output te~minal ::
connacted to one o~ the NOT nput terminals o~ an AND de- ~-vice A16. me output terminal of the AND devlce A16 is .:
connec~ed to the input te~minal o~ the transient blocklng network TD2, The input terminal 37 o-~ ~oard ~5A un~ike the input terminal ~7 of the board 35 is connected to one o~ the ~OT input terminals of the AND n~twork A16 and to the NOT
input terminal o~ the AND device A17, whieh per~orms the :Eunctlon~ performed by the AND networks A2 and A5 of the board 35. me output o~ the AND d~vice A17 i~ cor~ected to the lower NOT input terminal of ANI~ device A16 and to one lnput terminal of an OR device 016, the output terminal of which is connected to one of the input terminal~ o~ the AND
devi ce A17, The other input terminal o~ the OR device 016 ~(~533~i9 i8 connected ~o the ou~p~;.t ~ermlnal of the ~ime ~elay TD3. It will be apparent ~hat i~ the timing devlce TD2 ha~ not timed out and a logical 1 signal is received at the input ternqinal ~8 the. AN:D network A15 will supply a logical 1 si~;n~l through the OR network 015 to a NOT input termiLnal of the ~ND network A16 and thereby terminate the ~urther operation of thc timing tim~r TD2 and reset lt to it~ initlal condition.

Claims (2)

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. A relaying apparatus for protecting a section of a power transmission line having first and second end portions, said apparatus comprising a fault detector for detecting the existence of a power line fault as determined at said first end portion of said line, an intelligence receiving portion for supplying a fault signal when fault power is flowing into said line section at said second end portion of said line section, first and second and third timers, each said timer having an input circuit and an output circuit, each said timer being effective to change its output quantity at its said output circuit from an initial quantity to a timed-out quantity at the expiration of a predetermined programmed time interval following a change of its input quantity at its said input circuit from a reset quantity to a timing quantity, an OR network having first and second inputs and an output, means connecting said output circuit of said first timer to said first input of said OR network and said output of said OR network to said input circuit of said second timer, means connecting said receiving portion to said second input of said OR network and including said third timer, said OR network being ef-fective upon the existence of said timed-out quantity of said first timer to supply said timing quantity to said second timer independently of the operation of said receiving portion, said receiving portion being effective in the absence of said fault signal to supply said reset quantity to said input circuit of said third timer thereby to supply said timing quantity upon the occurrence of said fault signal, said OR network being effective to supply said input circuit of said second timer with its said timing quantity when said output circuit of said third timer is energized with said time-out quantity.

2. The apparatus of claim 1 including a breaker tripping network having first and second and third inputs and an output, means connecting said first input of said breaker tripping network to said output circuit of said second timer whereby said first input of said network is energized with a first control quantity solely when said output circuit of said second timer is energized with its said initial quantity, means connecting said fault detection to said second input of said breaker tripping network whereby said second input of said network is energized with a second control quantity solely when said fault detector detects the existence of a power line fault, and means connecting said receiving portion to said third input of said tripping network whereby said third input of said network is energized with a third control quantity solely when said receiving portion is receiving said fault signal, said tripping network being effective to provide a tripping quantity at its said output solely when all of its said inputs are energized with control quantities.