CA1049153A - Memory module - Google Patents

Abstract

ABSTRACT OF THE DISCLOSURE

A data processing system in which the operating logic thereof is arranged to provide for an overlapping of the access, or "fetch" operations such that access to a second memory module can be obtained by a processor unit before a data transfer has been completed with respect to a first memory module and read-out of the second memory module can process during the rewrite cycle of the first module to reduce the overall processing time. Such operation is made even more effective by arranging the system to utilize memory interleaving techniques. Further, the system of the invention can provide for multi-processor operation with a single memory system by the use of appropriate time-sharing techniques wherein processors can be operated in time-phased pairs, suitable multiprocessor control logic being arranged to provide for preselected priority allocations among the multiple processors to permit the most effective management of the multiprocessor system.

Description

~0~53 l~his invention relates generally to data processing syste~s and, more particularly, to high speed data processing systems adapted to utilize a single memory system with either one or a plurality of central processor units ~Iherein appropriate logic is available on each module of such memory system for increasing the overall operating speed o~ the memory system and further wherein an appropriate multiprocessor control unit is used to provide time-shared control of address and data transfers among multiple processor units and a single memory system.
In data processing systems it is conventional to utilize a single central processor unit (CPU) with a single memory system with appropriate control logic in the CPU for controlling the transfer of address and data information bet~een such units on suitable buses. In the design thereo~
it is desirable to arrange the logic control so that a processor is capable of operating with a memory unit even when the cycle time of operation is not the same as the cycle time of operation of the central processor ~1nit, i.e., the CPU and memory timing are not exactly synchronous and the CPU
can operate, for example, with memory units having different speeds of operation. Such non-synchronous operation is often most effectlvely arranged so -that the CPU and memory operating time cycles are not completely asynchronous but rather are quasi-synchronous, i.e., there is a de~ined phase, or time, relation between them. One such system has been described in ~.S. Patent No. 2~,01~,006 March 22, 1977 Sorensen et al.

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,: . ~ , :, ~4930S3 In making the most effective use of such a quasi-synchronous system it is desirable that the speed of operation of the overall system be reduced as much as possible by pro~iding for simultaneous operation of more than one memory module so that access to a second module can be obtained not only before the first memory module has comple~ed its rewrite cycle of operation, but even before the first module has completed its data transfer.
Further, since the design and fabrication of memory units is generally relatively more expensive than the design and fabrication of central processor units, one approach to reducing the overall costs of data processing systems is to provide accass to a memory sub-sys~em by more than one central processor unit.
If a single memory unit is made available to multiple ~PUs and appropriate address and data information transfers can be efficiently arranged and controlled at relatively little increase in cost and equipment, the overall effectiveness of operation as a function of cost can be considerably enhanced. Moreover, since only one ssction of memory is active at a time, utilization of the rest of ~he memory system can be more fully realized if more than one processor is sharing the system (i.e., more data can be processed per unit time).
Discussion of the Prior Art One method that has been suggested for providing a~
least pa~tially simultaneous operation of more th m one memory msdule has been to interleave the memory words stored in the memory syste~ so that sequential words normally stored sequen~ially in the same memory module are stored in different memory modules so that a data processing operating sequence can access dif~erent modules in sequence. Such interleaved systems

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~C~4~53 as are presently known tend to reduce the overall memory operating time by permitting access to a second memory module during the time when a first memory module is performing îts rewrite, or recycling, operation. In applications whera eYen higher overall operating speed is desired, the advantages of such interleaving principle of memory managemen~ are not always realized in the most effective manner.
Further, in presently known systems which arrange for the use of a single memory system by a pair, or more, of central processor units, the ~emory system is usually arranged as a combination of separate~ fixed-capacity memory modules and separate address and data buses, or ports, are connected be~ween ~-each central processor unit and each memory module of the memory system which is going to be accessed thereby. The number of addisional buses required increases both the complexity and the cost of the system and, while such space sharing techniques are helpful, the overall increase in data processing effectiveness ~;
per cost is not maximized.
In other multi-procassor data processing systems, a main central processor unit is appropriately connected to a memory system and the system operaSion logic is specially arranged to provide for a separate external data channel operating state so that another processor unit, external to the system, can be given access to the mem~ry system so that the desired data can be extracted for processing independently of the main central processor unit. In such a system, the external data channel operating state must be specially programmed so that the exte~nal processor unit can utilize the memery system onlr when the latter is available~ i.e., only when the main central processor unit does not desire access thereto. The complexity of the rcquired logic,the

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1~49~S3 need for additional interface equipment~ and the relatively inef~icient use of the system tend to make the overall effectiveness~ per cost of the system operation relatively lo~. -In accordance with this invention there is provided in a data processing system which includes a memory system comprislng at least one memory module for use with at least one processor unit and a data bus for transferring data between said processor unit and said memory system, wherein said processor unit provides a plurality of memory control signals for requesting the performance of a plurality of operations by said memory module, one of said memory control signals requesting the inhibition of a data transfer operation of said memory module, said memory module comprising means responsive to said one of said memory control signals for inhibiting the use of said data bus by said memory module thereby -to inhibit any current data transfer by said memory module.
In the data processing system of the invention the operating logic of the system is arranged so that access to a second memory module can be obtained by a central processor unit before a data transfer has been completed with respect to a first memory module and read-out of the second memory module can proceed during the rewrite cycle of the first module. The use of such overlapping of the access, or "fetch", operation of the memory modules reduces the overall processing time and is most effective when it is coupled with the use o~ interleaving techniques to provide an even greater reduction in processing time than is achieved with presently known interleaved systems. Such operation is advantageous whether the memory system is used for single, or multiple, central pro-cessor operation.
~ oreover, for multiprocessor operation of the data processing system of the invention, a plurality of central processor units are arranged to have access to a single quasi-synchronous memory system through the utilization o~ a unique time-sharing technique requiring a single address ~ - 5 -., . . . :
, ' ' ,' ,' ~

bus and a single memory/data bus which permits a high efficiency of operation with a relatively low additional cost incurred in the design and fabrication of the necessary control logic therefor. As explained in more detail below, in the time-sharing setup of the invention, if two processor units share the same memory system and do not require simultaneous access to the same memory module, each can operate at its own full operating speed without any degradation of overall system performance. If four - 5a -'~ ' ' ", ' ,' ,. "' ,'` ' ~'' ' : ', , ; ' ~ ' ,. , ` , .. ` ' ' :

~4~;3 proce~sors share access to the same memory unit the processor units can be operated in time-phased pairs, as explained more fully below, so that performance tegradation occurs only when two processor units in the same time phase require simultaneous access to the address bus or to the memory/data bus or when two processor units in different phases require access to the same memory module.
In the case of a multiprocessor system utilizing four central processor units, for example, every transaction, i.e., information transfer, on either the address bus or the memory/data bus is arranged to be performed in a fixed time period which has an intogral relationship with the minimum expected time period for an instruction word. For example, where the minimum instruction word time is 200 nanoseconds ~nsoc.)J
each bus transaction is arranged to be performed in 100 nsec.
The overall instruction word ti~e is, therefore, divided into two phases, one set of the central processor units performing the desired address and data transfers during one selected phase (i.e., an "A" phase) and the other set of central processor units performing ~heir transactions during the other selected phase (i.e., a "B" phase).
Control of the overall time-sharing opera~ion i5 ::
provided by the use of a multiprocessor control (MPC) unit operatively connected between the processor units and the memory , system. The MPC unit controls the priorities of use of the memory system by the Multiple processors in accordance with a presolected priority allocation among the processor units. For example, for a system using four processors, one of the processors is given the high~st priori~y, a second processor is provided with the next highest priority, and the remaining two processors aro given effectively equal, and alternating, priorities.

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~L0491~
More detailed information for implementing the inter-leaving and fetch-overlap process of the invention and for implementing the multi-processor control unit in combination with the central processor units and the memory modules of the memory system is provided below, with the assist-ance of the accompanying drawings wherein FIGURE 1 shows a broad block diagram of the system of the invention utilizing a single processor and memory system;
FIGURE 2 shows a block diagram of a typical memory module of the me~ory system of the invention;
FIGURE 3 shows part of the logic circuitry used in the memory module Or FIGU~E 2; .
FIGURE 3A shows a chart depicting alternative connection for the -.
logic cirruitry of FIGURE 3;
FIGURE 4 which is shown on the page of drawings along with FIGURE 10 shows another part of the logic circuitry of FIGURE 2;
FI W RE 5 shows still another part of the logic circuitry o~
FIGU~E 2;
FIGURE 6 shows still another part of the logic circuitry o~
FIG~RE 2;
20 , FIGURE 7 shows still another part of the logic circuitry of :
~IGURE 2;
FIGUR~ 8 shows still another part of the logic circuitry of FIGURE 2;
FI W ~E 9 shows still another part of the logic circuitry of FIGURE 2;
FIGURE 10 shows still another part o~ the logic circuitry of FIGURE 2; ~-~

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~049~LS3 FIGURE 11 shows a broad block diagram of the system of the inven-tion utilizing a plurality of processors and a common memory system together with a multiprocessing control unit therefor;
FIGURE 12 shows a graphical representation of one embodiment of the time-sharing -techniques used for the multiprocessing system of FIGURE 11;
FIGURE 13 shows a graphical representation of certain exemplary si~nals of the system of FIGURE 11 to demonstrate a particular operating case thereof;
FIGURE 14 shows a graphical representation of certain exemplary signals of the system of FIGURE 11 to demonstrate another particular operating case thereof; -FIGURE 15 shows another graphical representation of certain exemplary signals of the system of FIGURE 11;
FIGURE 16 shows still another graphical representation of certain exemplary signals of the system of FIGURE 11;
FIGURE 17 shows still another graphical representation of certain exemplary signals of the system of FIGURE 11;
FIGURE 18 shows still another graphical representation of certain e~emplary signals of the system of FIGURE 11; :
FIGURE 19 shows a block diagram of an embodiment of the multi-processing control unit'of the system of FIGURE 11;
FIGURE 20 which is shown on the page of drawings along with FIGUEE 12 shows part of the logic circuitry used in the multiprocessing control unit of FIGURE 19 _ 8 --, . .

1~4~1~S3 FIGURE 21 shows another part of the logic circuitry of FIGURE 19;
FIGURE 22 shows still another part of the logic circuitry of FIGURE 19;
FIGURE 23 shows still another part of the logic circuitry of FIGURE 19;
FIGURE 24 shows still another part of the logic circuitry of FIGURE 19, : :.
FIGURE 25 shows still another part of the logic circuitry of FIGURE 19; ~
FIGURE 26 shows still another part of the logic circuitry of : .
FIGURE 19;
FIGURE 27 shows still another part of the logic circuitry of FIGURE 19, and FIGURE 28 which is shown on the page of drawings along with FIGURES 23 and 2~ shows still another part of the logic circuitry of FIGURE 19 `
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~L~49153 :

As can be seen in FIGURE l, a single memory sys~em lO, , . ... .
comprising a plurality of separate memory modules, shown and discussed in more detailed drawings below, is arranged so that it can be accessed by a central processor UDit 11. The central procassor unit ll has access to an address bus 16 and to a memorytdata bus 17 so tha~ appropria~e processor address information can be transferred from the processor to a selected memory module and da~a can be transferred between such processor and the selected memory module. In the embodiment described herein, the address bus is an 18-bit unidirectional bus and the memory/data bus is a 16-bit bi-directional bus. The interfaca signals between CPU 11 and the memory system lO include five memory control signals 18, identified as MCl through MC5 for conveying information concerning address and da~a requests from :
tha processor to the memory. Two memory sta~us in~erface signals 19 from the memory system So the CPU provide information concern-ing the status of the memory module which has been accessed, such signals being identified in FIGURE 1 as the MSl and ~
signals. Additional signals Tela~ed to address and data port : -control opsration and address and memory select signals are also shown as being available for multiple processor operation with the single memory syst0m lO but are described later with respec~ :
to FIGURES 11-27 and, accordingly, arc not discussed at ~his point with rsspect to single processor operation.
Th~ overall m~mory sys~em 10 of FIGURE 1 can be divid~d into relatively small blocks, or memory modules, each typically containing 8~ or 16K memory words. Each memory module contains all of the timing and control logic needed for operation independently from each other memory module. For example, in a core memory system, if the processor is reading information from ", ~ ,' .
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~L~4~153 a particular memory module, as in an Instruction Fetch operation, for example, the rewriting of the data back into the addressed location in such module is done automatically by the module itself after the data has been obtained by the processor. The arrangement of the necessary logic in the memory motule for providing such a data rewrite operation without tying up the operation of the processor allows the processor to proceed to its next instruction or to process the data which has been retrieved, independently of the core memory system.
Further, the memory system may be arranged to be used in an interl0aving process. In non-interleaved memory systems, groups of memory words (e.g., instruction words) which are normally used in sequence are often stored in the same memory module. Accordingly, such sequentially used words cannot be made available simulataneously since access to only one module at a time can be achieved. The process of interleaving memory words reduces the chance that sequentially used memory words will reside in the same memory module and increases the chance that sequential worts can be accessed simultaneously. In accordance with such an in~erleaving memory word arrangement, words which are normally expected to be used sequentially are stored in diferent memory modules.
In an extremely simplified example for illustrating the interleaving principle, let it be assumed that the memory system comprises two mamory modules each storing 4 memory words, In a non-interleaved system, the 8 words which might normally be expected to be used sequentially ~i.e., words 0, 1, 2, 3, 4, 5, 6, 7), are stored so that words 0, 1, 2 and 3 ars in module #1 and words 4, 5, 6 and 7 are in motule ~2. In a two-way inter-leaving arrangement such words can be stored alternately in each ., - 1 1 -- . . . . ...................... . . : : . .: .

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module so that words 0, 2, 4 and 6 are stored in module #1 and words 1, 3, 5 and 7 are stored in module #2.
Extending the interleaving arrangement to an 8-way interleaving process ~i.e., a system using 8 memory modules), sequential words may be stored in different modules as shown by the following chart.
MODULES
#1 #2 #3 #4 #5 #6 #7 #8 ,, . . . , . :
~ ~ 1 2 3 4 5 6 7 ] 10 11 12 13 14 lS 16 17 ~ -words ]

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]'''''''' No m ally, without interlsaving, the most significant bit or bits (MSB) of an address identify the memory module which is addressed and the remaining bits of the address identify the particular word within a memory module. Thus, in 64K memory system using eight 8~ memory modules, a 16-bit address is ::
required, the first three most significant bi~s identifying the module which is addressed and the remaining 13 bits identi~ying one word of the 8K words within such selected module.
If the memory words are in~erleaved in an 8-way inter-leaving arrangement, i~ can be shown that the three least significant bits (LSB) identify the module which is addressed, while the remaining 13 bits identify one word of the 8K words within such module.

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, In accordance with the structure and operation of the memory modules of the invention, memory access and read operations are arranged ~o provide reduced overall processing time, whether interleaving is used or not. Thus, the operating logic is arranged to provide for access and read overlap wherein a processor is able to access and begin the read process with respect to a second memory module before data transfer has been completed with respect to a fi~s~ memory module, as exemplified in the discussion below.
Such oparation, when coupled with an arrangemcnt in which the modules are interleaved, provides a most ~ffective overall arrangemen~, The interleaving technique reduces the chances of requiring simultaneous access to two addresses in the same memory module. The overlap technique takes advan~age thereof by permitting access and read operation substantially simultaneously with respect to two different memory modules so that overall processing time is reduced considerably.
For example, if a first module (e.g., Mod 1) is addressed and data therein is to be read, and a second module (e.g., Mod 2~ is addressed immediately after the first module and data therein is to be read, both modules can proceed with their rsad and re-write operations in an oveTlapping manner as shown below. Each time period shown below is equal to a normal processor opera~ing time cycle (e.g., 200 nanoseconds, as mentioned above).

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~L9~53 to tl ~2 t3 ~4 ~5 t6 _ l ~ -? ~ - , CPU AddressRead Mod 1 COMMANDS Mod 1 ` ~ 3 ~ -Address Read Mod 2 Mod 2 MOD 1 Mod Not ¦Mod Reads ¦ Mod Core ¦ Mod Not OPERATION Busy Addressed Core Rewrite _ i Busy ~ ~ ~ , MOD 2 Mod Not lusy Mod Read~ Mod Core OPERATION Addressed Core Rewrite ~ ~ - > ~ ~ .,:'' Thus, the overlap operation permits both modules to be -~
accessed and read in only four time periods because the second module was permit~ed to be accessed and to begin its read operation before data transfer was completed for first module so long as two different modules were involved, the latter condition made more probable by the use of interleaving technique.
Thus, for e~ample, by the use of interleaving, the ~ime ~ -required to read or write four consecutive word locations is considerably reduced over the time required in non-interleaved systems wherein, for example, if the time required to read four consecutive word locations in a non-interleaYed memory system which uses overlap techniques is 3.2 microseconds, a two-way in~erleaved process for such a system requires only 1.2 micro-seconds and a four-way interleaved process requires only 1.2 ~icroseconds. The write time is similarly reduc0d from 3.2 microseconds in a non-interleaved system to 1.6 microseconds ` and 0.8 microseconds for two~way and four-way interleaving, respectively.

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~L049~53 As mentioned above, the memory system utilized in the invention is quasi-synchronous and each memory module is responsible for synchronizing data transfers to or from a memory module by the use of the two memory status lines as shown in FIGUR~ 1 which lines carry memory status signals MS0 and MSl.
If the processor requests access to a particular memory module and such module is in a "busy" stato because of a previous request for a data transfer, the memory module will asser~ the ~g~ signal to notify the processor of its "busy" status. When the module ultimately is free to service the processor, the signal is no longer asserted. If the processor wishes to read information from a pre~iously started memory module and the data is not ready for a "read" operation and the subsequent transfer on the memory bus, the module asserts the MSl signal to notify the processor that it must wait for validation of the data. When the module is ultimately ready for transfer, the MSl signal is no longer asserted and the data is available for transfer on to the memory bus.
If the processor wishes to write data into a previously -s~arted memory module which it has selected, the module will accept the write data immediately ~i.e., the M51 signal is not asserted) and it will prevent the stored data from being placed in the I/0 data buffer, and will ~rite the new data into the addressed location.
Control of the memory module by ~he processor is accomplished by the use of appropria~e logic for generating th~
memory control signals MCl-MC5. Such signals and the uses th~reof ar0 described in more detail below. The logic for the goneration thereof need not be tescribed in detail here as the generation of such signals for any specific processor system would be obvious , .

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~ 91S3 to those in the art. An example of such logic can be found in United States Patent 3,990,056, November 2, 1976, Ronald H. Gruner entitled "~icroprogram Data Processing System" and United States Patent 4,042,972, August 16, 1977,Ronald H. Gruner and Carl L. Alsing entitled "~icroprogram Data Processing Technique and Apparatus".
As can be seen with reference to FIGURE 1, the assertion of an MCl signal will initiate a start in a selected memory module if that module is currently not in a "busy" state. When the MCl signal is asserted, the memory address location is always present on the 18-bit physical address bus 16 and each memory module examines the memory address and the appropriate module is, accordingly, selected.
The MC2 signal is asserted when it is desired that any selected module not be started and such a signal can only be present when the MC~
signal is asserted. Ihus, if a memory module is currently not "busy" and the MCl signal is present for selecting such module, the assertion of the MC2 signal prevents the start of that selected module and the particular memory module remains in its "not busy" state.
The MC3 and ~ signals are asserted in combination and are appropriately coded as discussed below with respect to the analogous signals ~ associated with each of the processors so that a READ ONLY twith no "rewrite"
operation), a WRITE ONLY, or a READ (with a "rewrite" operation) occurs.
Thus, the MC3 and ~ signals identify-the type of data transfer which the processor desires to perform with reference to a selected memory module, once the processor has successfully started the memory cycle process.
The coding of such signals is set forth in the table below. AB shown therein, the designations T (for "True") and F (for "False") are used to indicate when such signals are asserted or not asserted, respectively.

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lL0491S3 MC3 MC4 Operation F F NULL, i.e., no transaction i5 to be performed F T READ ONLY~ i.e., the selected memory is to be read but the memory cycle is not yet completed T F WRITE, i.e., a Write signal is applied to the selected memory and the memory cycle is completed T T READ, i.e., the selected memory is to be read and the memory cycle is completed In connection with the abo~e code, if a READ-MODIFY^WRITE operat-ion is desired to be performed, the coded signals would firs~ indicate a READ ONLY operation, which is thereafter followed by a WRITE operation.
Either or both of the MC3 and MC4 signals are held asserted so long as the or hgi signal is asser~ed.
Assertion of the MCS signal indicates that a processor wishes to -inhibit the current data transfer portion of the memory cycle and, therefore, such signal inhibits the use of the memory/data bus by the memory module so as to leave such bus available.
A typical memory module for use with a single processor or wi*h ~ultiple processors is shown in FIGURE 2. Initially this discussion thercof relates to the use of a single processor with the memory systemJ and a description of ~he portions of the memory module which relates to mul~iple processor operation is pro~ited l~ter. While FIGURE 2 shows an overall - ;
i memory module arrangement in relatively broad block diagram form, specific logic for performing the ~unctions generally discussed below are shown in ~ ~
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FI~URES 3-lO. As can be seen in FIGUR~ 2, the address select logic 20 accepts !
the ~i and appropriate address input signals from the processor, which latter signals identify the particular memory module to which access is desired, as shown more specifically in ~IGURE 3. The memory module that is selected then provides an internal address select signal which is supplied : , . . .

~04~1S3 to the memory instruction logic 21 to star~ the memory module operation.
The latter logic accep~s the internal address select signal, as well as the memory control signals MC2, MC3, MC4 and MC5 to provide appro-priate internal signals for controlling the memory module operation for starting the me~ory module operation, for read and write operations, or for preventing the memory module from starting or from performing a data transfer, as shown more specifically in FIGURE 4.
The memory operating cycle is timed by memory timing generator 22 which is in the form of a conventiDnal Gray code timer which has a predeter-mined time relationship with reference to a system olock signal (SYS CLK) and which provides appropriate timing pulses internal to the memory module as required for memory opera~ion, as shown more specifically in FIGURE 5.
The memory status register 23 provides appropriate signals for indicating whether there is a ~ransfer of data pending with respect to ~he module, whether the memory module is waiting for a data transfer to be performed by another memory module, or whether the memory module is in the proper timing state to accept data for writing into ~he memory module. Such status output signals are responsive generally to tha memory operating signals and the memory timing output signals as well as the memory s~atus output signal MSl via status input logic 23A, as shown more specifically in FIGURE 6.
The latter signal is generated by mamory status logic 24 which provides both the ~ and MSl signals in response to appropriate memory operating and timing signals and also provides a signal indicating the BUSY - :
status of the memory, as shown more specifically in FIGURE 7.
The sensing logic 25 is responsive to the memory timing ou~put signals to produce ~he conv~n~ional read, write, strobe and inhibit signals for core memory operation, as shown more specifically in FIGURE 8. The priority a~bitration logic 26 and port comparison logic 27 are discusscd later with reference to multiple processor operation, and are shown more specifically in FIGURES 9 and 10, respectively.
The memory buffer registers 28 and 29 are of generally well-known coniguration, register 28 being the address-register which accepts the - '; ' " ' ' . ' .` ' ~
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~L~491~3 address signals and provid0s the memory address for the specific X/Y
core devices and register 29 being the memory data register for providing read data for transfer from the memory module onto the memory/data bus or for providing write data for transfer from the memory/data bus into the memory module. The structure and operation thereof is well-known to those in the art and is not described in further detail in the figures.
As can be seen in FIGURE 3, ~he address bits XPA2, PAl and PA2 represent the three most significant address bits of the 16-bit address signal (comprising bits XPA2 and PAl through PA15) which can be used to identify which of eight 8R memory modules is being addressed in an 8-module (64K) non-interleaved memory system. Alterna~ively, the three least signif-icant bits PA13, PAl4 and PAl5 can be used to identify which of eight modules is being addressed in an 8-way interleaved system, as discussad above. Various combinations of 2-way and 4-way and 8-way interleaving for a memory system using 8K modules can be arranged in accordance with the connections shown in the chart of FIGURE 3A. Moreover, additional address j ;
bits ~ and XPAl can be used to extend the memory capacity up to a 256R
memory sys~em, using thirty-two 8K memory modulcs, for example. In the latter case, five bits are required to identify the addressed module, the address comprising 18 bits. In any event, when an address in a particular memory module is selected, the ADDRSEL signal is generated by logic 20 together with the three memory address select bi~s ~MASEL 13, MASEL 14 and MASEL 15) representing the las~ three bits of the core address, which bits ~ -may be either the most significant bits, the least significant bits, or a combination thereof in ~he address depending on whe~her the system is inter-leaved or not.
PlGURe 4 shows specific logic for providing a START MEM signal when an ADDRSEL is present and no BUSY or MC2 are available to prevent such start. The DATA ENABi~ signal is provided for enabling ths memory data buffer register 29 provided the MC5 signal does not signify that a data transfer inhibit is required, and further provided the PORT COMP signal does not indicate that the module must await the data transfer of another module - . ; ' .. . . . . ' , . ~ ' ' ., , 9~53 (WAITING) and does indicate that a data transfer is pending (TRANSPEND).
FIGURE 5 shows the Gray code timing generator for gener~ting the four timing pulses (~G0, MTGl, MTG2, MTG3) required for Gray code timing operation, in accordance with wellknown principles. The memory timing pulses have pred0termined time rela~ionships with the timing pulses of the central processor unit which is controlled in accordance with the system clock (SYS CLK) signal supplied to the clock input of the timing register 29.
FIGURE 6 shows the status logic input 23A which provides the input signals to register 23 which, like the timing register 22, is in timed relation with the CPU clock via the SYS CLK signal. In accordance therewith the TRANSPEND signal indicates that a transfer of data is pending and, accordingly, is set whenever the memory module is started and is cleared whenever the data has been success~lly transferred to or from the memory module.The WAITING signal is set whenever the memory module is started and ~ -another motule already has a data transfer pending, in which case the module in question must wait for the other module to transfer its data. The WAITING
signal is cleared when the data transfer of the otheT module has been successfully transferred.
The MBLOAD signal is set when a write command is recei~ed from the processor and the memory is in a proper timing state to accept data for a "WRITE" operation into the memory module. This signal stays asserted until the end of the memory timing cycle. The MBLOAD signal is not set except for a "WRITE" condition and in all other conditions it rsmains unasserted.
The memory status logic of FIGURE 7 provides the ~g~, MSl and BUSY
signals. The ~g~ signal informs the processor that the module is busy and the MSl signal informs the processor that data is not yet ready for transfer (the memory has no~ yet reached the point in its timing cycle at which the data is available, e.g., the MT0.MTG3 point in the Gray code timing cycle) and, accordingly, such signals stop the processor operation un~il the data becomes available. Further, if the memory module is fulfilling a previous request for data transfer it provides a BUSY signal which also asserts the .. ..
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1a349~L~i3 signal to indicate the unavailability of the module for data transfer.
The logic 25 of FIGUR~ 8 is substantially conventional when using Gray code timing and is well-known in the art for providing the required READ l, READ 2J STROBE, INHIBIT and WRITE signals for X/Y core memory operation.
Although the above description has discussed the operation of the invention wherein a single central processor unit is used with the memory system, operation of a plurality of central processor units with a single memory system can also be achieved. Thus, as can be seen in FIGURE 11, a single memory system lO, comprising a plurality of separate memory modules as shown and discussed above, is arranged so that it can be accessed by four central processor units ll, 12, 13 and 14, identified as the A0, Al, B0 and Bl processors, respectively. A multiprocassing control (MPC) unit 15 is connected to each of the four processor units and to the memory system so as to provide appropriately time shared control of the use of the latter unit by the processors in accordance with a preselected priority relation-ship. Each of the central processor units 11-14 has time-shared access to the single address bus 16 and to the single memory/data bus 17, both dis-cussed previously in connection with the single processor oparation~ so that under control of the multiprocessor control unit app~.ropriate processor address information can be transferred from the processor to ~he salected memory unit and data can be transferred between such processor and the sel-ected memory module. The interface signals between aach CPU 11-14 and the multiprocessor control unit 15 each include five memory control signals 18, identified as XMCl through XMC5 ~where "X" identifies a particular one of the A0, Al, B0 or Bl processor units~ for conveying information concerning address and data requests from each procsssor to the MPC unit 15. Three additional interface signals l9 from the MPC unit to each CPU provide inform-ation concerning the validation of a processor's reques~s for access to ths address and memory/data buses, the latter signals being identified in FIGURE
1 as tha XADDRSEL, XMEMSEL and XMS0 signals (again where 1'X" identifies either the A0, Al, Bp or Bl processor unit).

- . , ~, . - ,., : .
., .,, . :., , ~ ' "",, , . . : '': ''. '~

~049~53 The interface signals between ~he multiprocessor control unit and the memory unit include five memory/data request signals from the MPC
to the memory, effectively the same signals supplied in a single processor operation and identified here also as signals MCl ~hrough MC5 and four port-code signals for uniquely defining the address and da~a ports of the request-ing central processor unit, such signals identified as the APORT0, APORTl, DPORT0 and DPORTI signals. Two additional interface control signals are supplied from the memory to the multiprocessor control unit to indicate whether a selected memory module is able to start a memo~y cycle and whether data from a selected module is ready to be read. Such signals are identified as above with reference to single processor operation as the ~ and MSl signals, respectively.
For the multiprocessor operation of the system of the invention the memory modules must be able to identify the requesting processor when such processor is either requesting access to or data transfer to or from a particular memory module. Such identification is established by the address port (A-PORT) code signal and a data port (D-PORT) code signal.
Each processor is assigned a unique port code. When a memory module is started by a requesting processor, the A-PORT signal (A-PORT0 and A-PORTl) is sent to the memory system together with the address and such A-PORT code is saved by the memory module which is thereby started, as mentioned above.
Before any data is transferred to or from the selected memory module for write or read operation, the A-PORT code which was saved must match the identifying D P0RT code ~D-PORT0 and D-PORTl) accompanying the data request.
Accordingly, the D-PORT code is always identical to the A-PORT code for any one processor.
Thespecific logic utilized in the multiprocessor control unit 15 is shown and discussed with reference to FIGURES 19 through 28 and, in the description which follows, the central processor units 11-14 are conveniently referred to, as shown in FIGURE 11, as processors Ap, Al, B0 and Bl, respect-ively.
Before describing the logic circuitry in detail, the time sharing . .
'. ~''''", ' ' .

~9153 process and priority control can be described with reference to FIGURE 12.
As can be seen therein, the minimum processor word cycle can be divided into anintegral number of successive time periods~ or phases. In one such convenient time relationship as specifically shown in FIGURE 12, the minimum processor word cycle is divided into two phases, identified as "A-Phase"
and "B-Phase", respectively. Thus, in a system utilizing a minimum processor word cycle of 200 nsec., for example each phase has 100 nsec. duration.
The system using four processors as in FIGURE 11 is arranged so tha~ central processors 11 and 12 ~A0 and Al~ can access the address and memory/data buses only during phase A, while processors 13 and 14 (B0 and Bl~
can access such buses only during phase B. In a system where only two processors are controlled by the multiprocessor control unit, one can be assigned to the A-Phase with the other assigned to the B-Phase. In such a case, as long as the processors are addressing differen~ memory modules, there can be no degradation in program execution speed. The only problem arises when each processor requires access to the same memory module, in which case a time sharing priority can be arranged.
In the case ~here a multiprocessor control unit is controlling the operation of four central processor units with a single memory unit, no conflict in address or memory data bus access can occur so long as the processors operating in any one phase do not require access to the same bus simultaneously and so long as a processor operating in the A-Phase does not require access to the same memory module as a processor operating in the B-Phase.
Accordingly, in a four processor system, if either of the A-Phase processors requires access to the same memory module as sither of the B-Phase processors, as appropriate inter-phase control must be arranged to provide appropriate priority of operation ~hsrebetween. Further, if a processor operating in a particular time phase requires access either to the address bus or to the memory bus simultaneously with the other processor opera~ing in the same time phase, an intra-phase priority control must also be arranged.

.. . . . . . .
. . ~

~049~53 The intra-phase control is discussed initially below with refer-ence to the A-Phase and the principles of such priority control are equally applicable to the B-Phase.
Since both ~rocesso~s A0 and Al share the same phase, one processor can be arbitrarily assigned a higher priority than the other. Thus, for example, A0 may be assigned the higher priori~y, so that when the A0 process-or requests access to a memory module it is provided such access as fast as possible, and any current processing that is being performed by the Al processor is suspended and processor Ap is allowed to proceed with minimum time latency. In order to understand how the control of such priorities within each phase is accomplished, consideration can be given to FIGURE 11 and to the timing diagrams of FIGURES 13 through 16. As seen in FIGURE 11, a processor is provided access to the address bus if, and only if, its unique -address selec~ signal (e.g., the ApADDRS~L signal or the AlADDRSEL signal) is asserted. Further, any processor is provided access to the memoTy bus if, and only if, its memory select signal (i.e., the A~MEMSEL or the AlMEMSEL
signal) is asserted.
In this connection and with reference to FIGURE 11 the interface signals between the multiprocessor control unit and each processor are particularly described below with reference to the A0 processor, it being clear that the analogous signals perform ~he same functions with respect to each of the other processors.
Thus, the assertion of the ~ signal by processor A0 indicates that such processor wishes to request a memory cycle. When it receives an ~i A0ADDRSEL signal from the multiprocessor control unit to indicate the avail-ability of the address bus, the A0 processor places an 18-bit address on the address bus 16 for addressing a specific memory module identified Ii thercby. The ~R~i signal is held asserted so long as the A~MS0 signal is asserted.
An assertion by the A~ processor of the ~E~ signal indicates that processor A0 wishes to inhibit its current memory cycle requsst and, accordingly, such signal can only be asserted when the ~ signal has been .... - , ,: . . . . :. . :. . .
, -. . ~ ; .
,,.. . ' ' .. ,' . : ,.. ,. ', : .'' .. , , . , , ,....... ~, ~

~9~53 asserted. Upon the assertion of ~-C2 the memory system will appropriately disregard the memory cycle request signal from the Ap processor. The A0MC2 signal is held asser~ed so long as the A0MS0 signal is asserted.
The A0ADDRSEL signal is asserted by ~he multiprocessor control unit 15 to indicate to the requesting A0 processor that it has access to the address bus. Such indication enables the reques~ing processor to gate the appropriate 18-bit address on to the physical address bus 16.
The assertion of the A~MEMSEL signal by the multiprocessor control unit indica~es to the requesting proccssor A0 tha~ it has access to the memory/data bus for a READ or WRITE data transfer. For a WRITE operation>
such indica~ion enables the requesting processor to gate the 16-bit WRITE
information on to the memory/data bus.
The A0MS0 signal is asserted by the multiprocessor control unit 15 during the A-Phase only when an address or a data transfer by She A0 processor is in process and during all B-Phases. When such signal is assert-ed during the A-Phase it indicates that the address or data transfer requested by the A0 processor is unable to occur. Accordingly, the reques~ing pro- ~-cessor must hold all of its control lines quiescent while the A0MS0 line is ~ ;
asserted.
In connection with ~he intra-phase priority control operation, e.g., as between the A0 and Al processors, various operating cases can be considered to explain the desired operation of the multiprocessor controller to achieve ~he appropriate priorities. Since the A0 processor is arbitrarily given the highest priority, the system is arranged so that the A1 processor has continuous access to the memory unit during the A-Phase only so long as the A0 processor is not requesting a memory cycle. Four operating casos can be considered to assist in understanding such a priority arrangement, such cases being exemplary of typical situations where priority allocations are required.
3~ CASE 1 , ~ .
In this case it can be assumed that the A0 processor wishes success-ive access to two different memory modules and that, during the kransfer of : ` . . , ., ~ ' ; ,. ~, . ' : , :' , . .
. :. , . . ~ , . . :

.

~L049153 data with respect to the second module, the Al processor calls for access to still another memory module. The appropriate signals for explaining such operation are shown in FIGURE 13 and, as can be seen therein, during the initial A-Phase time period the A0MCl signal calls for access by the A0 processor to the address bus which, since such bus is not being accessed by the Al processor, is accessed by the Ap processor ~the A0ADDRSEL signal is asser~ed by the multiprocessor control unit). The address of the first selected memory module (identified as MOD 1) is placed on the address bus.
During the next A Phase, the A0 processor calls for access to a second module (MOD 2) and receives an ~Zr---RSEL signal to indicate that the address bus is available, whereupon the MOD 2 address is placed thereon. Simultaneously, the A0MC3 and A0MC4 signals are asserted in accordance with a code signify-ing that a data transfcr operation is requested with respect to data in the first selected memory module, e.g., a READ or WRITE operation. If the data is not yet ready for transfer ~e.g., if the speed of the memory operating -cycle is such that data cannot be accessed within a single inst~uction word -cycle) the data is not available for transfer, i.e., a "not valid" situation, during the current A-Phase and it çannot be placed on the memory/data bus. ~ - -During the second A-Phase time period the ~ signal is asserted to signify that the A0 processor must wait until the next A-Phase because the microin-struction word cannot be complately implemented. Thus, in this instance, the microinstructuction word requests the placement of the MOD 2 address on the address bus and transfer of the MOD 1 date on th~emory bus. Since the latter cannot take place, the A0~MS0 signal is asserted here and the microins~ruction word is held until the next A-Phase. I~ should be noted tha~, as long as the Ap or Al processor has transfer pending, the MPC auto-matically asserts the ~ or AlMS0 signal, respectively, during the B-Phase.
During the next A-Phase ~he A0MEMSEL signal is asserted high by the controller to indicate that the data from MOD 1 is a~ailable for transfer and the data is thereupon transferred from such memory module to the A0 processor on the memory/data bus and tha MOD 2 address is placed on the address bus. The A0MS0 signal is asser~ed high during such address and data .. . .

.

34~53 transfer. During the succeeding A-Phase, the Al processor calls for access to a third module (identified as MOD 3) while the A0 processor is simultane-ously calling for access to the memory/data bus to provide for a data trans-fer from MOD 2. The A0MEMSEL signal from the mul~iprocessor control unit is inserted to indicate that the memory/data bus is available for the appro-pria~e data transfer from MOD 2 while the AlADDRSEL signal is simultaneously asserted to indicate the availability to the Al processor of the address bus for placing the address of the selected memory of MOD 3 thereon by the Al processor. In both cases the A~ and AlMS0 signals are not asserted to permit the respective data and address information transfers to take place on the appropriate buses.
During the next succeeding A-Phase, ~h0 A0 processor has completed its memory module data transfers so that the memory/data bus becomes avail able to ~he Al processor for transferring data with reference ~o ~he selected MOD 3. At that point, however, the data is not valid and such data cannot be placed on the memory/data ~us until *he AlMS0 signal is asserted low to hold the microinstruction word until the following A-Phase time period when the data is validated and ready for transfer. At such time the AlMEMSEL
signal is again asserted and the data from MOD 3 is transferred to ~he Al processor on the memory/data bus as desired ~the ~ signal is appropriate-ly asserted high).

In this case the A0 and Al processors call simultaneously for access to different memory modules. Under the assumed priority control the A0 processor is permitted to access its memory module first because of its high assigned priority and is allowed to complete its data transfer before the Al processor can access its selected memory module. FIGURE 14 shows the appropriate signals involved in a manner analogous to that discussed with referonce to FIGURE 13 and, as can be seen, the address for the selected module called for by the Al process is not placed on the address bus until the A-Phase time period following that A-Phase period in which the address of the memory module called for by the A0 processor has been placed thereon.

. .
. . . - ~
, - - ' ' :, ~1~49~l53 The address of the module selected by the Al processor can be placed on the address bus at the same time the data transfer to ~he memory/data bus is called for by the A0 processor, even though the actual A~ data transfer does not occur until the following A-Phase cycle. The transfer of data from the selected module of the Al processor cannot take place until the A0 processor's data is fully completed at which time the respective AlMS0 and A~MS0 signals are not asserted as shown. ~-Case 3 In this case the A0 processor calls for access to a selected memory module while the Al processor is in the process of transferring data from a previously selected memory module. Under such conditions as shown in FIGURE ~ ~
15, while the A0 processor can access i~s selected module the A0 processor ~ -cannot transfer data with respect thereto until the data transfer with respect to the moduls selected by the Al processor is completed. Thus, even though the latter data may not be ready for such transfer at the tîme the ii A0 processor requests access to its selected module, the Al module is per-mitted to completP the data transfer during the succeeding A-Phase time period before the data transfer for the module selected by the A0 processor is permitted to be made in order to prevent a memory system lock-up even though the A0 processor has the high priority. As can be seen in the next case discussed below, if the A0 processor wishes to retain access to the ;
address and data buses for subsequent memory selection and data transfer operations, the Al processor must wait until all of the data transfers for the A0 processor have been completed. ~ ;

.
In this case both the Al processor and the A0 processor each call for access to two successive memory modules, the Al processor, for example, beginning its calls for access prior to those of the A0 processor. As can be seen in FIGURE 16 the Al processor addresses its first select~d module (e.g., MOD 1), and, while it is calling for a data transfer in the next A-Phase time period, the A0 processor calls for access to its selected module (e.g., MOD 3~. Since the A0 processor has a higher priority than the Al .

~9L9~LS3 processor it receives priority control for its access to the address bus during the second A-Phase time period 50 ~hat the call for memory access (e.g., for MOD 2) by the Al processor is prevented and the selected address for MOD 3 is placed on the address bus by the A0 processor. During the next A-Phase cycle, the Al processor instruction word calls for a data transfer with respect to MOD 1 and an address transfer for selected MOD 2.
However, since ~he A0 processor has priority control of the address bus for subsequent addressing of its selected memory module ~e.g., MOD 4) the Al processor instruction word cannot be fully implemented. However, in order to avoid loss of ~he data that has been accessed by the Al processor with reference to its selected MOD 1, the data therein is placed in a buffer register located in the multiprocessor control unit ~identified in FIGUR~ 16 as the AlBUF) so that during succeeding phase cycles, such da~a remains available in the AlBUF until it can be transferred on to the memory/data bus. Placement of the Al data also allows MOD 1 to rewrite its data and, thus, become available for access by another processor (e.g., ~he A0 pro-ccssor). When the address bus becomes available, the address of MOD 2, selected by the Al processor, can be placed on the address bus. Meanwhile, the A0 processor is able to ~ransfer the MOD 3 data on the memory/data bus.
Since the A0 processor retains its access to the memory/da*a bus, the data stored in the AlBUF must be held therein until the memory/data bus becomes available. It is not until the A0 data transfer with reference to MOD 4, selected by the A0 processor, is completed that the data from the AlBUF can be transerred on to the memory bus. The data transfer with reference tO
MOD 2, as selected by the Al processor, can then subsequently be transferred in the next succeeding A-Phase cycle as shown in FIGURE 16. In each of the above operations the appropriate A~MS0 and ~3~ signals are asserted low when the microinstruction word cannot be implemented and asserted high when such word can be carried o~t.
The above exemplary cases in which appropriate priorities are arranged between Ap and A1 processor operation tor analogously between Bp and B1 processor operation~ deal essentially with intraphase priorities.

,' , ' , , : .

~49153 Although the multiprocessor control unit 15 can thereby efficiently allocate the desired priorities to resolve processor conflicts within each phase, a problem arises wh~n an A-Phase processor wishes to access ~he same memory module currently being used by a B-Phase processor. If an appropriate inter-phase priority allocation is not arranged, a high priority processor, e.g., the A0 processor, may be prevented from obtaining access to such memory module until a lower priority B-Phase processor, e.g., the Bl processor, has finished accessing such module, a time period which, under some conditions, could be extensive. Without such priority allocation the high priority A0 processor may have an excessive operational latency time (i.e., the time it must wait in order to obtain access to a selected memory module).
An effective inter-phase priority allocation can be arranged in accordance with the following coding scheme with reference to the memory address ports (designa~ed as the A-Port 0 and A-Port 1~
A-Port 0 A-Port 1 Priority ~ --0 0 Designates the processor having the highest priority (e.g., the A0 processor) which is provided with a minimum latency period in accessing a selected memory module by such -~
processor.
p 1 Designates the processor having the next highest priority (e.g., the Bp processor~
which is provided with a minimum latency ~ime only so long as the highest priority ! ' ... . .
processor is no~ requesting access to the same memory.
l 0 Designates a processor of one phase having a shared low priority (e.g., the Al processor) which is provided with a minimum latency time only so long as no other processor ~ -~i,e " either the A0, B0 or B1 processors) is requesting access to the same memory .

~. ,,. .: , : :,: . .,.: , . .. . .. . .

A-Port 0 A-Port 1 Priority .
module.
1 1 Designates a processor of the other phase having shared low priority (e.g., the Bl processor) which is provided with a minimum latency time only so long as no other processor (i.e., either A0, B0 or Al) is requesting access to the same memory module.
As can be seen from the above table, the low priority Al and Bl processors are given effectively equal priority allocation so that if a memory module is currently "busy" on the Al processor port and a request is pending from the Bl processor port, the memory module automatically switches to the Bl processor port on the next B-Phase, following the co~pletion of the memory cycle, assuming no higher priority reques~s from either the A0 or the Bp processors are present. In accordance wîth the operation of the above priority logic the port code of ~he processor port that initially starts the ~emory module is appropriately stored. If, at any time during the time the module is "busy" and such port code is stored, the memory module recelves a request from a still hîgher priori~y port, the previously stored port code is replaced by the higher priority code. When such high priority ~.!.
port code is saved via such a storage operation, a "priori~y swi~ch pending"
1ip-flop (providing a "PSP" signal) is set in the memory module so that it automatically switches to the stored high priority port during the next memory cycle, even if such operation requires a switching ofthe operating phase. If another request is made from an even higher priority code, then the priority port code which was previously saved is discarded and the new, higher priority port code is sa~ed. ~hen the memory module is in a "not busy"
state it will then only accep~ a request from the priority port which has been saved or a higher priority code which has displaced it.
As an illustration, if a memory module has been selected and, there-fore, has been set "busy" by the Bl processor port, for example, and a request is issued by the Al processor, the latter request is rejected since the ,': " :' .
, ,,, , . ' .
., , .. .. " . . . .
, ., : , . : , ~4~53 memory module is currently ~'busy"~ The Al processor por~ code, however, is saved and the priority switch pending flip-flop is set so that at the next memory cycle the Al processor is given access to the memory module as desired When the memory module becomes "not busy" during the B-Phase it will reject any new request from the Bl processor and in the next A-Phase it will accept the request from the Al processor port.
The priority flow could have been redirected in the above two cases under the following conditions. First of all, when the module selected by the Bl processor became "not busy" and a request was present from the B0 processor, the module would have accepted the request from B0. Since the ~ ~ -B0 processor is at a higher priority then the Bl processor, the memory pro cessor controller would have allowed the B~ processor to proceed to complete its data transfers on the B-Phase.
When the module selected by the Bl processor became "not busy" and ~ ~-switched to the A-Phase, a reques~ for access to the same module was present from the A0 processor port, the Al processor port request would have been held off by the multiprocessor control unit and the A0 processor request -allowed to proceed.
Two fur~her exemplary cases in which the above in~erphase priority ` ~
allocations can be illustrated are discussed with reference to the two situations depicted in FIGURES 17 and 18.

In this case depicted in FIGURE 17> the Al processor, for example, calls for access to and data transfers with respect to two different modules ~e.g., MOD 1 and MOD 2). The Bl processor then calls for access to and starts, the latter module (MOD 2~ before the Al processor has obtained its access thereto. As seen ~herein, the Al instruction word requlring the addressing of MOD 2 and the transfer of MOD l data cannot be implemen~ed because MOD 2 is ~'busy~ due to the addressing thereof and data transfer by the Bl processor. Accordingly, the data from MOD 1 is transferred to the Al buffer register ~i.e " as designated by the AlBUF signal) for temporary storage, while the Bl processor completes its MOD 2 data transfer and its :: ~ ' , ' ~ ........................................ ' '', :, ' ' , : .. '.' . ' ' ', ' ,.. ' , ' :

4~153 automatic rewrite opera~ion. After the latter data transfer, th~ Al pro-cessor can then address MOD 2 and simultaneously transfer ~he MOD l data from the AlBUF to the memory bus. Subsequently it can transfer the MOD 2 data on the memory bus, as shown.

The case depicted in FIGURE 18 illustrates the use of the above interphase priority allocations in a situation in which a high-speed memory is used (e.g., wherein the memory operating cycle is equal to the minimum instruction word cycle) and in which both the Al and Bl processors request access to the same memory module, the Al processor requesting such module prior to ~he Bl processor. In such case the MOD 1 data transfer with respect to the Al processor must be completed before the Bl processor data ~ransfer can be made, as shown.
~ .
The specific implementation of one embodiment of the overall multi-processor and memory logic required to provide the above priorit~ allocations with respect to a system using four processor uni~s and a memory system having a plurality of memory modules is shown in FIGURES 2-10 and 19-28. FIGURES
19-28 show the logic and control circuits u~ilized in the multiprocessing control unit 15 which circuits provide the required interface signals between the multiprocessor unit and the four processors and memory unit as well as the in~ernal ~ontrol signals needed in unit 15, while the previously dis-cussed FIGURES 2-10 show a memory module of the memory system lO and the logic and control circuits for controlling the operation of such a module and for producing the desired processor/memory interface signals, as well as the internal control signals needed in the module.
FIGURe 19 depicts in broad block diagram form the arrangement of the multiprocessing unit 15 wharein various logic circuitry is utilized to accept interface signals from the processors and memory unit and to produce the desired control signals for transfer to the processors and memory unit.
Thus the address and memory select logic 20 generates the ~ADDRSEL, XMEMSEL, and XMS~ signals for each of the processors (where "X" cnrresponds to one of the processors A0, Al, B0 and Bl) as determined by the MS0 and MSl signals . .

~4~1S3 from the memQry unit, together with the XMCl through XMC5 signals from each of the processors. A specific exemplary configuration for the address and memory select logic 20 is shown and discussed with reference to FIGURES 20 and 21. :~
Memory control logic 21 utilizes the XMEMSEL signals from the address and memory select logic 20, together with the XMCl through XMC5 signals from the processors to provide the appropriate control signals MCl through MC5 for the memory unit. A specific exemplary configuration for such logic is depicted in more detail in FIGURE 22. The port selection logic 22 utilizes appropriately generated internal control signals from the address and memory select logic 20 in order to produce the A PORT and D PORT signals for the memory unit. A specific exemplary configuration for such logic is ... . ... .. . .
depicted in more detail in FIGURES 23 and 24. The A-Phase port control logic 23 and the B-Phase port control logic 24 utilize the ~ and MSl control signals from the memory unit and the XMCl through XMC5 signals from the pro-cessors, as shown, in order to control the operation of the A-Phase and B-Phase ports which are supplied with appropriate control signals to indicate the "pending~, "wai~" and "buffer" status of such ports. A specific exempl-ary configuration for such logic is depicted and discussed in more detail with reference to FIGURES 25 and 26. Th~ buffer registers and buffer control lGgic 25 are depicted in more detail in PIGURES 27 and 28.
As can be seen in the address and memory select logic of FIGURE
20, a plurality of "JK" flip-flops 31-34 are used to determine which of the four processors is selected for access to the address bus or access to a memory module for da~a transfer thereto or therefrom during either the A-Phase or the B-Phase. The presence of an A-Phase or a B-Phase is defined by a system clock signal, which arises in a processor unit, and is fed to a "JK"
flip-flop 30 to provide the appropriate PHASE A and PHASE B clock signals at the output terminals thereof. The waveforms for such clock signals are shown in FIGURE 12. Flip-flops 31 and 32 proYide the appropriate address select signals and memory select s~gnals for the A0 and Al processors, while the flip-flops 33 and 34 provide the address select and memory select signals .:

.. - , . , ~4~5;3 for the B~ and Bl processors. In accordance with the logic shown in FIGURE
20 for the A0 and Al processors, for example, the AlADDRSEL signal is provided for transfer to the Al processor so long as the A0 processor is not request-ing access to the address bus through the assertion of its A0MCl signal. In the latter case an A0 select signal (SELA0) is appropriately generated to produce an A~ADD-RSEL signal indicating access ~o the address bus has been given to the A0 processor.
Similarly, access to the memory/data bus is provided to ~he Al processor as signified by the generation of the AlMEMSEL signal, unless the A0 processor is requesting access to the same memory module and is provided priority access thereto. Such priority access can be provided only so long as the Al processor has not already been given prior access to the memory/
data bus (signified by the presence of the AlP~ND signal), or so long as the Al processor is not loading its selected data into the Al buffer register (signiied by the AlBUFL signal), or so long as the Al processor is not completing an actual data transfer tsignified by AlXFER signal), or so long as there is no signal requesting a hold for the A0 processor operation (signified by HOLDA~ signal).
Similar operation with respect to address and memory selections occurs with reference to the B0 and Bl processors as shown with reference to "JK" flip-flops 33 and 34.
The remainder of the address and memory select logic 20 is shown in FIGURE 21 wherein the XMS~ signals are generated for feeding back ~o the processors. As seen therein, the address select the memory select signals sho~m in FIGURE 20, together with the memory select signals (~ and MSl) from the memory unit and the memory control signals XMCl through XMC4 are combined to produce the ~ signals which, when asserted, indicate which proeessor is holding the address and/or memory bus in a "busy" state.
Logic for producing the memory control ~ through hE~ signals which are supplied to the memory unit by the memory control logic 21 is shown in FIGURE 22. As seen therein, ~he appropriate memory control signals through XMC5) are supplied from the processors together with the ;' ... .. ..
.

internally generated address select ~SELX)signals, the memory select (XMEM) signals, the A and B phase drive signals from the address and memory select logic 20, and the buffer load signals (XBUFL), the s~ates of all of such signals thereby producing the appropriate memory control signals which, as discussed above, either in;tiate the start of particular selected memory modules, prevent the start thereof, initiate a data transfer thereto or therefrom, or inhibit such data transfer.
FIGURES 23 and 24 depict the logic for providing the A PORT and D PORT signals which are fed from the multiprocessing control unit to the memory unit. As can be seen therein, the appropriate in~ernally generated address and memory select signals (SELX and XMEM) with reference to each processor, together with the "Phase B" signal produces the desired port code signals which uniquely define the address and data ports of the requesting processor, as required.
FIGURES 25 and 26 depict the logic for controlling access to the A-Phase and B-Phase ports, which logic generates appropriate signals for indicating when the Al (or Bl) processors are utilizing such ports, either by holding them for a subsequent data transfer ~e.g., and AlPEND state), by holding them for an actual data transfer ~an AlWAIT state), or by holding them for a transfer to the buffer register for temporary storage of data (AlBUFL and A0BUFL states). For such operation the relationship among the memory control signals from the processors, the memory status signals from the memory unit, and the various internally generated status signals con-cerning the pending, wait and holding states as well as the address and memory select signals are required as shown.
FIGURE 27 shows the multiprocessor control unit buffer register system and the control arrangement thereof which includes a first memory/data bus buffer register 40 which is a single 16~bit registsr and has stored therein whatever data is on the mem~ry/data bus delayed by one-half of the minimum instruction word cycle (e.g., a 100 nsec. delay for the 200 nsec.
cycle discussed above). The data in the buffer register 40 is thereupon clocked into the output buffer regis~er 41 which, in effect, comprises four - 36 _ :. . . . . .
- ~

i~9~53 16-bit registers, one associated with each processor, the data from buffer register 40 being clocked into the appropriate register of the output buffer in accordance with the XBUFL signals at multiplexer 42. The data is held in the appropria~e output buffer register until the processor for which it is intended can accept it, at which point the Readsel is asserted so as to place the desired data on to the memory/da~a bus for transfer to the appro-priate processor as identified by the data port code signals DPORT0 and DPORTl. Thus, ~he buffer system permits data on the memorytdata bus to be continually monitored in the buffer register 40 and to be temporarily stored in the output buffer register 41 until the processor for which it is intended to be transferred is ready to accept it.
With respec~ to the operation of the buffer control register of FIGURE 28, the register is arranged so that the presence of a READSEL signal ~for placing data from buffer register 41 on to the bus for acceptanc~ by .
a processor) prevents the assertion of a WRITE signal so that such data will not be written back into the buffer register system. As soon as the processor : -accepts the data, the READSEL signal is no longer asserted and the WRITE
signal is appropriately asserted by the buffer control register so that whatever is in the bus register 40 is written into the buffer regist~r 41.

: , . - . . .
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. .
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. . . . . . .

Claims

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:

1. In a data processing system which includes a memory system comprising at least one memory module for use with at least one processor unit and a data bus for transferring data between said processor unit and said memory system, wherein said processor unit provides a plurality of memory control signals for requesting the performance of a plurality of operations by said memory module, one of said memory control signals re-questing the inhibition of a data transfer operation of said memory module, said memory module comprising means responsive to said one of said memory control signals for inhibiting the use of said data bus by said memory module thereby to inhibit any current data transfer by said memory module.