CA1044769A - Latching driver circuit and structure for a gas panel display - Google Patents

Abstract

LATCH DRIVER CIRCUIT AND STRUCTURE
FOR A GAS PANEL DISPLAY
Abstract The circuit and structure of a high voltage switch with latchup is disclosed for a latching driver used in a gas panel display. The driver circuit functions as a high voltage, single pole, double throw switch with memory. A plurality of the latch-ing driver circuits may be integrated on an LSI chip. Each posi-tion lighted on a gas panel display requires two latching driver circuits which are operated in a complementary fashion by suit-able logic. The latching driver circuit is comprised of a com-plementary transistor, high voltage output switch which is con-trolled by a positive feedback silicon controlled switch which serves as the latching mechanism. The structure of the latching driver is of an advanced integrated design employing a plurality of lateral complementary transistors in two isolation regions.

Description

FIELD OF THE INVENTION
The invention relates to an integrated monolithic switch for high voltage application. More particularly, the invention relates to drivers for gas panel displays.
CROSS REFERENCES TO RELATED APPLICATIONS AND PATENTS
This application concerns an improvement in the coordinate line driver circuit with latching control shown in ~igure 3 of the - United States Patent 3,811,124 to B.G. Kleen et al which is assigned to the instant assignee. The Kleen et al United States patent is entitled "Solid State Gas Panel Display Circuits With Non-Inductive Solid State Isolation ' :
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,7~t3 1 Between Low Level Logic and High Level Drive Signal Functions"
and discloses the system environment in which the instant in~
vention finds its principal application.
Another related patent is Canadian Patent 929,253 issued .
June 26, 1973 by T.N. Criscimagna, et al, and entitled "Method and Apparatus for a Gas Panel Display" and assigned to the ~ :.
assignee of the present application. . :
BACKGROUND OF THE INVENTION ::-Prior art gas panel display control systems are not easily .
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adapted to parallel selective manipulation of an entire line of discharge sites spanning one panel coordinate. Thus, since it is . .
usually necessary to interpose at least one sustaining cycle be~
tween successive writing operations (to prevent excessive dissi- ~ .
pation of existing polorization conditions of the gas panel), the max~mum range of panel write/erase manipulation in such systems is ~
~ significantly curtailed by comparison to a system having full `~ parallel line write/erase capability. The above-mentioned Kleen, .
et al U.S. patent 3,811,124 solves this problem with thc prior art by including a field effect transistor latch along with the high , 20 voltage driver switching circuit. This enables the rapid pre-'. conditioning of a large number of the latc'ning FET elements selec-tively, one at a time (to set up selective drive switching control ;
conditions for parallel manipulation of a full line of ;'i .
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"'~ ,' :,'. : ~, ",. "' ~, `' '' ~ .'' ~3 1 panel sites in one coordinate direction, row or column) ; 2 during a fraction of the quiescient sustaining period 3 preceeding each write/erase manipulation. The contri-4 bution of the Kleen, et al patent includes among other ; 5 things, the association of a latching circuit with the 6 high voltage driver to permit extremely fast precon-7 ditioning of the drivers on the order of nanoseconds, 8 in comparison to the minimum duration of a write/erase 9 cycle on the order of multi-microseconcls, permitting the selective preconditioning of latching elements 11 associated with an entire line of gas panel displays ' 12 sites. This permits the manipulation of any part or 1 13 the whole of a line of panel discharge sites in each 14 write/erase cycle.
The invention disclosed herein, improves 16 upon ~he design of a high voltage driver and latching 17 circuit shown in figure 3 of the Kleen, et al patent 18 by increasing the switching speed of the latching 19 driver circuit while decreasing both the size of the ~ 20 circuit and its heat dissipation.
:' 21 OBJECTS OF THE INVENTION:
1 22 It is an object of the invention to increase 23 the speed of operation of a high voltage latching 24 driver.
It is another object of the invention to 26 redu~e the size of a high voltage latching driver. -~
' 27 It is still another object of the invention -~
, 28 to reduce the heat dissipation per unit area for a 1 29 high voltage latching driver.

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1 It is still a further object of the invention

2 to provide a high voltage latching driver for a gas

3 panel display of an improved design.

4 A further object of the invention is to layout a silicon controlled switch for a latching driver in a 6 smaller area than has been done in the prior art.
7 An additional object of the invention is to .
8 layout a latching driver in an integrated circuit which 9 occupies less space than has been done in the prior art.
SUMMARY OF THE INVENTION ~.
11 An improved high voltage latching driver is 12 disclosed for use in a gas panel display. A pa:ir of 13 monolithic semiconductor bodies, one for each gxoup 14 of row conductors and column conductors in a ga~ dis-lS charge panel display, contain a plurality of functionally 16 idential high voltage latching drivers. The circuit con-17 figuration for the high voltage latching driver includes 18 a high voltage switch formed by a pair of complementary 19 bipolar transistors with a first NPN transistor having a collector connected to a high reference pokential and 21 its emitter connected to the emitter of a first PNP
22 transistor having its collector collected to a low .. ....... . ..
23 reference potential. The emitter node constitutes an 24 output node connecting to one of the panel conductors.
:l 25 A silicon controlled switch is connected to the base 26 of the first NPN and the first PNP transistors of the ~ 27 high voltage switch to control the alternate conduction 1 28 of these transistors, in response to an input con~xol l 29 signal to the silicon controlled switch. The silicon ;
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~ 30 controlled switch is operated in a positive feedback . . :
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1 mode therehy providing a latchinq of the conductive 2 state of the high voltage switch in its selected state.
3 The associated panel conductor is thereby selectively 4 connected to either the high reference potential or the low reference potential thus enabling the write or 6 erase function to be performed on the qas panel sites !''' 7 associated therewith.
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8 An improved structure for the latching driver ~- 9 is also disclosed which is of an advanced integrated design employing a plurality of latera:L complementary 11 transistors in two isolation regions. The circuit 12 structure disclosed permits the implementation of a 13 latching driver which has a higher switching speed, 14 a smaller size, and a lower power dissipation, than do high voltage latching drivers disclosed in the 16 prior art.
17 DESCRIPTION OF THE DRAWINGS:
18 The foregoing and other objects, features, 19 and advantages of the invention will be apparent from the following more particular description of the . . .
21 preferred embodiments of the invention, as illustrated .
22 in the accompanying drawings.
23 Figure 1 is adapted from figure 2 of the 24 Kleen patent and illustrates the control circuitry for the gas panel display~
26 Figure 2 is adapted from figure 3 of tha Klesn 27 patent and shows the prior art latching driver circuitry.
28 Figure 3 is a circuit diagram of the latching 29 driver invention.
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" ., 1 Fi~ure 4A is a circuit diagram showing the 2 operation of the latching driver invention in the sus-3 tain mode for the first half period.
4 Figure 4B is a circuit diagram illustrating the operation of the latching drivex invention in the sustain ,.- . .- . ., - .. .
6 mode for the second half period.
7 Figure 4C is a circuit diagram of the operation ; ~ of the latching driver in the write or erase mode when 9 the bit is selected.
Figure 4D is a circuit diagram of illustrating 11 the operation of the latching driver for the write or -12 erase mode when the panel site is deselected.
; 13 Figure 4E is a circuit diagram illustrating the 14 operation of the latching driver in the write or erase mode when the panel site is half selected in the X con-16 ductor.
I 17 Figure 4E' is a circuit diagram illustrating the i 18 operation of a latching driver in the write or erase .-i . . :, ! 19 mode when the panel site is half selected in the Y con-j 20 ductor.
21 Figure 5A is a diagram of the layout of the ' 22 integrated circuit structure or the latching driver 23 invention.
24 Figure 5B i8 a cLetailed diagram of the layout of the silicon controlled switch structure for ~he latching ;;
.1 ~ , 26 driver shown in figure 5A. :~
27 Figure 6A is a cut-away view of the silicon . . -i 28 controlled switch along line A-A' in figure 5B, showing . ~ :
, 29 the lateral transistor structure.
;I 30 Figure 6B is a cut-away view of the silicon 31 controlled switch along line B-B' in figure 5B.

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1 DISCUSSIOI`l OF TH~ PREFERRED EMBODIMENT
2 The latching driver invention herein is an 3 improvement of the latching driver circuit of fiyure 3 4 of USP 3,811,124, assigned to the instant assignee.
Figure 3 shows the circuit diagram of the latching 6 driver invention. The conductor bus 50 of Vu i~ the ~ ~-7 same conductor bus as the "UBR (upper bus)" of figure 3 8 of the Kleen, et al patent. The conductor bus 52 or 9 V~ in figure 3 is the same as the conductor "LBR
(lower bus)" shown in figure 3 of the Kleen, et al 11 patent. The SET line of figure 3 in the Kleen patent 12 corresponds to the SET line in figure 3 of the instant 13 application. The RESET line o figure 3 of the Kleen 14 patent corresponds to the RESET of figure 3 o the lS in~tant application. The C~ data line of ~igure 3 of 16 the Kleen patent corresponds to the line 2 input to 17 the base of transistor T10, with the T10 emitter 18 connected in the "Y" configuration 16 to the base of 19 T9, as shown in figure 3 of the instant application.
The line ~ data Shown in figure 3 of the Kleen patent ;;~
21 corresponds to the line 2 input to the base of the 22 ~ransistor T10 when transistor T10 has its emitter 23 connected to the X position 17 to the ba~ of transistor 24 T8 of figure 3 in the instant application. Thus it is seen that the latching driver circuit shown in figure 3 -~
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26 of the instant application can be connected into the 27 gas panel display control system shown in figures 2 and -~
28 3 of the Kleen, et al patent.
29 It is seen that the operation of the latching driver circui~ disclosed herein is similar to that ~ '' ' ,. ~ ' M~9_74-001 7 : ' ' l disclosed by Kleenl et al, and illustrated in his table 2 at column 6 lines 40-53 as follews:
3 Table I:
4 Drive Control~Latch Element Relationship~
Axis Sustain Write/Erase ~ ~-6 Select l/2 Select Deselect 7 X Se~ (All X) Reset Reset Set Set 8 Y Set (All Y) Set Reset Set Reset 9 Figure l in the instant disclosure is an adaption of figure 2 of the Kleen, et al patent and ll illus~rates the system diagram for the control for the 12 gas panel display. One object of the instant invention 13 is to reduce the overall size of the circuitry for the 14 latching drivers in the ga panel display. Figure 3 illustrates a schematic diagram o~ the decoding logic 16 and latching driver circuitry which can be integrated ;
17 on a single small chip. Shown in figure 3 is the one ~, . . . ~ . .
18 out of 5 of the inverter pairs 4 for the decode input 19 for the line decoder 47 shown in the KIeen, et al -~
~, 20 patent. The diode D12 is one of the line decode diodeR.
`~ 21 The section decode inverter 6 is one out of three in-. .
22 verters for the section decode 43 shown in igure 2 of ; 23 the Kleen, et al patent. The diode D13 i8 a section 24 decode diode. Figure 3 shows the SET and RESET emitter I 25 followers 8 comprising transistor T16 and transistor ;l 26 Tl7 of whlch there is one circui~ per chip. Line 10 ~-~
27 fxom the emitter of transistor Tl6 is output from the -~ 28 SET~RESET circuit 8 to the base of transisto~ T8. ~ine 29 11 from ths emitter of transistor 17 is output from ~he SET/RESET circuit 8 to the base of T9. The selective :.f , MA9-74-001 - 8 - ~ ~

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r7 ~6 t3 1 connection of the emitter of T10 with either the base 2 of T9 or the ~ase of T8 corresponds to the use of the 3 latching driver as a Y line driver or an X line driver, 4 r~spectively. This corresponds to the Xleen, et al designation of X as the row and Y as the column con-6 ductor. Tr~nsistors T8, T9, and T10 of which there 7 are 32 per chip, function as the on and off current 8 drivers for the silicon controlled switch in the 9 latching driver of figure 3. With a positive signal of the S~T line, T9 is turned on delivering current 11 to the terminal 12 of the latching driver. When the 12 positive signal of the reset occurs, T8 is turned on ;
13 delivering current to the terminal 14 of the latching ~ ~ ;
14 driver. When the chip is a Y driver chip, T10 has its i' ' .:
emitter connected to the base of T9 so that when the 16 driver is selected, T10 is turned on and it turns on 17 T9 delivering current to the terminal 12 of the latching 18 driver. When the chip is an X driver chip, the emitter 19 of T10 is connected to the base of T8 so that when the m driver is selected, T10 is turning on the transistor ` 21 T8 uhich delivers current to the terminal 14 of the 22 latching driver.
i 23 The latching driver shown in igure 3 co~lprises ; 24 a silicon controlled switch which is the combination of the PNP transistor T3 and the NPN transistor T2, where 26 the base of the transistor T3 and the collector of 27 transistor T2 are the same N-type diffusion and the 28 collector of transistor T3 and the base of transistor ., .j 29 T2 are the same P-type diffusion. Transistors T2 and T3 are connected in a positive feedback mode so that ~';, :''.
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1 when T2 is off it tends to turn T3 off and when T2 is 2 on it tends to turn T3 on thereby yielding a latching 3 function. The silicon controlled switch 20 draws current 4 from a load 22 which in the specific example shown in figure 3, is the PNP transistor T6. When the silicon 6 controlled switch 20 is conducting curxent, th~ low 7 reference potential from the bus VL twrns the PNP .
8 transistor T18 on and the NPN transistor T4 off. Thus 9 a sinking current path will be from the output node 24 .. :.
through the transistor T18 and T2 to the lower bus VL.
11 A portion of the current will also be shunted through . :
12 T22 to the lower bus VL- When the silicon controlled .
13 switch 20 is in its off state, node 15 potential rises 14 thereby turning PNP transistor T18 off and the NPN . .
15 transi6tor T4 on. In this state, current from the :
16 upper bus Vu will pass through transistor T4 and out 17 through the node 24 to the panel conductor. The com~
18 plementary transistor pair T4 and T18 are r.eferred to ;~: .
19 as the complementary output switch 26 whose conductive states alternate under the control of the silicon 21 controlled switch 20. The diode D2 is connected with 22 its po6itive pole at Vcc and its negative pole connected 23 to line 50. D2 serves tc bias line 50 at voltage Vu which 24 will always be greater than the voltage VL of line 52.
When the silicon controlled switch 20 is latched in it~
26 off state, this biasing effect of D2 will maintain silicon 27 controlled switoh 20 in its off state even though positive 28 current flows into the output node 24 and into the high , 29 voltage switch 26. There need be only one diode D2 per . .

semiconductor chip.

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1 To illustrate the operation of the latching 2 driver, assume the silicon controlled switch 20 is on.
3 Current from Vcc passes through resistor R5 and feeds 4 steadily through PNP transistor T3 to t:he base of T2 ~:
thereby keeping it latched on. To turn the silicon 6 controlled switch 20 off, a positive current pulse is 7 input to terminal 14 turning the transistor Tl on~
8 Transistor Tl performs a base-robbing function, re- ~ :
9 moving base current from the NPN transistor T2, thereby turning T2 off. As transistor T2 is turned off, the 11 potential at node 15 rises thereby tending to turn the .
12 PNP transistor T3 off. As transistor T3 turns off, the 13 current supply to the base of T2 is further reduced `.
14 thereby positively reinorcing the unlatching operation . ` `
o the silicon controlled switch comprised of T2 and 16 T3. Simultaneously, the current feeding through the 17 resistor R5 is diverted from the path through the PNP ~ .
18 transistor T3 into the base of transistor T7 and the ~`
19 shunting diode formed by the transistor T~l connect~d between the base and the emitter of T7. The diverted 21 current through the transistors T7 and T21 feeds steadily 22 into the base of transistor Tl thereby keeping Tl on 23 which continues to rob base ~urrent from T2, ~hereby : :
24 maintaining the silicon controlled switch in its off state.
26 . Continuing the description of the operation,~ :~
27 to latch the silicon controlled switch 20 back on again, 28 a positive pulse on the terminal 12 will turn T5 on :~
29 thereby forward biasing the emitter base ~unction of 3Q the PNP transistor T3, turning it on. With T3 now . :
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2 transistor T2 turning it on. With current flowing 3 through transistor T2, the potential at the node 15 4 falls thereby reinfoxcing the on condition of PNP
; 5 transistor Y'3. Thus the silicon controlled switch 20 6 is latched on in a positive feedback reinforcing mode.
7 Simultaneously, the current passing through transistors - 8 T7 and T21 is diverted therefrom and back through the -9 transistor T3 thereby supplying the base of transistor ~-T2 with furkher current, insuring T2's on aondition 11 Tl, now in its off state, will remain in its off state 12 due to the lack of a source of base current through 13 resistor R4, since T7 and T21 are now off. The cycle 14 may be repeated.
Thu~ it i~ seen that when a positive pulse 16 is input on terminal 12, the output node 24 is made 17 common with the VL bUs 52. When the po~itive pulse 18 is on terminal 14, the output node 24 is made common 19 with the Vu bus 50. Thus the overall funation of the driver circuit is the same as that shown by Kleen, 21 et a} for the operation of the driver cirauit in the ~` 22 ga~ panel di8play context.
23 The operation of the latahing driver when 24 applied to driving conductors in the gas panel display ~ `~
is ~hown in the ~equence of figures 4A through 4F D .
;j 26 Figure 4A shows the operation of the latching driver 27 for the sustain mode in the first half. For the X
28 coordinate, positive pulse on terminal 12 turns the 29 silicon controlled switch 20 on thereby ~onnecting the output node 24 to the lower voltage bus 52 at ~L =100 .1 .
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1 volts. For the Y coordinate, the positive pulse on 2 the terminal 12 of the latching driver turns the silicon 3 controlled switch 20 on thereby connecting the output 4 node 24 with the lower voltage bus 56 at VL equal to a potential of zero volts. In the X driver, current from ~;
6 the lower voltage bus 52 with VL With a voltage of 100 7 volts, flows through the diode Dll of t,he X latching 8 driver 40, the X conductor 42, the gas panel display ~ . .
9site 44, the Y conductor 46, and into the Y latching 10driver 48. Current flows in through the node 24 of the 11latching dxiver 48, through the PNP transistor T18, NPN -12transistor T2 and the shunt transistor T22 down to the ,~
13 lower voltage bus 56 having VL at zero potential. Thus it 14 is seen that a potential of 100 volts i~ impressed acro~ -L5 the gas panel display discharge site 44.
16 The operation Oe the latching d.river is further ;' 17 illustrated in figure 4B where the sustain mode obtains 18 for the second half period. A positive pulse on terminal ,~, ~ "
19 12 of the X latching driver 40 turns the silicon con-trolled switch 20 on, thereby conditioning the high 21 voltage complementary output switch 26 so as to make 22 the output node 24 common with the lower voltage bu~
23 52 having a potential of zero volts. Positive pul~e 24 on the input terminal 12 of the ~ latching driver 48 '' .
turns the silicon controlled switch 20 on thereby `..;
26 conditioning the high voltage complementary output :
27 switch 26 so as to make the output node 24 common with ,, 28 the lower voltage bus 56 where VL has a potential of';;;
29 100 volts. Positive current flows from bus 26 th:rough the diode Dll through the Y conductor 46, through the''' .

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1 gas panel display site 44 through the x conductor 42 2 and through the node 24 of the X latching driver 40.
3 Positive current flows through the PNP transistor Tl8 4 and T22 to the bus 52 having VL at a potential of æero volts. Thus it is seen that in the second hal period 6 of the sustain mode, a 100 volt potential is impressed 7 across ~he gas panel display site 44 in a direction 8 opposite to that which obtained during the first half 9 period.
Further illustration on the operation of the ;
11 latching driver is shown in figure 4C where the write 12 or erase mode obtains and a gas panel display discharge 13 site is selected. A positive pulse on terminal 14 turns 14 the silicon control switch off thereby conditioning the hlgh voltage complementary output ~witch 26 to make the 16 output node 24 common with the bus 50 having Vu at a 17 potential of 170 volts. A positive pulse on terminal 12 18 of the Y latching driver 48 causes the silicon controlled 19 switch to turn on thereby conditioning the high voltage output switch 26 to make the output node 24 common with 21 the bus 56 having VL at a zero potential. Positive current 22 from the bus 50 passes through the transistor T4 o the 23 X latching driver 40, through the X conductor 42, the gas 24 panel display site 44, the Y conductor 46, and through the output node 24 of the latching driver 48. Positive 26 current passes through the ~ransistors T18 and T22 of :
27 latching driver 48 to the bus 56, having VL at zero 28 potential. Thus it is seen that a potential difference , 29 of 170 volts is impressed across the gas panel aisplay site 44, igniting a discharge at that point.

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1 ~ further illustration on the operation of the ~:
2 latching clriver is shown in figure 4D where the write or ~ ~.
3 erase mode obtains and the gas panel display site is de-4 selected. Positive pulse on the terminal 12 of the X : :
driver 40 turns the silicon controlled switch 2 n on ~.
6 thereby conditioning the high voltage complementary : 7 output switch 26 to make the output node 24 common with .. .8 the bus 52, with V~ at 120 volts. A pulse on t~rminal ~ -9 14 of the Y latching driver 48 turns the silicon con-10 trolled switch 20 off thereby conditioning the high 11 voltage complementary output switch 26 to make the 12 output node 24 common with the bus 54, having Vu at a 13 potential of 50 volts. Positive current from the bus 14 52 passes through diode Dll of the latching driver 40, the X conductor 42, the gas panel display site 44, the 16 Y conductor 46, and through the output node 24 of the : 17 latching driver 48. Positive current passes th~ough , ;~ .
, 18 the emitter and out of the base of the transistor 18 .~
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19 and into the base and through the collector of tran~
, 20 sistor T4 and into the bus 54. Thus it is seen that .
21 a potential difference of only 70 volts is impressed across .. ~
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22 the gas panel display site 44. This potential is not ~uf~
23 ficient ~o ignite a discharge at that point. :-.. 24 A further illustration o~ the operation of 1 ,;! ., the latching driver is shown in figure 4E where the 26 write or erase mode obtains and the gas panel display ::
27 site is half selected in X. The X latching driver 40 :. .
;. 28 has a positive pulse input on terminal 14 which turns .. ~
29 off t~e silicon controlled switch 20 thereby condition- . .
' 30 ing the high voltage complementary output 3witch 26 to .;~
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1 make the O~ltput node 24 common with the bus 50 having ;.
2 Vu at a p~.te~tial of ~170 volts. The Y latching driver : ~;
; 3 48 has a positive input pulse on terminal 14 which 4 turns the silicon controlled switch off thereby con-~ 5 ditioning the high voltage output switch 26 to make :-: 6 the output node 24 common with the bus 54 having Vu 7 at a potential of 50 volts. Thus a positive current 8 flows from the bus 50 through transistor T4 of the 9 X latching driver 40, onto the X conductor 42, the gas panel display site 44, the Y conductor 46, and 11 through the output node 24 of the Y latching driver 12 48. Positive current flows through the emitter and 13 base of transistor T4 to the bus 54. Thus it is seen -14 that a voltage of 120 volts is impressed across the .
gas panel display ~ite 44. Such voltage is not ~uf~
16 ~icient to alter the discharge condition of the hal~- :
17 selected panel site 44. -18 A further illustration of the operation of 19 the latching driver is shown in figure 4F where the write or erase mode obtains and the gas panel display ~;
21 site is half selected in YO The X latching driver 22 40 has a positive pulse on the input terminal 12 : -23 which turn~ the silicon controlled switch 20 on 24 thereby condi*ioning the high voltage complementary output switch 26 so that the output node 24 is ~
26 connected to the bus 52 having VL at a voltage of ..
27 120 volts. The Y latching driver 48 has a positive - :
28 input pulse on terminal 12 which turns the silicon .:
29 controlled switch on thereby conditioning the high ~ :
~, 30 voltage complementary output swltch 26 so that the ~: MA9-74-00~ - lh -,~

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1 output terminal 24 is common with the bus 56 having :
2 VL at a voltage of zero volts. Thus a positive . :
3 current flows from the bus 52 ~hrough the diode Dll ~ . .
4 of the X driver 40, the X conductor 42, the gas panel display site 44, the Y conductor 46, an.d through the .
6 node 24 of the Y latching decoder 48. Positive current 7 flows through transistors T18 and T22 to the bus 56.
8 Thus it is seen that a voltage of 120 volts is impressed ~ .
9 across the gas panel display site 44. This potential is not sufficient to change the discharge state of .
11 the site 44 which is half selected in Y.
12 SEMICONDUCTOR STRUCTURE_FOR THE LATCHING DRIVER LNVENTION .
13 Figure 5A illustrates the layout of the latching 14 driver invention 1 shown in figure 3. Figure 5B shows the ': , .
silicon controlled switch 20 contained within the layout . ; ;
16 of the latching driver of fiyure 5A, Cross sectional views :, . : .
17 of the structure along the line A-A' is shown in figure 6A
.. 18 and along the line BB' shown in figure 6B. .~ ;
19 The latching driver structure is formed on a silicon P type semiconductor wafer 60, a cross sectional view of which . ~:
21 is shown in figure 6A. On the surface of P type wafer 60, ` .:
:
~ 22 N~ subcollector region 76 is diffused. Subsequently, an N . ;:.
.;23 type epitaxial layer 62 is grown on top o~ the wafer surface : ~
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24 60. The P + isolation region 64 i~ then diffused into the ;- :.
N type epitaxial layer 62 so as to make contact with the P ~......... .
i6 type substrate wafer 60, thereby forming isolation islands ~ ;
~ 27 such as 62 and 82 shown in igure 5B. Then a P-type diffusion ;.
.. 28 and an N-typ~ diffusion are executed to form the lateral .~2., i 29 transistor structors which will now be described. ::.
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~ 30 As previously discus-ecl, the latching driver . . :~
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~ . MA9-74-001 - 17 -~ i3 _ invention is comprised of the silicon controlled switch 20 2 and the high voltage switch 26. The silicon controlled 3 s~itch is formed within the isolation island 62 by means 4 of the P-type diffusion 68, the N+ diffusion 70, the P-type diffusion 74, and the epitaxial region 70 encompassed within 6 the P type diffusion 68. A cross sectional view of the 7 silicon controlled switch 20 is shown in figure 6A where the 8 N+ region 66 functions as the collector for transistor T2, ; 9 the P region 68 functions as the base oE the transistor T2 and the collector of transistor T3, and the N+
11 region 70 functions as the emitter of T2. The region 72 of 12 the N type epitaxial layer 62 functions as the base of T3 and '~
13 the P diffusion 74 functions as the emitter of T3. In~;
...: , 14 operation, positive current from node 18 flows into the emitter region 74 of the transistor T3 and flows through the region 72 16 o the epitaxial layer 62 which operates as a base, and into 17 the P type region 68 operating as the collector of T3. Since 18 region 68 also serves as the base for T2, T3 effectively 19 supplies base current to T2. The N+ diffusion 70 ser~ing as the emitter of T2 injects the electron~ into the P type , . . .
)' 21 base region 68 for transis~or T2, which are then collected . . .
22 by means of the N~ region 66, by way of the lower resistance 23 path formed by the subcollector 76. This layout coniguration 24 for the silicon controlled switch 20 presents a more compact configuration than those ound in the prior art. The 26 metallization 90 serves as the nodal point 18 and connects to 27 the emitter diffusion 74 of the transistor T30 The metallization 28 92 serves as the nodal point 15 and connects with the N~ :
29 di~usion 66 which serves as a collector for T2 and a guard . , .
j 30ring for the silicon controlled switch.

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1 Transistor T18 constitutes the PNP component of the 2 high voltage switch 26 for the latching driver 1 shown in .`.
3 figure 3. Transistor T18 is formed in the region outside of 4 the subcollec-tor area 76 and is comprised of the P type diffusion~
78 which s~rves as the emitter of transistor T18 and transistor 6 T22 as well as the output node 24 for the latching driver .
7 device. The epitaxial layer 62 in the region beneath the : :
8 P type diffusion 78 and in the region between the P type ; .
9 diffusion 78 and the isolation diffusion 54, serves as the base region for the transistor T22. The region 80 of the i ;
11 epitaxial layer 62 lying between the P type diffusio:n 78 : ~.
12 and the P type diffusion 68 serves as the base region for ~ -13 the transistor T18. The potential of the N type epitaxial -14 region 62 is governed by the conductive state of the silicon controlled switch 20 since the N+ type diffusion 66 and the 16 N type epitaxial layer 62 serves as the collector of T2 17 and the base of T3. It is the pokential at which this 18 epitaxial layer 62 rests which governs the conduct.~vity ~ .
19 of the transistor T18 since epitaxial layer 62 also serves : :
as the base region for transistor T18. Thus when th~
21 potential of the epitaxial layer 62 is low, the transistor . :.~ ..
22 T18 formed by the emitter region 78, the base region 80 ~;
23 o epitaxial layer 62, and the collector region 68, will ,:
24 be forward biased thereby connecting the ou~put node 24 :
with the potential of the collector region 68 for transistor ,::
26 T18. The epitaxial layer 62 was initially driven to its . :.
27 lower potential by means of input to the base of transistor 28 T3, which is structurally the region 72 of the epitaxial .
29 layer 62. Since T3 is conducting, the base-emitter junction in T2 is forward biased thereby making the potential of the ~.
. .
MA9-74-001 19 ~
....

1 collector region 68 the same as the potential of the - 2 emitter region 70 and T2. Thus the high voltage switch :;
3 26 presents a closed conductive path between the output 4 node 24 and the lower bus 52. ~ .
Transistor T22 serves as a current shunting path 6 from the output node T4 to the bus 52. Transistor T22 is formed ;:
7 in the isolation island 62 between the P type emitter diffusion 8 78, the regions of the epitaxial layer 62 beneath diffusion `~
9 78 and between diffusions 78 and the P~ isolation region 64. ~;:
Positive current is injected from the P type region 78 into ~ ~ -11 the N type epitaxial layer 62 when the pn junction is forward 12 biased by the potential of the epitaxial layer which serves 13 as the base region. Current is collected by the P type wafer 14 substrate 60 constituting a vertical transistor configuration and is collected by the P+ isolation region 64 as a lateral ~ :
16 transistor configuration. Since Tl8 and T22 share the epitaxial 17 layer 62 as a common base region, transistor T22 turns on when 18 transistor T18 turns on, thereby performing a current shunting .`
19 function around the transistor 18. Metallization 94 constitutes the node 24 and connects with the emitter diffusion 78 for the , ; .
21 t~ansistors T18 and T22 The potential of the emitter ragion 22 78 is transferred through node 24 to the output line 42 as the ~ :
23 output potential for the latching driver 1 of ~igure 3.
24 The transistor T4 which, along with transistor T18, ~ `
constitutes the high voltage switch 26 of the latching driver 26 l of figure 3, i5 formed in the isolation island 82 shown in 27 figure 5b. The transistor T4 is formed in the epitaxial layer -28 82 by means of a P type base diffusion 86 and N+ type emitter 29 diffusion 84. The N-type epitaxial layer 82 which serves as the collector of transistor T4, is connected by mleans of -', ',., , :~

MA9-74-001 - 20 - ~.
. ~ , .
: '',~, , ' .j .:
:~, ,. . . , . .:

1 metallization 50 to the relatively high reference potential Vu.
2 The metallization 94 which constitutes the node 24, makes contact .
3 with the emitter diffusion 84 of the transistor T4 as shown in ; 4 figure 5~. The metallization 92 which constitutes node 15, is connected to the collector diffusion 66 of transistor T2 and ~ :
6 thus has the potential of the epitaxial layer 62 in the .
: 7 isolation island 62. This potential is carried by the 8 metallization 92 to the base diffusion 86 for the transistor 9 T4. Thus since transistor T4 is an NPN and the transistor - 10 T18 is a PNP, when the potential of metallization 92 and 11 epitaxial layer 62 is relatively high, the NPN transistor T4 ::.
12 is on and the PNP transistor T18 is, off, connecting output :;
13 node 24 to the higher potential Vu on metallization 50.
1~ Conver~ely, when the relative potential of the m~tallization ~` .
l 15 92 and the epitaxial layer 62 is low, the PNP transistor T18 ~
; 16 is on and the NPN transistor T4 is off, connecting output node ~::
, 17 . 24 to the lower potential V2 on metallization 52. Thus the .~ . .
! 18 function of the high voltage switch 26 is performed by the 19 structure in which the transistors T4 and T18 are embodied ;~
.....
', 20 in figure 5B. Thus the output node 24 can alternately be . ~
21 connected to the relatively high potential of the collector , : .;.
, 22 of transistor T4 or the relatively low potential of the 23 collector o transistor Tl8 under the control of the silicon 2~ controlled switch 20. The potential of the output node serves .--~
; 25 as the drive potential output on line 42 for utilizationi in 26 a gas panel display. ~.
27 The layout for tha latching driver shown in figure ~ ;
' 28 5A shows the transistor Tl laid out in isolation island 30, , 29 transistors T2, T3, T5, T18, and T22 laid out in isolation .
t 30 i~land 32, transistor T6 and T7 laid out in isolation island ' MA9-74-001 - 21 ~-.'' ' . .
~ ", '. ' ' ' -.., :"
....:

1 34, transistor T21 laid out in isolation island 36, and tran-2 sistor T4 laid out in isolation island 38. Input node 12 is 3 shown as the metallization 98 which is input to the base of 4 transistor T5 in isolation island 32. Input node 14 shown as metallization 100 is connected to the base region of 6 transistor Tl in the isolation island 30. Metallization 50 7 is the upper bus and is connected to the collector of ~' 8 transistor T4 in isolation island 38. The lower bus 52 9 shown as the metallization 52 and is connected to the emitter of T2 in isolation island 32.
11 Thus it is seen that the improved lateral transistor 12 structure of which the silicon controlled switch and the high 13 voltage switch are comprised, constitutes a more compact 14 configuration generating a lower power dissipation in its off state then prior art latching driver structures. The structure 16 of the latching driver circuit shown in figure 5A with its 17 shunting transistor T22, provides a lower resistance path 18 between the output node 24 and the lower bus 52 that has 19 been achieved in the prior art.
While the invention has been particularly shown and '~
21 described with reference to the preerred embodiments thereof, 22 it will be understood by those skilled in the art that the 23 foregoing and other changes in orm and detail may be made 24 therein without departing from the spirit and the scope of the invention.
26 I Claim:
., ~ , ' '1~ "' :' -!

. MA9-74-001 - 22 -~: '' ''''"' '-~.

Claims (13)

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. A high voltage latching driver comprising:
a high voltage switch having a first NPN transistor with a collector connected to a high reference potential and its emitter connected to the emitter of a first PNP transistor having its collector connected to a low reference potential;
said emitters constituting an output node;
a silicon controlled switch comprising a second NPN
transistor having its collector connected through a load to said high reference potential and its collector connected to the base of said first NPN transistor and to the base of said first PNP transistor and having its emitter connected to said lower reference potential;
said silicon controlled switch further having a second PNP transistor having its emitter connected to a current source, its base common with the collector of said NPN transistor and its collector common with the base of said second NPN transistor;
said silicon controlled switch controlling the alternate conduction of said first NPN transistor and said first PNP transistor and latching the state of conductivity of said transistors in response to an input control signal;
whereby said output node can be selectively connected to said high or said low reference potential.

2. The circuit of Claim 1, which further comprises:
a third NPN transistor having a collector connected to the base of said second PNP transistor in said silicon controlled switch, having an emitter connected to said low reference potential and having its base as a first input terminal;
whereby a position input control signal on said first input terminal causes said third NPN transistor to enter into conduction thereby forward biasing the emitter-base junction of said second NPN

transistor, initiating the turning on said silicon controlled switch.

3. The electrical circuit of Claim 2, wherein said collector of said third NPN transistor and said base of said second PNP transistor are formed by the same diffused region in the integrated circuit.

4. The electrical circuit of Claim 1, which further comprises:
a third NPN transistor having a collector coupled to the base of said second NPN transistor of said silicon controlled switch, having an emitter coupled to said low reference potential and having a base connected to a first input terminal;
whereby a positive input control signal on said first input terminal causes said third NPN transistor to enter into conduction thereby diverting base current from said second NPN transistor, initiating the turning off of said silicon controlled switch.

5. The electric circuit of Claim 4, which further comprises:
a current source for feeding positive current through a node and into said emitter of said second PNP transistor of said silicon controlled switch;
said collector load for said second NPN transistor in said silicon controlled switch being a third PNP transistor having its collector connected to the collector of said second NPN transistor and having an emitter connected to said high reference potential;
a fourth NPN transistor having its collector connected to the base of said third PNP transistor, having its base connected to said node of said current source and having its emitter connected to the base of said third NPN transistor;
whereby an input control signal turning off said silicon control switch causes current from said source which was passing through said second PNP transistor to be diverted through the base and emitter of said fourth NPN transistor to supply base current to said third NPN transistor thereby sustaining the off state of said third NPN transistor and thus the off state of said silicon controlled switch.

6. The electric circuit of Claim 4, which further comprises:
a resistor connected between a power supply potential node and said emitter of said second PNP transistor of said silicon controlled switch;
a diode having its positive pole connected to said power supply potential node and its negative pole connected to said high reference potential;
whereby when said silicon controlled switch is latched in its off state, said diode will positively bias said high reference potential with respect to said low reference potential, thereby maintaining said silicon controlled switch in its off state even under the condition that positive current flows into said output node from said conductor.

7. The circuit of Claim 1, which further comprises:
a diode having its negative pole connected to said low reference potential and its positive pole connected to the output node of said high voltage switch;
whereby positive current can be shunted from said low reference potential to said output node when the potential of said output node is below the potential of said low reference potential.

8. The electric circuit of Claim 1, wherein said first PNP tran-sistor and the base and emitter of said second NPN transistor constitute a current sink from said output node to said lower reference potential when said silicon controlled switch is in its conducting state.

9. The electric circuit of Claim 1, wherein said first NPN trans-istor of said high voltage switch constitutes a current path from said high reference potential and said output node when said silicon controlled switch is in its non-conducting state.

10. The electric circuit of Claim 1, wherein the emitter and base of said first PNP transistor and the base and collector of said first NPN
transistor in said high voltage switch constitute a current sinking path from said output terminal to said high reference potential when said silicon controlled switch is in its off state.

11. A latching, high voltage driver integrated circuit structure, comprising:
A first P type semiconductor substrates An N type epitaxial layer formed on the surface of said substrate;
An isolation region formed in said epitaxial layer so as to enclose a first area of said epitaxial layer;
Said first area of said epitaxial layer being connected to a first control signal source;
A first P type region within said first area of said epitaxial layer, having an open configuration enclosing a second area of said epitaxial layer within said first area and switchably connected to a low voltage source in response to a second control signal;
A second P type region within said second area of said epitaxial layer, having a connection to a positive current source;
An N type region within said first P type region connected to said low voltage source;
A third P type region within said first area of said epitaxial layer and connected to an output node;
Said epitaxial layer forming the collector of a first NPN tran-sistor having said first P type region as its base and said N type region as its emitter;
Said epitaxial layer forming the base of a first PNP transistor having said first P type region as its collector and said second P type region as its emitter;
Said first NPN transistor and said first PNP transistor forming a silicon controlled switch device;
Said epitaxial layer forming the base of a second PNP transistor having said first P type region as its collector and said third P type region as its emitter;
A second NPN transistor formed in said epitaxial layer outside said isolation region, with its emitter connected to said third P type region, its base connected to said epitaxial layer within said isolation region, and its collector connected to a high voltage source;
Said second NPN transistor and said PNP transistor forming a high voltage switch for alternately connecting said output node to said high voltage source or to said low voltage source;
Whereby said first control signal will cause said silicon con-trolled switch to latch on thereby causing said high voltage switch to connect said low voltage source to said output node and said second control signal will cause said silicon controlled switch to latch off thereby causing said high switch to connect said high voltage source to said output node.

12. The latching high voltage driver integrated circuit structure of Claim 11, which further comprises:
Said isolation region being composed of a P type material and being connected to said low voltage source;
Said first area of said epitaxial layer within said isolation region forming the base of a third PNP transistor having said third P type region as its emitter and said isolation region as its collector;
Whereby said third PNP transistor constitutes a current shunt between said output node and said low voltage source, which is responsive to the conductive state of said silicon switch.

13. The latching, high voltage driver integrated circuit structure of Claim 11, which further comprises:
A fourth P type region within said first area of said epitaxial layer, connected to said first control signal source.
A second N type region within said fourth P type region, con-nected to said low voltage source and forming the emitter of a third NPN
transistor having said fourth P type region as its base and said first area of said epitaxial layer within said isolation region as its collector;
Whereby said first control signal renders said third NPN transistor conductive thereby forward biasing the emitter base junction of said first PNP

transistor, thereby serving as a switching means for initiating the conductive state of said silicon controlled switch.