CA1044349A

CA1044349A - Inspection machine memory

Info

Publication number: CA1044349A
Application number: CA246,116A
Authority: CA
Inventors: John W. Juvinall
Original assignee: Owens Illinois Inc
Current assignee: OI Glass Inc
Priority date: 1975-03-27
Filing date: 1976-02-19
Publication date: 1978-12-12
Also published as: JPS5652255B2; GR59911B; ZA761032B; GB1530684A; PT64944B; BR7601239A; ES445670A1; DE2608610B2; FR2305824A1; DE2608610A1; NL7602312A; PT64944A; AU1139076A; IT1057268B; FR2305824B1; US3941686A; ES450214A1; DE2608610C3; JPS51114983A

Abstract

INSPECTION MACHINE MEMORY
ABSTRACT OF THE DISCLOSURE
An improved memory for a glass container inspection machine. In one common form of glass container inspection machines, the containers are indexed through multiple stations where they are inspected for various attributes. Rejection of defective containers can take place only after all of the inspections have been made. The information relative to a defective container is placed in a master-slave type flip-flop uniquely associated with a particular inspection station. In-formation is then shifted through a group of series-connected master-slave type flip-flops in synchronism with the movement of the container until the container, if defective, reaches a location where it can be rejected. The information is moved or clocked by a generated clock pulse that has a rise time that is faster than the information transfer time through the flip-flops.

Description

17 BACKGROU~ OF THE INVENTION
lQ This invention relates to a memory for a glass con-19 tainer inspection machine. More particularly, this invention ao relates to a memory for a slass container inspection machine

2~ which indexes glass containers from station to station for 22 inspection. Specifically, this invention relates to a solid 23 state memory for such an inspection machine.
2~ one well-known type of inspection machine for glass 26 containers is that known as the FP machine, manufactured by - 26 Owens-Illinois, Inc. This is a rotary, ir.dexing machine where 27 glass containers are indexed through a plurality of stations -~8 for inspection. A defect may be found at any station, but 29 rejection of a defec.ive container cannot occl~r until ~he last ~0 inspection station has been passed. Th-us, these machines ....

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orm 233 ~ . , ;

lU44349 J-13792 !r .:' , .
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1 reguire a memory to allow retention of defective container 2 information until a rejection location is reached. In the E
past, pin-type or magnetic belt memories have been used. How-ever, these are basically mechanical devices which have pre-6 sented not only maintenance problems but also accuracy of in-6 formation storage problems. I have devised a solid state 7 memory for this machine which uses reliable, durable electronic 8 components. This reduces maintenance problems and raises the ~ reliability with which the memory is retained. A very fast 10 clock pulse is used to clock a group of series-connected flip-11 flops in a time less than the transfer time of informatlon 12 through the flip-flops.
18 Memory systems of this general type are not unknown 1~ in the prior art. For example, see U.S. Patents 3,259,240;
1~ 3,263,810; 3,565,249; and 3,581,889. The best example of the 16 prior art known to me is U.S. Patent 3,757,940. This patent Iq teaches a solid state memory for a similar FP type machine.
18 The memory of the cited patent has been successful, but it is 19 quite complex and is designed for very high speed operation.
20 It requires two memories and two separate clock frequencies to 21 allow downstream rejection of the defective containers. In 22 addition, the clock pulses must be delayed and conditioned to 28 avoid false shifts of information. My invention is designed ; 24 for FP machines which operate at moderate speeds and do not 26 require downstream rejection. In adaition, I have simplified 26 the circuit of the cited patent and eliminated the need for 27, delay and conditioning of the clock pulses. Furthermore, my 28 clock pulse generation technique is much simpler since only 29 a single clock pulse at a single frequency is required.

~o sa ~r~ 23~

1 SUMMARY OF THE INVENT~ON
~ -- .. I
2 M~ invention resides in an inspection machine for 8 glass containers. In this machine, the glass containers are removed one at a time from a continually moving convevor and 6 serially indexed through a plurality of inspection stations.
6 m e inspection machine includes a bottle defect logic and 7 detection means which generates output signals if the inspected 8 glass containers are defective in one or more aspects at any ~ one of the inspection stations. My invention is specifically 10 an improved memory for this machine. A plurality of master- ¦
11 slave type flip-flops are connected in series, with the number 12 of flip-flops being one more than the number of inspection 18 stations. Means are provided for connecting an output con-4 ductor from the logic means to each one of the flip-flops 16 except the last one of the plurality of flip-flops. A timing 16 means presents a first electrical state when the inspection machine is inspecting and a second electrical state when the 18 inspection machine is in its index cycle. An electronic clock 19 circuit means generates a clock pulse having a rise time faster 20 than the information transfer time through any one of the flip-21 flops in response to the transition of the timing means from 22 the second electrical state to the first electrical state. The 23 clock circuit means is connected to the timing means and each 24 of the flip-flops. An electronic output circuit means generates 26 a signal when the last of the plurality of flip-flops carries a 26 signal indicating the presence of a defective glass container 2~ and when the clock pulse is present. The output circuit means 28 is connected to an output terminal of the last flip-flop and ~o the clock circuit means.

~1 ... ~ . .. .. . . .

~o~ 9 ; BRIEF DESCRIPTION OF THE DRAWINGS

- FIG. 1 is a schematic top plan view showing the inter-- relation of the present invention with a glass container ~;

inspection machine; and .. ',' .
FIG. 2 is a block diagram of the memory of the present invention. `
DETAILED DESCRIPTION OF THE DRAWINGS
, ~; FIG. 1 shows the mechanical and electronic apparatus ~ -of the present invention in a schematic form. The present -~
invention is designed specifically to operate with a bottle gauging apparatus such as that described in U.S. Patent 3,313,409.
- It is believed that the teachings of the cited patent are : sufficiently clear to allow one skilled in the art to utilize ~ -the present invention when described in a schematic form. A
gauging apparatus or article inspection machine is generally aesignated by the numeral 10. The inspection machine 10 includes a rotatable disk 12 having pockets cut therein for receiving glass containers 14 to be inspected. The glass containers 14 -are presented to the inspection machine 10 in a single file by a continually moving conveyor 16. The conveyor 16 also serves to remove the articles from the gauging machine 10. The conveyor - 16 thus serves as a means for ~elivering and removing articles from the gauging apparatus 10. As taught in U.S. Patent

3,313,409, the glass container 14 which is positioned in the pocket designated as A is sequentially rotated or indexed to positions or stations designated as B, C, D, E and F. In- -spection of the glass container 14 is carried out ~t positions B, C, D, E and F by apparatus which is not shown but which is !:
well known to those skilled in the art. Position G is a position ., , ;.. ~ .
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:. -' ' , . -' ' . ' ~ ' `~-~. Form 233

4~349 J-13792 1 in which a container 14 is held prior to its release to the 2 conveyor 16. If the container 14 has been passed by all the 8 inspections performed upon it during its indexing from ~ station to station, the co.ntainer 14 is released and allowed ~ to proceed down the con~eyor 16. If the container 14 has 6 shown some defect, it is rotated toward the position noted 7 as H. However, a diverter bar 1~ sweeps the container 14 8 off the conveyor 16 and into a rejection area before it can g complete the index and then be further indexed to position A
10 where it would interfere with incoming containers 14. At 11 station G, an air motor 20, supported from the conveyor 16 12 by a suitable bracket 22, serves to control the release of 18 containers to the conveyor 16 and for holding defective con-14 veyors for rejection by the diverter bar 18. The air motor 1~ 2~ includes an extensible operating rod 24 which carries on 16 its end a tip 26. The tip 26 is retracted or removed from 7 contact with the glass container 14 by retraction of the 18 operating rod 24 in response to a si~nal indicating that a 19 glass container 14 has passed all of the inspections performed 20 upon it in the inspection machine 10. If the glass container 21 14 has proven defective in one or more attributes, the operating a2 rod 24 is not retracted and consequently the tip 26 prevents 2s the glass container 14 from moving along the conveyor 16.
24 Then, the next index cycle of the inspection machine 10 forces 26 the container 14 into contact with the diverter bar 18 for 26 rejection. The operation of the air motor 20 is controlled by 2? a solenoid valve 2~ which is furnished a source of air under 28 pressure from a source not shown through a pipeline 30. This 20 air is then selectively supplied to the air motor 20 through a 80 pipeline 32. As is well known in these general types of F~T`~ ~33 .: :
1 inspection machines 10, the glass containers 14 are indexed 2 from station to station in a controlled manner by an indexing drive. A rotary cam 34 is driven in a continuously rotating fashion by the main machine drive. This cam 34 is thus in 6 synchronism with the indexing drive and can be used to pro-6 vide timing signals. While the disk 12 is driven in an inter-q mittent, indexing mode, the cam 34 rotates continuously and 8 makes one complete revolution for each cycle of the disk 12, ~ one cycle including an inspection mode when the disk 12 is lo stopped and an index mode when the disk 12 is moved. In 1I fact, a switch 36, which has an operating plunger 38, is 12 positioned in proximity to the cam 34 so that the cam 34 18 operates the plunger 38 of the switch 36 and thus generates 14 electrical timing signals along two output conductors 40 and 16 41. The conductors 40 and 41 carry information from the 16 switch 38 indicating whether the machine is in the inspection 1~ mode or in the indexing mode. The information is carried in 18 terms of two different electrical states of the switch 36 and 1~ the cam 34 and switch 36 therefore form a means to present 20 these two states. The conductors 40 and 41 are connected 21 to a main machine memory 42. The bottle defect logic and 22 detection unit 46 is of the type well known in the art and may 28 be of that type as shown in U.S. Patent 3,313,409. Signals 84 from the detection equipment mo~nted above or below the 26 rotatable disk 12 are fed into the logic unit 46 through five 86 input conductors 4~a, b, c, d and e. It is possible for a 27 glass container 14 to be inspected for multiple attributes at 28 any one of the stations B through F. It should be quite 2~ evident that a glass container 14 may be found defective at 80 any one of the in5pection stations B, C, D, E or F. However, ~2 . ~ . . . ... . .. .. . . . . .. ... .. . . . . . . . . .. . .

L

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Form 233 ~044349 1 implementation of the decision to reject such a defective 2 glass container 14 cannot be made until station G is reached.
8 Therefore, the memoxy 42 serves the function of maintaining the information which indicates that a particular glass con-tainer 14 is defective and processing this information so 6 that any glass container which exhibits a defect in any one q of the inspection stations will be rejected at stations G and g F. To this end, five separate sets of conductors SOa and b, 9 51a and b, 52a and b, 53a and b, and 54a and b carry defective bottle information from the bottle defect logic and detection 11 unit 46 to the memory 42. Then, at the proper time, a signal 12 is transmitted from the memory 42 through an electrical con-18 ductor 56 to the solenoid valve 28 to cause cycling of the 14 solenoid valve 28 to either accept or reject a glass container 1~ 14 presented at station G.
16 ~IG. 2 shows the construction of the memory unit 42 iq in a block diagram form. The conductors 50a and 50b are con-18 nected to a normally open relay 58 which is a part of the bottle 19 defect logic and detection unit 46. When a defective glass 20 container 14 has been detected at station B, the relay 58 will 21 close in response thereto and therefore complete a circuit with 82 the conductors 50a and 50b. The circuit is completed with an 28 optical isolator 60. The optical isolator 60 is of a generally 24 conventional type which contains within it a photo-diode 62 a~ which is connected in series with the conductors 50a and 50b 2¢ and the relay 58, and a photo-transistor 64 whose base is 27 positioned to receive light energy from the photo-diode 62 28 when it is turned on. In operation) closing of the relay 58 29 will allow power to flow through the conductors 50a and 50b, 80 noting th~t the conductors 50a and 50b are connected across a r~ 2~,~
;' 1U L~4349 1 voltage supply 59, noted by way of illustration as an AC
- 2 source, thereby energizing the photo-diode 62. This in turn 8 will allow the photo-transistor 64 to generate an output signal ~ from its emitter along a conductor 66. Note that the collector C of photo-diode 64 is connected to the positive voltage supply 6 of the circuit. In a similar fashion, the conductors 51a and 7 5Ib are connected to a relay 68, the conductors 52a and 52b to - 8 a relay 70, the conductors 53a and 53b to a relay 72, and the 9 conductors 54a and 54b to a relay 74. The relays 68, 70, 72 and 10 74 are also connected to the voltage supply 59 in the same 11 manner as the relay 58. The relays 68, 70, 72 and 74 correspond 12 to the inspection stations C, D, E and F and will be closed in 18 response to a defective glass container 14 being detected at 14 these stations. As was the case with the first pair of con-16 ductors 50a and 50b, all the other conductors 51a through 54b 1~ are connected to respective optical isolators 76, 77, 78 and 79.
17 The operation and functioning of the optical isolators 76 through 1879 is identical to that described with respect to the optical . 19isolator 60 and further detailed discussion is believed un-. 20necessary. In addition, all of the photo-transistors in the v 21optical isolators 76 through 79 have their collectors connected 22to the positive voltage supply of the circuit~ In a similar 28manner, each of the optical isolators 76 through 79 present 24 individual outputs from their emitters on respective conductors 2682, 83, 84 and 85. Of course it is understood that these output . 26signals will be generated on these conductors only when a signal 27has been received from the appropriate inspection station in-28dicating the presence of a defective glass container 14. The 29conductor 66 from the optical isolator 60 is connected to the 80direct set input of a f.irst flip-flop 88. The flip-flop 88 Jtnrm 253 . `
: ' ! io443~9 1 contains in addltion to the direct set input a conditional 2 set input D, a clock input C and an output terminal Q. The 8 flip-flop 88 is preferably a model CD4013 AE manufactured by ~ the RCA Corporation. This particular type of flip-flop is of 6 the master-slave type which indicates that internally there 6 is a two-stage transfer of information from the D terminal to q the Q terminal before the Q tel~inal will display information 8 presented to the D terminal. This function is of importance ~ in that there is a delay in propagation of information through 10 the flip-flop 88. This particular property will be taken ad-11 vantage of a~s will be described later. It is possible that 12 other types of flip-flops could be used, and the conditions 18 for their use will be described with respect to th~ description 14 o~ the clocking of the flip-flops. The D terminal of the first 16 flip-flop 88 is connected to ground to assure that no spurious 16 or false inputs are placed in this particular unit. The only l7 input co the first flip-flop 88 is through the direct set 18 terminal S and is from the optical isolator 60. Thus a signal 19 to the first flip-flop 88 indicates that a defective glass 20 container 14 has been detected at inspection station B. In 21 order to present a consistent signal to the flip-flop 88 when 22 no signal is present from the optical isolator 60, the S terminal 28 of the first flip-flop 88 is also connected to ground through 24 a resistor 90. The Q output terminal of the first flip-flop 88 26 is connected to the D or conditional set terminal of a second 26 flip-flop 92 which is identical to the first flip-flop 88.
27 Similarly, the Q output terminal of the second flip-flop 92 is 28 connected to the ~ input terminal of a third flip-flop 94. The 29 Q output terminal of the third flip-flop 94 is connected to the 80 D input terminal of a fourth flip-flop 96. The fourth flip-flop _g_ ~orm 233 ~ !

1 96 has its Q output terminal connected to the D input terminal 2 of a fifth flip-flop 98. The fifth flip-flop 98 has its Q
8 output terminal connected to the D input terminal of a sixth and final flip-flop 100. There are therefore in total six ~ flip-flops, five of which are used to store information relative 6 to defective bottles which are detected at stations B, C, D, E
7 an~ F. ~he second flip-flop 92 has its S terminal connected 8 to the conductor 82 which carries information from the optical 9 isolator 76 relative to defects occurring at station C. As 10 was the case with the first flip-flop 88, the second flip-flop 11 92 also has its S terminal connected to ground through a re-12 sistor 102. The third flip-flop 94 has its S terminal connected 18 to the conductor 83 which carries informaticn from the optical 14 isolatOr 77 indicating the presence of a defective glass con-16 tainer 14 at station D. A resistor 104 connects the S terminal . v ~
~6 of the third flip-flop 94 to ground. The fourth flip-flop 96 ~7 has its S terminal connected to the conductor 84 which in turn 18 carries a signal from the optical isolator 78 which will in-lg dicate the presence of a defective glass container at station E.

20 A resistor 106 connects the S terminal of the fourth flip-flop ~1 96 to ground. The fifth flip-flop 98 is the final unit which 28 actually receives direct information relative to the detection 28 of a defective glass container during the inspection cycle.

24 The conductor 85 is connected to the S terminal of the fifth 26 flip-flop 98 and carries information from the optical isolator 26 79 indicating the detection or presence of a defective glass 27 container at inspection station F. A resistor 108 connects the 28 S terminal of the fifth flip-flop 98 to ground. The sixth 2~ flip-flop 100 is a final output flip-flop which carries the 80 total sum of the information which has been stored in the 8a ~rm 233 1~)4~3~9 J-13792 1 preceding five flip flops. Its S terminal is connected to 2 ground directly to prevent entry of any signal into this ~ particular terminal of the flip-flop 100. This is necessary - ~ because any information entered into the flip-flop 100 must 6 be information which has been passed through the preceding 6 flip-flops in series. It should therefore be clear from this 7 arrangement and connection of units that any signal indicating 8 the presence of a defective glass container 14 at any one of ~ the inspection stations is independently entered into its 10 respective flip-flop at the time this defect is detected.
1I This information is then shifted in sequence as this particular 12 glass container is indexed ~rom station to station until the 18 information finally enters the final flip-flop 100. At this 14 time, the decision must be made whether to accept or re~ect 16 the glass container 14 which has been passed through the entire 16 inspection machine 10. An anti-bounce fast-rise time circuit 17 110 is used to provide a very fast rising clock pulse and to 18 overcome any tendency of the switch 36 to bounce during its 19 cycle. As is evident in FIG. 2, the switch 36 is connected to 20 ground and has two separate terminals, one connected to the 21 output conductor 40 and the- other connected to the output con-22 ductor 41. The output conductor 41 is connected to one input 28 terminal of a first NAND gate 112. The conductor 41 is also 24 connected to the positive voltage supply v plus of the circuit 26 through a resistor 114. The conductor 40 is connected to one 26 input terminal of a second NAND gate 116. The conductor 40 a7 is also connected to the positive voltage supply of the circuit 28 through a resistor 118. The output terminal of the second NAND
29 gate 116 is connected to a second input terminal of the first 80 NAND gate 112 by a conductor 120. The output of the first .. . . .. . . . . . . . , l~or~ z 3 . I J

~443~9 J-13792 : .
: I ~AND gate 112 is connected to a second input of the second 2 ~AND gate 116 through a conductor 122. The output of the 8 first NAND gate 112 is also connected to the C or clocking 4 input terminal of all of the flip-flops 88, 92, 94, 96~ 98 G and 100 through a conductor 124. The output of the first .~ 6 NAND gate 112 is also connected to one input terminal of a 7 third ~AND gate 126 by a conductor 128. The Q output terminal - 8 of the final flip-flop 100 is connected to a second in~ut 9 terminal of the third NAND gate 126 by a conductor 130. The lD output terminal of the third NAND gate 126 is connected to a 1I control relay 132 ~y a conductor 134. The output of the 12 control relay 132 is the conductor 56 which controls the 18 cycling of solenoid valve 28.
. 14 The operation of the memory system seen in FIG. 2 16 may be described as follows: During the time the cam 34 is 16 indicating that the gauging of the glass containers 14 is l7 taking place, the switch 36 is in the position shown in FIG.
18 2. Under these conditions, the resistor 114 is actually 1~ grounded and may not supply the v plus voltage to the input 20 of the ~AND gate 112. Therefore, the NA~D gate 112 has one 21 zero input at this time. It is well known that the character-88 istics of ~AND gates are such that if one of the inputs to a 28 ~AND gate is zero the output of the NAND gate must be one or 24 high regardless of the condition of the other inputs thereto.
2s Therefore, the conductor 122 will carry a high or one signal 26 to one of the inputs of the second NAND gate 116. Since the 2~ conductor 40 is not connected to ground at this time, the 28 resistor 118 will connect the voltage supply to the other in-~9 put of the second NAND gate 116 therefore making the output 80 Of the second NAND gate 116 zero or low. This signal will be ~orm 233 1 transmitted along the conductor 120 to the other input of 2 the first NAND gate 112. The output of the first N~ND gate 8 112 therefore being high or one will be transmitted along ~ the conductor 124 to the clock inputs o~ all o~ the flip-~ flops. The flip-flops are all of the type which will clock 6 or move the information therein one stage whenever a rising 7 pulse is presented to them. Note that since all of the flip-8 flops are clocked by the same pulse, it is necessary that the xise time of the clock pulse be less than the total propagation o time within the flip-flops. In this case, these particular 11 flip-flops have a propagation time of approximately 150 nano 12 seconds as a result of the master-slave relationship built 18 into them. Therefore, the rise of the clock pulse which is 14 generated by the first NAND gate 112 must be faster than 150 -16 nano seconds. This will occur, as will be demonstrated, and 16 therefore the information contained within the flip-flops 88, Iq 9~, 94, 96, 98 and 100 will be moved one stage when the clock 18 pulse is received. Assume, for example, that a defective glass 19 container has been detected and that this information is stored 20 in the flip-flop 98 which would then indicate that the output 21 Q of the flip-flop 98 is one or high. When the clock pulse 22 occurs, this information is then shifted into the flip-flop 100 28 which then presents this information on its Q output terminal a4 along the conductor 130 to the NAND gate 126. Simultaneously, 26 the output from the ~AND gate 112 will be high or one and will 26 be carried by the conductor 128 to the NAND gate 126. This is 27 a unique condition for the NAND gate 126, that is two simul-28 taneously high inputs, and the output of the NAND gate 126 will 20 be a zero signal along the conductor 134. Note that while 80 these signals from the NAND gate 112 remain on during the entire ~2 : ;;

Form 233 ~-13792 3~9 -1 gauging period, all of the flip-flops will be clocked only 2 once during this time since they are responsive only to ~he 8 rising voltage which occurs at the beginning of the gauging ~ cycle or conversely at the end of the index cycle. Thus 6 with a zero output on the conductor 134 to the control relay 6 132, the control relay 132 will transmit a signal to the 7 solenoid valve 28 along the conductor 56 which will cause the 8 tip 26 to remain extended during the gauging period. Then, 9 during the next index cycle, the glass container that was so lo held will be rejected by the diverter bar 18. At the end of 11 the gauging cycle, the switch 34 will move from contact with 12 the conductor 41 to contact with the cor.ductor 40. When this 18 occurs, it is desired to have a very sharp transition to give 1~ the fast rise time necessary to prevent spurious clocking of 15 the flip-flops within the system. Also, it is desirable to 16 avoid ambiguous signals resulting from possible bouncing of Iq the contacts within the switch 36. Therefore, note that when 18 a wiper arm 136 within the switch 36 begins to move from the 19 conductor 41 to the conductor 40, the output of the ~AND gates 20 112 and 116 will not change state immedi~tely. This is so 21 because the NAND gate 112 will i~mediately see a high input 22 through the resistor 114 to the positive voltage supply. In 28 addition though, it will continue to see a low input along 24 the conductor 120 from the ~AND gate 116. When contact of a6 the wiper arm is made with the conductor 40, the N~ND gate 116 26 will then have one low input, since the resistor 11~ will now 27 be grounded, and will therefore immediately switch states since 28 it no longer has presented to it two high inputs. Likewise, 29 the first NAND gate 112 will also switch states immediately 80 at this point since it will then have presented to it two high ~1 .

~14-l~c~rm 23.

' 1~)4~349 . I
1 inputs, namely the input through the resistor 114 to the 2 ~ositive voltage supply and the now high output along the 8 conductor 120 from the NAND gate 116. The result is a very 4 fast switching time ~ith a correspondingly fast rise time of 6 the voltage and immunity from ambiguous results caused by 6 possible bounce of the wiper arm 136 as it makes contact with 7 the conductor 40. Since the switch 36 is a mechanical switch, 8 there may be some vibration at the time the wiper arm 136 9 moves. However, as can be seen in the description of the lo movement of the wiper arm 136 from one position to another, Il once contact is made, the ~A~D gates 112 and 116 unambiguously 12 switch states and will stay in the state to which they were 18 switched unless the wiper ar~ 136 has sufficient momentum to 14 make contact once again with the conductor 41. The net result lS is an output which is very rapid in rise time and which is 16 immune to switch bouncing. Then, at the beginning of the next 17 gauging cycle, the wiper arm 136 will then move from contact 18 with the conductor 40 into contact with the conductor 41 with 19 the result previously noted Oc rapidly clocking all of the 20 flip-flops one position whlle not allowing the information 21 contained therein to be moved more than one position. I have, 28 therefore, determined that, in general, any master-slave flip-28 flop may serve as the information storage and transmission 24 element so long as the clock pulse thereto may be shaped to 2$ have a rise time which is faster than the transmission time of 26 information through the flip-flops.

a8 sa

Claims

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. In an inspection machine for glass containers wherein glass containers are removed one at a time from a continually moving conveyor, wherein said glass containers are serially indexed through a plurality of inspection stations and wherein said inspection machine includes a bottle defect logic and detection means, having a plurality of output conductors, for generating signals on said output conductors if said inspect-ed glass containers are determined to be defective in one or more aspects at any one of said inspection stations, an improved memory system for said inspection machine which comprises, in combination:
a plurality of master-slave type flip-flops, connect-ed in series, said plurality of flip-flops being one more in number than the number of said inspection stations;
means for connecting an output conductor from said logic means to each one of said flip-flops except the last one of said plurality of flip-flops;
timing means for presenting a first electrical state when said inspection machine is inspecting and a second electri-cal state when said inspection machine is in its index cycle;
electronic clock circuit means, connected to said timing means and each of said flip-flops, for generating a clock pulse, having a rise time faster than the information transfer time through said flip-flops, in response to the transition of said timing means from said second electrical state to said first electrical state; and electronic output circuit means, connected to said clock circuit means and the output of the last one of said flip-flops, for generating a signal when said last flip-flop carries a signal indicating the presence of a defective glass container and when said clock pulse is present.

2. The memory system of Claim 1 which further includes:
means responsive to a signal from said output circuit means for causing rejection of a defective glass container.

3. The memory system of Clain 1 wherein said means for presenting a first and a second electrical state comprises:
a rotary cam; and a switch operated by said cam, said cam being contoured to place said switch in a first electrical state when said inspection machine is inspecting and in a second electrical state when said inspection machine is indexing.

4. The memory system of Claim 1 wherein said electronic clock circuit means comprises:
A first NAND gate having a first input terminal connected to ground through said timing means when said inspection machine is gauging, a second input terminal and an output terminal connected to a clock input terminal of each one of said plurality of flip-flops and further connected to said electronic output circuit means;
a second NAND gate having a first input terminal connected to ground through said timing means when said inspection machine is in its index cycle, a second input terminal connected to the output terminal of said first NAND gate, and an output terminal connected to said second input terminal of said first NAND gate;
a voltage supply;
a first resistor connecting said voltage supply to said first input terminal of said first NAND gate; and a second resistor connecting said voltage supply to said first input terminal of said second NAND gate.

5. The memory system of Claim 1 wherein said plurality of flip-flops each includes a direct set input terminal and where-in said means for connecting said logic means to each of said flip-flops comprises:
a plurality of optical isolators, equal in number to the number of inspection stations, one optical isolator being uniquely associated with each one of said inspection stations, said optical isolators generating an output signal when the inspection station with which it is associated detects a defective glass container as determined by a signal from said bottle defect logic and detection means; and a plurality of electrical conductors for conducting a signal from the optical isolator associated with a particular inspection station to the direct set input of one of said flip-flops is associated with the first one of said inspection stations and the Nth one of said flip-flops is associated with the Nth one of said inspection stations.

6. A method for retaining memory of a defective glass container during the entire cycle of a glass container inspection machine which indexes glass containers through a plurality of inspection stations and generates a defect signal when a glass container fails to pass the inspection performed at any one of said plurality of inspection stations, which comprises the steps of:
loading a defect signal from any one of said inspection stations into a master-slave type flip-flop uniquely associated with that one of said inspection stations;
presenting a first electrical state when said inspection machine is inspecting;
presenting a second electrical state when said inspection machine is in its index cycle;
generating a clock pulse, in response to the transition from said second electrical state to said first electrical state, having a rise time faster than the information transfer time through said flip-flop;

shifting any information carried by said first mentioned flip-flop into a second master-slave type flip-flop uniquely associated with the next one in sequence of said inspection stations in response to said clock pulse;
continuing to shift information relative to a defective glass container in response to successive clock pulses as said glass container is indexed from inspection station to inspection station;
shifting any information carried by a flip-flop associated with the last one of said inspection stations into an output master-slave type flip-flop in response to said clock pulse; and rejecting any glass containers causing a signal to be carried by said output flip-flop.