CA1043871A - Digital controller for thyristors - Google Patents

Abstract

ABSTRACT OF THE DISCLOSURE
Apparatus for digitally controlling a thyristor includes a pulse frequency modulator having a resettable inte-grator that is coupled to an alternating current power source which supplies the thyristor. A predetermined number of inte-grated signals are produced by the integrator in response to each half-cycle of the alternating current waveform. The integrated signals are processed by a comparator circuit relative to a ref-erence voltage to produce a corresponding pulse train output having an inverse-cosine time separation between pulses. Means are provided to synchronize the pulse train with the power source by introducing compensating changes in the reference voltage that correspond to the time difference between the end of each positive half-cycle of the alternating current waveform and the time taken to generate the predetermined number of pulses. A counter pro-duces a binary output signal corresponding to the pulse train which is compared with input data from a digital computer. A digital comparator generates a signal to enable a gate that couples the pulse train to a thyristor control input when the binary output signal and the computer data are in numerical coincidence.

Description

This invention relates to thyristor control apparatus and more particularly to apparatus for controlling a thyristor in response to data from a digital computer.
Thyristors are electrical devices used in the control of current flow to electrical loads and comprise any two, three, or four terminal semiconductor switch having a bistable action.
They are available as unidirectional and bi-directional devices, - both requiring control circuits for switching the devices on and off. Using such circuits, thyristors are switched into the on-state by applying a triggering signal to their gate or by in-creasing an o~f-state voltage until it exceeds a breakQver voltage value.
Much of the interest in the theory and design of phase-¦ control circuits for thyristors arises from the fact that a variety of industrial equipments require convenient control of electrical - power supplied to them. Applications in which such equipment is .i, - .
used include lighting-control installations, motor-speed control, power regulation, and the like, all of which are conducive to thyristor control.
~;, 20 A popular thyristor is a three terminal Silicon-Controlled Rectifier (SCR) which is a unidirectional device having anode, cathode and contral gate electrodes. The ability of the SCR to .. .. . .
~, switch from a nonconducting to a conducting state in response to ~ ;
a small control trigger signal applied to its control gate is a key factor in its popularity for control of electrical power and the impetus which led to the discovery of the present invention.
The direct current component of the rectified output from a SCR supplied from an a.c. line is proportional to the cosine of the trigger pulse angle referred to the line voltaye. This is , 30 the interpretation of "phase control" and there exist many known circuits for controlling thyristors by this means. In order to make the d.c. output proportional to a control input, an inverse--- 1 -- ~ .
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cosine function is required to be introduced into the control ... .
circuit. A problem in this respect is that good linearizationis difficult to achieve with certain known control circuits whereas other known control circuits require an accurate cosine : : -wave to add to the control input. In the event that digital data are to be used to control the thyristor, the foregoing ~-control circuit types also require digital-to-analogue (D/A) converters which adds to the complexity of control systems using such circuits and increases manufacturing costs.
The present invention provides apparatus for phase control o~ a thyristor which will yield a good linearization -of the direct current component of the rectified output from a SCR supplied from an a.c. line.
The invention also provides apparatus for directly ;~
controlling the triggering of a thyristor in response to input data received from a binary computer.
A further provision of the invention is that the received -;
computer data does not require digital-to-analogue converters for digital control.
The problems of the prior art as noted in the foregoing remarks may be substantially overcome and the various provisions o~ the subject invention achieved by xecourse to the invention which is a digital controller for triggering a thyristor that ;' is operably connected to a gate and to a power source of cyclic signals. The controller comprises pulse frequency modulator means having an input coupled to the source and an output pro-ducing a predetermined number of pulses with a predetermined time separation in response to each half-cycle of individual ones of the signals, the pulse output being coupled to an input , of the gate. Binary counter means are provided having a first input coupled to the pulse output and first, second and third digital outputs each producing predetermined binary count -

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,. . .. .. . . . . .

signals corresponding to the pulses. The invention further com-prises digital comparator means having a first input adapted to receive data from a digital computer, a second input coupled to the first digital output, and an output producing a signal coupled to the gate input to enable the gate for triggering the ~ -~
thyristor when the first binary count signals and computer data ;
are in numerical coincidence.
The subject invention also relates to an integral pulse .
frequency modulator that is responsive to a source of cyclic signals and a source of reference voltage for producing a train -~;
.. . .
of pulses having a predetermined time separation. The modulator -comprises resettable integrator means having an input coupled to the source of the signals and an output producing a pre-~'1 determined number of integrated signals in response to each half-cycle of individual ones of the cyclic signals. The mod-ulator further comprisas comparator means having a flrst input ;~
coupled to the integrated signal output, a second input connected ~i to the source of reference voltage and an output forming a pul~e ¦ when each integrated output signal is equal in magnitude to the 1 20 reference voltage. A portion of each output pulse is coupled via reset means to the integrator means to reset the modulator to ¦ a zero input condition after each pulse is produced.
;. :.: :
The invention will now be more particularly described with reference to embodiments thereof shown, by way of example, 3 ln the accompanying drawinys, wherein:
Fig. 1 is a block diagram of a thyristor connected to ., . : .
a load and supplied by an a.c. line, including a controller in !: accordance with the subject invention;
., : -~
Fig. 2 is a graph showing a voltage waveform from the .. ,.
a.c. line of Fig. 1 and a load voltage waveform appearing across the load;
Fig. 3 is a block diagram of a digital controller for .,~ , .
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' ;~',, ' ' ," ~ , . " ' ' ' '' ', . ' " "' ' , ' " ' "' ' , " ' ,, ' . 1,,, '. ' , . . . .

~ æ~, a thyristor in accordance with the invention;
Fig. 4 is a circuit diagram of a pulse-frequency mod-ulator and a zero-crossing detector in accordance with the in-vention;
Fig. 5 is a circuit diagram of a pulse train synchron- -., ization controller used in the digital controller of Fig. 3; ~ -Fig. 6 is a timing diagram of signals used in connection -with the synchronization controller of Fig. 5;
~! Fig. 7 is a circuit diagram of a digital counter-com-parator and counter reset logic used in the controller of Fig. 3;
Fig. 8 is a timing diagram of signals used in connection with the circuits of Fig. 7; ~ -3 Fig. 9 is a circuit diagram of a gate control circuit used in the controller of Fig~ 3; and l Fig. 10 is a circuit diagram of a thyristor triggering ~`
circuit.
A basic thyristor circuit employing a digital controller 11 in accordance with the invention may be seen in Fig. 1. The ,7~ ~ thyristor, shown as a Silicon-Controlled Rectifier (SCR) 12, is ; 20 supplied through a fixed load 13 from a power source of cyclic signals indicated as an a.c. line 14. An output of triggering ,~ signals from the digital controller ll is coupled to an input of the SCR 12 through a pulse transformer 15 to fire the SCR. A
digital input signal to the controller 11 is obtained from a digital computer (not shown) and is applied to a digital control input 16.
Fig. 2 graphically illustrates the relationship of the - line 14 voltage and the load voltage developed across the load 13 when the SCR 12 conducts during the positive half-cyale of an a.c. waveform 18. And, it will be noted that a load voltage . : .
waveform 17 is initiated at a phase angle of e degrees after the :.'.

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zero crossing point of the positive going half-cycle of the waveform 18. Phase control of the SCR 12 using the controller ~
11 provides the required initiation of the waveform 17 in respect ~-of the waveform 18. Moreover, the controller 11 provides good ~-linearization of the load voltage relative to the digital input -~
signal without recourse to digital-to-analogue converters.
The component parts of th~ controller 11 are shown inter- ~ ~
connected in Fig. 3 and include various inputs to the controller, -as well as the trigger output therefrom which is applied to the -~
SC~ 12. It ~ill be observed that the signal paths shown as broken IjL,''j~,. '," "' ' ' lines represent digital signal routes whereas the paths shown in solid line form represent continuous signal paths. The con- -~
troller 11 comprises an integral pulse-frequency modulator 20 ~
having an input 21 connected to the line 14. A pulse train out- -put 22 of the modulator 20 produces a predetermined number, M, of pulses with an inverse-cosine time separation in response to each half-cycle of the waveform 18, where M is a number of equal d.c. output increments required from the SCR 12.
The modulator 20 includes a resettable integrator khat produces integrated signals in response to each half-c~cle of the wave~orm 18. The pulse train appearing at the output 22 is kept constant in response to the threshold voltage applied to a pulse emission threshold input 2~ from the pulse train synchronization controller 31 driven b~ a binary counter 27. When the time integral of the modulator 20 attains the magnitude of a predeter-~... :
mined pulse-emission threshold voltage, a pulse is emitted which also resets the integrator to zero~ A portion of each emitted pulse is coupled via an internal reset circuit 25 to the resettable integrator to achieve reset. With the aforenoted choice of in-put waveform, the time separation of the pulses at the output 22yields the required inverse-cosine characteristic.

The output 22 is also coupled to inputs of an SCR gate .~
26 and the binary counter 27. The gate 26 .is normally disabled ~:
until enabled by an output signal from a digital comparator 28.
In order to obtain the required enabling signal, the binary ; - -counter 27 produces binary count output signals, corresponding to the pulses of the pulse train, which are applied to one input .
of the comparator 28. A second input 16 of the comparator 28 - -receives data from the output of a digital computer (not shown).
When the binary count signals and the data from the aomputer are ~ - .
in numerical coincidence, the comparator produces tha enabling signal which permits the gate 26 to transmit the pulse train ~
from the modulator 20 to a thyristor triggering circuit for the :
~ remainder of the positive half-cycle of the waveform 18.
.1 The controller 11 further comprises a zero-crossing . :, .
-~ detector 29 which has an input coupled to the source 14 and a reset output 30 that produces a cycle-end signal for each po-~, larity change in the waveform 18~ The output 30 is shown coupled ~:
.~ : to the modulator 20 and the cycle-end signal resets the mod~
ulator to a zero input condition at the end of each waveform 18.
¦~ Z The output 30 is also coupled to the gate 26 to disable the gate .. ~ .
during the negative half-cycle of the waveform 18.
A pulse train synchronization controller 31 is employed I to provide compensation for variations in the integrated signals .l and the voltage 23 so that the pulses at the output 22 will remain substantially constant for each half cycle of the wave-form 18. It should be noted that the instantaneous frequency of ! ~ the output pulses from the modulator 20 increase with the input ¦ magnitude of the waveform 18 and also vary in accordance with the time integral of the modulator 20. Moreover, any disturbance 30 in the voltage 23 which introduces a corresponding disturbance at the input 24 will cause the output pul~es to occur at different . - 6 -...
., , 3~
times. These effects are undesirable and are reduced by the controller 31 which introduces compensating changes in the mag- -nitude of a pulse emission threshold voltage and thus ensures that the predetermined number of pulses are emitted and main~
tained for each half-cycle of the waveform 18.
A first input 35 of the controller 31 is connected to the source of the voltage 23. In accordance with the fore-going discussion, the voltage at the input 24 is compensated ~ ;
in amplitude by the controller 31 for any disturbances in the voltage 23 which introduces a corresponding disturbance at the input 24. A second input of the controller 31 is coupled to a second binary signal output from the counter 27. Slgnals from the second binary signal output correspond to the time differenae between the end of a positive half-cycle of each line voltage waveform 18 and the time taken to generate M pulses.
~ A third input to the controller 31 is the cycle-end signal from Z the output 30 of the zero crossing detector 29 which is used in , conjunction with the binar~ signal input to make the compensating ;;
¦ adjustments in the threshold voltage applied to the input 24 in order ~o synchronize the operation of the modulator 20 with -~
the waveform 18. A more detailed description of the controller 31 and its operation is presented in a following description of the controllercircuit.
A counter reset loyic 33 receives a first input from the reset output 30 and a second input from the counter 27. This Z latter input receives signals that correspond to the time taken ,~ to generate M pulses. This combination of both input signals ;
operate the logic 33 to produce a reset signal that is applied i to the counter 27 in order to provide reset of the counter 27 to a zero input condition at the end of each half-cycle of the ..
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waveform 18. In addition, the logic 33 provides that the reset output is delayed in the event that the M pulses have not been produced at the time of zero crossing of the negative going wave-form 18. The logic 33 and its operation are described in greater detail in a following description of a circuit therefor.
' Fig. 4 lllustrates circuit diagrams for the modulator 20, , , the internal reset circuit 25 and the zero-crossing detector 29 , which form part of the controller 11. The input 21 is connected , ' ', across the line 14 and includes resistor 40 in series with an in- ' put terminal 41 of an amplifier 43. The resettable integrator o~
, the modulator 20 comprises a capacitor 44 which controls integ- ;
ration of the waveform 18 using the amplifier 43. ~ -s ~ .
~ In the selection of the amplifier 43, which is used here , ~, ', as an integrator, the amplifier selected requires a relatively ~` high "slew rate": i.e., an amplifier in which the time rate of change of its closed-loop output voltage under large~signal con~
s, ditions is high. This will ensure that the amplifier settling time will be at least as short as the integrator capacitor dis-' charge time so that the governing actor in resetting the integ- , , ''' 20 ra~or to zero is the time taken to discharge the capacitor 44. '' ,~l The time constant of the resettable integrator portion of the modulator 20 is yoverned by the value of the capacitor 44 l which is selected to provide M lntegrated signals at the output ,1, 42 of the amplifier 43. Considering for the moment only the positive half of the waveform 18, as the waveform inareases positively ~rom zero, a first integrated output signal appears . .
'i, at the output 42 and concurrently appears at i.nputs 45 and 46 of 'l comparator amplifiers 47 and 48 respectively. When the inte- ' , grated signal equals the magnitude of a negative d.c. threshold '"

~, 30 voltage 23', derived from the voltage 23 and coupled through a "

resi,stor 49 to an input 50 of the amplifier 47, the amplifier 47 .
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switches on and produces a corresponding positive pulse at its output 51. A portion of the output pulse is coupled through a resistor 52 and a diode 53 to the base electrode of a transistor 54. It will be observed that the emitter and collector elec- -trodes of the transistor 54 are connected across the capacitor -~
44. The positive output pulse triggers the transistor 54 into --conduction which discharges the capacitor 44 and resets the mod-ulator 20 to a zero input condition after the output pulse is -produced. The foregoing operation continues successively until M output pulses are produced at the output 51.
In a similar manner, the comparator amplifier 48 pro-duces negative pulses at its output 55 during the interval of the ;
negative half-wave of the waveform 18. In this case, it will be noted that the negative output pulses are produced when positive ,~, .
integrated signals appearing at the input 46 equal in magnitude a positive d.c. threshold voltage 23" . The voltage 23" is 1: .. , :~ .
derived from the voltage 23 and i~ applied through a resistor 56 j~ to a second input 57 of the amplifier 48.

3 ~ In like manner to the transistor 54, a transistor 64 .~ . . .. ...
~20 conducts and discharges the capacitor 44 on ~he occurrence of each negative pulse at the output 55 which is coupled to the base o the transistor 64 through a resistor 65 and a diode 66.
', Sensitivity to noise of the comparator amplifier switch-ing levels is reduced by introducing hysteresis in the modulator 20. This ef~0ct is achieved by feeding a portion of the output ~i~ Of each comparator amplifier 47 and 48 to its input terminals 50 and 57, respectively. ~hus, in the amplifier 47, the signal is -i~ fed back via a resistor 76 and in the amplifier 48, feedback occurs through a resistor 77.
The zero-crossing detector 29 comprises a comparator amplifier 58 having its input connected across the line 14. The ~''i '. ~

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amplifier 58 is res~sive to polarity changes on its input which cause it to switch on and off to produce signals at its output 59. ~ -The signals appearing at the output are limited to values of zero and +5VDc by means of clamping diodes 60 and 61. Accordingly, a cycle-end high pulse signal is generated at a junction of the diodes 60 and 61, representing an input 67 to a NAND gate 62, to disable the SCR gate 26 during the negative half-cycle of the waveform 18. And, using the NAND gate 62 as an inverter, a cycle-end low pulse signal is produced which is required in the counter reset logic 33.
The output of the gate 62 is coupled through a capacitor 63 to the base electrode of a transistor 64 which is also con-nected across the capacitor 44. Discharging the capacitor 44 ~-resets the modulator 20 to a zero input condition at the end of each line voltage cycle thereby ensuring that the resettable integrator starts every cycle with zero initial condition. ~ ;
Each of the outputs 51 and 55 are lîmited to correctly interface the output voltages to transistor logic units in which . .
the logic levels are 0 VDc and ~5VDc. ~his is accomplished using ~; 20 clamping diodes 68 and 69 for the amplifier 47 and clamping diodes 71 and 72 for the amplifier 48.
A NAND gate 73 operates as an inverter for the output of the amplifier 47. The output of the gate 73 and the output of the ampliier 48 are coupled to a NAND gate 74 which produces a continuous train of positive pulses corresponding to the two ~ -. .
pulse trains produced by the positive and negative half-cycles o~ the waveform 18. The continuous pulse train appears therefore ~: :.: ., ~ ~ at the output 75 and supplies the binary counter 27 and the SCR
,~ .
gate 26.
Fig. 5 is a circuit diagram of the pulse train synch-ronization controller 31 which comprises three amplifiers. I'he ' ,: ' , - 10 - .
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first amplifier 80 is a summing integrator. The second amplifier 81 is a weighted summing amplifier. And, the third amplifier 82 operates merely as an inverter. A feedback network comprising a capacitor 97 in parallel with a resistor 99 bridges the amplifier 81 and a similar network comprising a capacitor 98 and a resistor 100 bridges the amplifier 82 to provide a measure of noise immunity in the amplifiers. -Two signals are applied to the input 32 of the amplifier 80. One input signal 84 comprises the cycle-end signal obtained from the output of the NAND gate 62 and corresponds to the time interval of the positive half-wave of the waveform 18. The waveform time relationship may be seen in Figs. 6(a) and (b).
The pulse signal 84 is coupled through a resistor 85 to the input 32. The other input signal is taken from a binary output 88 of the counter 27 and appears as a positive pulse signal 86 '~ in Fig. 6(c). The signal 86 is coupled through a resistor 87 ~ to the input 32. It will be noted that the signal 86 corresponds ;l~ to a time interval representing the time taken to produce M
b pulses where ~he time is less than the duration of the positive ' 20 half-wave portion of the waveform 18. This condition could arise , .. .. .
as a result of a decrease in the reference voltage 23O
~' Under the foregoing condition where the modulator 20 ;
J is operating fast and pro~uces M pulses in less time than the duration of the positive half-wave portion of the waveform 18, the controller 31 operates to vary the voltage 23 and produces a d.c. threshold voltage output which is applied to the pulse -emission threshold input 24 of the modulator 20 to slow its ,~ , operation. In this way, the modulator 20 is synchronized with ;
, the waveform 18.
:, . .
The algebraic sum of the signals 84 and 86 is shown as a pulse siynal 90 which is integrated by the amplifier 80 .~ ', .', ; .

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at a rate determined by the value of an integrating capacitor 91. The output of the amplifier 80 is a positive signal 92 shown in Fig. 6(e). The signal 92 is coupled through a resistor ~ -93 to an input 94 of the amplifier 81. It will be seen that the voltage 23 is similarly coupled to the input 94 through a ,,~, resistor 95. The signal 92 is inverted in the amplifier 81 and is added to the voltage 23, producing a modified negative thxeshold voltage 23' with a proportionally increased value at the output of the amplifier 81. The voltage 23' is coupled '' through a resistor 96 to the input of the amplifier 82 and appears at its output as a modified positive threshold voltage l 23" with a like proportionally increased value. The higher `~ speed of operation of the modulator 23 is thus reduced for the '~'i case where the voltage 23 falls below a predetermined value. ~-.~' In the case where disturbances'in the voltage 23 cause i~ it to be increased, a negative signal 92' appearing in Fig. 6(i) - ' is subtracted from the voltage 23 to proportionally,decrease the j~ voltages 23' and 23" . The operation of the controller 31 is ,'' '1~ similar to that already described except for the different ' relationships of the signals. Thus, in Fig. 6(f) the signal 84 "' i again represents the time interval of the positive half-wave of 'I the waveform 18, whereas a pulse signal 86' in Fig. 6(g) cor- ';
responds to a time requirsd to produce M pulses where the time ' is greater than the duration of the aforenoted positive half- ;
~ wave portion. The sum o the signals 84 and 86' therefore '¦~; produces a pulse signal 90' which appears at the output of the ,' .~ ..... . .
amplifier 80 as an integrated negative signal 92'. As with the : ~, signal 92, the signal 92' is added algebraically to the voltage , , 23 with the result that the negative signal 92' is subtracted , ¦ 30 from the voltage 23 to produce modified voltages 23' and 23" ' ~, which are proportionally decreased. In this way, control of , ' l . .
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pulse train synchronization is obtained so that step changes in -.:
the voltage 23 will be compensated and a constant M number of pulses will be generated for each half-cycle of the waveform 18. -~
FigO 7 is a circuit diagram of the binary counter 27, ' the digital comparator 28, and the counter reset logic 33. The;, counter 27 uses eight flip-~lops 105 for the digital comparator -, 28 and an additional flip-flop 106 to generate logic levels required for the controller 31. It will be noted that if M, .
, the number of d.c. increments required from the thyristor 12 1 10 has been selected as 256, then, since M=2n, there is required a chain of ~=8 J~ master-slave flip-flops 105.
~, The operation of the counter 27 requires the following conditions:
(i) A clock pulse applied to the input of the counter , 27 must be wide enough to allow data to settle in ~ ;
, 1 a master section thereof. This time, which is set .
~ ~ ,. : .. .
up time for logic "1", is 20 ns minimum. This ~-condition is provided by the pulses of the con-tinuous pulse train at the output 75 which is ;
coupled to an input 122 of the counter 27.
(ii) All flip-flops are connected to a positive supply ~ ~ ,... ..
'l voltage so that terminals J and K are high. This l ~ is accomplished by means of a resistor 107 con-, ... . . ..
nected to the supply voltage. ';
(iii) Flip-flops 105 are reset on application to a reset ~; bus 108 o~ a low transition generated by the out-put o~ the counter re~et logic 33. ,;~
(iv) An output s~age flip-10p 106 is reset on a negative pulse produced by a resistor 109 shown connected from a reset terminal 110 to a positive source of operating voltage, and a capacitor 111 , ~ ~ , ; - 13 -1, ' - ' ' ' ' , :":' ~ ' ; . ;' .,, : , . .. .

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which is connected from the reset terminal 110 to the output 7~ of the NAND gate 62.
The counter reset logic 33 comprises three NAND gates 112, 113 and 114 arranged in the configuration shown in Fig. 7.
The reset logic 33 has one input that is coupled to an output 115 of the counter 27 which produces output signals 116 and 116' shown in Figs. 8(c) and (f) respectively. It will be noted that these signals correspond to the time taken to generate M

, .
pulses. For example, the signal 116 corresponds to a time j 10 which is less than ~, the duration of the positive half-wave of the waveform 18. The signal 116', on the other hand, cor-responds to a time which is greater than ~.
Under the condition where M output pulses are generated ~ :
in a time less than ~ and the signals 84 and 116 are applied to the inputs of the NAND gate 112, a reset signal 117 is generated ;! which is applied to the reset bus 108 to reset the flip-flops 105 at the end of the positive half-wave of the waveform 18. On the other hand, in the event that M pulses are generated in a time greater than ~, then the input signals applied to the NAND
gate 112 are 84 and 116' which results in the formation of a re~et signal 117' that is of greater duration than the reset slgnal 117. This last condition implies counting of the first part of the train of pulses ~or the negative half-cycle of khe , . .
waveform 18, assuming symmetry of the trains of pulses about After M pulses are generated, the 1ip-flops 105 are reset by the signal 117'. In effect, thereore, the reset signal 117' ~i acts to inhibit reset of the flip-flops 105 after the end of .1;: '. ,.`.'. :.
the positive half-wave of the waveform 18 until the required pulse count is obtained.
.
It will be seen from Figs. 8(c) and (f) that the output ~ 115 stays high for the remainder of the period even after the ; reset condition is obtained for the flip-flops 105. Therefore, .:
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the flip-flop 106 must be reset separately at the end of each cycle in order to obtain the signals required by the controller 31 for the conditions stated above. Separate reset is described in paragraph (iv) of the required operating conditions for the counter 27.
The operation of the digital comparator 28 of Fig. 7 will next be described. When all of the outputs 118 from the flip-flops 105 are respectively different from the computer ;;
data which is applied to the input 16, then a logic "1" for each and every one of the exclusive OR gates 119 will be ob- ~ ' tained at their respective outputs. Accordingly, a NAND gate 120 generates an enabling signal at its output 121 for a numerical coincidence of the inputs 118 and the data from the computer.
! A circuit diagram of the SCR gate 26 is shown in Fig. 9 and comprises three NAND gates 125, 126 and 127. When enabled, l , the SCR gate 26 admits the pulse train for the remainder of 3~ the positive half-cycle of the waveform 18 to fire the SCR 12 l under conditions predetermined by the external digital control .
l~ 20 comput~r (not shown~.
, .:. . ,: .
A first input 128 receives a signal from the OUtpllt 67 o~ the zero-crossing detector 29 which is coupled from the input of the NAND gate 62 and corresponds to the positive hal- ;;
f cycle of the waveorm 18. A second input 129 receives the ena-bling signal rom the output 121. A third input 130 receives the continuous positive pulse train from the oukput 75. And, ii an output 131 of the NAND gate 127 produces a corresponding j negative pulse train which is applied to an SCR trigger circuit ~, shown in Fig. 10, coupled to an input 137.
In the foregoing description of the embodimentq of the invention, there were introduced all the circuits required to ~ .

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generate a pulse train which could be used for the direct diqital control of a thyristor. The SCR is actuated when the pulse train from the output 131 is coupled to the input 137 of a NAND gate 132 in Fig. 10. The pulse train is inverted at the output of the gate 132 and is coupled through a resistor 133 to the base electrode of a transistor 134. The positive pulses appearing at the base trigger the transistor 134 into conduction to energize the primary winding of the transformer 15 and to produce in the secondary winding a voltage Vc required to fire ~ 10 the SCR 12 of Fig. 1. ;~
`, A diode 135 is connected across the primary winding - , . - .
l and conducts when the transistor 134 is cut off and a back emf ; `~-!
, is generated. The back emf is therefore short-circuited to , ., :
prevent possible damage to the transistor 134. Further pro tection for the transistor is achieved by means of a bias diode ,-136 connected in series with the emitter electrode to ensure that the transis~or does not conduct when its base is at zero volts.
It is to be understood that the invention herein dis-closed is not limiked to the use of a sinusoidal line voltage waveform. Although the embodiments of the invention have been described using the sinusoidal waveform, other cyclic waveforms may be used such as square waves and sawtooth waves provided that the same waveform is supplied to the thyristor and the i;
digital controller of the invention~ In this event, the output -22 of the modulator 20 produces M pulse with a predetermined . ~ .
time separation in response to each half-cycle of the other l~ ~ cyclic waveforms.
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Claims (19)

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:

1. A digital controller for triggering a thyristor operably connected to a gate and to a power source of cyclic signals, the controller comprising:
pulse frequency modulator means having an input coupled to said source and an output producing a predetermined number of pulses with a predetermined time separation in response to each half-cycle of individual ones of said signals, the pulse output being coupled to an input of the gate;
binary counter means having a first input coupled to the pulse output and first, second and third digital outputs each producing predetermined binary count signals corresponding to said pulses; and digital comparator means having a first input adapted to receive data from a digital computer, a second input coupled to the first digital output, and an output producing a signal coupled to said gate input to enable the gate for triggering the thyristor when the first binary count signals and computer data are in numerical coincidence.

2. A controller as claimed in Claim 1 wherein the pulse frequency modulator means includes resettable integrator means coupled to said source and producing integrated signals in said predetermined number in response to each half-cycle of individual ones of the cyclic signals, a threshold voltage input, the pulse output producing a train of pulses in response to the integrated cyclic signals and threshold voltage, and means coupling a portion of the output pulses to said integrator means to reset the mod-ulator means to a zero input condition after each pulse is pro-duced.

3. A controller as claimed in Claim 2, further comprising thyristor gate means having a control gate output coupled to a control input of the thyristor, a first input coupled to the pulse output, and a second input responsive to the enabling signal to couple the pulse train to said gate output.

4. A controller as claimed in Claim 3, further comprising zero-crossing detector means having an input coupled to the source of cyclic signals and a reset output producing a cycle-end signal for each polarity change in individual ones of the cyclic signals, and means coupling the reset output to the re-settable integrator for resetting the modulator means to a zero input condition at the end of each cyclic signal and to the gate means to disable said gate means during the negative half-cycle of each cyclic signal.

5. A controller as claimed in Claim 4, further com-prising pulse train synchronization controller means having a first input coupled to a source of reference voltage, a second input coupled to the reset output, a third input coupled to the second digital output, the second binary count signals each cor-responding to the time difference between the end of a positive half-cycle of each cyclic signal and the time taken to generate said pulses, and a threshold voltage output producing compensating changes in the reference voltage in response to the algebraic sum of each cycle-end signal and second binary count signal to com-pensate for variations in the integrated cyclic signals and ref-erence voltage so that the predetermined number of pulses will remain substantially constant for each half-cycle of individual ones of the cyclic signals.

6. A digital controller as claimed in Claim 5, further comprising counter reset logic means having a first input coupled to the reset output, a second input coupled to the third digital output, each third binary count signal corresponding to the time taken to generate the predetermined number of pulses, and an output generating a reset signal coupled to the binary counter means to reset an output counter and intermediate counters thereof to a zero initial condition on the occurrence of a cycle-end signal, and a signal to inhibit reset of the inter-mediate counters until the predetermined number of pulses have been generated.

7. A controller as claimed in Claim 6 wherein the predetermined time separation is an inverse-cosine time separation.

8. A controller as claimed in Claim 1 wherein said modulator means is responsive to the source of cyclic signals and a source of reference voltage for producing a train of said pulses with a predetermined time separation, the modulator means comprising:
resettable integrator means having an input coupled to the source of said signals and an output producing a predetermined number of integrated signals in response to each half-cycle of individual ones of the cyclic signals;
comparator means having a first input coupled to said output, a second input connected to the source of refer-ence voltage and an output forming a pulse when each integ-rated output signal is equal in magnitude to the reference voltage; and reset means coupling a portion of each output pulse to the input of said integrator means to reset the modulator means to a zero input condition after each pulse is produced.

9. A controller as claimed in Claim 8, further comprising feedback means connected between the output of the comparator means and the second input thereof for feeding back a portion of each pulse to reduce the sensitivity of the comparator means to noise interference signals.

10. A controller as claimed in Claim 9 wherein the resettable integrator means comprises an amplifier having a closed-loop output including a capacitor connected between the input and output of the amplifier.

11. A controller as claimed in Claim 10 wherein the reset means is included in the closed-loop output and comprises switch means bridging the capacitor, the switch means being normally non-conductive to allow the capacitor to charge and permit integration of the cyclic signals, and conductively responsive to each output pulse for discharging the capacitor and resetting the integrator means to a zero input condition.

12. A controller as claimed in Claim 11 wherein the comparator means comprises, a first comparator amplifier that is responsive to positive going half-cycles of individual ones of the cyclic signals and a second comparator amplifier that is responsive to negative going half-cycles of indi-vidual ones of the cyclic signals.

13. A controller as claimed in Claim 12 wherein the source of reference voltage includes positive and negative voltages, the negative voltage being coupled to a second input of the first comparator amplifier and the positive voltage being coupled to a second input of the second comparator amplifier.

14. A controller as claimed in Claim 13 wherein the switch means comprises a first transistor having collector and emitter electrodes connected across the capacitor and a base electrode coupled to the output of the first comparator amplifier.

15. A controller as claimed in Claim 14 wherein the switch means further comprises a second transistor having collector and emitter electrodes connected across the capacitor and a base electrode coupled to the output of the second comparator amplifier.

16. A controller as claimed in Claim 15 further comprising zero-crossing detector means having an input coupled to the source of cyclic signals and an output producing a cycle-end signal for each polarity change in individual ones of the cyclic signals coupled to the integrator means for resetting said integrator means to a zero input condition at the end of each input signal cycle.

17. A controller as claimed in Claim 16 wherein the output of the zero-crossing detector means is coupled to the base electrode of the second transistor.

18. A controller as claimed in Claim 17 further comprising pulse train synchronization controller means including summing integrator means for integrating individual ones of the cycle-end output signals and individual ones of a plurality of second binary count signals, each second binary count signal corresponding to a time difference between the end of the positive-going half of each cyclic signal and the time to generate the predetermined number of said pulses, and means coupling the integrated output of the summing integrator means in algebraic summing relation with the source of refer-ence voltage to produce compensating changes in the positive and negative reference voltages so that the predetermined number of pulses will remain substantially constant for each half-cycle of individual ones of the cyclic signals.

19. A controller as claimed in Claim 18 wherein the predetermined time separation is an inverse-cosine time separation.