CA1040742A - Credit accumulator for coin enabled apparatus - Google Patents

Abstract

Title of the Invention CREDIT ACCUMULATOR FOR
COIN ENABLED APPARATUS
Abstract of the Disclosure An electronic credit accumulator for a phono-graph or the like which accumulates credit in succession from any one of five monetary inputs, which adds bonus credits at various input levels to enable a customer selectively to play a standard record or a premium record upon the accumulation of sufficient credit, which accepts cancel signals for reducing credit by an appropriate amount when a selection has been made and which can readily be adjusted to change the bonus levels as well as the prices at which selections can be made. One form of the invention functions in terms of a basic monetary unit while a second form functions in terms of a standard play unit.

Description

104~)742 Background of the Invention There are known in the prior art coin operated phono-graphs in which, in response to the deposit of coins, a customer may make a selection of one or more records. Arrangements have heretofore been devised giving the customer a bonus selection after he has deposited coins aggregating a multiple of the price of a single selection. Such systems of the prior art employ electro-mechanical credit devices.
At the present time a phonograph must be able to per-~it a customer seiectively to play a standard record or a premium record which may, for example, be an album. Moreover, with increase in prices and with the increasing popularity of premium records as well as standard records, and with the present capa-bility of mechanisms to accept bills the credit mechanism, as ` well as the bonus mechanism, necessary to provide the required credit levels and various bonuses at different levels has .
become extremely cumbersome. Not only is the apparatus cumber-some, it is not versatile in that the levels at which bonus credits are awarded cannot readily be changed. Moreover, the 2a prices at which the different selections can be made are not easily changed.
I have invented an electronic credit accumulator which overcomes the defects of credit accumulators of the prior art. My accumulator does not require the multiplicity of electro-mechanical switching devices required in the prior art. My accumulator permits the price at which selections can be made to be changed with ease. It makes provision for changing the bonus levels at which bonus credit are awarded.
Summary of the Inve~tion ! 3Q One object of my invention is to provide an electronic ~- credit accumulator which overcomes defects of credit accumulators of the prior art.

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Another object of my invention is to provide an electronic credit accumulator which does not require a multipli-city of electro-mechanical switches.
A further object of my invention is to provide an electronic credit accumulator which permits the prices of differ-ent selections to be changed with ease.
Still another object of my invention is to proyide an electronic credit accumulator which makes provision for vary-ing the credit level at which bonus credits are awarded to the ; 10 customer.
Other and further objects of my invention will appear from the following description.
In general, my invention contemplates the provision of an electronic credit accumulator for a phonograph or the like which accumulates credit in the form of monetary units or a numbers of standard plays in succession from a plurality of , monetary inputs and which adds bonus credits at various input levels to permit a customer selectively to play standard or premium records upon the accumulation of sufficient credit.
20 Cancel signals resulting from a selection deduct an appropriate ; amount of credit. Provision is made for changing both the prices at which selections can be made and the credit levels at which bonus credits are awarded.
Brief Description of the Drawings In the accompanying drawings which form part of the instant specification and which are to be read in conjunction therewith and in which like reference numerals are used to ;~ indicate like parts in the various views:
Figure 1 is a block diagram of a form of my electronic 30 credit accumulator which operates in terms of money units.
Figure 2 is a schematic view of the money responsive ` and credit cancelling portion of my electronic credit accumulator.

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Figure 3 is a schematic view of the pulse train gener-ator of my electronic credit accumulator.
Figure 4 is a schematic view of the up/down credit counter of my electronic credit accumulator.
Figure 5 is a schem~tic view of the bonus counter of my electronic credit accumulator.
Figure 6 is a schemat~ view of the bonus credit pulse generator of my electron~c credit accumulator.
Figure 7 is a schematic view of the output converter of my electronic credit accumulator.
Figure 8 is a schematic view illustrating an alter-nate mode of operation o~ my electronic credit accumulator.
Figure 9 is a schematic ~iew illustrating yet another mode af operation of my electronic credtt accumulator.
Figure 10 is a diagrammatic view illustrating the ; wave forms at various points~in my credit accumulator for one oondition of operation thereof.
Figure ll is a schematic view of a portion of an alternate embodiment of my credit accumulator.
Figure 12 is a schematic view of the remaining portLon of the alternate embodiment of my credit accumulator.
; ! DescriptiQn o~ the Preferred Embodiment Referring now to Figure 1 of the drawings, my elect-,~ ,.
ronic cre~t accumulator, indicated generally by the reference character 10, includes a cIock pulse oscillator 12 of any suit-able type known to the art adapted to produce clock pulses at a frequency of, for exa~ple, one thousand pulses per second.
An inverter 14 applies the c~ock pulses to one terminal of a . ., two-input NAND circuit 16. A pulse train generator 18 is adapted to be actuated in a manner to be described to apply an output ~ `.!
' signal to a channel 20 which provides the second input for the ~AND circuit 16. When that circuit is enabled, clock pulses cb~ 3 ~`.,' ,, . .~ . ~ - . : :

io4074z are fed to generator 18 on channel 22 to cause the generator to count down.
Generator 18 includes eleven respective input ter-~inals 24a through 24k. These terminals respectively correspond to one, two, three, four, five, six, seven, eight, nine, ten and twenty pulse output from NAND circuit 16. That is, for example, if a signal is applied to terminals 24h and 24b, the generator 18 will actuate NAND circuit 16 to pass a train of ; ten pulses.
The credit input circuitry of my accumulator includes five credit input switches CSl to CSS corresponding respectively to monetary inputs of 5~, lQ¢, 25¢, 50¢, and $1.00. ~nput circuits 26a through 26e are adapted to apply signals respectively to terminals 28a through 28e upon the concurrence of the closure ` of one of the switches CSl to CS5 and of a signal on a sample channel 30. Switches CS1 to CS5 each closes for a minimum period of fifty-five milliseconds. As will more fully be sxplained hereinbelow, thirty milliseconds following closure of any one of the switches CS1 to CS5 a control circuit 32 provides a sampling signal on line 30.
I so connect the terminals 28a to 28e to terminals 24a to 24k as to provide the desired correspondence between the amount of money deposited and the number of pulses produced by generator 18. in the particular arrangement illustrated in the drawings, one pulse corresponds to 5~ in credit. Thus, the 25¢ terminal 28c is connected to the five pulse terminal 24e to represent a credit of 25~. A reset pulse generator 34 applies a reset pulse to a channel 36 leading to generator 18 to ensure that the generator is reset after a credit operation.
- 30 During the period of time ~or which generator 18 ; produces an output signal to enable the NAND circuit 16, clock pulses pass to channel 38 which is connected by an inverting c~/ - 4 -;;'' amplifier 40 to the input term~nal of an up/down credit counter 42. When credit is being re~istered, control circuit 32 applies signals through channels 44 and 46 to a counter control circuit 48 which then produces an output on channel 50 leading to the "count up" input control 52 of counter 42. ~hen the counter is to count down circuit 48 provides a signal on channel 54 leading to the "count down" control 56 of counter 42.
Counter 42 carries s~gnals on respective output lines 58a to 581 representing, in binary form, the credit presently stored therein. I so interconneet the output lines 58a to 1 of eounter 42 to input lines 60a to 60m of a eonverter 62 that predetermined amounts of credit in decimal form are indicated on the output lines 64a to 64h of converter 62.
The album seleetion circuit terminal 66 is connected to one of the terminals 64a to 64h representing the minimum eredit required to play an album. Similarly, the standard seleetion eireuit terminal 68 is eonneeted to one ef the lines 64a to 64h representlng the minimum eredit required to play a standard seleetion. In the partieular example illustrated in the drawings I have shown terminal 66 as being connected to the equal to or greater than six line 64c representing 30¢ of eredit. Term~nal 68 ~s eonneeted to line 64i corresponding to equal to or greater than two eredit units whieh, in the example shown, is 10~.
Cloek pulses on ehannel 38 leading to inverter 40 also are applied to one terminal of a two input NOR eircuit 70.
Counter control eircuit 48 produees a signal on line 72 leading to the other input terminal of cireuit 70 to enable that circuit ~hen credit is being aceumulated. The output from eireuit 70 is applied to a bonus eounter 74 whieh counts only in the up ., direction to produce a binary output representation on output terminal 76a to 76k indicating the total eount of the bonus c~ - 5 _ -, ~ ': . ...

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counter. I connect predetermined ones o$ the output lines 76a to 76k of counter 74 to a bonus generator 78 to which pulses also are applied from inverter 14 through a line 80. When the end of a train of pulses is reached an inverter 82 activates gener-ator 78. Respective output lines 84, 86 and 88 from generator 78 are adapted to apply signals to terminals 28h to 28j to actuate the generator 18 to generate additional or bonus counts. In the particular example shown, terminals 28h to 28j are connected respectively to terminals 24a, 24b and 24f so that lines 84, 86 and 88 respectively represent a 5¢ bonus, a 15¢ bonus, and a 30¢
bonus. The reset pulse on line 36 is applied to bonus generator 78 by a line 90 and by an inverter 100 to the bonus counter 74 to reset the counter and generator.
In response to selection of a standard play switch 102 closes in a manner known to the art. Both switch 102 and a second switch 104 close when a premium selection has been made.
In response to closure of switch 102 a circuit 106 provides an output on line 108 to one terminal of circuit 26g. When both switches 102 and 104 close circuit 106 provides an output on channel llO to cirauit 26g. A third output from circuit 106 on line 112 actuates the control circuit 32 to provide a sample pulse inpu* to both circuits 26f and 26g and to actuate the circuit 48 to cause the counter 42 to count down. I connect cirCuits 26f and 26g to terminals 28f and 28g. In the parti-cular arrangement shown, these two terminals are connected to terminals 24f and 24b o~ generator 18 so that a signal on line 110 results in a subtraction of six units or 30~ worth of credit while a signal on line 1~8 results in a subtraction of two units or 10¢ wortk of credit.
;
Referring now to Figure 2 showing the details of the money responsive and credit-cancelling portion of the accumulator, I connect respective resistors Rl to R5 in series with capacitors ''' cb/ - 6 -, .
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Cl to C5 between ground and the terminal 114 of a suitable source of potential of, for example, five volts. The coin switches CSl to CSS are respect~vely connected acxoss capacitors Cl to C5. Inverters 116a to 116e connect the upper terminals of the capacitors respectiuely to first input terminals of two input NAND circuits 118a to 118e, the outputs of which are connected to terminals 28a to 28e. Line 30 provides the other input for each of the N~ND circuits 118a to 118e. From the structure just described, it will be appreciated that with no lQ coin sWitch actuated the corresponding input terminals of circuits 118a to 118e receive no inputs. When any switch closes, however, an input is applied to the corresponding NAND circuit 118a.
I connect the upper terminal of each of the capacitors C1 to C3 to a respective input terminal of a five input NAWD
circuit 120. A two input NOR circuit 122 couples the outputs of inverters 116d and 116e to the fourth input terminal of cir-cuit 120. As will be explained hereinbelow, a line 124 leading to the fifth input to circuit 120 normally carries a signal.
Thus, under normal conditions NAND circuit 120 produces no out-put. When any one of the switches CSl to CS5 is actuated or when the signal on line 124 disappears, NAND circuit 120 produces an output signal which is applied to sample pulse generator 126 which, approximateiy thirty milliseconds thereafter, provides a signal on line 128. This signal passes through respective inverters 130 and 132 so that upon the concurrence of the closing of one of the switches CSl to CS5 and the signal on line 30 an output is removed from one of the NAND circuits 118a.
An R-C circuit 134 normally provides an input at one terminal of a two input NO~ circuit 136. An inverter 138 res-ponsive to this signal is coupled to one input terminal of another two-input NOR circuit 140. A circuit 142 normally provides ''`
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no output at the input of an inverter 144 coupled to the other input terminals of NOR circuits 136 and 140. The output of inverter 144 is coupled to line 124.
Under the conditions just described both terminals of NOR circuit 136 carry inputs so that circuit produces no output.
At the same time, the lower terminal of circuit 140 carries an input so that the NOR circuit produces no output. When switch 102 closes circuit 142 applies an input to inverter 144 so that circuit 140 produces an output which is fed to one input terminal of a two-input NAND circuit 118g the other terminal of which is connected to line 30. The output of circuit 118g is applied to terminal 28g. At the same time, closure of switch 102 results in a loss of signal on line 124 so that NAND circuit 120 causes generator 126 to produce a sampling pulse.
When an album or premium selection is played, both switches 102 and 104 close. Under these conditions NOR circuit 136 provides an output- which is applied to one terminal of the two input NAND circuit 118f connected to terminal 28f. Con-comitantly, a sampling pulse is applied to the other terminal ' 20 of circuit 118f.
I apply the output of inverter 144 to one terminal . of a two-input NAND circuit 146 and to one input terminal of a two-input NOR circuit 148. The other terminal of NAND circuit 146 receives the sampling pulse from line 30. The other input l terminal of NOR circuit 148 receives the output of inverter 130 l~ or the complement of the sampling pulse. Thus~ whenever switch ;l 102 is open and a sampling pulse exists, the outputs of both circuit 146 and 148 are removed so that no signals are present on the output lines 44 and 46.
~, Referring now to Figure 3, the pulse train generator 18 is a five stage down counter including respective dual J-K
flip flops, GFl, GF2, GF3, GF4 and GF5 corresponding respectively cbj - 8 -to binary counts of 1, 2, 4, 8 and 16. As is known in the art, each of the flip flops GFl to GF4 includes a clock pulse input terminal I to which clock pulses from line 22 are applied. In addition, each flip flop has J and K terminals, an output terminal Q, a complement output terminal Q', a set terminal S and a reset terminal R. In operation of the flip flops the presence of a set signal at the set terminal S causes the output to go positive and to remain positive until it is changed. If both J and K
terminals are positive the output reverses on each clock pulse.
If terminal J is negative and terminal K is positive the clock pulse causes the terminal Q output to be negative. If the J in-put is positive and the K input is negative, a clock pulse causes the output to go negative and the complement to be positive.
I connect the J and K terminals of flip flop GFl to a source 150 of positive potential. A five-input NAND circuit 152 and an inverter 154 are adapted to supply a set signal to flip flop GFl. I connect the complement output terminal Q' of flip flop GFl to the J and K terminals of flip flop GF2~ A second five-input NAND circuit 156 and an inverter 158 are adapted to apply a signal to the set terminal of GF2. A two-input NOR
icircuit 160 responsive to the outputs of flip flops GFl and GF2 provides an input to the J and K terminals of the flip flop GF3.
A th~rd five~input NAND circuit 162 and an inverter 164 are adapted to apply a set signal to GF3. A two-input NAND circuit ~,166 responsive to the output of NOR circuit 160 and to the com-plement output of flip flop GF3 provides an input to an inverter 168 connected to the J and K terminals of flip flop GF4. A three-input NAND circuit 170 and an inverter 172 are adapted to apply a set signal to GF4. A two-input NOR circuit 174 responsive to the ::, ~ 30 output of NAND circuit 166 and to the output of GF4 provides an . .
input to the J and K terminals of a flip flop GF5. I connect the co~mon termln~l of a res~stor 176 and a ca~acitor 178, connect-ed in series between ground and a terminal 180 carrying a potential cb/ _ g _ of about five volts, to the set input terminal of flip flop GF5.
A two~input NAND circuit 182 couples the output of NOR circuit 174 and the complement output of flip flop GF5 to the generator output line 20. Respective capacitoLS 184 conne~t the output terminals of the NAND circuits 152, 156, 162 and 164 to ground.
In operation of the generator 18, application of a set signal to the flip flops GFl to GF5 causes the generator to actuate NAND circuit 16 to pass a train of output pulses equal in number to the binary count represented by the flip flops to which the set signals are applied. I connect the terminals 24a to 24k to the inputs of NAND circuits 152, 156, 162 and 170 to cause the generator 18 to produce a number of output pulses corresponding to the number represented by the terminal~ For example, terminal 24f is connected to the inputs of both NAND circuits 156 and 162 so that set signals are applied to flip flops GF2 and GF3 to cause the generator to produce an outpu~ train of two plus four, or six, pulses.
, Referring now to Figure 4, the up-down credit counter 42 is a six stage counter made up of six dual J-K flip flops CFl, CF2, CF3, CF4, CF5 and CF6. In response to the application of ~ clock pulses to the counter from inverter 40, the output terminals v of the various flip flops carry signals which provide a binary representation of the credit presently registered in the counter.
As has been explained hereinabove, these outputs are selectively coupled from output lines 58a to 58i to the input lines 60a to 60m of the converter 62. Counter 42 also receives signals on lines 44 and 46 leading from ci~cuits 146 and 148. I connect line 44 to one input terminal of a two-input NAND circuit 186, `~ the other input of which is provided by a two-input NAND circuit 188. An inverter 190 couples line 46 to one input terminal of the two-input NAND circuit 188 the other input to which is provided by NAND circuit 186. Circuits 186 and 188 provide cb/ - 10 -~04074Z
respective output~ion lines 192 and 194 to cause the counter 42 to count up or to count down. Respective two~input NAND cir-cuits 196 and 198 each responsive to the signal on line 192 and respectively responsive to the output from flip flop CFl and to the signal on line 194 and the complement output of flip flop CFl provide the inputs for a two~input NAND circuit 200 which provides the J and~K inputs to flip flop CF2. Respective two-input NOR circuits 202 and 204 xespectively responsive to the output of NAND circuit 136 and the complement output of flip flop CF2 and to the output of circuit 198 and the bit out-put of flip flop CF2 provide inputs to a two-input NOR circuit 206 coupled to the J and K terminals of flip flop CF3 by means of an inverter 208. Two-input NOR circuits 210 and 212 respect-lvely responsive to the output of circuit 202 and the bit output of flip ~lop CF3 and to the output of circuit 204 and the com-, _plement output of fl~p flop CF3 provide the inputs for a two-input NOR circuit 214 connected to the J-K terminals of flip flop CF4. Two-input NOR circuits 216 and 218 respectively res-ponsive to the output of circuit 210 and the complement output 2Q of CF4 and to the output of circuit 212 and the bit output of flip flop CF4 provide inputs for a two-input NOR circuit 220 connected by an inverter 222 to the J and K terminals of flip .,, flop CF5. Two~input NAND circuits 224 and 226 respectively responsive to the output of circuit 216 and the bit output of flip flop CF5 and to the output of circuit 218 and the comple-: .
ment of flip flop CF5 provide the inputs for a two-input NOR

, circuit 228 connected to the J and K terminals of flip flop CF6.

~; A two-input NOR circuit 230 couples the complement output of flip . ..
- flop-CF6 and the output of clrcult 224 to the line leading from - 30 inverter 40.

Referring now to Figu~e 5, the bonus counter 74 counts up as the up/down counter 42 counts up in response to the deposit cb/ - 11 -~V4074;~
of money. The operation of counter 74 is controlled by the signals on lines 44 and 46 and by a signal on line 232 leading from the bonus generator 78. I apply the signal on line 44 to one input terminal of a two-input NAND circuit 234 the other .~ terminal of which is connected to the output of a two-input NAND circuit 236. A two-input NOR circuit 238 receives inputs from lines 46 and 232 and provides one.input to circuit 236 the other input of which is provided by circuit 234. When the bonus counter is to register counts circuit 236 provides the appropriate signal on line 72 leading to one terminal of NOR circuit 70 the other input of which is provided by the NAND circuit 16.
, Bonus counter 74 includes six dual J-K flip flops BFl to BF6 pulse inputs to which are supplied by NOR circuit 70.
The complement output of 1ip flop BF3 provides the J input for flip flop BFl. The bit output of flip flop BFl provides the J and K inputs for flip flop BF2. I also connect the bit out-put of BFl to one contact 240 of a switch having a contact arm 242 which selectively engages contact 240, contact 244 or con-:; tact 246. A two-input NOR circuit 248 receiYing its inputs ` 20 respectively from the output of flip flop BFl and from the com-. plement output of flip flop BF2 is connected to contact 244.
;; I apply the complement outputs of flip flops BFl and BF2 to the respective.input te~minals ~ a two-input NOR circuit 250 connect-ed to contact 246. Arm 242 iS selectively positioned to connect one of the contacts 240, 244 and 246 to the J input of flip flop BF3. I apply the output of flip flop BF3 to the J and K terminals o~ flip flop BF4 and to one input terminal of a two input NAND
circuit 252 which rece~ves its other input from the bit output of flip flop BF4. An inverter 254 couples the bit output of 30 circuit 252 to the 3 and K terminals of flip flop BF5. I apply the complement output of flip flop BF5 and the output of the circuit 252 to the respective input terminals of a two-input Cb/ - 12 -NOR circuit 256 coupled to the J and K terminals of flip flop BF6. As is pointed out hereinabove, selected outputs of the bonus counter 74 are applied to the bonus generator 78 by lines 76. More specifically, I connect the output of flip flop BF4, the output of flip flop BF6 and the complement output of flip flop BF6 respectively to lines 76f, 76j and 76k leading into the bonus generator 78.
Referring now to FIGURE 6, the bonus generator 78 includes respective dual J~K flip flops BGl, BG2 and BG3.
All of the flip flops BGl to BG3 receive clock pulses from line 80 and a reset pulse from line 90. Respective inverters 258, 260 and 262 connect the J and K terminals of the flip flops BGl to BG3.
A two-input NOR cixcuit 264 receives its inputs from lines 76j and 76h. An inverter 266 applies the output of NOR
circuit 264 to one lnput terminal of a two-input NOR circuit 268.
~` Line 76f supplies the other input to circuit 268. A capacitor 270 couples line 76k to one input terminal of a two-input NAND
~ circuit 272~ the other terminal of which receives its input - 20 from a two-input NAND circuit 274. I apply the output of NAND
circuit 272 to one input terminal of a two input NAND circuit 276, the other input of which is provided by inverter 82 to initiate generation of a bonus of one pulse.
. .
I apply the output of NAND circuit 276 to inverter 258 connected to the J and K terminals of BGl and to one input of a three-input NAND circuit 278 which provide~ one of the inputs for .,.
NOR circuit 238. A capacitor 280 couples the output of NOR cir-cuit 264 to one input terminal of a two-input NAND circuit 282 which receives its other input from the output of a,~AND circuit 30 284. A capacitor 286 couples the`output of NOR circuit 268 to one input terminal of a NAND circuit 288 which receives its other input from the output of a NAND circuit 290. I apply cb/ - 13 _ the output of NAND circuit 274, the output of NAND circuit 282 and the output of amplifier 82 to a three input NAND circuit 292 which provides an input for inverter 260 connected across the J and K terminals of fl~p flop BG2. NAND circuit 292 also provides an input to N~ND circuit 2~8. I apply the output of NAND circuit 284, the output of NAND circuit 288 and the output of amplifier 82 to a three input NAND circuit 294 which provides an input for inverter 262 whtch is connected across the J and K
terminals of flip flop BG3. Circuit 294 provides the third input for NAND circuit 278.
NAND circuit 276 provides an input for each of a two-input NAND circuit 296 and a two input NOR circuit 298. The output of flip flop BGl and its complement respectively provide the other inputs to circuits 296 and 298. NAND circuit 296 provides one input for clrcuit 290 the other input to which is ; the output of circu~t 288. NAND circuit 292 provides one input :~ to each of a two-input NAND circuit 300 and a two-input NOR cir-, cuit 302. I apply the output of flip flop BG2 and its complement respectively to the other input terminals of circuits 300 and 302. Circuit 294 provides one input to each of a two-input NAND
circuit 304 and a two~input NOR circuit 306. The output of flip '1 flop BG3 and its complement respectiyely provide the other inputs , to the circuits 304 and 306.
I apply the output of NAND circuit 288 and the output of NOR circuit 298 to the input terminals of a two input NAND
cirCuit 308 to provide a signal at terminal 28h to generate a bonus count of one when required. The outputs of NOR circuit 302 and of NAND circuit 282 proYide the inputs to a two-input NAND circuit 310 to generate a bonus count of three pulses when 3a required. I apply the output of NOR circuit 306 and the output of NAND circuit 272 to a two~input NAND circuit 312 to generate a bonus count of six pulses when required.

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Referring now to Figure 7, as has been explained hereinabove, certain of the output lines 58a to 581 of the counter 42 are applied to predetermined input lines 60a to 60m of the converter 62 to produce outputs on terminals 64a to 64h indicating at least certain amounts of credit. In the particular arrangement shown, lines 58g and 58-i are connected to lines 60b and 60c to prov~de inputs for a two-input NOR
circuit 314 which provides onec~input to a two input NAND circuit 316, the other input o which is taken from line 581 through line 60a. I connect the output of circuit 316 to terminal 64a indicating at least eight units of credit. Lines 58f and 58d connected respectively to iines 60d and 60e provide inputs to a two-input NOR circuit 318 the output of which provides one input to a two-input NAND circuit 320 the other input of which 18 derived from line 58a through line 60f. Circuit 320 provides one input to a two-input NAND circuit 322 the other input of ,;
which i8 from an inverter 324 to which the output of circuit 316 ~ is applied. I connect the output of circuit 322 to terminal ' 64b indicating a credit of at least seven units. The outputs of circuits 318 and 322 are applied to a two-input NOR circuit 3 326 the output of which is coupled to terminal 64c through an ,~ inye~ter 328 to indicate a credit of at least six units.

`~ Line 58e and line 58a proYide inputs for a two-input ''' NAND circuit 330 through l~nes 60~ and 60h. I apply the output ,.1 ,q1 of NOR circuit 326 and the output of'NAND circuit 330 to a NOR
circuit 332 connected to terminal 64d to indicate a credit of at least five units. Line 58f proYides one,-'input for a two-' ~nput NAND circuit 334 the othe~ input of w~ich is derived .:
,f,rom inYerter 324. I connect the output of circuit 334 to ' 30 tèr~inal 64e to indicate ,a, c~edit of at lea$t four units. A

~ pair of serially connected ~nVerters 336 and 338 are connected - between circuit 334 and terminal 64f. Lines 58c and 58a '~
cb/ - 15 -, ~04074Z
provide two inputs for a NAND circuit 340 through lines 60j and 60k. I apply the output of circuit 340 to the common terminal of inverters 336 and 338. Terminal 64f corresponds to a credit of at least three units. Clrcuit 334 provides one input for a two-input NOR circuit 342, the other input of which is derived from line 58c through line 601. An inverter 344 couples the output of NOR circuit 342 to terminal 64g which corresponds to a credit of at least two units. NOR circuit 342 provides one input to a two-input NAND circuit 346 the other input of which is derived from line 58a through line 60m.
I apply the output of circuit 346 to terminal 64h to indicate a credit of at least one unit.
As has been explained hereinabove, in Figures 1 to 7 I have illustrated my accumulator so connected that each pulse counted represents a credit of 5¢. Further, in response to a deposit of 25~ one pulse is generated so that 30¢ worth of - credit results. In response to the deposit of 50¢ ~hree ; additional bonus pulses are generated so that the total credit is 70¢. One dollar generates $1.50 in credit. The position of switch arm 242 determines the multiple of pulses or monetary level at which the first bonus credit is generated. That is, ,., it determlnes whether three, f~ur or five money pulses are ; necessary to initiate the first bonus credit. Stated otherwise, the switch including arm 242 causes BFl, BF2 and BF3 to function as a divide by N counter where N = 3, 4 or 5. The Q output of BF3 goes through one cycle for N clock pulses into the circuit.
While the positiQn of arm 242 determines the level at which the bonus is generated~ the amount of bonus i5 deter-m~ned by the programmed connection between terminal 28h and the terminal or terminals of generator 18. The amount of the bonus which may be entered at a level in the first form of my system is from one to ten pulses or twenty pulses. The second cb/ - 16 -1040'~^'42 bonus is always added at a credit level equal to twice the first bonus credit level and the third bonus at four times the first level. For example, bonuses may be given at levels of twenty-five cents, fifty cents and one dollar.
; The purpose of switch 242 is to permit a change in the level at which the first bonus is given. For example, for a coin ratio of 1:5:10:20 such as a nickel, a ~uarter, a half dollar and a dollar bonuses can be gi~en at the quarter leyel, the half dollar level and the dollar level by moving arm 242 into engagement with contact 246. For foreign currency such ;; as deutschmarks we may have one pulse equal to one quarter of a deutschmark and award bonuses at one and two deutschmark levels. For this coin ratio of 1:4:8 switch arm 242 engages contact 240. The third sw~tch position corresponding to a divide-by-three operation is provided for some as yet undeter-mined future application. In the setup I have shown in Figures :~' ~ 1 to 7, 10~ worth of credit is required to permit a standard :j record to be played as indicated by the connection of terminal 68 to terminal 64g. In order that an album be able to be selected it is necessary that at least six units of credit corresponding to 30¢ worth of credit have been established.
Referring now to Figures 8 and 9, I have illustrated the interconnection of terminals 24 and 28 for a different setup.
In the setup shown in Figure 8, each pulse counted represents 5¢ of credit. In response to the deposit of 25¢, one bonus credit is generated. In response to the deposit of 50¢, 75¢
wQrth of credit is established and in response to the deposit of ~ne dollar, $1~65 worth of credit is established. When the accumulator has this setup, switch arm 242 engages contact 246. Further, in such a setup terminal 68 may be connected to terminal 64f so that at least three units of cred~t must be available to permit a standard record to be played. Further, ~/ - 17 -10407~Z
terminal 66 is connected to terminal 64c so that at least six units of credit are required to play an album.
In the arrangement illustrated in Figure 9, two pulses represent a credit of 25¢. In response to the deposit of 25¢, two pulses are generated. When 50¢ is deposited, 5iX
pulses are counted so that 75¢ worth of credit is established.
In response to the deposit of $1.00, fourteen pulses are gener-ated and stored, thus representing $1.75 in credit. In this setup, switch arm 242 engages contact 244. With this arrangement terminal 68 is connected to terminal 64g indicating that at least two credit units, in this case, 25¢, ~ust be established before a standard record can be played. Terminal 66 is connect-ed to terminal 64e establishing that at least four credit units corresponding to 50~ must be present before an album or premium selection can be played. The flexibility of my system will readily be apparent.
The operation of the form of my accumulator shown in Figures 1 to 7 can best be understood by considering a parti~
cular example. Assuming the setup to be that illustrated in .:
Figures 1 to 7 and further assuming that ~0¢ has been deposited ` so that switch CS4 closes, the waye forms at various points in the system will be as indicated in Figure 10. When switch CS4 closes, the control circuit 32 puts out a sample pulse on line 30 and inverter 16d provides a second input for circuit 118a. Since terminal 28d is connected to terminal 24j, set pulses are applied to the binary "8" flip flop GF4 and to the binary "2'! flip flop GF2 of the pulse train generator 18.
As a result, NAND circuit 182 is enabled for a period of ten pulses and both line 22 and the output of invexter 40 carry ten pulses. At the same time, N~ND circuit 236 is enabled for a period of ten pulses so that the bonu5 counter receives the ten pulses through NOR circuit 70. Under these conditions, cb/ - 18 -~040742 bonus flip flop BFl puts out a train of four pulses and bonus flip flop BF2 puts out a train of two pulses. As a result, , bonus flip flop BF3 provides an input to flip flop BF4 which triggers flip flop BF4 "on" at the end of the fifth pulse and "off" at the end of the tenth pulse. Flip flop BFS is triggered on at the end of the tenth pulse. Flip flop BF6 produces no output. The bonus counter outputs are fed to generator 78 which is activated by a signal from inYerter 82 at the end of the tenth pulse passing through circuit 16. As a result, NAND
circuit 272 and inverter 82 provide inputs to circuit 276 to actuate the flip flop BGl to produce an output which actuates .....
,;, circuits 296 and 298 to provide signals to circuit 308 which ~ through terminal 28h and 24a cause the generator 18 to permit ....
', a bonus clock pulse to go to the counter 42. This represents the bonus credit corresponding to 25¢ deposit.
Further under these conditions, the outputs from the bonus counter actuate the circuits 282 and 292 to operate ~, flip flop BG2 to produce an output pulse which actuates circuits 300 and 302 to cause a si~nal to be applied to terminal 28i ',~ 20 which is connected to term~nal 24c to cause the generator 18 ':i ,, to permit three addit~onal bonus pulses to pass to the counter ','', 42, , Finally, following the deposit of 50~,, up down counter 42 has counted fourteen pulses so that a crèdit of 70¢ has-been given in response to the deposit of S0~. Under ~, these conditions, converter 62 produces outputs on lines 64c ~; and 64i so that either an album, or a standard can be selected.
After the counting operation is complete, reset pulse generator ~ ensures that all the flip flops are retuxned to zero condition.
;, 3Q- When a standard selection is made, switch 102 closes t~ cause the control circuit 32 to provide a sample pulse and to apply a pulse to the circuit 118g to cause the generator cb/ - 19 -' ' ' :
: . .

18 to pass two pulses through circuit 16~ Further under these conditions, a signal is applied to line 54 to cause counter 42 to count down in response to these two pulses. Thus a credit corresponding to the value of a standard selection is subtracted from the total count of counter 42. When switch 102 closes, six units of credit are subt~racted. Ultimately when the amount of credit in counter 42 is less than six units, terminal 66 is disabled and an album cannot be played. When less than two units are available, terminal 68 is disabled and a standard ; 10 cannot be played.
Referring now to Figures 11 and 12, I have shown a ,: .
preferred form of credit accumulator in which I connect the ; terminals of coin switches CSl, CS2 and CS3 to respective input terminals of a ftve-input NOR circuit 350, a four-input NOR
circuit 352, and a four-input NOR clrcuit 354. The outputs of the respective circuits 350, 352 and 354 are connected to ;~ three input terminals of a binary down counter 356. Respective ;1 inverters 358 and 360 connect input switches CS4 and CS5 to the remaining two binary~input terminals of down counter 356. A two-input NAWD circuit 362 connects coin switch CS3 t~ anothe~ input terminal of NAND circuit 350. A two-input NAND
circuit 366 connects CS4 to a second input terminal of the NOR
circuit 352. Similarly, a NAND circuit 370 connects coin switch ; CS5 to a second input terminal of NOR circuit 354.
As indicated in F~gures 11 and 12 each of the NAN~
circuits 362, 366 and 370 is arranged to provide an "O" output m response to the presence of an "O" at both its input terminals.
Each of NOR circuits 350, 352 and 354 is arranged to p~oduce a "1" at the output thereof in response to the p~esence of a "O"
at any one of its input terminals. These operations are indicated by the presence of circles at the input terminals.
A coin ratio terminal 374 provides the other input cb/ - 20 -~040742 for each of the NOR circuits 362, 366 and 370. In the arrangement shown where the coin switches CSl to CS5 corres-pond respectively to deposits of 5¢, 10~, 25¢, 50~, and $1.00, the coin ratio termlnal 374 is at ground. In the event that it is desired to have the sw~tches CSl to CS5 correspond to deposits of sums having a binary relationship as in some foreign currencies a positive potential may be applied to the coin ratio terminal 374 so that the NAND circuits 362, 366 and 370 never provide outputs. in response to actuation of coin switches CS3 to CS5.

.. , In the particular arrangement shown, closing of switch CS3, for example, causes NOR circuit 350 and 354 to produce outputs to supply the binary equivalent of five units to the counter 356. Similarly, closure of switch CS5 causes NOR circuit 354 and inverter 360 to supply the down counter ~; .
356 with a binary input of twenty units.
A decoder circuit 374 associated ~ith counter 356 pr~vides an output on a line 376 so long as the counter contains a CQunt which is equal to or greater than one unit. A delay network 378 applies the signals on line 376 to a gating circuit ` 380 supplied with clock pu~ses from a suitable source 382.
When activated, the gating circuit 380 passes pulses from source 382 to a line 384 which is connected to the stepp~ng input terminal of counter 356.
The particular coin switches with which my system is used have switch bounce and may produce spurious signals of a duration of ten milliseconds. To prevent such spurious signals from affecting the stored credit in my syste~, I
proyide a circuit 386 which strobes the coin switch signals into the counter 356 ten mllliseconds after the beginning of the coin switch sIgnal. The strobe enables the counter 356 through a two-input OR circuit 388 and is controlled from a cb/ - 21 -:'~

iO407~
suitable source 390.
As a result of the operation described above, follow-ing the deposit of coins, a train of pulses is generated on line 384 with the number of pulses aggregating the number of basic coin units which have been deposited. I apply the train of pulses to a p~ay price di~ ing network 392 which divides the number of pulses by a number Nl equal to the number of ~, basic coin units making up the price of a standard selection.
; This standard price is set on terminals 394 associated with network 392. For example, i the number of pulses in the train is thirty representing a deposit of $1.50 and the stand-ard price is 15¢, network 392 divides the number of pulses , in the train by three to result in ten output pulses corres-ponding to ten plays which can be made for deposit of $1.50.
A two~input NOR circuit 396 couples the output of ,~ network 392 to one input terminal of a three-input NAND
circuit 398 which actuates a play registering eight bit up/down counter 400. In the particular instance under con-~ideration, following the deposit of $1.5Q, counter 400 contains a count of ten indicating that ten standard records can be played. A decoding circuit 402 associated with counter 400 provides an output on the standard play-terminal 404 so long as the count content in the register 400-is equal to or greater than one. I apply the content of register 400 to an eight-bit comparator 406 which provides an output on the pre-mium play terminal 408 so long as the content of register 400 is equal to or greater than N2 where N2 is the number of stan-dard plays corresponding to a single premium play. In order to achieve this operation, I connect the premium price input 30 terminals 410 and 412 to the other input terminals of comparator ; 406. I apply the ~utput of decoder 402 and the output of com-parator 406 through an inverter 414 to a two-input AND circuit 416 cb/ - 22 -, .

connected to the standard onl~ light terminal 418 of the phonograph.
I apply the signal on line 376 to reset terminals of a bonus flip flop 420 and an up down counter flip flop 422 when-ever the down counter 356 goes to zero if or when the counter switches open. At the same time a five-input NOR circuit 448 connects all of the coin sw~tches CSl to CS5 to the set input terminal of flip flop 420. As a result, so lon~ as any coin switch is closed the complement output terminal of flip flop 420 carries a zero which I employ to inhibit a NAND circuit 442 adapted to bypass di~ider 392 when bonus or cancel pulses are being handled. Further whenever counter 356 contains at least one count and no cancel signal is present the complement output from flip flop 422 represents a one to enable NAND circuit 398.
The bit output of flip flop 422 tnhibits a NAND circuit 440.
Circuit 422 is enabled only when a cancel signal is entered from line 424 or line 426. Moreo~er in the presence of a cancel signal circuit 398 is disabled and circuit 440 is enabled.
In response to selection of a standard play, a stan-dard cancel terminal 424 returns t~ ground. Similarly, in res-ponse to selection of a premium play, a premium cancel terminal 426 is returned ta ground. As a premium selection is made, a decoding circuit 428 wh~ch receiyes an input from terminal 426 and from terminals 410 and 412, proyLdes output signals on lines 430, 432 and 434 such as are necessary to generate the . ~
required number of pulses to deduct W2 plays fr~m register 400.
These lines 430, 432, and 4-34 are connected respectively to third input terminals of NOR circuits 350, 352 and 354.
It is to be noted that these cancel pulse5~ as well as the bonus pulses to be discussed hereinbelow, are in terms of numbers of plays rather than in terms of numbers of coin units. When a cancel signal appears on either of terminals 424 or 426, a : ~.
_ 23 -cb/

:

NOR circuit 438 applies a signal~ to the set input terminal of flip flop 422. As a result, the NAND:.circu1t 398, which receives an input from the complement output of flip flop 422, and which leads to the up-count terminal of register 400, is disabled. At the same time, the bit output terminal of flip flop 422 enables NAND circuit 440, the other input terminal of which is supplied by NO~ circuit 396. In addition, with no coin switch closed the flip flop 420 enables a NAND circuit 442 to cause pulses on line 384 to bypass the play price divided circuit 392. The output of NAND circuit 442 is applied to one input terminal of a three-input NOR circuit 444 to reset divider 392. NOR circuit 396 carries the pulses from NAND circuit 442 to NAND circuit 440 which is now enabled to ,:
pass the pulses to one input terminal of a two-input NOR circuit 446 leading to the down-count terminal of register 400 to sub-tract the required number of plays from those contained in register 400.
The bonus provided by the form of my accumulator illustrated in Figures 11 and 12 is adapted to proYide bonus pulses in terms of numbers of plays rather than in terms of numbers of coin units. A plurality of respective gates 450, 452 and 456 are adapted selectively to be enabled to couple yarious binary bonus values into an OR circuit 458 which carries the bonus value to the NOR clrcu~ts 350, 352 and 354.
Pulses on line 384 are coupled to one input terminal of a two-input NAND circuit 460, which produces a "1" at its output when both inputs are "O", the other terminal of which is connected to the banus flip flop 420. Pulses pass-ing through circuit 46Q are fed to a diyide by N3 counter 462 30. where N3 is the number of ~oney units which is to correspond to one bonus unit. This is achieved by coupling a bonus leyel signal from terminals 464 through a decodlng network 466.
,.,~
cb/ - 24 -I feed the output of counter 462 to the NAND~circuit 444 to reset the play price dlvider 392 and to a 3-6it counter 468.
The output of counter 468 is coupled to a decoder 469 which puts out signals on lines 470, 472, 474 and 476 when the number of bonus units is respectively equal to or greater than one, equal to or greater than two, equal to or greater than three, or equal to or greater than our. These lines prsvide one input for respective three-input NAND circuits 478, 480, 482 and 484~
,~
A two-input NAND circuit 486 responsive to the strobe circuit 386 and to the signal on line 376 acts through a delay network 488 to provide another input for each of the circuits 478, 480, 482 and 484. The delay network 488 preYents bonus signals from being entered until after all coin switches are open. When any of the NOR circuits 478, 480, 482, or 484 provides an output, the corresponding gate 450, 452, 454 and 456 , , is enabled to couple one of the bonus levels to OR circuit 458.
We proyide the bonus circuitry with a two bit counter 490 which registers the entry o~ the bonus levels in succession 20 to inhibit the NAND circuits 478, 480,, 482 and 484 as required.
A ~our~input NOR circuit 492 responsive to the NAND circuits '~ ~r~vi,des an output which is applied to NOR circuit 388 to , activate CQunter 356 and which is applied to the t~o-bit : counter 490 to indicate bonus levels which haye previously been entered. A NAND ci,rcuit 494 responsive t~ the tWQ bit outputs o~ counter 490 indicates that no bonus level has been entered and provides the third input for NAND circuit 478.
A NAND circuit 496 responsive to the less significant complement and greater significant bit outputs of counter 490 provides a ~, 30 signal indicating that the ~irst bonus leyel h,as been entered ` and it provides the third input for circuit 480. A third NAND
: cirCuit 498 is responsive to the less significant bit and more cb/ - 25 -.~ .

significant complement to indicate that the second bonus level has been entered. It provides the third input for circuit 482.
A fourth NAND circuit 500 responsive to both complement outputs indicates that the third bonus leyel has been entered. It provides the third input for circuit 484.
Thê output from circuit 484 is applied directly to one terminal of a two-input NOR circuit 502 and is applied to the other terminal of the NO~ circuit through an inverter 504 the output terminal of which is coupled to ground by a capacitor ~ 10 506. NOR circuit 502 provides an input for one terminal of ; a thrèe-input NOR circuit 508 adapted to reset counter 462 and 468. The signal from circuit 502 resets counters 462 and 468 ~when the highest bonus level has been entered so that the same bonus levels will be given for additional money. I apply the output from ~OR circuit 438 to one input terminal of each of the NOR circuit 508 and a NOR circuit 509 adapted to reset ; counter 490.
Each time a selection is made a clear signal on terminal 512 actuates a reset signal circuit 510 supplied with potential from a terminal 514 to produce both a reset and a reset complement output. I apply the reset signal to each of the down counter 356 and the up~down counter 400. The comple-ment of this reset signal is applied to the NOR circuits 444, 508 and 509. For purposes of clarity the connections between the output lines of circuit 510 and the circuits described above have not been shown on the drawing. Further for purposes o~ clarity, we have indicated the conductors connecting the portion of the circuitry in Flgure 11 with the portion of the circuitry in F1gure 12 by the same reference characters in each of the Figures. Conductors 516a to 5i6c carry the output of the OR circuit 458 to the respective NOR circuits 350, 352, and 354. Conductor 518 applies the signal output from NOR

cb/ - 26 -~04074;~
circuit 492 to NOR circuit 388. A conductor 520 applies the output from counter 462 to the NOR circuit 444 leading to the play price divider 3~2. Conductor 522 applies the complement output from flip flop 422 to NOR circuit 460. A conductor 524 couples the output of NAND ctrcuit 438 to NOR circuit 509.
I have so arranged the system shown in Figures 11 and 12 that when the circuitry is incorporated in a large-scale integrated chip, the chip may be used as a money meter also.
To achieve this result, an inverter 526 couples conductor 376 to one input terminal of a two,input NAND circuit 528, the other input to which is supplied by the decoder 402. NOR
circuit 528 provides one input for a two-input AND circuit 530, the other input of which is from a source 532 of pulses having a frequency such as to provide a five Hertz square wave output. AND circuit 530 actuates a circuit 534 the output of Which i8 coupled by an ~nverter 536 to a mechanical counter of any suitable type known to the art (not shown) to print out the total money used for any period of time. The output of circuit 434 is applied directly to one terminal of a two-input NOR c~rcuit 538 and to the other input terminal of the circuit through an inYerter 540, the output of which is connect-ed,to grQund by a capa~itQr 542. NOR circuit 538 provides an input to circuit 446 leading to the count down terminal of counter 400,. In this way the gate pulses from source 532 count down the counter 400 at a very slow rate so that the out-put from inVerter 536 is a square waye output for driving a mechanical counter. In this way, I have provided hi~h speed cLrcuitry which can accept various denominations of money and which can be used with an inexpensive low speed printout devlce.
'``~ 30 The operation of the form of my invention shown in .:
,-, Figures 11 and 12 will be apparent fro~ the description herein-, above. In response to signals from coin switches CSl to CS5 :
cb/ - 27 -~04074Z
down counter 356 produces a train of pulses equal in number to the number of basic money units in the surn deposited.
The play price divider div1des the num~er of pulses in the train by a number Nl equal to the number of money units in the standard price. As a result, counter 400 counts up to the number of plays represented by the money deposited to pro-vide signals at terminals 404 and 408 depending upan the deposited sum.
To credit bonuses counter 356 is actuated to produce a number of pulses equal to the number of bonus plays to be credited. These bonus pulses bypass divider 392 and are fed to counter 400. When a standard selectlon is played, a single cancel pulse is fed to the count down terminal of counter 400.
When a premium pla~ is made, counter 356 generates a number of cancel pulses corresponding to the number of standard plays represented by a premium play and these cancel pulses bypass divider 392 and are applied to the down count terminal of counter 400 to reduce its count by the appropriate number of plays. Where the system is to be used in connection with a printout device as a money meter, the count registered in counter 400 is read out slowly i~n response to the clock pulses ~rom source 352 to provide a square wave output from inverter 536 for actuatlng a su~table printout device.
It will be seen that I have accompllshed the objects op my invention. I have provided a credit accumulator for a phonograph or the like which overcomes the defects of accumula-tors of the prior art. It does not requi-re the use of many cumbersome electromechanical switching arrangements. It is versatile in that the price at which a standard or premium ;~; 30 selection can be made is readily changed. It ~enerates bonus credits as desired in response to the deposit of Yarious sums.
The counts at which bonus pulses are generated and the number cb/ - 28 -: . ~04(~74Z

of pulses generated can be changed with ease. `
~- It will be understood that certain features and sub-combinations are of utility and may be employed without refer-ence to other features and subcombinations. This is contemplat-ed by and is within the scope of my claims. It is further obvious that various chan~es may be made in details within '' the scope of my claims without departing from the spirit of i my inventlon. It is, therefore, to be understood that my invention is not to be limited to the specific details shown and described.
Having thus described my invention, what I claim ~s:
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cb/ - 29 -~ ' " '. ' -

Claims (8)

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE PROPERTY
OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS.

1. A credit accumulator for a machine adapted to sell goods or services including in combination, a pulse generator adapted to be actuated to produce a train of pulses, means responsive to the deposit of money in different denomina-tions for actuating said pulse generator to produce a train of basic monetary unit pulses, the number of pulses in said train being equal to the number of basic monetary units in the amount of money deposited, a credit counter, means res-ponsive to said monetary unit pulses for adding to the credit in said credit counter, means responsive to a predetermined number of said monetary unit pulses for actuating said pulse generator to generate a bonus pulse and means for passing said bonus pulse to said credit counter to add to the credit stored therein.

2. A credit accumulator as in claim 1 including means responsive to a sale by said machine for actuating said pulse generator to generate a cancel pulse, and means for passing said cancel pulse to said credit counter to subtract from the credit therein.

3. A credit accumulator as in claim 1 in which said machine is adapted to sell at a standard price unit which is an integral multiple of said basic monetary unit, said means responsive to said monetary unit pulses for adding credit to said counter comprising means for dividing said number of monetary unit pulses by said integral multiple to produce a train of standard price unit credit pulses equal in number to the number of standard price units contained in the sum deposited, and means for passing said price unit credit pulses to said credit counter to add to the credit contained therein.

4. A credit accumulator as in Claim 3 in which said means for passing said bonus pulse to said credit counter comprises means for bypassing said dividing means.

5. A credit accumulator as in Claim 1 in which said means for actuating said pulse generator to generate a bonus pulse comprises means for counting the number of pulses in said train and means responsive to the end of said train of pulses for actuating said generator to produce said bonus pulse.

6. A credit accumulator as in Claim 5 in which said means for actuating said pulse generator to produce said bonus pulse is adapted to actuate said generator to generate different numbers of bonus pulses in response to different levels of money deposited.

7. A credit accumulator as in Claim 3 in which said machine is adapted to sell at a premium price which is a second integral multiple of said standard price, said accumulator including means responsive to a premium price sale by said machine for actuating said pulse generator to generate a number of cancel pulses equal to said second integral multiple and means for passing said cancel pulses to said credit counter to subtract from the credit therein.

8. A credit accumulator as in Claim 1 in which said first pulse generator includes a first source of clock pulses of a certain repetition rate, said accumulator including a second source of clock pulses having a second repetition rate appreciably slower than that of said first source and means responsive to said credit counter and said second source for producing an output pulse train of pulses equal in number to the count in said counter and at said second repetition rate.