CA1040292A - Electronic identification system - Google Patents

Abstract

ELECTRONIC IDENTIFICATION SYSTEM

ABSTRACT OF THE DISCLOSURE

An electronic detection and identification system operating with coherent microwave frequencies wherein a transmitter continuously transmits a beam of electromagnetic energy, in a predetermined direction, so as to impinge on an identification tag suitably attached on a passing object. The identification tag derives a harmonic signal from the impinging beam and radiates a beam of energy, at the harmonic frequency, which is pulse modulated in accordance with a preset identification code. The receiver receives the reflected beam and detection means therein generates signals repre-sentative of the code modulation. Other detection means in the receiver responds to electromagnetic energy which has been reflected without modulation from the tag for generating other output signals. Output processing means is provided to receive and process signals from both detecting means.

Description

RCA 65,884 104f~Z9Z
1 This is a division application serial No. 213,135 filed November 6, 1974. The invention described and claimed herein relates to an electronic detection and identification system, and in particular, to a vehicle identification system.
With the ever increasing volume of traffic on public highways, traffic bottlenecks, such as toll booths, are becoming serious problems. There is thus a need for a means of identifying vehicles and recording such identification from a remote site without requiring the vehicle to stop or slow down.
Various optical systems have been proposed but have been found unsuited to a highway environment, since they require maintenance in that lenses, "windows," and optical indicia must be kept substantially dirt free or erroneous readings may result. Moreover, a critical spatial alignment is usually required between the optical sensors and optical indicias.
- Radio frequency transponder systems such as that described in U.S. Patent No. 3,270,330, have been employed in vehicle identification. However, such systems are too bulky and expensive for so wide spread an application as general automotive vehicle identification.
Microwave transponder systems, such as that disclosed in U.S. Patent 3,745,569, provides a transponder, of small dimensions, containing an oscillator and a preset memory comprising a plurality of counters and decoders and a diode matrix. The transmitter component provides a pulse modulated interrogation beam to energize the oscillator and drive the memory. It should be noted, however, that the oscillator frequency is .
, RCA 65,884 ~04~29Z
1 different from and not related to the transmitter frequency, i.e., the interrogation and return signals are uncorrelated. The output of the preset memory is utilized to pulse modulate the oscillator output signal with a preset identification code and the modulated signal is transmitted to a receiver adapted to identify the code.
However, such systems using active microwave elements, such as an oscillator are, for the practical reason that microwave oscillators are usually unreliable at the higher frequency bands, limited to a modulated return signal in the lower bands of the microwave region of the electromagnetic spectrum. For example, in the system disclosed in U. S. Patent 3,745,569, the interrogation beam is of a x-band microwave frequency (8,000 - 12,500 MHz) while the frequencies of the modulated return signal from the oscillator are in the L band (1,000 - 2,000 MHz). Utilization of such lower frequency information carrying return signals is disadvantageous as compared to x-band or Ku band tl2.5 - 18GHz) returns for several reasons: (1) spectrum availability is greater in the higher regions; (2) there is greater freedom from electromagnetic ¦ interference (EMI) at the hi8her bands of frequencies;
! 25 and (3) the realizable gain of the antenna is larger for a given overall antenna size at the higher frequencies.
, In addition, the use of uncorrelated interroga-¦ tion and return frequencies as in such a system as described in U. S. Patent 3,745,569 necessitates the ,3D use of wide band detectors. Moreover, the transmission i ~ 3_ '. ;

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1 power requiremcllts of suc ~ Q~ Zakc it ~irri~ult to stay within sa~e radiation limits.
Vehicle detection systems h~c been described in which a "reflected" second harmonic of a transmitte~
fundamcntal signal is derived from the transmitted fundamental signal and detected. These disclosed systems also provide for use of passive non-linear elements which are, in turn, deployed as targets to derive and "reflect"
the sècond harmonic signal. One such system, is described in U.S. Patent 3,781~879-Staras et al granted December 25,1973, entitled "Harmonic Radar Detecting and Ranging System for Automotive Vehicles". The target of the system described in U.S. Patent 3,781,879 provides a derived harmonic return signal which is orthogonal to the polarization of the trans-mitted fundamental signal thereby providing polarization, as well as frequency (i.e. harmonic frequency return signal) discriminal,ts against "blinding" and ciutter.
Another such system, described in U.S. Patent 3,631,484-Augenblick,granted December 28,1971 further discioses effecting an amplitude modulation of the reflected signal by applying an analog periodic bias voltage to a non-linear device. The amplitude modulation is utilized to cause a shift of the modulated frequency equal to the modulating frequency. The frequency of the modulating voltage is measured and particular vehicles are identified by their individual modulation characteristics. Analog modulat;on identification systems are disadvantageous in that they do not readily lend themselves to automatic correlation techniques for large numbers of vehicles.
Another example of the prior art systems is shown - . . ~- . . ..
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l in U.S. Patent 3,754,250-l~runer, granted August 21, 1973.
That system provides a short-range detecting and identifica-tion system comprising a transmitter, receiver, and output processing mcans cooperating with any one of a plurality of remote identification devices. The transmitter generates electromagnetic energy signals of a predetermined frequency, which are suitably directed to impinge upon such a device.
Each device comprises a harmonic radiator which derives from the signals received there ~ 5ignals which are related harmonically to such received signals. There also is pro-vided for each device means for pulse modulating the harmonically related signals in accordance with a pre-determined digital identification code unique to the particular device. A timing means derives a clock signal for controlling the encoder. The receiver detects the modulated h~rmonic signals radiated from any such device and g-~nerates output signals indicative of the identifi-cation code modulation of the radiated signals. Means, are also provided to decode the output signals of the receiver in order to determine the identification code number of the device.
One aspect of the present invention is directed to an improvement in the above-mentioned device shown in U.S. Patent 3,754,250. In the case of the present invention the device is an identification tag of the type suitable for use in a short range detecting and identification system.
In the contemplated system are used the above-mentioned transmitter, receiver and output processing means (22) receptive of output signals from the receiver. The receiver detecting means detects from the ~dg the pulse modulated :: . ,. , . . ~ . -. ,.:
.:. -.. ... . . , - , . :

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RCA 65,884 I signal which is harmo~nlcally related to the predeter~ined frequency signal. The tag comprises as does the device shown in the patent: (a) a harmonic radiator (27) for deriving from the signals of the predetermined frequency received at the tag the harmonically related signals and for radiating those harmonically related signals in a direction toward the receiver, and (b) encoding means for pulse modulating the derived harmonically related signals. The encoding means includes control means for controlling the derivation and radiation of the harmonically related signals in accordance with a predetermined digital identification code.
In the contemplated invention the above-mentioned is borne past a transmitter and receiver.
The transmitter comprises means for generating the electromagnetic energy signals of predetermined frequency.
The receiver comprises first means for detecting from the tag a modulated signal which is harmonically related to the predetermined frequency signal, and for generating first output signals indicative of the modulation of the detected signals.
In accordance with the invention, the receiver inclutes a second detector which responds in the presence of the signals (originating from the transmitter) of predetermined frequency, which signals: (a) have been reflected during the passage of the tag past the transmitter and receiver, but (b) have not been modulated by virtue of operation of the tag encoding means. In the presence of suchireflected signals, the second detector means r~esponds by generating second output signals.

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RCA 65,884 ~040292 1 The output processing means is further operative to -:
indicate the occurrence of the second output signals from the second detection means independently from the operation of the first detection means.
In the following detailed description reference i5 r<ade to the accompanying drawin5s In whl ch:

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RCA 65,884 ~04()29Z
1 Figures 1, la and lb are diagrams of a system and a tag antenna array incorporating the present invention.
Figures 2, 3, and 4 are block schematic diagrams : showing use of the identification tag embodying the present invention;
Figures 5, 6, 7,.and 8 are block schematic diagrams showing use of the identification tag features which may be used with the present invention.
Figure 9 is a block schematic diagram of a decoder;
Figure 10 i8 a chart showing the timing relation-ship of various signals involved in the decoding process used in the decoder illustrated in Figure 9. ~ :
Figure 11 is a schematic diagram which illustrates how the invention may be used in a vehicle detection and identification system;
Figures 12 and 12a are schematic diagrams illustrating an embodiment of an invention directed to an automatic locking device.
:. 20 In Figure 1 i8 shown a short range detecting and identification system having a transmitter 10 coupled to a suitable directional transmitter antenna 12, a~d a receiver 14 coupled to a directional receiving antenna 16.

Receiver 14 includes output terminals 18 and 20 which are 2S connected to output processing means, generally indicated a~ di~play 22, which may be remotely situated from the receiver.
Transmitter 10 is arranged to generate electro-magnetic energy signals of a predetermined frequency f, at low power in the order of 150 milliwatts, by use of a . ~ -7a-.. - ~ . . . . . .

RCA 65,884 :~040~9Z
1 negative resistance semiconductor device, such as TEO 11, coupled to filter means, such as a low pass filter 13, to prevent spurious harmonics pas~ing to transmitting antenna 12. -Antenna 12, preferably having directional characteristics, is arranqed to direct a beam of electro-magnetic energy signals 24 of predetermined frequency, f, in a predetermined direction to expose to the beam a tag carried on a vehicle or person positioned in or passing therethrough.
The target or tag 26 as shown in Figure 1 i9 ~_, _ . .. , . . , .. .. , . ., .,, .. .. . . ,, . - , . - ., . , - .. - . .

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l formet of a harmonic radiator 27, comprising an antenna 28, adapted to operate at a base frequency (f) and a chosen harmonic thereof, and a harmonic generator 30.
Antenna 28 is arranged to receive the predetermined frequency (f) signal beam 24 from the transmitter 10, and lS coupled across harmonic generator 30. Harmonic generator 30 is formed of a passive non-linear element, such as, for example, a zero bias Schottky barrier silicon diode.
Antenna 28 is suitably a flat corporate-network printed circuit antenna system, of the type described in U. S. patent 3,587,110, comprising 16 dipoles and a corporate feed, being tuned to the geometric mean frequency between the base frequency f and the chosen harmonic thereof.
For example, if base frequency f is chosen to be 8.75 GHz lS (X-band), and the chosen harmonic is the second harmonic (2f) thereof, namely, 17.5 GHz (Ku-band), the antenna dipoles are 1/2 wavelength Iong at 12.4 GHz. Figure la is a schematic showing such an a~t~nna structure. One-half of the antenna pattern is etched on one sid~ of a circuit board (indicated by solid lines in Figure la) suitably a .020 inch thick, touble clad board, 3-inches wide by 3.5 inches long (for the exemplary base frequency 8.75 GHz); the other half of the antenna pattern being etched on the opposite side of the board (indicated by dotted lines).
The corporate feed structure 281 is coupled to harmonic gonerator 30, here a doubler circuit, by means of a capacitive gap 28.2 etched on the first half of the circuit pattern. Impedance transformers included in the feed structure match the antenna impedance to the doubler at 8.75 GHz and 17.5 GHz. To achiove a unidirectional RCA 65,884 ~o40zg2 I radiation pattern from the antenna a back cavity is placed behind the antenna. A polystyrene sheet 0.240 inches thick by 3 inches square maintains the spacing of the antenna in the back cavity. A spacing of 0.240 inches corresponds to a quarter wavelength at the geometric mean frequency 12.4 GHz.
The harmonic generator (double~ circuit) 30 - consists of a nonlinear element 30.1 (suitably a Schottky barrier diode chip) assymetrically disposed between an - 10 open circuit 50Q transmission line 30.2 and a short circuit 50Q transmission line 30.3. The lengths of the open circuit and short circuit lines are chosen so that the equivalent circuit of transmission line and diode is resonant at 8.75 GHz and 17.5 GHz. The equivalent circuit of harmonic generator (doubler circuit) 30, is shown in Figure lb. The resonant condition enhances the doubling efficiency at low microwave power levels. A matching stub 28.8 is placed .220 wave-lengths at 8.75 GHz from the open circuit end toward the antenna 28 to enhance the power coupled from the antenna to doubler at 8.75 GHz.
Similarly, a reactive termination, 30.4, suitably an open circuit 44n stub, is placed on the short circuit line 30.3 where the 17.5 GHz signal is near maximum, i.e., ap-proximately a quarter wavelength at 17.5 GHz from the short 2S circuit ent; suitably 0. 375 wavelengths from the short, to recover the 17. 5 GHz (harmonic) signal at the antenna 28.
- It i8 observed that separate receiving and radiating antennas can be readily utilized in the stead of the single "dual frequencyU antenna above described.
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RCA 65,884 1040Z9;~
1 Referring again to Figure 1, antenna 28 radiates the output signals of harmonic generator 30, generated in response to signal 24, as a directional beam 34 of electro-magnetic energy in the direction of the source of signal 24.
The beam 34 may include components at the base frequency f ~here 8.75 GHz) of the signal 24, as well as components at frequencies harmonically related thereto. Output signal 34 of harmonic generator 30 may be filtered, if desired, as by the resonant transmission lines sho~n in Figure lb, to substantially attenuate all but selected harmonic components, preferably the second harmonic.
The signal beam 34 will, therefore, hereinafter, be referred to as harmonically related to the predetermined frequency f. Thus, if the plane of harmonic radiitor 27 is lS orthogonal to the received radiation, radiator 27, radiates harmonic electromagnetic energy, in response to such impinging illumination of a corresponding fundamental frequency (f), in a direction, generally to the source (antenna 12) of the fundamental frequency electromagnetic energy 24.
In the preferred embodiment of the invention, the predetermined frequency f of the impinging beam 24 is a microwave frequency within the x-band region of the - radiation spectrum, e.g. 8.75 GHz. Accordingly? the 2S radiated harmonically related signal may then occur in the Ku-bsnd of the spectrum, e.s. 2f - 17.5 GHz wherein there is relatively higher spectrum availability and less electromagnetic inter~erence (EMI) than at lower regions of the spectrum. Further, return signals in the higher regions allow utilization of a smaller antenna to achieve . : . . . . . .

RCA 65,884 104~129Z
a given gain.
Tag 26 is provided with a timing means 36 and an encoding means 38. Timing means 26, suitably a crystal oscillator, provides a clock signal over conductor 40 (Fig. 1) to encoding means 38. Encoding means 38 includes suitable storage means tnot shown) for storing a preset digital identification code and is coupled to harmonic generator 30 over conductor 42. For an attenna structure and harmonic generator such as shown in Figure la, conductor 42 is coupled to a transmission line 30.5, and therefrom through a low pass filter 30.6 consisting of a 1 mil diameter wire, 0.140 inches long, serving as a rf (radio frequency) choke, and a 60 pf (pica farad) capacitor chip 30.7 to the open circuit transmission line 30.2 lS of the (doubler circuit) harmonic generator 30.
-~ It should be noted that although conductors are shown in the drawing as single lines, they are not so shown in a limiting sense and that the conductors may comprise plural connections as understood in the art.
Referring again to Figure 1, timing means 36 and encoding means 38 may be free running or triggered by illumination of tsg 26 by signal 24 (as will later be explained in conjunction with Figure 6). For either of such forms, illumination of tag 26 by beam 24 enables 2S harmonic generator 30, and harmonic radiator 27 generates and transmits harmonic signals 34. Encoding means 38, driven by timing means 36 is arranged to inhibit selectively harmonic generator 30 for certain of the tim~ periods defined by timing means 36, in accordance with the preset digital identification code. Alternatively, harmonic ~' . -11-: . .

RCA 65,884 104~)Z9Z
I generator 30 can be normally inhibited and be selectively activated during periods of enabling illumination by the encoding means 38. Thus, the radiated second harmonic beam 34 is effectively pulse modulated in accordance with the preset identification code.
Receiving antenna 16 of receiver 14 is arranged to be illuminated by signals radiated from tag 26; the harmonic signals of beam 34, and beam 46, representing signals reflected in a conventional skin radar sense, from the tag, and the vehicle or person to which the tag is affixed. Receiver 14 maintains a sufficiently ~ - wide bandwidth to enable it to receive such signals.
; Receiving antenna 16 may be a suitable dual frequency antenna or comprise suitable separate antennas respectively tuned to the fundamental frequency ~f) and the desired harmonics.
Receiver 14 includes a detector 48 connected in parallel with a serially connected high pass filter 50 and detector 52, each of the parallel b~anches being receptive of the signals received by antenna 16.
Detector 48, suitsbly a diode detector, generates an output signal, comprising the modulation envelope (waveform) of the totality of the received signals; both skin radar type reflection 46 and harmonically 2S related signals 34 from the tag 26, thereby indicating ~; the passage of any vehicle or object, ~hether or not ` such vehicle is carrying a tag 26, and if such vehicle is j carrying a tag 26, whether or not the tag is operating to provite an identification, as will hereinafter be 3 - further explained. The output signals of detector 48 ` ' .

RCA 65,884 104(1Z92 1 at terminal 18 are suitably communicated to a suitable indicator, serving as a vehicle presence indicator 54, in the display or output processing means 22.
Signals 34 and 46 received by antenna 16 are routed through high pass filter 50 to detector 52, again suitably a diode detector. High pass filter 50 is arranged to attenuate all signals below the selected harmonic frequency, e.g. 2f, thus alleviating the need for strict filtering of the harmonic generator output signals in the tag. The output signal of detector 52 is, thus, the pulse-modulation envelope of the ratiated harmonic beam 34. The detected pulse modulation waveform is passed from detector 52 to terminal 20 and to a decoder 56 in the display or output processing means 22.
In operation: a tag 26, when illuminated by signal 24, responds by deriving and radisting harmonically related signals 34, which are pulse modulated according to a preset code for each tag. Receiver 14 detects received harmonically related signals 34 and any signals 46 reflected, as in conventional skin radar, from the vehicle to which the tag 26 is affixed, to provide indication of the presence of a vehicle and establish the identification of such a vehicle if the vehicle bears an operable tag.
2S ~ncoding means 38 of tag 26 may be implemented in any of several forms as will be described with reference to Figures Z, 3, and 4.
Figure 2 illustrates tag 26 utilizing an arrangement of encoding means 38, which comprises a binary logic storage means 60 connected to control means 62 . .

: . - . . , RCA 65,884 ~040292 1 through conductor 64. Timing means 36 supplies clock signals to control means 62 through conductor 66. Control means 62 communicates with harmonic generator 30 through line 68.
Control means 62 is arranged to respond to the clock signals from timing means 36 to successively pass the binary content of each individual member bit of storage means 60 to the harmonic generator 30, as an appropriate enabling or inhibiting control signal.
Storage means 60 may be a suitable binary logic read only memory (ROM) while control means 62 may be a suitable gating circuit of binary logic both well known in the art.
Control means 62 may be formed of a plurality of AND gates and a ring counter. Referring to Figure 3, tag 26 is shown utilizing such an arrangement of AND
gates and a ring counter. Timing means 36, through conductor 66, drives a suitable ring counter 70 comprising a plurality of member bits 72, 74, 76, 78j for a four-digit code. The output terminals of the individual member bits 72-78 are connected, via conductors 80-86 respectively, to one input terminal of respective associated gating means, such as two input AND gates 88-94. rhe second input terminals 96, 98, 100, and 102 2S of two input AND gate 88-94, are respectively connected ; to a voltage bit or ground grovided by storage means 60 corresponding to a logical one or a logical zero, in accordance witll the desired preset identification code. The output terminals 104-110 of AND gates 88-94, are connected, respectively, to an OR gate 112 which : .

RCA 65,884 1 communicates with harmonic generator 30 through conductor 68. Figure 3 illustrates thus a tag for a preset four digit code. It will be clear that an additional ring counter bit and an associated AND gate would be needed for each additional bit of code for this logic arrangement.
In operation, assuming that harmonic generator 30 is arranged to be normally inhibited and the encoding means 38 generates an enabling control signal, the following sequence of events occur for a preset identification code number 13 ~binary 1101). Timing means 36 generates a (free running) clock signal, which sequentially advances a value of logical one through ring counter 70, beginning with member bit 72. The logic 1 value in bit 72 enables associated AND gate 88 for the duration of the clock interval. The second input terminal 96 of AND
gate 88 receives in accordance with the binary code, a logical one value, i.e. it is connected to a Bl voltage by storage means 60. Thus, a logical 1 value is generated at AND gate 88 output terminal 104. The logical 1 value is communicated to harmonic generator 30 via bus line 112 and conductor 68. Thus, the harmonic generator 30 is enabled for the first clock pulse.
The second clock pulse from timing means 36 advances the logical one value on line 82 and thereby enabling associated AND gate 90. However, in accordance with the preset code, storage means 60 applies a logic zero value to the second input terminal 18, i.e. does not connect terminal 98 to B~ volatage, but instead is connected } to grount and a logic zero voltage is established - .

RCA 65,884 1 on output terminal 106 of AND gate 90. Thus, the harmonic generator 30 remains inhibited for the duration of the second clock pulse. The third and fourth clock pulses from timing means 36, respectively, advance the logical 1 value to member bits 76 and 78 in the ring counter 70 and thereby enabling AND gates 92 and 94 for the respective clock pulses. The second terminals 100 and 102 of AND
gates 92 and 94, in accordance with the identification code, have applied logical 1 values. Thus, a logical 1 value is established at output terminals 108 and 110 and the harmonic generator 30 is thereby enabled during the duration of the third and fourth clock pulses respectively.
Subsequent clock pulses, advance the logical one value into delay line 114, which comprises a preset number of member bits, to establish a predetermined duration of off time to be utilized if desired by the decoder (56, Fig. 1 e.g.) as will be subsequently further explained.
Thus, the control means 62, in response to the timing means 36, selectively enables (or in,hibits) the derivation (and radiation) of harmonics by harmonic radiator 27 in accordance with an identification code stored in storage means 60.
Figure 4 is a schematic of an embodiment of tag 26 wherein control means 62 is formed of a parallel load, serial output type shift register and a mode selection control for the register. Timing means 36 supplies - continuous clock pulses over conductor 66 to automatic mode ~ , selection means 116, suitably a counter/divider and shift ~v register 118. Shift register 118 is also responsive to a mode control signal from mode selection means 116 over RCA 65,884 1 conductor 120 to receive (in parallel) the contents of storage means 60 over parallel lines 64. The output signals of shift register 118 are applied to harmonic generator 30 through conductor 68 and r.f. choke 122. The value 50 or 1) of the bits on each of the respective lines 64 is deter-mined by the wired connection between each such line 64 and B+ or between each such line and ground. In this manner, storage means 60 is capable of delivering to register 118 a 16 bit identification code.

In operation, mode selection means 116, in accordance with the clock signals received from timing - means 36, supplies a control signal, e.g. logic 1, over conductor 120 to shift register 118, causing 118 to receive i in a parallel load mode bits over lines 64. In this manner, lS shift register 118 is loaded with the contents of storage - -means 60 by applying B+ voltage bits to specified lines 64 in accordance with the identification code and ground bits to remainder of lines 64.
At the end of the loading of register 16, which i~ marked by the occurrence of a specified number of clock pulses (e.g. 16 pulses) from 36, mode selection means 116 8upplies a second control signal (e.g. logic 0 over 120) to cause shift register 118 to switch to a serial output mode, and thus to shift (or read out) in response to the 2S clock signals from timing means 36 the bits of the code ln register 118 serially onto output conductor 68. Each serially occurring bit of the binary code on conductor 68 is applied via r.f. choke 122, to a suitable harmonlc gonerator 30 (such as non-linear diode element 124) as an appropriate biasing voltage which inhibits or enables . r . - . . . . :

RCA 65,884 104~)Z9Z
1 second harmonic generation. Accordingly, generator 30 produces appropriate output signals in accordance with the preset code set into storage means 60. R.f. choke 122 serves to block any r.f. signal leakage from antenna 28 to encoding means 38.
After application of a number of clock pulses (16-pulses) sufficient to advance all the bits of the predetermined specified code from shift register 118 onto conductor 68, mode selection means 116 again provides the parallel load control signal (logic 1), so that shift register 118 is again loaded with the same code number preset in storage means 60 in the manner previously described. The cyclic unloading operation of regi~ter 118 in accordance with the clock signals may then be continued.
The embodiment of Figure 4 may be implemented utilizing an RCA CD4004 COS-MOS 32 bit counter for the mode ~election means (116) and two serially connected RCA CD4014 COS-MOS 8-stage shift registers for shift register 118. The storage means ~60) provides for 16 active bits of a 32 bit identification code. The code also-includes 16 bits of off time, during which the shift registers ~118) are loaded.
Figures 5 through 8 are schematic diagrams illustrating additional features.
-2S Figure 5 is a schematic diagram illustrating a tag 26, including a power source 150 for timing means 36 and encoding means 3a. The illustrated tag is for use in a system where the impinging signal (24) from transmitter 10 (Figure 1) is pulse modulated with a signal having a specified duty cycle, such as 50~ (square wave amplitude ; ~ -18--. . - . . ~ ............. , . , . : - ,........... . . ~, . . .:
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RCA 65,884 1 modulation). In such an arrangement, timing means 36 detects a~d amplifies the pulse modulation envelope of the impinging signal (24~ and the amplified signal is utilized as the clock signal.
S Specifically, one terminal 126a of the balanced transmission line that feeds tag antenna 126 (which cor-responds to antenna 28 in Figure 1) is connected RCA 65,884 1 through a coupling capacitor 128 to the snode of a detector diode 130 over conductor 132. The other terminal 126b of the balanced transmission line that feeds tag antenna 126 is connected over conductor 134, through an r.f. choke 136, to one terminal of resistor 138. The other terminal of resistor 138 is connected to the cathode of detector diode 130 at junction 142. A capacitor 138a, serving as an r.f. bypass, is also connected across resistor 138.
Conductors 132 and 134 are connected together through an r.f. (radio frequency) choke 144. The r.f. choke 144 has a small impedance at low frequencies, but presents a high impedance to high frequency signals and hence "chokes off" high frequency signals but allows a D.C. return for capacitor 128. An operational voltage amplifier 146 is connected across resistor 138, with its non-inverting input 145 connected at the junction 142 between resistor 138 and diode 130, and its~nverting input 147 connected at junction 140. The output of amplifier 146 is coupled - over conductor 148 to encoding means 38 as a clock signal 149. Amplifier 146 and encoding means 38 are powered - by a power supply such as dry cell battery 150 over conductors 152 and 154, respectively. Encoding means 38 is connected across a non-linear element harmonic generator 30 through r.f. chokes 156 and 158. Harmonic generator 30 is, in turn, connected across the balanced transmission line thst feeds tag antenna 126.
In operation of the tag of Figure 5, detector diode 130, resistor 138, and capacitor 138a function as an onvelope detector 160, which detects the modulation envelope of the remotely transmitted predetermined frequency ,. . ~ , .
... ; ,. . . .. . . . .

RCA 65,884 I (f) beam impinging on antenna 126. A signal having the waveform of the modulation waveform is amplified by amplifier 146 and applied to encoding means 38 as clock signal 149. slocking capacitor 128 and r.f. chokes 136, 144, 156, and 158, serve respectively to maintain isolation of the d.c., the code modulation, and r.f. signals by virtue of their frequency dependent reactances.
Figure 6 i9 a schematic illustrating a tag accord-ing to the invention wherein power is applied to the timing and encoding mean~ only when signals of predetermined fre-guency impinge on the tag. Specifically, one terminal 162a of the balanced transmission line that feeds tag antenna 162 (which corresponds generally to antenna 28 in Figure 1) is connected to the anode of a rectifier diode 164 through lS capacitor (C) 166a by conductor 166. The second terminal 162b of the balanced transmission line that feeds tag anténna 162 is connected to one terminal of capacitor 168 by conduc-tor 170, at junction 172. The second terminal of capacitor 168 is connected to the cathode of detector diode 164 at junction 173. Junction 172 is d.c. grounded through r.f.
choke 174. Conductors 166 and 170 are d.c. coupled through r.f. cho~e 176. The non-inverting input 177 of an operation-al voltage amplifier 178 i8 connected to junction 173 between detector diode 164 and capacitor 168. A power supply (battery 180) provides power for amplifier 178 and is tapped by conductor 182 to supply a small d.c. voltage "e" to the inverting input terminal 184 of amplifier 178. The output ~ignals of amplifier 178 are applied a~ B~ voltage over con-~uctor 186 to timing and encoding means I88. Encoding means 188 is connected across a non-linear el-ment 190, s-rving as a RCA 65,884 1041~)Z92 1 harmonic generator, through r.f. chokes 192 and 194.
R.f. chokes 192 and 194 readily pass the relatively low frequency code signals from encoder 188 but present a high impedance to high frequency signals such as the impinging signal f. Harmonic generator 190, is in turn, connected across the terminals of the balanced transmission line that feeds tag antenna 162.
In operation of the tag of Figure 6, rectifier diode 164 and capacitor 168 function as a voltage rectifier 196, which generates a positive d.c. voltage greater than the threshold voltage of "e" volts at junction 173 when signals of suitable amplitude of frequency f ~ impinge on antenna 162. Thus, amplifier 178 serves as a - comparator generating an output signal (B+) only when lS the voltage at junction 173 (and therefore the voltage at noninverting input 177 connected thereto) is greater than the reference voltage "e" applied to inverting input 184. The output signal of amplifier 178 is applied as a Bt voltage to the timing and encoding`means 188.
Thus, rectifier 196 and amplifier (comparator) 178, serve as switching means, responsive to received signals at predetermined frequency (f) for applying power to the timing and enaoding means (188) only in the presence of ~ -such signals.
R. F. coupling capacitor 166a serves to isolate the D.C., the coding waveform, and the RF from mutual interference. It should be apparent to those skilled in the art that capacitor 168 discharges, in the absence of received signal, through the finite input resistance of amplifier 178 and the finite back resistance of d`iode 164 RCA 65,884 1 or through an appropriate shunt resistance (not shown).
Figures 7 and 8 are schematics showing alternativeembodiments of the identification tag wherein the power for operating the timing and encoding means is derived from S the energy 86 impinging signal.
Figure 7 illustrates schematically such a tag for use with a continuous wave (CW) impinging signal. The terminals of the balanced transmission line that feeds tag antenna 200 (which corresponds generally to antenna 28 in Figure 1) are connected across suitable impedance trans-formation means such as one or more 1/4 wave matching trans-formers 202, and therefrom, are respectively a.c. coupled through an r.f. capacitor 204 to junctions 206 and 208.
Junctions 206 and 208 are d.c. coupled by an r.f. choke 210.
lS Junction 208 is d.c. grounded through a second r.f. choke 212. Junction 206 is connected to the anode of a rectifying diode 214, the cathode of which being connected to junction - 216. Junction 216 is r.f. bypassed to ground by capacitor 218. The voltage at junction 216 is applied as B+ voltage to the timing and encoding means 220 over line 222~ The encoding means 220 communicates with a nonlinear element harmonic generator 224 through r.f. chokes 226 and 228.
Harmonic generator 224 is connected across the terminals of the balanced transmission line that feeds tag antenna 200.
2S In operation of the tag of Figure 7, impedance transformation means 202 steps-up the impedance of antenna 200 thereby increasing the r.f. voltage with respect to ground seen at junction 206. Rectifying diode 214 and capacitor 218 rec~ifying the voltage and produce a B+
3 voltage to power the timing and encoding means. The RCA 65,884 I operation is otherwise the same as previously described.
Figure 8 illustrates schematically a configurationof an identification tag wherein power for timing and encoding is derived from an amplitude modulated signal having a predetermined frequency. Specifically, the terminals of the balanced transmission line that feeds tag antenna 228 (which corresponds generally to antenna 28 in Figure 1) are connected across suitable impedance transformation means such as one or more 1/4 ~ matching transformers 230 and are respectively coupled, through a capacitor 232, to junctions 234 and 236. Junctions 234 and 236 are d.c. coupled through an r.f. choke 238. Junction 234 is connected to the anode of detecting diode 242, the cathode of which being applied to one terminal of the primary coil of a voltage step- -lS up transformer 244. The other terminal of the primary i~ returned to junction 236. One terminal of the secondary coil of transformer 244 is connected to a junction 240 and therefrom to the anode of a rectifying diode 246.
Th- voltage modulation signal at junction 240 is also 20 applied over conductor 240a as the timing or clock signal to encoder 254. The cathode of diode 246 is connected to a junction 248, which is, in turn, A.C. bypassed to ground through a capacitor 250. The D.C. voltage derived at junction 2g8 is applied over line 252 as a B+ voltage 2S to the encoding means 254. The encoding means 254 is coupled to a non-linear element harmonic generator 256 through r.f. chokes 258 and 260. Harmonic generator 256 is, in turn, coupled across the terminals of the balanced transmission that feeds tag antenna 228.
In operation of the tag of Fig. 8, the impedance - ~. , - , , . . . ~
: , . . . - . .

RCA 65,884 ~04Q292 1 of antenna 228 is stepped up by impedance matching means 230, thereby increasing the voltage levels of the modulation of the signal received by antenna 228 as seen at junction 234. Diode 242, dctects the amplified modulation envelope of the received signal and applies the detected : signal to the primary coil (P) of step-up transformer 244. Transformer 244 further increases the voltage of the modulation signal and applies the signal to junction ; 240 and therefrom to encoder 254 as a clock signal and . 10 also to a rectifier 262, comprised of diode 246 and capacitor 250. The rectifier 262 derives a substantially constant B+ voltage, which is applied over conductor 252 to power the encoding means 254. The tag operates : thereafter as previously described.
The standard dot notation is used on the modulation frequency step-up transformer 244.
Before proceeding to the other embodiments, : reference is made to Flgure 1. The detector 52 in the receiver 14 as previously described produces an output signal representative of the code modulation impressed on the harmonic signal 34 reflected from tag 26. The code : .
modulation is passed to receiver output terminal 20 and j therefrom communicated to a decoder 56 in the output means . 25 22. Figure 9 is a schematic of a preferred embodiment of decoder 56, which will be now described in detail in conjunction with the wave-form chart shown in Figure 10.
The identification code utilized in the preferred embotiment of the invention comprises a 32 bit code, ` having 16 ac;ive bits followed by 16 bits that are always , 30 .
~- zero, with the first of the 16 active bits being a logic 1.

~ ... .. , ,. : .. . . . ... . .. . . .... ..

RCA 65,884 104~Z9Z
I The code modulation 270 from the receiver terminal 20 (Fi~ure 1) is coupled to a suitable adjustable threshold device 272, such as a suitable comparator in decoder 56. The output signals 270A of threshold device S 272 are applied over conductors 274 and 276 to a 16-stage divider 278, which is also receptive of clock signals 326 from decoder clock 282, typically 400 KHz. Output signals 328 from the third stage of divider 278 are applied as clock signals to input register 280 over path 279.
The output terminals of each of the member bits of input register 280 communicate in parallel over conductors 284 with an associated ~it in a storage register 286. The output terminals of the 16th (last) member bit is also connected to a "first one detector" flip- flop 285 over lS conductor 287. The output terminals of the member bits of storage register 286, in turn, are coupled on a respective bit-to-bit basis over lines 288 with a read out/
recorter 290. The output terminals of each member bit of the input register 280 and storage register 286 are also couplet over lines 292 and 294, respectively, with a parallel comparator 296.
The comparator 296 receives at its start comparison terminal 298, output signals from flip- flop 285 over conductor 300. Flip- flop 285 also communicates its output signals o~er conductor 3Ql, through an OR gate 303, to stop - terminal 320 of divider 278 and over conductor 300a to enable terminal 306a of a reset and load control 306.
Comparator 296, in response to a start comparison command from detector 285, generates an appropriate first output signal, here, a logical "one" when the contents I

- . .. - . . . . :. ;., .
- . .. .,, ,, ,. , ,.. , ., . ~ , .
. . . . , . ~ . . . . ~ -RCA 65,884 104~Z92 l Of input register 280 and storage register 286 are equal -- on a bit for bit basis and generates an appropriate second output signal, e.g. logic zero when the respective contents thereof are unequal. The output signals of comparator 296 are applied to (1) the stop terminal 320 of divider 278 via OR gate 303, (2) the unblanking/enable input terminal 304 of read out/recorder 290 and (3) reset and load control 306 over conductors 308, 310 and 312, respectively.
Reset and load control 306, typically an arrangement logic gate applies, in response to appropriate output signals, a first output signal over conductor 314 to the reset input terminal 316 of input register 280, and a second output signal to the load control input 318 of storage register 286 and the reset terminal 302 of IS flip-flop 285 over conductors 322 and 324, respectively.
In operation, threshold device 272 serves to prevent spurious relatively low level signals from enteri~g the decoder by making requisite a desired signal-to-noise - ratio, e.g. suitably in the range of 3 to 6 db. In addition, the bandwidth of threshold device 272 may be narrower than the bandwidth of receiver 14, suitably by a fsctor of 3 to 1, to further reduce the possibility of a spurious signal causing decoder error. Threshold tevice 272 may also act as an interface between the 2S code modulation 270 and the decoder logic, which converts ;; the code modulation signals to appropriate voltage levels compatible with the logic circuits of decoder 56 or alternatively, as a gate, which, once set by an appropriate signal level, passes signals for a time sufficient for the decoding process. With the exception of threshold RCA 65,884 104~292 1 device 272, the decoder 56 may be implemented entirely in TTL logic chips, thereby allowing the decoder to be in an advantageous compact form.
In operation of the decoder of Figure 9, the first positive going transition of code 270 (and therefore of identical converted code 270A) enables counter/divider 278 and causes counter/divider 278 to become responsive to clock signals 326. Counter/divider 278 thereafter counts in accordance with the clock signals 328 from the decoder clock 282. The frequency (400 ~Hz) of decoder clock 282 is chosen at a multiple, suitably 8, of the frequency of the clock signals produced by the timing means (50 KHz) in tag 26, i.e., the time base of code modulation 270.
lS Input register 280 samples and stores the instantaneous logic level of codeword 270A in accordance with negative transitions in the output signals 328 over line 279 from the third state of divider 2i8 for reasons as will be described. With reference to Figure 10, the first positive-going transition 330 of converted code modulation 270A enables counter/divider 278 ~with respect to) to receive decoder clock pulses 326. The first stage of counter/divider 278 thereafter changes state with every positive-going transition of decoder clock signal ~ 25 326. Similarly, the second stage of divider 2?8 changes - state in accordance with every positive-going transition . in the output signal of the first stage. The third stage, in turn, changes state in accordance with every positive-~oin~ transition in the output signal of the second stage, and so on. Thus, the third stage output signal 328 will - . - : . .

RCA 65,884 104~29Z
l initially change state, from logic one to logic zero, after four cycles of decoder clock signal 326 and will make subsequent negative-going transitions henceforth after every eight cycles of decoder clock signal 326.
As illustrated in Figure 10, the negative-going transitions of the third state output signal 328 occur in the center of each of the modulation code 270A bits. By sampling code 270A in accordance with the negative-going transitions of the third stage output signal, the code bits are sampled essentially in the middle of their allotted time period, thus alleviating the need for an absolute frequency lock between the clock signals of tag 26 and the decoder clock signal 236 of decoder 56. Relative frequency shift between the tag clock and the decoder clock can be as much as l1/2 bit per word without affecting the accuracy of the - decoder. Thus, for a 16 active bit code word, a prescribed accuracy of approximately 3% can easily be attained utilizing crystal controlled oscillators for the respective clocks.
Referring again to Figure 9, it is seen that third stage output signal 328 is accordingly applied over ~line 279, as a clock signal to "shift and load~' input terminal 332 of input register 280. The converted code 270A is therefore sampled, over line 276 and stored in the first member bit of input shift register 280, in accordance with the negative-going transition of signal 328.
Previously stored data is accordingly shifted wit-hin the register with each subsequent sampling, until the first code bit, as previously noted being, for the present arrangement, a logic 1, is shifted into the 16th .. . ...

RCA 65,884 1(~40Z9Z
(last) member bit of input register 280.
The presence of a logic one value in the 16th member bit of input register 280 is detected by "first one detector" flip-flop 285, which accordingly generates an output signal. The "first one detector" output signal is passed through OR gate 303 and applied to stop terminal 320 of counter/divider 278, thereby inhibiting divider 278 - and hence stopping clock signals 328 to the input - register 280. The "first one detector" output signal is also applied over conductor 300 to the start terminal 298 of comparator 296, thereby initiating in comparator . 296 a parallel, bit-for-bit comparison of the contents of input register 280 and storage register 286.
Comparator 296 generates a first output signal lS ~a logical one) in accordance with a favorable comparison and a second output signal (a logical zero) in accordance with an unfavorable comparison.
The readout/recorder 290, is responsive to first 1 output signals (logic 1) from the comparator (indicative of i favorable compsrison) applied to lts unblanking/
~ enable terminal 304. The application of the appropriate ¦ signal to terminal 304, causes readout/recorder 290 to ¦ become receptive of information carried on parallel line 1 288. Thus, the contents of the storage register 286 are ; 25 '~ ~ transferTed to readout/recorder 290 over line 288 and are i therein recorded and/or converted to decimal form and displayed in any suitable way as desired.~ Readout/recorder . means 290 may thereafter suitably reset the system ~not shown) or the system may be reset manually (as shown in Fig 9).

.'.'. ' . ' ., ,' .. . " ~` ' ` :
;... . ~ ' ' . ' .. ' ' .

RCA 65,884 l If the comparison is unfavorable, the comparator 296 generates an appropriate second output signal (logical zero) to which reset and load control 306 and divider 278 (through OR gate 303) are responsive. Reset and load control 306 accordingly generates the aforementioned first and second output signals which effect a parallel ~ransfer of the contents of input register 280 into storage register 286 through parallel line 284, clear input register 280 and reset "first one detector" flip-flop 285. The divider 278 is reset, uninhibited, and is thereafter restarted by the next positive-going transition received at its start terminal over line 274.
With reference to Figures 1 and 9, it should be unterstood that as beam 24 impinges on tag 26, tag 26 reflects or retrodirects harmonically related beam 34, pulse modulated in accordance with a 32 bit code word comprising 16 active bits and 16 offtime bits ~ith the first active bit always having a logic 1 value. Beam 34 is detectet via the receiver 14, and code'modulation 270 is communicated to the decoder 56. Décoder 56 is actuatet by the first logic 1 value bit in the word received and thereafter samples, and loads into input shi$t register 280, 16 consecutive code bits. The sampled . code word is compared with the contents of storage register 286, which is initially zéro, and the sampled ' ' 'word is therefore loaded into storage register 286. If beam 24 impinged upon tag 26' at such a time that the first logic one value received by the decoder is by coincidence -~ the first active bit of the code word (requisitely a logic - one value) an accurate sampling of the code is stored in ~ - 30 , - . , .... . , .- - - ....... .. . , . . .-;. . . , . ~.. , ~, . . .

. ~ . ... . . - . .- .. . . .. . . . -RCA 65,884 1~4~29Z
I storage register 286. Thus, the next sampled word will compare favorably with the stored word and will therefore be recorded.
However, if beam 24 impinges on tag 26 at such a time that the first logic one value received by decoder 56 is not the first active bit of the code word 270, an inaccurate sampling of the word would result; e.g. if the initial reflected reply is initiated on bit 2 of code word 270, the decoder would be activated by bit 3 of code word 270 and active bits 3-16, and off time bits 1 and 2 Of the code word would be sampled and subsequently stored in storage register 286. In view of the 16 bit offtime - of identification code word 270, however, the second sample taken by decoder 56 necessarily begins with the first active bit of the word, regardless of where in code word IS 270 the first sampling was initiated. The comparison of the subsequent sampling with the first will therefore be unfavorable and the accurate subsequent sampling will replace the inaccurate first in storage register 286. A third - sampling taken by decoder 56 will thereore favorably compare with the stored word and will be recorded by readout/recorder means 290.
The decoder, therefore, requires two consecutive identical receptions of the code modulation 270 to assure an accurate identification and recording or display or 2S such identification. Consequently, in order to ensure accurate identification in instances where beam 24 impinges on tag 26 at such a time that the first logic 1 value received by decoder 56 is not the first active bit of the code word 270, the bit rate of the identification code, i.e. the frequency of the timing means or clock in ,~ .

.. .. . - . : ~ .
.. ". . ~ : ~ ~ "

RCA 65,884 ~040Z9Z
1 tag 26, must be chosen so that a minimum of three reradiated replies will be generated during the time -interval that the tag is within the predetermined frequency beam 24. Systems have been implemented uiilizing a S 50,000 bit per second code, which is capable of accurate identification of tags passing through beam 24 at speeds up to 100 miles per hour.
Referring now to Figure 11, there is a schematic of a vehicle identification system embodying the present lo invention. Transmitter 460 and receiver 462 are situated in a station 464 located below ground level in the access to a toll road.
Transmitter 460 (similar to transmitter 10, Figure 1 previously described) continuously generates IS electro-magnetic energy at a predetermined frequency f, which is transmitted in an upward substantially vertical direction by transmitting antenna 466, which, in turn, is situated in an appropriate radome 467. The radiation pattern of the transmitted signal is generally indicated in Figure 11, as main beam 468, and first and second side lobes 470 and 472, respectively.
Vehicles having access to the system on the toll roat is assigned a tag ~26 Figure 1, etc.~ having a unique and individual identification code number. Such a tag

2~ 474 is shown suitably affixed to vehicle 476, for cooporation with the transmitter ant receiver. When ` Yehicle 476 passes over station 464, tag 474 is Illuminated by the main beam 468. Tag 474, as previously explained retrodirectively radiates 8 beam 478 of signals at a chosen harmonic of the predetermined frequency, pulse-modulated --:- . . .

. ' .
' ' . ' . ' . , ' ' , .

- RCA 65,884 ~04a292 1 in accordance with the identification code in the manner described above. Signals of the predetermined frequency are also reflected from tag 474 and vehicle 476, and are, illustratively, indicated as beam 484. Vehicles with no tag or with an inoperative tag therefore reflect, in the skin-radar type reflection sense, only signals at the predetermined frequency f.
Receiver 462 (of the type described above, e.g.
14 of Figure 1) is coupled to a receiving antenna 480, which is situated in a suitable radome 481. Antenna 480 is arranted to have a response pattern with a main lobe 482 in an upward substantially vertical direction and including first and second side lobes, 486 and 488.
As illustrated in Figure 11, by the overlapping of the second side lobe 472 of antenna 466 and the first side lobe 486 of antenna 480 owing to close proximity of the transmitter and receiver antenna, there may be a small but finite direct leakage between the transmitter 460 and receiver 462. Thus, antenna 480 receives a~small 2D leakage signal of predetermined frequency f, the retro-directive harmonic beam 478 and the skin-radar reflected signals 484 reflected from the passing vehicle 476.
The signals received by antenna 480 are passed to -a first detector 490 and in parallel therewith to a series 2~ combination of high pass filter 492 and second detector 494 within receiver 462.
Detector 490 generates an output signal which is representative of any modulation or change from steady state in the signals received by antenna 480. The leakage 3D signal is essentially a steady state constant value and ., .. ~ :, .. ' , .. . . . . ~
. . , . . ~ , , : . , .. ., , ,, . ~ . ~

: - :~ . :
,: -,, . : . : . :

RCA 65,884 1~40Z92 I can be monitored to establish that transmitter 460 is in proper operation. Detector 490 generates output signals different from steady state value only when the passage of a vehicle creates reflected (or radiated) signals, either of the predetermined base frequency (f) of the transmitter or at the chosen harmonic. High pass filter 492 effectively attenuates all signals not of the chosen harmonic frequency and the output signals of - second detector 494 are thus indicative of the identification code pulse-modulated signals from the tag.
The output signals of detector means 490 and 494 are respectively passed to receiver output terminals 496 and 498, and are therefrom communicated to a vehicle presence ~- indicator 500, and decoder 502 within a remote output means lS 504. The decoder translates the detected pulse modulation - code into a suitable recordable form, which is stored by recorder 506. The output signals of vehicle presence indicator 500 and decoder 502 are passed to suitable data processing means 508.
If passing vehicle 476 has no tag, or has an in~
operable tag, only signals of the predetermined base frequency f will be reflected. The reflected f frequency signals will cause the first detector 496 to generate an output signal and thereby actuate the vehicle presence 2S indicator but no identification code will be registered on the decoder. Data processing means 508 can, accordingly generate a warning to the proper authorities. Similarly, tats processing means 500 can generate a warning upon the pass~ge of a vehicle with a specified identification

3 number.

.
, ~ , .. . . . .. .. . ..

RCA 65,884 1 The recorder 506 is periodically read and bills or credits for pre-paid tickets can be sent to the owners of those vehicles recording as passing. Thus, a toll road can be effectively maintained without requiring the vehicles to reduce speed at tolling stations.
An alternative to the above described system is to establish the transmitting and receiving antennas in radomes situated in the side of a toll station and suitably affix the tag to the side of the vehicle. The alternative method may be of particular utility in converting previously established toll stations.
Similarly, mobile or hand held stations, may be established. An experimental vehicle identification system using a 50,000 bit/sec. code has been implemented and testet. The tag was suitably affixed to an automotive vehicle and a mobile station was established at road side. The system was tested and proven accurate at vehicle speeds up to and including 40 miles per hour. It has been calculated that such a system using the 50,000 bit/sec.
code is accurate for vehicles passing the station 464 at speeds up to lOO miles per hour.
The threshold device in an experimental unit was set to establish a signal to noise ratio between 3 ant 6 db. The transmitter radiated lS0 milliwatts of 2S power and utilized a 25 db. gain transmitting antenna.
The receiver similarly used a 25 db. gain receiving antenna, and used direct detection. The maximùm range - of the system, for the above noted parameters is found to be approximately lO ft.
The sensitivity of the implemented system can be . .

- . . : - . . ., ~- . , :. .

RCA 6S,884 ~40292 improved by a factor of 30 to 40 db. by utilizing a superhetrodyne configuration, i.e. a homodyne, rather than direct detection of the code modulations. Thus, for the same maximum range, smaller, lower gain transmitting and receiving antenni can be utilized.
Figure 12 is a pictorial illustration of a remotely actuated electronic lock embodying the present - invention. A transmitter 510 and a receiver 512 are suitably attached to or within a vehicle 514 or some other lockable enclosure. Transmitter antenna 516 is suitably arranged to illuminate the approach to the vehicle door 518 or other suitable entrance means. Similarly, transmit~
ting antenna 516 is suitably arranged to receive harmonically related signals reflected from the approach area. When lS a person 522 carrying a tag 524 with a specified preset identification code number approaches the vehicle door 518, a beam 526 of predetermined frequency f impinges on tag 524. Tag 524 responsively radiates a code-modulated harmonically related beam 528, which is received by receiving antenna 520.
Figure 12a is a schematic showing such a system.
With reference now to Figure 12~, it is seen that received modulated signals 528 from the approaching tag 524 are communicated from receiving antenna 520, 2S through a high pass filter 530, to a detector 532.
Detected code-modulation signals are therefrom passed to output means 534 comprising suitable decoder 536 and a suitable comparator 538. Decoder 536 is receptive of the detected code modulations and establishes the identification code number of approaching tag 524. Comparator 538 has . . . , . . . - . . . . ,, " . ....

RCA 65,884 ~04~)Z92 1 applied in parallel, over parallel line 540, the establish ed identification code number of approaching tag 524, and compares the established code number with a preset code number. Comparator 538 is operationally coupled over line 538 to a suitable servo-latching and/or locking means 542.
If the identification code number of the approach-ing tag is identical to that preset in comparator 538, comparator 538 generates an output signal over line 544 10 to activate servo-latching means 542 and open the vehicle door 518.
It is apparent from the foregoing description that the present invention provides a particularly advantageous electronic detection and identification lS system. It will be understood that the above description is of illustrative embodiments of the present invention and that the invention is not limited to the specific forms shown. Modifications may be made in the design and arrangement of the elements without departing from the spirit of the inventqon.
.

' . ~ . ' ' ' : :, , : : , , .. . . . , . , .:

,- . , . . . :-:

.. .. . . .. . .

Claims

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. A short range detecting and identification system, wherein: the system comprises a transmitter, a receiver, output processing means receptive of output signals from the receiver, and a tag to be borne past the transmitter and receiver; the transmitter comprises means for generating electromagnetic energy signals of a pre-determined frequency; the receiver comprises first detect-tion means for detecting from the tag a modulated signal which is harmonically related to the predetermined frequency signal, and for generating first output signals indicative of the modulation of the detected signals; the tag comprises:
(a) a harmonic radiator for deriving from the signals of the predetermined frequency received at the tag the harmonically related signals and for radiating those harmonically related signals in a direction toward the receiver, and (b) encoding means for modulating the derived harmonically related signals; where the encoding means includes control means operative for controlling the derivation and radiation of the harmonically related signals in accordance with a predetermined identification code; and the output processing means is responsive to the output from the first detection means for extracting information from the predetermined identification code; wherein there is further included: second detection means in the receiver operative in the presence of signals of the predetermined frequency which have been reflected during

Claim 1 continued.

the passage of the tag past the transmitter and the receiver but which are unmodulated by the tag encoding means for generating second output signals indicative of the receipt at the receiver of such reflected signals;
and the output processing means is further operative to indicate the occurrence of the second output signals from the second detection means independently of the operation of the first detection means.