CA1038049A - Gated ramp generator - Google Patents
Gated ramp generatorInfo
- Publication number
- CA1038049A CA1038049A CA234,769A CA234769A CA1038049A CA 1038049 A CA1038049 A CA 1038049A CA 234769 A CA234769 A CA 234769A CA 1038049 A CA1038049 A CA 1038049A
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- Prior art keywords
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- capacitor
- ramp voltage
- voltage
- currents
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- 239000003990 capacitor Substances 0.000 claims abstract description 40
- 230000004044 response Effects 0.000 claims description 3
- 230000008878 coupling Effects 0.000 claims 1
- 238000010168 coupling process Methods 0.000 claims 1
- 238000005859 coupling reaction Methods 0.000 claims 1
- 230000004075 alteration Effects 0.000 abstract description 7
- 238000007599 discharging Methods 0.000 description 3
- 238000006073 displacement reaction Methods 0.000 description 3
- 238000010894 electron beam technology Methods 0.000 description 3
- 230000006872 improvement Effects 0.000 description 2
- 230000000977 initiatory effect Effects 0.000 description 2
- 238000011084 recovery Methods 0.000 description 2
- 230000007704 transition Effects 0.000 description 2
- 101100384355 Mus musculus Ctnnbip1 gene Proteins 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000009738 saturating Methods 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
- 230000000007 visual effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K4/00—Generating pulses having essentially a finite slope or stepped portions
- H03K4/06—Generating pulses having essentially a finite slope or stepped portions having triangular shape
- H03K4/08—Generating pulses having essentially a finite slope or stepped portions having triangular shape having sawtooth shape
- H03K4/48—Generating pulses having essentially a finite slope or stepped portions having triangular shape having sawtooth shape using as active elements semiconductor devices
- H03K4/50—Generating pulses having essentially a finite slope or stepped portions having triangular shape having sawtooth shape using as active elements semiconductor devices in which a sawtooth voltage is produced across a capacitor
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Abstract
GATED RAMP GENERATOR
ABSTRACT OF THE DISCLOSURE
A precision ramp voltage generator is provided which exhibits exceptionally small start-up aberrations and simultaneously maintains baseline stability. The perturbations in the output are corrected by an increase or decrease in an error current developed via feedback means to charge or discharge a timing capacitor in the direction necessary to maintain the desired baseline, whereas start-up aberrations are minimized by effecting a very fast current switch to a timing element from a current source to a current sink of greater magnitude.
ABSTRACT OF THE DISCLOSURE
A precision ramp voltage generator is provided which exhibits exceptionally small start-up aberrations and simultaneously maintains baseline stability. The perturbations in the output are corrected by an increase or decrease in an error current developed via feedback means to charge or discharge a timing capacitor in the direction necessary to maintain the desired baseline, whereas start-up aberrations are minimized by effecting a very fast current switch to a timing element from a current source to a current sink of greater magnitude.
Description
Q`~
BACKGROUND OF INVENTION
In an apparatus such as an oscilloscope or related equipment for precision testing or measurement of an electrical phenomenon, the phenomenon is ordinarily displayed as a visual plot of the instantaneous voltage o~ a wave as a function of time. In mos-t cases, the time ref-erence is supplied by the apparatus itself. For example, a sweep generator develops a sawtooth, or ramp, voltage which after being processed in a horizontal amplifier is applied to the horizontal deflection plates of the cathode-ray-tube (CRT), producing the horizontal sweep. When the voltage required to produce a linear unit of beam displace-ment (i.e., deflection factor) and the ramp voltacJe rate of rise are known ~uantities, the horizontal dimensions of any waveform traced on the CRT face plate can be conver-ted to units of time.
I~ precise time measurments are to be made, it is essential that equal increments of horizontal distance represent equal increments of time. If the displacement of the electron beam is at all times proportional to the voltage applied to the horizontal deflection plates, it must follow that the sweep voltage change at a linear rate. Additionally, the electron beam must be returned to a quiescent position else, apparent positional shifts of the displacement of the electron beam occurs.
Thus, two important re~uirements for precision ramp generators are the stability of the baseline voltage prior to initiation of the ramp waveform and the lack of aberrations following initiation of the ramp.
Basically, all ramp generators for generating xamp voltages generate the ramp voltage by charging and discharging ~., Q~
of a capacitor by a charging current. Previous schemes for baseline stabilization have limited the ~harging current to a particular value thus requiring longer times for recovery from negative transients such as discharge overshoot. Start-up abberations, due to the time interval to effectively switch current into the timing capacitor have been reduced by other schemes such as overdriving an emitter coupled amplifier however, such schemes also produce aberrations caused by stray and device capacitances.
The present invention overcomes the limitations of the prior art ramp or sawtooth voltage generators in that simultaneouslv, ba~eline ~kabilization and sta~t-up aberrations are maintained at a constant quiescent position ; and at a linear rate, respectively.
In the most basic essence, the present invention provides a ramp voltage generator which comprises a timing element or capacitor into which a timing current and an error current are alternately driven~to charge and discharge the element to produce the ramp voltage. A current sink for sinking the timing current and the error current is provided via an emitter coupled pair operated as a gate in accordance with a gating signal. A pair of bipolar or asymmetrical conducting devices such as diodes are included with the gating components to steer the error current and provide an additional current path.
It is thereore an object o the present invention to provide an improved ramp voltage generator that can eliminate the limitations described above.
~3~
It is anotller obj t of the present invcntion to provide an improved ramp voltage generator that can simultaneously eliminate the limitations described above.
In accordance with one aspect of the present invention there is provided a gated ramp voltage generator, comprising:
a current source for providing a first current;
capacitor means connected to said current source for developing the ramp voltage thereacross in response to current applied thereto;
10comparator means having a first input coupled to receive the ramp voltage and a second input connected to a reference voltage source, said comparator means producing a second current at the output thereof which is proportional to the diEference in amplitude botwoon tho ram~ voltagc ancl said reference voltage; and current steering means coupled to both said capacitor means and said comparator means for steering to said capacitor means said first and said second currents to produce the ramp voltage, said current steering means including means for gating said first and said second currents to cause the ramp voltage developed to be a gated ramp voltage.
The foregoing and numerous other objects, advantages, and inherent functions of the present invention will become apparent as the same is more fully understood from the following description, which describes the preEerred embodiment of the present invention; it is to be understood, however, that this embodiment is not lntended to be limiting nor exhausting of the invention, but is given for purposes of illustration in order that others skilled in the art may :Eully understand the invention and principles thereof and the manner of applying it in practical use so that they may modify it in various ~ _ 3 _ `A
3~
forms, each as may best be suited to the conditions of the particular use.
DESCRIPTION OF DRAWINGS
In the drawings:
Figure l is one embodiment of the prior art for generating a linear ramp voltage wave;
Figure 2 shows the waveforms associated with the embodiment of the prior art in accordance with Figure l;
Figure 3 is the preferred embodiment of the ramp voltage generator according to the present invention; and Figure 4 shows the waveforms associated with the embodiment of the present invention in accordance with ~igure 3.
DETAILeD D~SCRIPTION 0~ T~l~'. INVe.NTION
:
Ref~rring now to the clraw:in~s and in particular Figure l, there is shown a particular ramp voltage generator according to the prior art for eliminating some of the limitations that have previously been discussed; such particular embodiment being the invention of U.S. Patent 3,723,762 by N. NaKaya. The ramp voltage generator comprises a capacitor 14 and a switching diode 12. Diode 12 is used to charge and discharge capacitor 14 so as to utilize the terminal voltage across the capacitor as the ramp voltage ; waveform. A signal source 10 for producing a switching signal P, has one terminal grounded and the other terminal connected to the cathode electrode of switching diode 12, the anode electrode thereof being connectecl to the junction 13 between the output of a source of charging current 15 and one terminal of capacitor 14. The polarity of source 15 is selected such that current Il flows into capacitor 14 via juncture 13. The other terminal of capacitor 14 is grounded and the juncture 13 is connected to an output terminal 16. As is well known, - 3a -in the absence of the switching signal P from source 10, current Il flows from source 15 via the diode 12 in~o source 10. With switching signal P, the switching diode 12 is reversed biased allowing current Il to charge the capacitor 14. As is well known, an exponential reverse current il(t), due to stored charge, now flows into the juncture 13 so that the capacitor also charges in response thereto. The effect of the additional exponential current produces the ramp voltage waveform 19 as shown in Figure 2 along with the switching signal P. As can be discerned from Figure 2, waveform 19 is not linear and contains start-up aberrations.
To overcome these limitations, a series circuit :including a source of constant voltage 11 and a seconcl diodo 17 is connected in parallel with capacitor 1~. 'I'he polarity of the second diode 17 and the positive terminal of constant voltage source 11 are connected together so that diode 17 is rendered conductive in the absence of the switching signal P
from signal source 10. If both diodes have similar characteristics, an additional exponential current i2(t) will be produced which will flow in the direction shown when the switching pulse P
is applied. As a result, the exponential currents effectively cancel each o~her and the ramp voltage waveform 18 is produced.
However, start-up aberrations, uncertainties due to temperature, diode mismatch, etc. still remain.
In U.S. Patent 3,621,282 by C. H. Haas there is described a sawtooth generator including a bistable comparator to compare the ramp voltage and a reference voltage for discharging a capacitor across which the ramp voltage is being produced to provide a stabilized ramp. ~lowever, the output of such a circuit will not return to a precise reference in that the output of the comparator can shift substantially due to A
~ ~3~4~
paramctcrs of the comparator.
In the prefcrred cmbodiment of the present invention detailed in Figure 3, there is sllown a gated ramp voltage generator to further improve the limitations of the prior art previously discussed as well as simultaneously maintaining the baseline at a reerence level. The gated ramp voltage generator comprises a capacitor 50 which is charged and discharged so as to provide the ramp voltage waveform. A
timing current source 52 is connected between a source of suitable potential (~) and one terminal of the capacitor 50 such tllat a current ICT 10ws into the capacitor 50; the other teminal o the capacitor is grounded. Curront lnto or out of capacitor 50 pro~uces a terminal voltagc Vc,r thereacross wh.ich is supplied to an output terminal 5~ by way of an ampliier 56 which has its non-inverting input also connected to the ungrounded terminal of capacitor 50 and its inverting input connected to its single output terminal and the output terminal 54; such amplifier thus connected as a voltage follower amplifier. As such, the output ramp voltage waveform at the output terminal 54 is defined conventionally by ddt = CT~ where ddt is the first derivative or linear ramp of the timing current IT charging the capacitor 50 ~CT in the above formula corresponds to the capacitor 50).
Connected to output terminal 54 is a next amplifier 58 which compares the output ramp voltage waveform Vo applied to its inverting input and a re~erence voltage, VREFI appliod to its non-inverting input during quiescent time. It should be noted that the voltage VREF is usually of the magnitude equal to the magnitude o the level desired for the baseline of the ramp voltage which is typically zero volts. The single output of amplifier 58 is therefore an error current controlled ~3~
by thc differcncc bctwccn the output ramp voltage Vo and the reference voltage, VREF. Connected between the ungrounded terminal of capacitor S0 and the output o amplifier 58 is an assymetrical conducting device or unipolar device such as a diode 60 and poled so as to allow current ID60 to flow in the direction shown when biased in the forward direction.
A pair of transistors 62, 64 have their emitters connected together, which are connected to a source of suitable potential (shown as - in the drawing) via a series connected current sink 66 for sinking the current Is in the direction sllown. The collectors of the transistors 62, 64 are connected to the anode and cathode of the diode 60 respectively, and the bases thcreof are connectcd to a gate source VGATE and a voltago source Vs. The gcnerator circuit is completed by a diode 68 having its cathode connected to the collector of transistor 62 and having its anode connected to ground.
Referring now to Figure 4 which details the waveforms associated with the present invention, there is shown a waveform 80 which represents the gate source VGATE. When VGATE is at least several tenths oE a volt more negative than the voltage source Vs (82 on drawing), transistor 64 conducts all of the current Is. (Transistors 62, 64 are connected in the well known differential manner and no discussion will be given as to their operation.) Since transistor 64 is conducting all of current Is, the voltage VcT across capacitor 50, hence Vo at the output terminal 54 moves under the influence of ICT where~ using Kirchoff current law is defined by:
ICT = IT ~ ID60 - Is where IT, ID60 and Is are as previously defined. By selecting Is greater than IT (i.e. J Is > IT), ID60 will be controlled by the difference between Vo and V F until ICT = 0. When ICT = O, Vo is approximatelY equal to VREF and no net current is available to charge or discharge capacitor 50. Vo is thus established at a potential close to VREF. It now becomes evident that under the above described ERROR ID60 = ID68 ~ IT- PerturbationS in Vo are corrected by an increase or decrease in IERRoR causing ICT to assume a non-zero value which charges or discharges capacitor 50 in the direction necessary to restore the correct baseline. This technique represents a significant improvement over the prior art because capacitor 50 may be discharged and charged by a current many times greater than the current IT
rather than limited by IT which would require longcr times for recovery from negative transients etc., such as dlschargc overshoot.
At a time 'rO, to gate the ramp 86 on, gate source VGATE
is switched from a potential several tenths of a volt more negative than voltage source Vs to a potential several tenths of a volt more positive than the voltage source Vs. During this transition period Is = IC62 + IC64' D60 ERROR G62 nd Recalling once again that prior to transition, IERRoR = Is - IT, it must follow that ICT = O. As such, no net current is charging or discharging capacitor 50. When a reduction of current IC6~ is reduced to a point where IC64 = IT, then ID60 = 0. Conduction through diode 60 ceases and changeS in IERRoR will no longer affect ICT. Diode 68 now conducts preventing transistor 62 from saturating. As a result, Ic~, = IT - IC64 and VcT, hence Vo begin to rise. As current IC64 is dropping to zero the ramp voltage rises at a slower rate than ideal for the interval of time when I~ > IC6~ > O.
By selecting Is much greater than IT (i.e., Is >> IT) such interval will only be a fraction of the actual risetime of VGATE thus effecting a very fast and "clean" current switch for capacitor 50. Thus, the present invention is an improvement over prior art in which the time interval taken to effectively switch current into the timing capacitor is essentially limited by the gating waveform risetime; or ~he loop bandwidth, for the particular case of operational integrator ramp generator schemes such as "Miller Integrators".
While there has been shown and described the preferrecd embodiment of the present invention, it will now be apparent to those skilled in the art that many changes and mocl:L~icat:lons may be made wlthout dopartin~ thereerom in its broa(lor aspects.
Therefore,the appended claims are intended to cover all such modifications and changes as fall within the true spirit and scope of this invention.
BACKGROUND OF INVENTION
In an apparatus such as an oscilloscope or related equipment for precision testing or measurement of an electrical phenomenon, the phenomenon is ordinarily displayed as a visual plot of the instantaneous voltage o~ a wave as a function of time. In mos-t cases, the time ref-erence is supplied by the apparatus itself. For example, a sweep generator develops a sawtooth, or ramp, voltage which after being processed in a horizontal amplifier is applied to the horizontal deflection plates of the cathode-ray-tube (CRT), producing the horizontal sweep. When the voltage required to produce a linear unit of beam displace-ment (i.e., deflection factor) and the ramp voltacJe rate of rise are known ~uantities, the horizontal dimensions of any waveform traced on the CRT face plate can be conver-ted to units of time.
I~ precise time measurments are to be made, it is essential that equal increments of horizontal distance represent equal increments of time. If the displacement of the electron beam is at all times proportional to the voltage applied to the horizontal deflection plates, it must follow that the sweep voltage change at a linear rate. Additionally, the electron beam must be returned to a quiescent position else, apparent positional shifts of the displacement of the electron beam occurs.
Thus, two important re~uirements for precision ramp generators are the stability of the baseline voltage prior to initiation of the ramp waveform and the lack of aberrations following initiation of the ramp.
Basically, all ramp generators for generating xamp voltages generate the ramp voltage by charging and discharging ~., Q~
of a capacitor by a charging current. Previous schemes for baseline stabilization have limited the ~harging current to a particular value thus requiring longer times for recovery from negative transients such as discharge overshoot. Start-up abberations, due to the time interval to effectively switch current into the timing capacitor have been reduced by other schemes such as overdriving an emitter coupled amplifier however, such schemes also produce aberrations caused by stray and device capacitances.
The present invention overcomes the limitations of the prior art ramp or sawtooth voltage generators in that simultaneouslv, ba~eline ~kabilization and sta~t-up aberrations are maintained at a constant quiescent position ; and at a linear rate, respectively.
In the most basic essence, the present invention provides a ramp voltage generator which comprises a timing element or capacitor into which a timing current and an error current are alternately driven~to charge and discharge the element to produce the ramp voltage. A current sink for sinking the timing current and the error current is provided via an emitter coupled pair operated as a gate in accordance with a gating signal. A pair of bipolar or asymmetrical conducting devices such as diodes are included with the gating components to steer the error current and provide an additional current path.
It is thereore an object o the present invention to provide an improved ramp voltage generator that can eliminate the limitations described above.
~3~
It is anotller obj t of the present invcntion to provide an improved ramp voltage generator that can simultaneously eliminate the limitations described above.
In accordance with one aspect of the present invention there is provided a gated ramp voltage generator, comprising:
a current source for providing a first current;
capacitor means connected to said current source for developing the ramp voltage thereacross in response to current applied thereto;
10comparator means having a first input coupled to receive the ramp voltage and a second input connected to a reference voltage source, said comparator means producing a second current at the output thereof which is proportional to the diEference in amplitude botwoon tho ram~ voltagc ancl said reference voltage; and current steering means coupled to both said capacitor means and said comparator means for steering to said capacitor means said first and said second currents to produce the ramp voltage, said current steering means including means for gating said first and said second currents to cause the ramp voltage developed to be a gated ramp voltage.
The foregoing and numerous other objects, advantages, and inherent functions of the present invention will become apparent as the same is more fully understood from the following description, which describes the preEerred embodiment of the present invention; it is to be understood, however, that this embodiment is not lntended to be limiting nor exhausting of the invention, but is given for purposes of illustration in order that others skilled in the art may :Eully understand the invention and principles thereof and the manner of applying it in practical use so that they may modify it in various ~ _ 3 _ `A
3~
forms, each as may best be suited to the conditions of the particular use.
DESCRIPTION OF DRAWINGS
In the drawings:
Figure l is one embodiment of the prior art for generating a linear ramp voltage wave;
Figure 2 shows the waveforms associated with the embodiment of the prior art in accordance with Figure l;
Figure 3 is the preferred embodiment of the ramp voltage generator according to the present invention; and Figure 4 shows the waveforms associated with the embodiment of the present invention in accordance with ~igure 3.
DETAILeD D~SCRIPTION 0~ T~l~'. INVe.NTION
:
Ref~rring now to the clraw:in~s and in particular Figure l, there is shown a particular ramp voltage generator according to the prior art for eliminating some of the limitations that have previously been discussed; such particular embodiment being the invention of U.S. Patent 3,723,762 by N. NaKaya. The ramp voltage generator comprises a capacitor 14 and a switching diode 12. Diode 12 is used to charge and discharge capacitor 14 so as to utilize the terminal voltage across the capacitor as the ramp voltage ; waveform. A signal source 10 for producing a switching signal P, has one terminal grounded and the other terminal connected to the cathode electrode of switching diode 12, the anode electrode thereof being connectecl to the junction 13 between the output of a source of charging current 15 and one terminal of capacitor 14. The polarity of source 15 is selected such that current Il flows into capacitor 14 via juncture 13. The other terminal of capacitor 14 is grounded and the juncture 13 is connected to an output terminal 16. As is well known, - 3a -in the absence of the switching signal P from source 10, current Il flows from source 15 via the diode 12 in~o source 10. With switching signal P, the switching diode 12 is reversed biased allowing current Il to charge the capacitor 14. As is well known, an exponential reverse current il(t), due to stored charge, now flows into the juncture 13 so that the capacitor also charges in response thereto. The effect of the additional exponential current produces the ramp voltage waveform 19 as shown in Figure 2 along with the switching signal P. As can be discerned from Figure 2, waveform 19 is not linear and contains start-up aberrations.
To overcome these limitations, a series circuit :including a source of constant voltage 11 and a seconcl diodo 17 is connected in parallel with capacitor 1~. 'I'he polarity of the second diode 17 and the positive terminal of constant voltage source 11 are connected together so that diode 17 is rendered conductive in the absence of the switching signal P
from signal source 10. If both diodes have similar characteristics, an additional exponential current i2(t) will be produced which will flow in the direction shown when the switching pulse P
is applied. As a result, the exponential currents effectively cancel each o~her and the ramp voltage waveform 18 is produced.
However, start-up aberrations, uncertainties due to temperature, diode mismatch, etc. still remain.
In U.S. Patent 3,621,282 by C. H. Haas there is described a sawtooth generator including a bistable comparator to compare the ramp voltage and a reference voltage for discharging a capacitor across which the ramp voltage is being produced to provide a stabilized ramp. ~lowever, the output of such a circuit will not return to a precise reference in that the output of the comparator can shift substantially due to A
~ ~3~4~
paramctcrs of the comparator.
In the prefcrred cmbodiment of the present invention detailed in Figure 3, there is sllown a gated ramp voltage generator to further improve the limitations of the prior art previously discussed as well as simultaneously maintaining the baseline at a reerence level. The gated ramp voltage generator comprises a capacitor 50 which is charged and discharged so as to provide the ramp voltage waveform. A
timing current source 52 is connected between a source of suitable potential (~) and one terminal of the capacitor 50 such tllat a current ICT 10ws into the capacitor 50; the other teminal o the capacitor is grounded. Curront lnto or out of capacitor 50 pro~uces a terminal voltagc Vc,r thereacross wh.ich is supplied to an output terminal 5~ by way of an ampliier 56 which has its non-inverting input also connected to the ungrounded terminal of capacitor 50 and its inverting input connected to its single output terminal and the output terminal 54; such amplifier thus connected as a voltage follower amplifier. As such, the output ramp voltage waveform at the output terminal 54 is defined conventionally by ddt = CT~ where ddt is the first derivative or linear ramp of the timing current IT charging the capacitor 50 ~CT in the above formula corresponds to the capacitor 50).
Connected to output terminal 54 is a next amplifier 58 which compares the output ramp voltage waveform Vo applied to its inverting input and a re~erence voltage, VREFI appliod to its non-inverting input during quiescent time. It should be noted that the voltage VREF is usually of the magnitude equal to the magnitude o the level desired for the baseline of the ramp voltage which is typically zero volts. The single output of amplifier 58 is therefore an error current controlled ~3~
by thc differcncc bctwccn the output ramp voltage Vo and the reference voltage, VREF. Connected between the ungrounded terminal of capacitor S0 and the output o amplifier 58 is an assymetrical conducting device or unipolar device such as a diode 60 and poled so as to allow current ID60 to flow in the direction shown when biased in the forward direction.
A pair of transistors 62, 64 have their emitters connected together, which are connected to a source of suitable potential (shown as - in the drawing) via a series connected current sink 66 for sinking the current Is in the direction sllown. The collectors of the transistors 62, 64 are connected to the anode and cathode of the diode 60 respectively, and the bases thcreof are connectcd to a gate source VGATE and a voltago source Vs. The gcnerator circuit is completed by a diode 68 having its cathode connected to the collector of transistor 62 and having its anode connected to ground.
Referring now to Figure 4 which details the waveforms associated with the present invention, there is shown a waveform 80 which represents the gate source VGATE. When VGATE is at least several tenths oE a volt more negative than the voltage source Vs (82 on drawing), transistor 64 conducts all of the current Is. (Transistors 62, 64 are connected in the well known differential manner and no discussion will be given as to their operation.) Since transistor 64 is conducting all of current Is, the voltage VcT across capacitor 50, hence Vo at the output terminal 54 moves under the influence of ICT where~ using Kirchoff current law is defined by:
ICT = IT ~ ID60 - Is where IT, ID60 and Is are as previously defined. By selecting Is greater than IT (i.e. J Is > IT), ID60 will be controlled by the difference between Vo and V F until ICT = 0. When ICT = O, Vo is approximatelY equal to VREF and no net current is available to charge or discharge capacitor 50. Vo is thus established at a potential close to VREF. It now becomes evident that under the above described ERROR ID60 = ID68 ~ IT- PerturbationS in Vo are corrected by an increase or decrease in IERRoR causing ICT to assume a non-zero value which charges or discharges capacitor 50 in the direction necessary to restore the correct baseline. This technique represents a significant improvement over the prior art because capacitor 50 may be discharged and charged by a current many times greater than the current IT
rather than limited by IT which would require longcr times for recovery from negative transients etc., such as dlschargc overshoot.
At a time 'rO, to gate the ramp 86 on, gate source VGATE
is switched from a potential several tenths of a volt more negative than voltage source Vs to a potential several tenths of a volt more positive than the voltage source Vs. During this transition period Is = IC62 + IC64' D60 ERROR G62 nd Recalling once again that prior to transition, IERRoR = Is - IT, it must follow that ICT = O. As such, no net current is charging or discharging capacitor 50. When a reduction of current IC6~ is reduced to a point where IC64 = IT, then ID60 = 0. Conduction through diode 60 ceases and changeS in IERRoR will no longer affect ICT. Diode 68 now conducts preventing transistor 62 from saturating. As a result, Ic~, = IT - IC64 and VcT, hence Vo begin to rise. As current IC64 is dropping to zero the ramp voltage rises at a slower rate than ideal for the interval of time when I~ > IC6~ > O.
By selecting Is much greater than IT (i.e., Is >> IT) such interval will only be a fraction of the actual risetime of VGATE thus effecting a very fast and "clean" current switch for capacitor 50. Thus, the present invention is an improvement over prior art in which the time interval taken to effectively switch current into the timing capacitor is essentially limited by the gating waveform risetime; or ~he loop bandwidth, for the particular case of operational integrator ramp generator schemes such as "Miller Integrators".
While there has been shown and described the preferrecd embodiment of the present invention, it will now be apparent to those skilled in the art that many changes and mocl:L~icat:lons may be made wlthout dopartin~ thereerom in its broa(lor aspects.
Therefore,the appended claims are intended to cover all such modifications and changes as fall within the true spirit and scope of this invention.
Claims (5)
1. A gated ramp voltage generator, comprising:
a current source for providing a first current;
capacitor means connected to said current source for developing the ramp voltage thereacross in response to current applied thereto;
comparator means having a first input coupled to receive the ramp voltage and a second input connected to a reference voltage source, said comparator means producing a second current at the output thereof which is proportional to the difference in amplitude between the ramp voltage and said reference voltage; and current steering means coupled to both said capacitor means and said comparator means for steering to said capacitor means said first and said second currents to produce the ramp voltage, said current steering means including means for gating said first and said second currents to cause the ramp voltage developed to be a gated ramp voltage.
a current source for providing a first current;
capacitor means connected to said current source for developing the ramp voltage thereacross in response to current applied thereto;
comparator means having a first input coupled to receive the ramp voltage and a second input connected to a reference voltage source, said comparator means producing a second current at the output thereof which is proportional to the difference in amplitude between the ramp voltage and said reference voltage; and current steering means coupled to both said capacitor means and said comparator means for steering to said capacitor means said first and said second currents to produce the ramp voltage, said current steering means including means for gating said first and said second currents to cause the ramp voltage developed to be a gated ramp voltage.
2. The generator according to claim 1 further comprising a voltage follower amplifier means disposed between said first input and said capacitor for coupling the ramp voltage to said comparator means.
3. The generator according to claim 1 wherein said second current maintains the base line level of the ramp voltage.
4. The generator according to claim 1 wherein said current steering means including means for gating further comprises:
current sink means for sinking substantially more current than both said first and said second currents;
differential amplifier means including first and second transistors having their emitters coupled to said current sink means for selectively steering both said first and said second currents to said current sink means;
unipolar device means coupled between the collectors of said first and said second transistors and also being directly coupled between said capacitor means and said output of said comparator means for selectively steering both said first and said second currents to said capacitor means; and control means for controlling the bases of said transistors to gate said first and said second currents to said capacitor means.
current sink means for sinking substantially more current than both said first and said second currents;
differential amplifier means including first and second transistors having their emitters coupled to said current sink means for selectively steering both said first and said second currents to said current sink means;
unipolar device means coupled between the collectors of said first and said second transistors and also being directly coupled between said capacitor means and said output of said comparator means for selectively steering both said first and said second currents to said capacitor means; and control means for controlling the bases of said transistors to gate said first and said second currents to said capacitor means.
5. The generator according to claim 4 further comprising an additional unipolar device means coupled to one of said collectors for preventing saturation thereof.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US51263374A | 1974-10-07 | 1974-10-07 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1038049A true CA1038049A (en) | 1978-09-05 |
Family
ID=24039914
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA234,769A Expired CA1038049A (en) | 1974-10-07 | 1975-09-04 | Gated ramp generator |
Country Status (6)
| Country | Link |
|---|---|
| JP (1) | JPS5164357A (en) |
| CA (1) | CA1038049A (en) |
| DE (1) | DE2543777B2 (en) |
| FR (1) | FR2287808A1 (en) |
| GB (1) | GB1516200A (en) |
| NL (1) | NL168670C (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2493084A1 (en) * | 1980-10-28 | 1982-04-30 | Thomson Brandt | VERTICAL AND / OR HORIZONTAL SCANNING DEVICE AND TELEVISION RECEIVER COMPRISING SUCH A DEVICE |
| GB8414313D0 (en) * | 1984-06-05 | 1984-07-11 | Motorola Inc | Timebase circuit |
| NL9001856A (en) * | 1990-08-23 | 1992-03-16 | Philips Nv | SAW TOOTH GENERATOR AND OSCILLOSCOPE WITH SUCH SAW TOOTH GENERATOR. |
| GB9403605D0 (en) * | 1994-02-25 | 1994-04-13 | Texas Instruments Ltd | Method and circuit for reducing transient currents |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR1393679A (en) * | 1964-03-17 | 1965-03-26 | Tektronix Inc | Ramp-shaped signal generator circuit |
| FR1582631A (en) * | 1968-08-14 | 1969-10-03 | ||
| JPS498446B1 (en) * | 1970-05-07 | 1974-02-26 |
-
1975
- 1975-08-27 NL NL7510114A patent/NL168670C/en not_active IP Right Cessation
- 1975-08-27 GB GB3532675A patent/GB1516200A/en not_active Expired
- 1975-09-04 CA CA234,769A patent/CA1038049A/en not_active Expired
- 1975-10-01 DE DE19752543777 patent/DE2543777B2/en active Granted
- 1975-10-06 FR FR7531206A patent/FR2287808A1/en active Granted
- 1975-10-06 JP JP12054775A patent/JPS5164357A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| NL168670B (en) | 1981-11-16 |
| FR2287808A1 (en) | 1976-05-07 |
| DE2543777A1 (en) | 1976-04-08 |
| GB1516200A (en) | 1978-06-28 |
| DE2543777B2 (en) | 1978-07-13 |
| DE2543777C3 (en) | 1979-03-22 |
| FR2287808B1 (en) | 1979-10-12 |
| NL168670C (en) | 1982-04-16 |
| JPS5535012B2 (en) | 1980-09-11 |
| JPS5164357A (en) | 1976-06-03 |
| NL7510114A (en) | 1976-04-09 |
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