CA1017875A - Reduction of dielectric isolation capacitance coupling - Google Patents

Reduction of dielectric isolation capacitance coupling

Info

Publication number
CA1017875A
CA1017875A CA212,875A CA212875A CA1017875A CA 1017875 A CA1017875 A CA 1017875A CA 212875 A CA212875 A CA 212875A CA 1017875 A CA1017875 A CA 1017875A
Authority
CA
Canada
Prior art keywords
reduction
dielectric isolation
capacitance coupling
isolation capacitance
coupling
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
CA212,875A
Other versions
CA212875S (en
Inventor
Ichiro Ohhinata
Masaaki Kusano
Shinzi Okuhara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP12275973A external-priority patent/JPS5615141B2/ja
Priority claimed from JP12276073A external-priority patent/JPS5615574B2/ja
Priority claimed from JP2626974A external-priority patent/JPS50120781A/ja
Priority claimed from JP8377674U external-priority patent/JPS5113255U/ja
Priority claimed from JP1974088378U external-priority patent/JPS5117461U/ja
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Application granted granted Critical
Publication of CA1017875A publication Critical patent/CA1017875A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76297—Dielectric isolation using EPIC techniques, i.e. epitaxial passivated integrated circuit
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73257—Bump and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1301—Thyristor

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Element Separation (AREA)
  • Semiconductor Integrated Circuits (AREA)
CA212,875A 1973-11-02 1974-11-01 Reduction of dielectric isolation capacitance coupling Expired CA1017875A (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
JP12275973A JPS5615141B2 (en) 1973-11-02 1973-11-02
JP12276073A JPS5615574B2 (en) 1973-11-02 1973-11-02
JP2626974A JPS50120781A (en) 1974-03-08 1974-03-08
JP8377674U JPS5113255U (en) 1974-07-17 1974-07-17
JP1974088378U JPS5117461U (en) 1974-07-26 1974-07-26

Publications (1)

Publication Number Publication Date
CA1017875A true CA1017875A (en) 1977-09-20

Family

ID=27520824

Family Applications (1)

Application Number Title Priority Date Filing Date
CA212,875A Expired CA1017875A (en) 1973-11-02 1974-11-01 Reduction of dielectric isolation capacitance coupling

Country Status (2)

Country Link
CA (1) CA1017875A (en)
DE (1) DE2451861A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6104078A (en) * 1994-03-09 2000-08-15 Denso Corporation Design for a semiconductor device having elements isolated by insulating regions

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5846860B2 (en) * 1977-12-23 1983-10-19 株式会社日立製作所 semiconductor crosspoint switch
US4232328A (en) * 1978-12-20 1980-11-04 Bell Telephone Laboratories, Incorporated Dielectrically-isolated integrated circuit complementary transistors for high voltage use
KR850004178A (en) * 1983-11-30 1985-07-01 야마모도 다꾸마 Method of manufacturing dielectric separated integrated circuit device
DE3905149A1 (en) * 1989-02-20 1990-08-30 Fraunhofer Ges Forschung POWER CIRCUIT WITH AN INTEGRATED CMOS OR BIPOLAR CIRCUIT AND METHOD FOR PRODUCING AN INTEGRATED CIRCUIT
DE4127925C2 (en) * 1990-02-27 1994-01-13 Fraunhofer Ges Forschung Process for producing an isolated, single-crystalline silicon island
DE4006158A1 (en) * 1990-02-27 1991-09-12 Fraunhofer Ges Forschung METHOD FOR PRODUCING AN INSULATED, SINGLE-CRYSTAL SILICON ISLAND
DE4042334C2 (en) * 1990-02-27 1993-11-18 Fraunhofer Ges Forschung Process for producing an isolated, single-crystalline silicon island
JPH06151573A (en) * 1992-11-06 1994-05-31 Hitachi Ltd Semiconductor integrated circuit device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6104078A (en) * 1994-03-09 2000-08-15 Denso Corporation Design for a semiconductor device having elements isolated by insulating regions

Also Published As

Publication number Publication date
DE2451861A1 (en) 1975-05-15

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