CA1015067A - Dynamically double ordered shift register memory - Google Patents

Dynamically double ordered shift register memory

Info

Publication number
CA1015067A
CA1015067A CA182,969A CA182969A CA1015067A CA 1015067 A CA1015067 A CA 1015067A CA 182969 A CA182969 A CA 182969A CA 1015067 A CA1015067 A CA 1015067A
Authority
CA
Canada
Prior art keywords
shift register
register memory
dynamically
ordered shift
double ordered
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
CA182,969A
Other languages
English (en)
Other versions
CA182969S (en
Inventor
David T. Brown
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of CA1015067A publication Critical patent/CA1015067A/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/76—Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data
    • G06F7/78—Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data for changing the order of data flow, e.g. matrix transposition or LIFO buffers; Overflow or underflow handling therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/02—Digital stores in which the information is moved stepwise, e.g. shift registers using magnetic elements
    • G11C19/08—Digital stores in which the information is moved stepwise, e.g. shift registers using magnetic elements using thin films in plane structure
    • G11C19/0875—Organisation of a plurality of magnetic shift registers

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Shift Register Type Memory (AREA)
  • Memory System (AREA)
  • Executing Machine-Instructions (AREA)
CA182,969A 1972-11-16 1973-10-09 Dynamically double ordered shift register memory Expired CA1015067A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US30725872A 1972-11-16 1972-11-16

Publications (1)

Publication Number Publication Date
CA1015067A true CA1015067A (en) 1977-08-02

Family

ID=23188926

Family Applications (1)

Application Number Title Priority Date Filing Date
CA182,969A Expired CA1015067A (en) 1972-11-16 1973-10-09 Dynamically double ordered shift register memory

Country Status (7)

Country Link
US (1) US3797002A (US07943777-20110517-C00090.png)
JP (1) JPS5246781B2 (US07943777-20110517-C00090.png)
CA (1) CA1015067A (US07943777-20110517-C00090.png)
DE (1) DE2356260C3 (US07943777-20110517-C00090.png)
FR (1) FR2207610A5 (US07943777-20110517-C00090.png)
GB (1) GB1398204A (US07943777-20110517-C00090.png)
IT (1) IT1001548B (US07943777-20110517-C00090.png)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4523290A (en) * 1974-07-22 1985-06-11 Hyatt Gilbert P Data processor architecture
US5339275A (en) * 1970-12-28 1994-08-16 Hyatt Gilbert P Analog memory system
US4445189A (en) * 1978-03-23 1984-04-24 Hyatt Gilbert P Analog memory for storing digital information
US5619445A (en) * 1970-12-28 1997-04-08 Hyatt; Gilbert P. Analog memory system having a frequency domain transform processor
US5615142A (en) * 1970-12-28 1997-03-25 Hyatt; Gilbert P. Analog memory system storing and communicating frequency domain information
US5566103A (en) * 1970-12-28 1996-10-15 Hyatt; Gilbert P. Optical system having an analog image memory, an analog refresh circuit, and analog converters
US3913077A (en) * 1974-04-17 1975-10-14 Hughes Aircraft Co Serial-parallel-serial ccd memory with interlaced storage
US3914748A (en) * 1974-04-29 1975-10-21 Texas Instruments Inc Isolation-element CCD serial-parallel-serial analog memory
US3950732A (en) * 1974-05-14 1976-04-13 International Business Machines Corporation Single technology text editing system
US3971003A (en) * 1974-11-18 1976-07-20 Rca Corporation Charge coupled device imager
US3967254A (en) * 1974-11-18 1976-06-29 Rca Corporation Charge transfer memory
US3953837A (en) * 1974-11-27 1976-04-27 Texas Instruments Incorporated Dual serial-parallel-serial analog memory
US4007446A (en) * 1975-06-30 1977-02-08 Honeywell Information Systems, Inc. Multiphase series-parallel-series charge-coupled device registers
GB1525045A (en) * 1976-02-11 1978-09-20 Nat Res Dev Computer stores
US4052704A (en) * 1976-12-20 1977-10-04 International Business Machines Corporation Apparatus for reordering the sequence of data stored in a serial memory
JPS6242363Y2 (US07943777-20110517-C00090.png) * 1980-07-08 1987-10-30
KR101667097B1 (ko) 2011-06-28 2016-10-17 휴렛 팩커드 엔터프라이즈 디벨롭먼트 엘피 시프트 가능 메모리
CN103890857B (zh) 2011-10-27 2017-02-15 慧与发展有限责任合伙企业 采用环形寄存器的可移位的存储器
US8854860B2 (en) 2011-10-28 2014-10-07 Hewlett-Packard Development Company, L.P. Metal-insulator transition latch
EP2771974A4 (en) 2011-10-28 2015-04-08 Hewlett Packard Development Co FLIP-FLOP WITH METAL-INSULATION PHASE TRANSITION
WO2013115779A1 (en) 2012-01-30 2013-08-08 Hewlett-Packard Development Company, L.P. Word shift static random access memory (ws-sram)
US9431074B2 (en) 2012-03-02 2016-08-30 Hewlett Packard Enterprise Development Lp Shiftable memory supporting bimodal storage
WO2017054132A1 (zh) * 2015-09-29 2017-04-06 华为技术有限公司 一种生成地址的方法及数据处理设备

Also Published As

Publication number Publication date
DE2356260A1 (de) 1974-05-30
IT1001548B (it) 1976-04-30
JPS4982241A (US07943777-20110517-C00090.png) 1974-08-08
DE2356260B2 (de) 1981-03-19
DE2356260C3 (de) 1981-12-24
JPS5246781B2 (US07943777-20110517-C00090.png) 1977-11-28
GB1398204A (en) 1975-06-18
US3797002A (en) 1974-03-12
FR2207610A5 (US07943777-20110517-C00090.png) 1974-06-14

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