BRPI1009228A2 - "armazenador configurável e método para configuração do mesmo" - Google Patents

"armazenador configurável e método para configuração do mesmo"

Info

Publication number
BRPI1009228A2
BRPI1009228A2 BRPI1009228A BRPI1009228A BRPI1009228A2 BR PI1009228 A2 BRPI1009228 A2 BR PI1009228A2 BR PI1009228 A BRPI1009228 A BR PI1009228A BR PI1009228 A BRPI1009228 A BR PI1009228A BR PI1009228 A2 BRPI1009228 A2 BR PI1009228A2
Authority
BR
Brazil
Prior art keywords
configuring
configurable
store
configurable store
Prior art date
Application number
BRPI1009228A
Other languages
English (en)
Inventor
Ajay Anant Ingle
Christopher Edward Koob
Jian Shen
Lucian Codrescu
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of BRPI1009228A2 publication Critical patent/BRPI1009228A2/pt
Publication of BRPI1009228B1 publication Critical patent/BRPI1009228B1/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G06F12/0895—Caches characterised by their organisation or structure of parts of caches, e.g. directory or tag array
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0864—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using pseudo-associative means, e.g. set-associative or hashing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/25—Using a specific main memory architecture
    • G06F2212/251—Local memory within processor subsystem
    • G06F2212/2515—Local memory within processor subsystem being configurable for different purposes, e.g. as cache or non-cache memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60—Details of cache memory
    • G06F2212/601—Reconfiguration of cache memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
BRPI1009228-5A 2009-03-03 2010-03-03 Cache configurável e método para configuração da mesma BRPI1009228B1 (pt)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12/397,185 2009-03-03
US12/397,185 US8266409B2 (en) 2009-03-03 2009-03-03 Configurable cache and method to configure same
PCT/US2010/026106 WO2010102048A1 (en) 2009-03-03 2010-03-03 Configurable cache and method to configure same

Publications (2)

Publication Number Publication Date
BRPI1009228A2 true BRPI1009228A2 (pt) 2016-03-15
BRPI1009228B1 BRPI1009228B1 (pt) 2020-12-01

Family

ID=42112122

Family Applications (1)

Application Number Title Priority Date Filing Date
BRPI1009228-5A BRPI1009228B1 (pt) 2009-03-03 2010-03-03 Cache configurável e método para configuração da mesma

Country Status (8)

Country Link
US (3) US8266409B2 (pt)
EP (1) EP2404241A1 (pt)
JP (2) JP5357277B2 (pt)
KR (2) KR101293623B1 (pt)
CN (3) CN104572503B (pt)
BR (1) BRPI1009228B1 (pt)
TW (3) TWI516932B (pt)
WO (1) WO2010102048A1 (pt)

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KR102317248B1 (ko) * 2014-03-17 2021-10-26 한국전자통신연구원 캐시의 부분연관 재구성을 이용한 캐시 제어 장치 및 캐시 관리 방법
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US9916252B2 (en) * 2015-05-19 2018-03-13 Linear Algebra Technologies Limited Systems and methods for addressing a cache with split-indexes
US20170046167A1 (en) * 2015-08-14 2017-02-16 Qualcomm Incorporated Predicting memory instruction punts in a computer processor using a punt avoidance table (pat)
CN106708747A (zh) * 2015-11-17 2017-05-24 深圳市中兴微电子技术有限公司 一种存储器切换方法及装置
US9747041B2 (en) * 2015-12-23 2017-08-29 Intel Corporation Apparatus and method for a non-power-of-2 size cache in a first level memory device to cache data present in a second level memory device
KR101780586B1 (ko) * 2016-03-16 2017-09-21 고려대학교 산학협력단 모놀리식 3d 집적 구조 기반 캐시메모리
CN105843360B (zh) * 2016-03-23 2018-06-12 中国电子科技集团公司第三十八研究所 一种降低指令高速缓冲存储器功耗的装置及方法
US10152276B2 (en) * 2016-07-18 2018-12-11 Winbond Electronics Corporation Memory device including data processor and program method of same
US20180088829A1 (en) * 2016-09-29 2018-03-29 Qualcomm Incorporated Area efficient architecture for multi way read on highly associative content addressable memory (cam) arrays
US10599566B2 (en) * 2016-11-29 2020-03-24 Qualcomm Incorporated Multi-mode cache invalidation
US10474458B2 (en) 2017-04-28 2019-11-12 Intel Corporation Instructions and logic to perform floating-point and integer operations for machine learning
KR102465213B1 (ko) * 2018-03-31 2022-11-10 마이크론 테크놀로지, 인크. 멀티 스레드, 자체 스케줄링 재구성 가능한 컴퓨팅 패브릭에 대한 조건부 브랜칭 제어
CN109801655B (zh) * 2018-12-19 2020-10-13 成都海光集成电路设计有限公司 标签存储位读出比较电路以及标签数据读出比较电路
TWI706250B (zh) * 2019-02-26 2020-10-01 慧榮科技股份有限公司 資料儲存裝置以及非揮發式記憶體控制方法
US11934342B2 (en) 2019-03-15 2024-03-19 Intel Corporation Assistance for hardware prefetch in cache access
BR112021016106A2 (pt) 2019-03-15 2021-11-09 Intel Corp Processador gráfico de propósito geral, método e sistema de processamento de dados
US20220180467A1 (en) 2019-03-15 2022-06-09 Intel Corporation Systems and methods for updating memory side caches in a multi-gpu configuration
CN110147330B (zh) * 2019-05-23 2023-09-01 深圳市创维软件有限公司 一种字模数据的缓存方法、装置、设备和存储介质
US11507174B2 (en) * 2020-02-25 2022-11-22 Qualcomm Incorporated System physical address size aware cache memory
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Also Published As

Publication number Publication date
KR20130080868A (ko) 2013-07-15
US20100228941A1 (en) 2010-09-09
WO2010102048A1 (en) 2010-09-10
US20140208027A1 (en) 2014-07-24
JP5650821B2 (ja) 2015-01-07
KR101293613B1 (ko) 2013-08-13
CN102341794A (zh) 2012-02-01
US8266409B2 (en) 2012-09-11
CN102341794B (zh) 2015-02-11
CN104598395B (zh) 2017-10-31
JP2013257902A (ja) 2013-12-26
CN104572503B (zh) 2018-07-03
US8943293B2 (en) 2015-01-27
TWI418982B (zh) 2013-12-11
TW201106158A (en) 2011-02-16
KR20110127733A (ko) 2011-11-25
TWI516932B (zh) 2016-01-11
CN104572503A (zh) 2015-04-29
TWI548992B (zh) 2016-09-11
EP2404241A1 (en) 2012-01-11
JP5357277B2 (ja) 2013-12-04
JP2012519334A (ja) 2012-08-23
TW201415228A (zh) 2014-04-16
BRPI1009228B1 (pt) 2020-12-01
US20120265943A1 (en) 2012-10-18
KR101293623B1 (ko) 2013-08-13
CN104598395A (zh) 2015-05-06
TW201610681A (zh) 2016-03-16
US8719503B2 (en) 2014-05-06

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Legal Events

Date Code Title Description
B06F Objections, documents and/or translations needed after an examination request according [chapter 6.6 patent gazette]
B06U Preliminary requirement: requests with searches performed by other patent offices: procedure suspended [chapter 6.21 patent gazette]
B15K Others concerning applications: alteration of classification

Free format text: AS CLASSIFICACOES ANTERIORES ERAM: G06F 12/08 , G06F 17/50

Ipc: G06F 12/0802 (2016.01), G06F 12/0864 (2016.01), G0

B07A Technical examination (opinion): publication of technical examination (opinion) [chapter 7.1 patent gazette]
B09A Decision: intention to grant [chapter 9.1 patent gazette]
B16A Patent or certificate of addition of invention granted

Free format text: PRAZO DE VALIDADE: 10 (DEZ) ANOS CONTADOS A PARTIR DE 01/12/2020, OBSERVADAS AS CONDICOES LEGAIS.