BR9908393A - Vertical integrated circuit layout - Google Patents
Vertical integrated circuit layoutInfo
- Publication number
- BR9908393A BR9908393A BR9908393-0A BR9908393A BR9908393A BR 9908393 A BR9908393 A BR 9908393A BR 9908393 A BR9908393 A BR 9908393A BR 9908393 A BR9908393 A BR 9908393A
- Authority
- BR
- Brazil
- Prior art keywords
- integrated circuit
- circuit layout
- vertical integrated
- vertical
- circuits
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/74—Masking faults in memories by using spares or by reconfiguring using duplex memories, i.e. using dual copies
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
- H01L23/556—Protection against radiation, e.g. light or electromagnetic waves against alpha rays
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/585—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries comprising conductive layers or plates or strips or rods or rings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
Patente de Invenção: <B>"DISPOSIçãO DE CIRCUITO INTEGRADO VERTICAL<D>. Está prevista uma disposição de circuito integrado vertical com ao menos um primeiro circuito integrado e um segundo circuito integrado, que ficam dispostos superpostos, sendo que em ambos os circuitos integrados é executada uma funcionalidade idêntica. Ao menos em um dos circuitos integrados, é prevista uma instalação de controle, que controla uma cooperação dos circuitos com idêntica funcionalidade.Invention Patent: <B> "VERTICAL INTEGRATED CIRCUIT ARRANGEMENT <D>. A vertical integrated circuit arrangement with at least a first integrated circuit and a second integrated circuit is provided, which are arranged superimposed, and in both integrated circuits an identical functionality is performed, at least in one of the integrated circuits, a control installation is provided, which controls the cooperation of the circuits with identical functionality.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19860817 | 1998-12-30 | ||
PCT/DE1999/004055 WO2000041240A1 (en) | 1998-12-30 | 1999-12-21 | Vertically integrated circuit system |
Publications (1)
Publication Number | Publication Date |
---|---|
BR9908393A true BR9908393A (en) | 2000-10-31 |
Family
ID=7893178
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
BR9908393-0A BR9908393A (en) | 1998-12-30 | 1999-12-21 | Vertical integrated circuit layout |
Country Status (6)
Country | Link |
---|---|
EP (1) | EP1060512A1 (en) |
JP (1) | JP2002534808A (en) |
KR (1) | KR20010083778A (en) |
CN (1) | CN1292151A (en) |
BR (1) | BR9908393A (en) |
WO (1) | WO2000041240A1 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI730941B (en) | 2014-04-09 | 2021-06-21 | 南韓商Ictk控股有限公司 | Apparatus and method for authenticating |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5588356A (en) * | 1978-12-27 | 1980-07-04 | Hitachi Ltd | Semiconductor device |
KR900008647B1 (en) * | 1986-03-20 | 1990-11-26 | 후지쓰 가부시끼가이샤 | A method for manufacturing three demensional i.c. |
SG52794A1 (en) * | 1990-04-26 | 1998-09-28 | Hitachi Ltd | Semiconductor device and method for manufacturing same |
EP0695494B1 (en) * | 1993-04-23 | 2001-02-14 | Irvine Sensors Corporation | Electronic module comprising a stack of ic chips |
EP0732107A3 (en) * | 1995-03-16 | 1997-05-07 | Toshiba Kk | Circuit substrate shielding device |
US5824571A (en) * | 1995-12-20 | 1998-10-20 | Intel Corporation | Multi-layered contacting for securing integrated circuits |
-
1999
- 1999-12-21 CN CN99803434A patent/CN1292151A/en active Pending
- 1999-12-21 KR KR1020007009608A patent/KR20010083778A/en not_active Application Discontinuation
- 1999-12-21 JP JP2000592881A patent/JP2002534808A/en not_active Abandoned
- 1999-12-21 BR BR9908393-0A patent/BR9908393A/en not_active IP Right Cessation
- 1999-12-21 EP EP99964450A patent/EP1060512A1/en not_active Withdrawn
- 1999-12-21 WO PCT/DE1999/004055 patent/WO2000041240A1/en not_active Application Discontinuation
Also Published As
Publication number | Publication date |
---|---|
KR20010083778A (en) | 2001-09-01 |
WO2000041240A1 (en) | 2000-07-13 |
JP2002534808A (en) | 2002-10-15 |
EP1060512A1 (en) | 2000-12-20 |
CN1292151A (en) | 2001-04-18 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
B08F | Application dismissed because of non-payment of annual fees [chapter 8.6 patent gazette] |
Free format text: REFERENTA A 4O, 5O, 6O E 7O ANUIDADES. |
|
B08K | Patent lapsed as no evidence of payment of the annual fee has been furnished to inpi [chapter 8.11 patent gazette] |
Free format text: REFERENTE AO DESPACHO 8.6 PUBLICADO NA RPI 1911 DE 21/08/2007. |