BR9600109A - Sistema de controle de conclus es distribuidas para um microprocessador e unidade de despacho para uso em um processador - Google Patents

Sistema de controle de conclus es distribuidas para um microprocessador e unidade de despacho para uso em um processador

Info

Publication number
BR9600109A
BR9600109A BR9600109A BR9600109A BR9600109A BR 9600109 A BR9600109 A BR 9600109A BR 9600109 A BR9600109 A BR 9600109A BR 9600109 A BR9600109 A BR 9600109A BR 9600109 A BR9600109 A BR 9600109A
Authority
BR
Brazil
Prior art keywords
microprocessor
processor
control system
dispatch unit
system distributed
Prior art date
Application number
BR9600109A
Other languages
English (en)
Inventor
Christopher Hans Olson
Terence Matthew Potter
Michael Thomas Vaden
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of BR9600109A publication Critical patent/BR9600109A/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3858—Result writeback, i.e. updating the architectural state or memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multimedia (AREA)
  • Advance Control (AREA)
  • Multi Processors (AREA)
  • Executing Machine-Instructions (AREA)
BR9600109A 1995-01-25 1996-01-16 Sistema de controle de conclus es distribuidas para um microprocessador e unidade de despacho para uso em um processador BR9600109A (pt)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US37781395A 1995-01-25 1995-01-25

Publications (1)

Publication Number Publication Date
BR9600109A true BR9600109A (pt) 1998-01-27

Family

ID=23490618

Family Applications (1)

Application Number Title Priority Date Filing Date
BR9600109A BR9600109A (pt) 1995-01-25 1996-01-16 Sistema de controle de conclus es distribuidas para um microprocessador e unidade de despacho para uso em um processador

Country Status (8)

Country Link
US (1) US5822556A (pt)
EP (1) EP0724214A3 (pt)
JP (1) JPH08241213A (pt)
KR (1) KR0175986B1 (pt)
CN (1) CN1075647C (pt)
BR (1) BR9600109A (pt)
CA (1) CA2163691A1 (pt)
TW (1) TW295646B (pt)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6016540A (en) * 1997-01-08 2000-01-18 Intel Corporation Method and apparatus for scheduling instructions in waves
US6032249A (en) * 1998-02-02 2000-02-29 International Business Machines Corporation Method and system for executing a serializing instruction while bypassing a floating point unit pipeline
US6134645A (en) * 1998-06-01 2000-10-17 International Business Machines Corporation Instruction completion logic distributed among execution units for improving completion efficiency
US6636928B1 (en) * 2000-02-18 2003-10-21 Hewlett-Packard Development Company, L.P. Write posting with global ordering in multi-path systems
US20060090015A1 (en) * 2004-10-26 2006-04-27 Bradfield Travis A Pipelined circuit for tag availability with multi-threaded direct memory access (DMA) activity
US20060206732A1 (en) * 2005-03-14 2006-09-14 Sony Computer Entertainment Inc. Methods and apparatus for improving processing performance using instruction dependency check depth
US8327120B2 (en) * 2007-12-29 2012-12-04 Intel Corporation Instructions with floating point control override
CN101706714B (zh) * 2009-11-23 2014-03-26 龙芯中科技术有限公司 指令发射系统及方法、处理器及其设计方法
GB2514618B (en) * 2013-05-31 2020-11-11 Advanced Risc Mach Ltd Data processing systems

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4149243A (en) * 1977-10-20 1979-04-10 International Business Machines Corporation Distributed control architecture with post and wait logic
US4740895A (en) * 1981-08-24 1988-04-26 Genrad, Inc. Method of and apparatus for external control of computer program flow
US4635186A (en) * 1983-06-20 1987-01-06 International Business Machines Corporation Detection and correction of multi-chip synchronization errors
US4903196A (en) * 1986-05-02 1990-02-20 International Business Machines Corporation Method and apparatus for guaranteeing the logical integrity of data in the general purpose registers of a complex multi-execution unit uniprocessor
US5127104A (en) * 1986-12-29 1992-06-30 Dataflow Computer Corporation Method and product involving translation and execution of programs by automatic partitioning and data structure allocation
US4762253A (en) * 1987-02-17 1988-08-09 Rhh Enterprises, Inc. Foam dispensing gun
US4991090A (en) * 1987-05-18 1991-02-05 International Business Machines Corporation Posting out-of-sequence fetches
EP0378415A3 (en) * 1989-01-13 1991-09-25 International Business Machines Corporation Multiple instruction dispatch mechanism
DE3908852A1 (de) * 1989-03-17 1990-09-20 Deutsch Franz Forsch Inst Verfahren und einrichtung zur bestimmung der mittleren signalfrequenz einer statistischen folge kurzer schwingungspakete
US5201056A (en) * 1990-05-02 1993-04-06 Motorola, Inc. RISC microprocessor architecture with multi-bit tag extended instructions for selectively attaching tag from either instruction or input data to arithmetic operation output
US5151981A (en) * 1990-07-13 1992-09-29 International Business Machines Corporation Instruction sampling instrumentation
DE69311330T2 (de) * 1992-03-31 1997-09-25 Seiko Epson Corp Befehlsablauffolgeplanung von einem risc-superskalarprozessor
CA2107305A1 (en) * 1993-01-08 1994-07-09 James Allen Kahle Method and system for nonsequential instruction dispatch and execution in a superscalar processor system

Also Published As

Publication number Publication date
JPH08241213A (ja) 1996-09-17
CN1136181A (zh) 1996-11-20
CA2163691A1 (en) 1996-07-26
EP0724214A2 (en) 1996-07-31
KR960029964A (ko) 1996-08-17
US5822556A (en) 1998-10-13
EP0724214A3 (en) 1997-06-18
KR0175986B1 (ko) 1999-05-15
CN1075647C (zh) 2001-11-28
TW295646B (pt) 1997-01-11

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Legal Events

Date Code Title Description
FA10 Dismissal: dismissal - article 33 of industrial property law