BR8301593A - Sistema de memoria de armazenamento auxiliar de multiplos niveis com capacidade de degradacao calculada - Google Patents

Sistema de memoria de armazenamento auxiliar de multiplos niveis com capacidade de degradacao calculada

Info

Publication number
BR8301593A
BR8301593A BR8301593A BR8301593A BR8301593A BR 8301593 A BR8301593 A BR 8301593A BR 8301593 A BR8301593 A BR 8301593A BR 8301593 A BR8301593 A BR 8301593A BR 8301593 A BR8301593 A BR 8301593A
Authority
BR
Brazil
Prior art keywords
memory system
storage memory
auxiliary storage
multiple levels
degradation capacity
Prior art date
Application number
BR8301593A
Other languages
English (en)
Inventor
James W Keeley
Edwin P Fisher
John L Curley
Original Assignee
Honeywell Inf Systems
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Honeywell Inf Systems filed Critical Honeywell Inf Systems
Publication of BR8301593A publication Critical patent/BR8301593A/pt

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/88—Masking faults in memories by using spares or by reconfiguring with partially good memories
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G06F12/121—Replacement control using replacement algorithms
    • G06F12/126—Replacement control using replacement algorithms with special data handling, e.g. priority of data or instructions, handling errors or pinning
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1032—Reliability improvement, data loss prevention, degraded operation etc

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
BR8301593A 1982-03-31 1983-03-28 Sistema de memoria de armazenamento auxiliar de multiplos niveis com capacidade de degradacao calculada BR8301593A (pt)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/364,052 US4464717A (en) 1982-03-31 1982-03-31 Multilevel cache system with graceful degradation capability

Publications (1)

Publication Number Publication Date
BR8301593A true BR8301593A (pt) 1983-12-06

Family

ID=23432812

Family Applications (1)

Application Number Title Priority Date Filing Date
BR8301593A BR8301593A (pt) 1982-03-31 1983-03-28 Sistema de memoria de armazenamento auxiliar de multiplos niveis com capacidade de degradacao calculada

Country Status (9)

Country Link
US (1) US4464717A (pt)
EP (1) EP0090638B1 (pt)
JP (1) JPS58179982A (pt)
AU (1) AU549615B2 (pt)
BR (1) BR8301593A (pt)
CA (1) CA1184665A (pt)
DE (1) DE3382111D1 (pt)
FI (1) FI80352C (pt)
MX (1) MX154471A (pt)

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US5347648A (en) * 1990-06-29 1994-09-13 Digital Equipment Corporation Ensuring write ordering under writeback cache error conditions
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US5345576A (en) * 1991-12-31 1994-09-06 Intel Corporation Microprocessor simultaneously issues an access to an external cache over an external cache bus and to an internal cache, cancels the external cache access on an internal cache hit, and reissues the access over a main memory bus on an external cache miss
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US5768295A (en) * 1995-03-10 1998-06-16 Nec Corporation System for parity calculation based on arithemtic difference between data
JP2799983B2 (ja) * 1996-02-16 1998-09-21 三信工業株式会社 船舶推進機のエンジン冷却装置
US5875201A (en) * 1996-12-30 1999-02-23 Unisys Corporation Second level cache having instruction cache parity error control
US5894487A (en) * 1997-07-15 1999-04-13 International Business Machines Corporation Error detection of directory arrays in dynamic circuits
US6014709A (en) * 1997-11-05 2000-01-11 Unisys Corporation Message flow protocol for avoiding deadlocks
US6092156A (en) * 1997-11-05 2000-07-18 Unisys Corporation System and method for avoiding deadlocks utilizing split lock operations to provide exclusive access to memory during non-atomic operations
US6052760A (en) * 1997-11-05 2000-04-18 Unisys Corporation Computer system including plural caches and utilizing access history or patterns to determine data ownership for efficient handling of software locks
US6049845A (en) * 1997-11-05 2000-04-11 Unisys Corporation System and method for providing speculative arbitration for transferring data
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US6314501B1 (en) 1998-07-23 2001-11-06 Unisys Corporation Computer system and method for operating multiple operating systems in different partitions of the computer system and for allowing the different partitions to communicate with one another through shared memory
US6687818B1 (en) 1999-07-28 2004-02-03 Unisys Corporation Method and apparatus for initiating execution of an application processor in a clustered multiprocessor system
US6665761B1 (en) 1999-07-28 2003-12-16 Unisys Corporation Method and apparatus for routing interrupts in a clustered multiprocessor system
JP3812258B2 (ja) * 2000-01-13 2006-08-23 株式会社日立製作所 キャッシュ記憶装置
US6728823B1 (en) * 2000-02-18 2004-04-27 Hewlett-Packard Development Company, L.P. Cache connection with bypassing feature
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US7191375B2 (en) * 2001-12-28 2007-03-13 Intel Corporation Method and apparatus for signaling an error condition to an agent not expecting a completion
US7581026B2 (en) * 2001-12-28 2009-08-25 Intel Corporation Communicating transaction types between agents in a computer system using packet headers including format and type fields
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US7184399B2 (en) * 2001-12-28 2007-02-27 Intel Corporation Method for handling completion packets with a non-successful completion status
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Also Published As

Publication number Publication date
FI831080A0 (fi) 1983-03-30
US4464717A (en) 1984-08-07
FI80352B (fi) 1990-01-31
AU549615B2 (en) 1986-02-06
FI831080L (fi) 1983-10-01
AU1185583A (en) 1983-10-06
CA1184665A (en) 1985-03-26
EP0090638A3 (en) 1987-04-08
EP0090638B1 (en) 1991-01-16
JPS58179982A (ja) 1983-10-21
DE3382111D1 (de) 1991-02-21
FI80352C (fi) 1990-05-10
MX154471A (es) 1987-08-28
EP0090638A2 (en) 1983-10-05

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