BR8102734A - PROCESS FOR RECOVERY OF CADENCIA FROM BINARY INPUT SIGNS NRZ WITH A PHASE OF REGULATION OF PHASE AND PROVISION FOR THE REALIZATION OF THE SAME - Google Patents

PROCESS FOR RECOVERY OF CADENCIA FROM BINARY INPUT SIGNS NRZ WITH A PHASE OF REGULATION OF PHASE AND PROVISION FOR THE REALIZATION OF THE SAME

Info

Publication number
BR8102734A
BR8102734A BR8102734A BR8102734A BR8102734A BR 8102734 A BR8102734 A BR 8102734A BR 8102734 A BR8102734 A BR 8102734A BR 8102734 A BR8102734 A BR 8102734A BR 8102734 A BR8102734 A BR 8102734A
Authority
BR
Brazil
Prior art keywords
phase
cadencia
nrz
realization
provision
Prior art date
Application number
BR8102734A
Other languages
Portuguese (pt)
Inventor
E Douverne
R Heer
Original Assignee
Licentia Gmbh
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Licentia Gmbh filed Critical Licentia Gmbh
Publication of BR8102734A publication Critical patent/BR8102734A/en

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
BR8102734A 1980-05-06 1981-05-05 PROCESS FOR RECOVERY OF CADENCIA FROM BINARY INPUT SIGNS NRZ WITH A PHASE OF REGULATION OF PHASE AND PROVISION FOR THE REALIZATION OF THE SAME BR8102734A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19803017237 DE3017237C2 (en) 1980-05-06 1980-05-06 Circuit arrangement for clock recovery with a phase locked loop (PLL)

Publications (1)

Publication Number Publication Date
BR8102734A true BR8102734A (en) 1982-01-26

Family

ID=6101688

Family Applications (1)

Application Number Title Priority Date Filing Date
BR8102734A BR8102734A (en) 1980-05-06 1981-05-05 PROCESS FOR RECOVERY OF CADENCIA FROM BINARY INPUT SIGNS NRZ WITH A PHASE OF REGULATION OF PHASE AND PROVISION FOR THE REALIZATION OF THE SAME

Country Status (3)

Country Link
AT (1) AT384132B (en)
BR (1) BR8102734A (en)
DE (1) DE3017237C2 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3149731A1 (en) * 1981-12-15 1983-06-23 Siemens AG, 1000 Berlin und 8000 München REGENERATOR FOR A DIGITAL MESSAGE SYSTEM
GB8414517D0 (en) * 1984-06-07 1984-07-11 British Telecomm Signal timing circuits
US8674754B2 (en) 2007-02-09 2014-03-18 Intel Mobile Communications GmbH Loop filter and phase-locked loop
US11148244B2 (en) 2019-08-05 2021-10-19 Computational Systems, Inc. Vibration spectra window enhancement

Also Published As

Publication number Publication date
ATA201881A (en) 1987-02-15
DE3017237C2 (en) 1985-05-02
DE3017237A1 (en) 1981-11-12
AT384132B (en) 1987-10-12

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Legal Events

Date Code Title Description
MK Patent expired

Effective date: 19960505