BR132012003099E2 - System-based energy saving device and igbt / fet method - Google Patents

Abstract

Igbtifet system-based energy saving device this certificate of addition refers to an igbt / fet (1) system-based energy saving device in which a predetermined amount of voltage below rated line voltage and / or below a rated appliance voltage, thereby conserving power. Phase input connections (2) are provided to input analog signals to the device and system (1). A magnetic flux concentrator (3) detects the incoming analog signal (20) and a zero volt crossing point detector (5) determines the zero volt crossing points (21) of signal (20). Positive half cycle (22) and negative half cycle (23) of signal (20) are identified and routed to a digital signal processor (10) to process signal (20). Signal 20 is reduced by pulse width modulation and the reduced amount of power is output, thus producing energy savings for an end user.

Description

Report on the Addition of Invention Certificate for "IGBT / FET SYSTEM-BASED ENERGY ECONOMY DEVICE".

Certificate of Addition of Invention of PI0815173-3, filed on August 5, 2008.

Cross Reference to Related Applications This application claims the benefit of U.S. Provisional Applications No. 60 / 964,587 filed August 13, 2007; 60 / 966,124 filed August 24, 2007; 61 / 009,844 filed January 3, 2008; 61 / 009,846 filed January 3, 2008; 61 / 009,845 filed January 3, 2008; and 61 / 009,806 filed January 3, 2008.

Background of the Invention This Certificate of Addition relates to energy-saving devices, systems and methods, more particularly, to an energy-saving device based on a system and method for use of isolated gate bipolar transistor / effect transistor. (IGBT / FET), where a predetermined amount of voltage is saved below a rated line voltage and / or below a rated appliance voltage, thereby conserving power.

Since the industrial revolution, the world's energy consumption has grown at a steady rate. Most of the power generated and energy consumed is from the combustion of fossil fuels, a non-renewable natural resource that is rapidly becoming depleted. As the depletion of the earth's natural resources continues, power generation and energy conservation has become an increasingly important issue with governments both at home and abroad. Also, not only are governments concerned about power generation and energy conservation, but businesses and consumers are also concerned, as costs for such resources are rising rapidly. Not only are there concerns worldwide with power generation and energy conservation, but there are also concerns with power distribution, especially in emerging economies. While power generation and power conservation are of great importance, the power distribution problem is also of great concern as it involves existing infrastructure that is usually inadequate to distribute power correctly and not readily suitable for improvement. This problematic situation is manifested by blackouts in which a rated AC voltage cannot be maintained in the face of a grid / generation overload.

Government entities and power companies are currently trying to remedy blackouts by raising AC voltage or by adding shedding power to appropriate locations in the power grid. This method usually results in a large voltage disparity available to consumers in homes and / or businesses. Voltage increases can range from ten percent to fifteen percent (10% - 15%) and, since power is calculated by Voltage2 / load, the result of remedy by the power utility government entities may result in increased power. consumer charges of up to twenty-five percent (25%). Thus, instead of conserving energy, government entities and power companies are using energy.

In addition, while most appliances and appliances used in businesses and homes are capable of operating to exactly the specification at rated voltage minus ten percent (10%), most power saving devices do not exploit this feature. . Thus, additional potential for energy saving is often overlooked.

Thus, there is a need for an energy saving device, system and method, wherein a predetermined amount of voltage below a nominal line voltage and / or below a nominal appliance voltage is saved, thereby conserving energy. The prior art includes the following relevant references: Patent / Serial No. Inventor Date of Issue / Publication (U.S., unless otherwise stated) 6,664,771 Scoggins et al. 12-16-2003 6,486,641 Scoggins et al. 11/26/2002 2005/0068013 Scoggins 31-03-2005 6,489,742 Lumsden 12-12-2002 7,010,363 Donnelly et al. 2006-07-07 5,652,504 Bangerter 7/29/1997 5,625,236 Lefebvre et al. April 29, 1997 5,543,667 Shavit et al. 08-06-1996 5,442,335 Cantinetal. August 15, 1995 5,134,356 El-Sharkawi et al. 07-28-1992 5,003,192 Beigel 26-03-1991 3,959,719 Espelage 05-25-1976 4,706,017 Wilson 10-11-1987 2007/0279053 Taylor et al. Dec 6, 2007 6,963,195 Berkcan 11-11-2005 6,184,672 Berkcan 6-02-2001 3,582,774 Forgacs 01-06-1971 5,994,898 DiMarzio et al. 11-30-1999 7,358,724 Taylor et al. 2008-04-15 7,259,546 Hastings et al. August 21, 2007 7,250,748 Hastings et al. 2007-07-31 7,298,132 Woolsey et al. 20-11-2007 7,298,133 Hastings et al. 11/20/2007 7,157,898 Hastings et al. 2007-02-02 6,912,911 Oh et al. 2005-05-05 5,180,970 Ross 19-01-1993 6,414,475 Dames et al. 02-07-2002 2008/0084201 Kojori 10-04-2008 7,358,724 Taylor et al. 2008-04-15 6,426,632 Clunn 07-30-2002 6,265,881 Meliopoulos et al. 7/24/2001 5,202,621 Reischer 4/13/1993 4,616,174 Jorgensen. 10-10-1986 4,513,274 Halder 4/23/1985 4,096,436 Cooketal. 06/20-1978 3,976,987 Anger 24-08-1976 2008/0084200 Kojori 10-04-2008 2004/0239335 McClelland et al. 12/02/2004 7,301,308 Akeretal. 2007-11-27 6,548,989 Duff, Jr. 4/15/2003 6,548,988 Duff, Jr. 4/15/2003 7,245,100 Duff, Jr. 7/17/2007 7,205,822 Torres et al. 2007-04-17 7,091,559 Fragapane et al. 8/15/2006 6,724,043 Ekkanath Madathil 4/20/2004 6,618,031 Bohn, Jr. et al. 09-09-2003 6,411,155 Pezzani 2005-06-25 5,559,685 Lauw et al. 09-24-1996 6,055,171 Ishiietal. 25-04-2000 7,355,865 Royak et al. 2008-08-08 7,123,491 Kusumi 2006-10-17 6,650,554 Darshan 11/18/2003 5,946,203 Jiangetal. 8/31/1999 5,936,855 Salmon 8-10-1999 5,600,549 Cross 02-02-1997 4,679,133 Moscovici 07-07-1987 2008/0043502 Billig et al. Summary of the Invention The main object of the present invention is to provide a device, system and method in which a predetermined amount of down voltage of a nominal line voltage is saved, thereby conserving energy.

Another object of the present invention is to provide a device, system and method, wherein a predetermined amount of voltage below a nominal appliance voltage is saved, thereby conserving energy.

A further object of the present invention is to provide a device, system and method which may be used for a variety of applications including, but not limited to, whole house energy saving devices, motor controllers, small appliance regulators and any appliance where AC current measurement is required.

Another object of the present invention is to provide a device, system and method which may be used for the following appliances: controllers for refrigerators, freezers, air conditioners, AC electric motors and AC voltage; single-phase, two-phase and multi-phase energy saving devices for the entire home; commercial and industrial energy saving devices; and AC voltage regulators.

A further object of the present invention is to provide a device, system and method that virtually eliminates blackouts caused by power overload in a power grid.

A still further object of the present invention is to provide a device, system and method that reduces a load on a power grid.

Another object of the present invention is to provide a device, system and method that can be used to reduce the load imposed on a power grid during peak load times.

A still further object of the present invention is to provide a device, system and method, which enables government entities and / or power companies to manage power from a demand perspective rather than a production and / or distribution perspective.

Another object of the present invention is to provide a device, system and method which is inexpensive after the initial cost of equipment used in the system is amortized.

Another object of the present invention is to provide a device, system and method that provides precise power control and regulation.

Another object of the present invention is to provide a device, system and method, wherein the device may be programmed by a user for activation for a specific time and / or date period.

A still further object of the present invention is to provide a device, system and method, in which a user can program individual and / or multiple energy savings percentage reductions.

A further object of the present invention is to provide a device, system and method that is adaptable to a plurality of powers and / or frequencies.

A further object of the present invention is to provide a device, system and method which may be small in size.

Another object of the present invention is to provide a device, system and method, which is preferably available to an end user.

A further object of the present invention is to provide a device, system and method, which allows a user to manage peak demand at the point of consumption rather than at the point of generation.

Another object of the present invention is to provide a device, system and method, which provides galvanic isolation of a central processing unit (if used) from an AC power source.

A further object of the present invention is to provide a device, system and method which may include synchronous or random pulse width modulation.

Another object of the present invention is to provide a device, system and method that reduces harmonics resulting from the currently used energy saving devices. The present invention serves the above and other purposes by providing a device, system and method, wherein a predetermined amount of voltage below a nominal line voltage and / or below a nominal household voltage is saved, thereby conserving energy. Phase input connections are provided to input analog signals to the device and system. A magnetic flux concentrator detects incoming analog signal and a zero volt crossing point detector determines the zero volt crossing points of the signal. The half positive and half negative cycle of the signal is identified and prorated to a digital signal processor to process the signal. The signal is reduced by a trigger control via pulse width modulation and the reduced amount of power is output, thus producing energy savings for an end user.

The above and other objects, features and advantages of the present invention should become even more readily apparent to those skilled in the art by reading the following detailed description along with the drawings in which illustrative versions of the invention are shown and described.

Brief Description of the Drawings In the following detailed description, reference will be made to the accompanying drawings in which: Figure 1 is a block diagram of a device and system of the present invention for use in a three phase electrical system; Figure 2 is a perspective plan view of a detector means of the present invention; Figure 3 is a circuit diagram of a detector means of the present invention; Figure 4 is a circuit diagram of a signal conditioning means of the present invention; Fig. 5 is an oscillogram for a means of determining zero volt crossing point of the present invention; Figure 6 is a circuit diagram for a means of determining zero volt crossing point of the present invention; Figure 7 is a circuit diagram of a loss detection means and phase rotation and rotation determination means of the present invention; Figure 8 shows a circuit diagram of a half cycle identifying means of the present invention; Figure 9 shows an oscillogram of a half-cycle identifying means of the present invention; Figure 10 shows an oscillogram of a half-cycle identifying means of the present invention; Figure 11A is a circuit diagram of the routing means of the present invention; Fig. 11B is a continuation of the circuit diagram of Fig. 11A; Figure 11C is a circuit diagram of a gate programmer of Figures 11A and 11B; Figure 11D is a circuit diagram of a resistor holder of Figures 11A and 11B; Figure 11E is a circuit diagram of a connector of Figures 11A and 11B; Figure 12A is an oscillogram of a voltage reducing means of the present invention; Figure 12B is an oscillogram of an IGBT-based voltage reducing means of the present invention; Figure 12C is a circuit diagram of an IGBT-based voltage reducing means of the present invention; Figure 12D is a circuit diagram of a circuit unit for the IGBT-based voltage reducing means of Figure 12C; Figure 12E is an oscillogram of a voltage reducing means of the present invention based on FET; Figure 12F is a circuit diagram of a FET-based voltage reducing means of the present invention; Figure 12G is a circuit diagram of a drive circuit unit for the FET-based voltage reducing means of Figure 12F; Figure 13 is a circuit diagram of a combined reclosing means and indicator means of the present invention; Figure 14 is a circuit diagram of a power supply unit of an energizing means of the present invention; Fig. 15A is a circuit diagram of a communication medium of the present invention; Fig. 15B is a circuit diagram of a USB interface of a communication medium of Fig. 15A; Fig. 15C is a circuit diagram of an isolating block of a communication means of Fig. 15A; Fig. 15D is a circuit diagram of a first connector of a communications medium of Fig. 15A within a digital signal processor; Fig. 15E is a circuit diagram of a second connector of a communication means of Fig. 15A; Fig. 16 is a screen image of a window interface of the present invention; and Figure 17 is a screen image of a window interface of the present invention.

Description of Preferred Modes For the purpose of describing the preferred embodiment, the terminology used in reference to the numbered components in the drawings is as follows: 1. IGBT / FET-based energy saving device and system 2. Phase input connection 3 Magnetic flux concentrator 4. Analog signal conditioning device 5. Zero volt crossing point detector 6. Phase loss detection device 7. Phase rotation device 8. Half-cycle identifier 9. Logic device 10. digital signal processor 11. A / D converter 12. power supply unit 13. reset switch 14. LEDs 15. IGBT / FET drive control 16. computing device 17. phase output connection 18. neutral 19. incoming power 20. analog signal 21. zero-volt crossing point 22. half positive cycle 23. half negative cycle 24. reduced power 25 c USB interface communications 26. circuit board 27. housing 28. conductor 29. upper half of housing 30. lower half of housing 31. pivot 32. first filter 33. second filter 34. compared r 35. Schmidt buffer 36. crossing signal at absolute zero 37. magnetic flux concentrator chip 38. aperture 39. incoming sine wave 40. windows interface 41. main monitoring screen 42. field, generally 43. operational mode field 44. phase field 45. starting field 46. calibration field 47. setpoint field 48. indicators 49. real time clock 50. digital electricity meter 51. Schmidt-activated inverter buffer 52. transorb device applied to negative half cycle control 53 diode 54. positive half-cycle control transistor - trc: T

vw. I I__ I 56. capacitor 57. transformer 58. negative half-cycle control transistor 59. first IGBT shunt control transistor 60. second IGBT shunt control transistor 61. shunt device 62. integrated circuit 63. resistor 64. split bus generator 65. optical isolator 66. optically coupled driver 67. first branch control FET transistor 68. second branch control FET transistor 69. square wave 70. operational amplifier 71. isolator 72. rectifier 73. transistor 74 USB port 75. Zener diode 76. first connector 77. second connector 78. inductor 79. resistor bracket 80. logic device connector 81. linear voltage regulator 82. positive half-cycle drive signal applied to positive half cycle 83. negative half cycle drive signal applied to negative half cycle control transistor 84. drive signal applied to color transistor positive half-cycle control during negative half-cycle 85. drive signal applied to negative half-cycle control transistor during positive half-cycle 86. drive signal applied to first derivative control IGBT transistor during negative half-cycle 87. drive signal applied to the second derivative control transistor IGBT during positive half-cycle 88. drive signal applied to the first derivative control transistor FET during negative half-cycle 89. drive signal applied to the second derivative control FET transistor during positive half-cycle 90 Switching Regulator Referring to Figure 1, a block diagram of an energy saving device and system 1 of the present invention for use in a three phase electrical system is shown. The energy saving device and system 1 includes a number of components and means for reducing the amount of energy introduced at which reduced energy produces a virtually non-existent or minimal effect on the performance of an electronically operated device.

A predetermined amount of incoming power 19 having at least one analog signal 20 therein is introduced into the device and system 1 via an input means, which is preferably at least one phase input connection 2. A neutral line 18 is also As shown in Figure 1, system and device 1 is used in a three-phase electrical system having a more neutral A-B-C phase to use as a reference point and as a flow for a Return EMF that is produced when current in a retarding power factor load is interrupted. However, the energy saving system 1 of the present invention may be used in a single phase system and / or a two phase system as well, where the only difference in structure is the amount of phase 2 input connections (for example , in a single phase system, only one phase 2 input connection is used besides a neutral connection (A) and in a two phase system, two phase 2 input connections are used (A and B) plus one neutral.

At least one phase 2 input connection is connected to at least one sensing means, which is preferably at least one magnetic flux concentrator 3, which detects the predetermined amount of incoming energy 19. Magnetic flux concentrator 3 isolates galvanically. the incoming power current 19 and reports any overcurrent conditions for a routing means, which is preferably at least one logic device 9. If any overcurrent conditions exist, then the overcurrent conditions are simultaneously reported to the logic device 9 and a processing medium, which is preferably a digital signal processor 10, wherein the digital signal processor 10 immediately shuts down the device and system 1. This electronic circuit breaker action is intended for protection of the device and system 1 itself, as well as the terminal equipment used in conjunction with device and system 1 in the event of a short circuit too much or overload. Thus, logic device 9 provides full protection of power control devices in the event of low frequency softwa-re / firmware interference and / or low frequency power line interference or real-time voltage or current surge. since the reaction time of the logic device 9 and the digital signal processor 10 is preferably 5 ps. Logic 9 arbitrates between the drive signals applied to the half-cycle IGBT / FET control transistors 54 and 58 and the signals applied to the IGBT / FET branch control transistors 59, 60, 67 and 68. Therefore, it prevents the half-cycle IGBT / FET control transistors and the IGBT / FET branch control transistors 59, 60, 67 and 68 are simultaneously driven to a switched-on condition which could lead to power control and / or element failure. bypass. Digital signal processor 10 preferably includes at least one A / D converter 11.

Prior to reporting the analog value of the phase current of the phase 2 input connection to the digital signal processor 10, the magnetic flux concentrator 3 first transmits the incoming energy 19 through at least one signal conditioning means, which is preferably by at least one analog signal conditioning device 4. After the signals have been conditioned by a method as described below, the conditioned signals are then sent to a means of determining zero volt crossing point, which is preferably at least one frequency detector. zero voltage crossing point 5, to detect the point where the AC voltage passes zero volts relative to neutral 18, which is commonly referred to as a zero crossing point.

After the zero crossing point is detected and using a three-phase electrical system, the conditioned signal then enters at least one loss detection means, which is preferably at least one phase loss detection device 6 and at least one phase. at least one phase rotation determination and rotation means, which is preferably at least one phase rotation device 7, in order to prepare the signal to properly input it into at least one half-cycle identifying means, which is preferably a half-cycle identifier 8, and then logic device 9 and digital signal processor 10. Details of the half-cycle identifier 8 are discussed below. Power control is performed via at least one voltage-reducing means, which preferably includes at least one drive control IGBT / FET 15, in electrical connection to the digital signal processor 10 to reduce a predetermined amount of power. Before the processed signals enter the reducing medium, however, the signals may once again be conditioned via at least one analog signal conditioning device 4 in order to clear a signal to remove any spurious signals or transient signals. The command signals for exercising drive control IGBT / FET control 15 of the voltage reducing means are determined by the digital signal processor 10 and mitigated by the logic device 9. The reduced energy 24 then enters at least one magnetic flux concentrator. 3 and then enters at least one output means, which is preferably at least one phase output connection 17, and is output to an electrically operated device for consumption. The system and device 1 is energized via a power means, which is preferably a power supply unit 12 in electrical connection with the digital signal processor 10. A king means, which is preferably a reset switch. 13, which is preferably provided to allow a user to reboot device and system 1 as desired. In addition, an indicator means, such as an LED 14, may be in electrical connection with the king reset switch 13 to alert a user if device and system 1 need to be reset. The device and system 1 may optionally include at least one digital electricity meter 50 and at least one communication medium, such as a USB communications interface 25, capable of interfacing with at least one computing device 16 having at least one USB port 74 and at least one window interface 40 via wired or wireless transmission. The USB communications interface 25 allows a user to monitor, display, and / or configure device and system 1 via their computing devices 16. However, the inclusion of the USB communications interface 25 is not required in device and system 1 implementation.

Further, a real time clock 49 may optionally be incorporated within the digital signal processor 10 or otherwise connected to the power saving device and system. 1- A user may determine the operating manner in which to use the device and power saving system. of the present invention, for example, a user may select how he / she would like to save energy either by entering the desired RMS value, or by entering the desired voltage percentage or by entering the desired savings reduction percentage into a computation 16. For example, if a user chooses to reduce incoming voltage by a fixed percentage, the energy saving device and system 1 allow such a percentage reduction in voltage and automatically lower the voltage to be consistent with a maximum allowable content. harmonic setting a lower voltage limit. The lower voltage limit ensures that under lower or blackout conditions, system and device 1 do not continue to attempt to reduce available voltage by the specified percentage reduction.

Figure 2 shows a perspective plan view of a detector means of the present invention. The detecting means, which is preferably at least one magnetic flux concentrator 3, measures AC current galvanically when connected to the active circuit unit of the device and system 1 of the present invention. A housing 27, which is preferably made of plastic, includes a top half housing 29 and a lower half housing 30 and a hinge 30 connecting the two halves 29 and 30, carry a circuit board 26 having a magnetic flux concentrator chip. 37 mounted to the underside of the top half housing 29. Each half housing 29 and 30 includes at least one notched portion wherein when the halves 29 and 30 are joined together, at least one opening 38 is formed to allow a conductor 28 to extend through them. The use of said housing 27 precisely defines the distance between magnetic flux concentrator chip 37 and the center of conductor core 28. A window detector associated with magnetic flux concentrator chip 37 accurately determines when current within negative or positive half-cycles is outside the normal range. In addition, magnetic flux concentrator 3 uses an open collector Schmidt buffer to allow multiple concentrators 3 to be connected to both analog signal conditioning device 4 and logic device 9. Housing 27 is snap-fit and presses on conductor 28, which is preferably a cable to ensure that conductor 28 is firmly secured against housing 27. Half-end housing 29 may be formed into various sizes to accommodate different wire sizes . A plurality of apertures 38 of various sizes may be formed when halves 29 and 30 are snapped together to accommodate conductors 28 of various widths. Magnetic flux concentrator 3, provides galvanic isolation of incoming energy 19, performs accurate current measurement, is adaptable to any current range through multiple cable passages located within housing 27, provides high voltage galvanic isolation, has distortion zero harmonics and superb linearity. Also, since the current measurement range is mechanically determined, no change is required for PCB 26. The following equation determines the approximate sensitivity: Output = 0.06 * I / (D + 0.3mm ) where i = current in conductor 28 and D = the distance in mm from the upper surface from the magnetic flux concentrator chip 37 to the center of conductor 28. Since no electrical connection is made for the measurement purpose, it is achieved. the full galvanic isolation. Also, there is zero insertion loss and therefore no heat is dissipated or energy lost as no electrical connection is made and no shunt or transformer is used. Figure 3 is a circuit diagram of the detector means of the present invention. Magnetic flux concentrator 3 measures the magnetic flux generated when an alternating electric current flows into conductor 28. Overcurrent is obtained by comparators 34 forming a window comparator. When the limits set by resistors 63 are exceeded by an output of the magnetic flux concentrator 3, which can produce a "High Current" signal, the comparator open collector outputs 34 go down and go to logic device 9 and an input microprocessor circuit breaker for disconnecting device and system I. To avoid ground loop problems, magnetic flux concentrator 3 preferably includes an integrated circuit 62 that regulates the operating voltage of magnetic flux concentrator 3 to 5VDC.

Referring to Figure 4, a circuit diagram of a signal conditioning means of the present invention is shown. The signal conditioning means, which is preferably at least one analog signal conditioning device 4, clears or conditions a 50 / 60Hz sine wave analog signal to remove any spurious signals or transient signals prior to its transmission to the half cycle identifier. 8. If the sine wave has any noise or distortion of sufficient amplitude, this may, under certain circumstances, cause false zero crossing detections. Thus, the inclusion of such analog signal conditioning device 4 is important.

To properly condition the sine wave signal, operational amplifiers 70 are used. An operational amplifier 70 is configured as a second order active low pass filter to remove or reduce harmonics and any transients or interference signals that may be present. When using such a filter, however, group delay occurs in which the group delay time shifts the zero crossing of the filtered signal from the actual zero crossing point of the incoming AC sine wave. To remedy the delay, operational amplifiers 70 are provided to allow the necessary phase shift to correct zero crossing with time precision as required. The output of the operational amplifiers 70 is the fully conditioned 50 / 60Hz sine wave signal that is connected to the A / D converter 11 of the digital signal processor 10 (see figure 1) to obtain the effective value (RMS) of the measurement. This signal is exactly half of the bus supply that is required to enable measurement of both positive and negative half cycles. The A / D converter 11 performs the well-known mathematical 2s compliment to enable it and requires the signal. of AC to deviate both positively and negatively with respect to the center or divide the bus voltage. The signal also enters the middle cycle identifier 8.

Figures 5 and 6 show an oscillogram and circuit unit diagram, respectively, for a means of determining zero volt crossing point of the present invention. The means of determining zero volt crossing point, which is preferably at least one zero volt crossing point detector 5 wherein the zero crossing point 21 is accurately determined. An operational amplifier 70 is configured as a comparator 34 with its reference at exactly half of the supply voltage using half of the supply bus. A comparator 34 operates at a very high gain and, as a result, switches within a few millivolts of split bus voltage.

Further conditioning of the zero crossing signal is further performed by a Schmidt buffer 35. Subsequent to the additional signal processing, a very precise square wave 69 is produced a few millivolts of the actual zero volt crossing point 21 of the sine wave. Figure 7 shows a circuit diagram of a loss detection means and a phase rotation determination and rotation means of the present invention. The loss detection means, which is preferably at least one phase loss detection device 6, and the phase rotation detection and rotation means, which is preferably at least one phase rotation device 7, work together to prepare correctly signal for transmission on logic device 9 and digital signal processor 10 when using a three phase electrical system. The phase loss detection device circuitry 6 includes operational amplifiers 70 configured as comparators 34 where each uses a high value of series resistors, comprising two 0.5Meg Ohm resistors in series, which is required to achieve the required working voltage of resistors 63, and two diodes 53 connected was inverse parallel. The diodes 53 are centered around the zero volt crossing points 21 of the incoming sine wave 39 at approximately the voltage drop ahead of the diodes 53, which is in turn applied to the comparator 34 which further conditions the appropriate signal to pass to the diode. logic device 9 and digital signal processor 10, resulting in the system being shut down in the absence of any of the signals.

In a three-phase electrical system, the phase rotation can be either A-B-C or A-C-B. To enable digital signal processor 10 to function properly, phase rotation must first be ascertained. Comparators 34 are used to detect crossing points at zero volt (s) 21 and report points 21 to digital signal processor 10. Digital signal processor 10, in turn, makes the rotational time count through the timing logic. Each of the operational amplifiers 70 acts as a simple comparator 34 with the input signal, in each case provided by the inverse parallel diode pairs 53 together with the series resistors 63.

Figures 8, 9 and 10 show a circuit diagram and oscillating grams, respectively, of a half-cycle identifying means of the present invention. The half-cycle identifying means, which is preferably at least one cycle-identifying means 8, provides additional data for the logic device 9 and digital signal processor 10, identifying whether the half-cycle of the analog signal is positive or negative. This is of great importance to avoid a situation where if the half-cycle IGBT / FET control transistors 54 and 58 and the IGBT / FET branch control transistors 59, 60, 67 and 68 are simultaneously connected, a short circuit could occur. -circuit through the input power.

Operational amplifiers 70, which are configured as window comparators 34, have separate switching limits determined by at least one resistor 63. As shown in Figure 9, there are three signals, one absolute zero crossing signal 36 and two matching signals in each other. that a co-incident signal has a positive half cycle 22 and a co-incident signal has a negative half cycle 23 of an incoming sine wave 39. The design allows the window to be adjusted to provide, when required, the "band" dead".

Referring to Figures 11A, 11B, 11C, 11D and 11E, circuit diagrams of the routing means of the present invention are shown. The routing means, which is preferably at least one logic device 9, works in real time outside the digital signal processor 10 to arbitrate between on-time times of the half-cycle control IGBT / FET transistors 54 and 58 and IGBT transistors / FET bypass control 59, 60, 67 and 68. Logic device 9 performs the routing function to ensure that all signals are suitable for the sine wave requirement and instantaneous polarity 39 and performs the pulse width modulation function to ensure safe operation of the device and energy saving system. 1, regardless of the state of the digital signal processor 10, presence of noise, interference or transients. Isolator circuit unit 71 as shown in figure 11C allows to program logic device 9. Resistor holder circuit unit 79 of logic device 9 as shown in figure 11 D is required to operate logic device 9 As shown in Figure 11E, the logic device connector circuitry 80 enables enabling and disabling of certain aspects of logic device 9.

Dealing with a resistive load is much less demanding than dealing with a reactive load, in particular an inductively reactive load. Pulse width modulation (PWM) is currently defined as modulation of a pulse bearer where the value of each instantaneous sample of a modular wave produces a pulse of proportional duration varying the front edge, rear edge, or both. edges of a wrist, which is also known as pulse duration modulation. However, for purposes of this invention and application, PWM is defined as the modulation of a pulse carrier wherein at least one slice is removed from an area under the wave curve of a modulating wave. When PWM is directly applied to incoming power, the inductive component reacts when the power is removed and attempts to keep the current going and will raise its self-generated voltage until the current finds a discharge path. This circumstance, without the branch circuit unit, would destroy the half-cycle control transistors.

Therefore, logic device 9 is a "supervisor" in which it takes the appropriate action that digital signal processor 10 should "shut down" if there is an overcurrent condition or if there is a phase loss.

In either of these situations, logic device 9 responds immediately, in real time, to protect the half-cycle control transistors and shunt devices and the equipment connected to it.

In addition, logic device 9 mitigates the complex drive requirements of IGBT / FET half-cycle control transistors 54 and 58 and iqbj / pet shunt control transistors 59, 60, 67 and 68 and to some extent discharges digital signal processor 10 of this task. Since logic device 9 controls this function, it can be performed in real time, so timing control of the triggering requirements can be kept at much stricter limits than would be achieved by the digital signal processor. 10. The ability to respond in real time is important for the safe, reliable operation of the energy saving device and system 1 of the present invention.

Figures 12A, 12B, 12C, 12D, 12E, 12F and 12G show oscillograms and circuit diagrams of a voltage-reducing means of the present invention. The voltage reducing means, which preferably includes at least one drive control IGBT / FET 15, reduces the analog signals of the incoming sine wave 39, which is the amount of energy introduced into the energy saving device and system 1 by modulation. of pulse width wherein at least one slice is removed from an area below the modulating sine wave curve 39, thereby reducing energy and without the assistant harmonics previously associated with such voltage control. This technique, as shown in Figure 12A, works in conjunction with the inherent characteristics of IGBT / FET devices that enable and disable the enable point to be controlled. All potential energy is contained in each half cycle and, in the case of a complete half cycle, has the largest area under the curve. If each half cycle is modulated to a 90% space ratio mark, the area under the curve is reduced by 10% and, as a result, the energy is reduced proportionally as seen in figure 12A. The original shape of the input sine wave is retained and, since modulation can be made high, possibly 10 s of KHz, output filtering is possible due to the smaller size of the coiled components making it a practical proposition. The overall effect is realized when the value of the square mean root (RMS), which is the square root of the mean square time of a quantity or, for a periodic quantity, the average is taken over a complete cycle and is also called effective value is correctly measured and the output voltage is seen to be reduced by a percentage similar to the space ratio ratio employed. Reduced voltage results in reduced current, thus resulting in reduced power consumed by an end user.

Since IGBT and FET devices are unipolar in nature, in the case of AC control, it is necessary to provide at least one drive control IGBT / FET 15 to control each half cycle. In addition, to avoid reverse deviation, steering diodes are used to route each half cycle to the appropriate device. Also, many IGBT and FET devices have a parasitic diode derived from the main element whereby connecting two IGBT or FET devices in reverse parallel would result in having two of the parasitic diodes in parallel reverse, thus rendering the inoperative arrangement as a controlling element.

Diodes 53 are connected via positive half-cycle transistor 54 and negative half-cycle control transistor 58 and ideally work for a purely resistive load or a reactive load ahead of current. However, when triggering a load with a power factor behind the current, when the current in an inductively reactive component is suddenly removed, as is the case when the modulation happens, the collapsing magnetic field tries to maintain the current. going, similar to an electronic flywheel, and produces an EMF that will increase in voltage until it finds a discharge path that will enable the release of energy. With this provision, this "against EMF" will cause the active components of the half cycle control element to fail. To prevent this from happening, additional IGBT / FET shunt control transistors 59, 60, 67 and 68 are placed in a shunt configuration.

During the positive half-cycle, the positive half-cycle control transistor 54 modulates and a diode 53 is active during the complete positive half-cycle. The second IGBT bypass control transistor 60 is fully wired and a diode 53 is active. Therefore, any opposite polarity voltages resulting from the counter EMF of the load are automatically fixed.

During the negative half cycle, other devices comprised in serial and branch networks are activated in a similar manner.

During switching transitions, a pointed pulse may be present which may remain for a very short period of time. The tip pulse is fixed by transorb devices 52, which are capable of absorbing large amounts of energy for a very short period of time and enabling very fast response time. Transorb devices 52 also fix any transient signals of main power supply due to lightning ignition or other sources that could otherwise damage the active components of half-cycle transistors or shunt transistors. Further, while each half-cycle transistor is pulse-width modulated, the other half-cycle transistor is turned on completely for the precise duration of the half-cycle. The work of these half cycle transistors reverses during the next half cycle. This process provides complete protection against EMF signals discussed above. This arrangement is necessary, especially close to zero crossing time when both branch elements are in transition.

Each of the IGBT / FET half-cycle control transistors 54 and 58 and the IGBT / FET branch control transistors 59, 60, 67 and 68 have separate port characteristics that require devices to be boosted to enable them to be powered on. . This booster voltage is preferably 12 Volts in magnitude and is preferably supplied by a floating power supply, preferably one for each pair. This is only possible since IBGT / FET devices are operated in common emitter mode for IGBTs and in common source mode for FETs; otherwise, four isolated power supplies would be required for each phase. Each pair requires a separate drive signal that is supplied by the individually coupled drives 66. These drives 66 make use of the isolated supplies and serve to turn each power device on and off very quickly. These drives 66 are active in both directions, which is required as the input capacitance of the power devices is high and must be actively discharged quickly at the off point and charged quickly at the on point. The problem with direct pulse width modulation is when inductively firing a reactive load such as when the IGBT modulates off, there is a counter EMF that needs to be fixed. Referring to Figure 12B, an incoming sine wave 39 is shown which is applied to the positive half-cycle control transistor 54 and the negative half-cycle control transistor 58. Typically, these half-cycle control transistors 54 and 58 are in "off" condition and need to be triggered to turn on. During the positive half-cycle, the positive half-cycle control transistor 54 is modulated and works in conjunction with a diode 53 to pass the modulated positive half-cycle to a line output terminal. The second IGBT shunt control transistor 60 is connected for half-cycle duration and operates in conjunction with a diode 53 to secure the EMF counter to ground. During the positive half-cycle, the negative half-cycle control transistor 58 is fully on and its on condition is sustained by a diode 53. These diodes 53 perform proper signal direction.

Due to the positive half-cycle modulation, a counter EMF signal occurs. Since the negative half-cycle control transistor 58 is on during this time, the negative EMF counter is passed through a _______ diode 53 to be fixed at the simultaneous AC positive half-cycle voltage.

Although no modulation is applied to the first branch control IGBT transistor 59 and the second branch control IGBT transistor 60, these transistors 59 and 60 work in conjunction with diodes 53 in a similar manner as set forth above.

As shown in Fig. 12B, which is an oscillogram of the IGBT-based voltage reduction means of the present invention, during the positive half-cycle 22, a drive signal is applied to the negative half-cycle control transistor 85 and a drive signal is applied to the second branch control IGBT transistor 87. During negative half cycle 23, a drive signal is applied to the positive half cycle control transistor 84 and a drive signal is applied to the first branch control IGBT transistor 86. Positive half-cycle drive signal 82 applied to positive half-cycle control transistor 54 and negative half-cycle drive signal 83 applied to negative half-cycle control transistor 58 are also shown.

Similarly, as shown in Fig. 12E, which is an oscillogram of the FET-based voltage reduction means of the present invention, during the positive half-cycle 22, a drive signal is applied to the negative half-cycle control transistor 85 and a The drive is applied to the second branch control FET transistor 89. During negative half cycle 23, a drive signal is applied to the positive half cycle control transistor 84 and a drive signal is applied to the first branch control transistor 88 Positive half-cycle drive signal 82 applied to positive half-cycle control transistor 54 and a negative half-cycle drive signal 83 applied to negative half-cycle control transistor 58 are also shown.

In summary, there are two fixation strategies used, the first for the positive half cycle and the second for the negative half cycle. During the positive half-cycle, when the positive half-cycle control transistor 54 is modulated, the negative half-cycle control transistor 58 and the second bypass control transistor 60 are on. During negative half-cycle, when negative half-cycle control transistor 58 is modulated, positive half-cycle control transistor 54 and first branch control IGBT transistor 59 are connected. The hardware used in the IGBT and FET 1 energy saving method 1 device of the present invention is identical with the only difference being the half cycle control IGBT / FET transistors 54 and 58 and the control IGBT / FET transistors 59, 60, 67 and 68.

The diagrams of the IGBT-based circuit unit of Figure 12C and the IGBT-based driver of Figure 12D, and the FET-based circuit unit of Figure 12E, and the FET-based driver of Figure 12F, are shown for comparison purposes.

Referring to Figure 13, a circuit diagram of a combined restart means and indicator means of the present invention is shown. The reset means, which is preferably at least one reset switch 13, and indicator means, which is preferably at least one LED 14, work together to indicate when the IGBT / IPST-based energy saving device and system. FET 1 are not working correctly and to allow a user to reboot device and system 1 as needed. Preferably, the LED 14 will indicate that the device and system 1 are working correctly by turning on / off. When in a fault condition, LED 14 preferably changes to an uneven pattern that is immediately obvious and recognizable as a fault condition. Figure 14 is a circuit diagram of a power supply unit 12 of an energizing means of the present invention. The power means, which is preferably at least one power supply unit 12, accepts a variety of inputs, including, but not limited to, 80Vrms to 265Vrms single phase, 80Vrms 600Vrms biphase, 80Vrms three-phase operation. at 600Vrms and 48Hz at 62Hz. The power supply unit 12 is completely isolated and doubly regulated in design. At the input, a diode composite rectifier 72 accepts single phase, biphase and three phase power. Power is applied to the switching regulator 90 and integrated circuit 62 via a transformer 57. In view of the large voltages existing across the DC terminals, the switching regulator 90 and integrated circuit 62 are supplemented by a FET transistor 73 employed in a FET Stack setting to raise your working voltage. Transformer secondary 57 has a diode 53 and a reservoir capacitor 56. The DC voltage across capacitor 56 is passed via the network resistors 63 and a Zener diode 75 to an optical isolator 65 and finally to the feedback terminals. . The use of optical isolator 65 ensures galvanic isolation between the supply input and output (6.4V DC). Finally, the output of the linear voltage regulators 81 (3.3VA DC) is passed to an operational amplifier 70, which is configured as a two resistor gain buffer unit 63 that fixes the bus voltage division. The main neutral is connected to this bus split point and also a zero ohm resistor. An inductor 78 isolates the digital supply bus (+ 3.3V) from the analog (3.3 VA) and reduces noise. Next, Figures 15A, 15B, 15C, 15D and 15E show the circuit unit of a communication medium of the present invention. The communication medium, which is preferably at least one USB communications interface 25, allows a user to monitor and set the parameters of the energy saving device and system 1 of the present invention as desired. The circuit unit of a USB communications interface 25 is shown in FIG. 15B, an isolator block 71 used in isolating the USB communications interface 25 of digital signal processor 10 is shown in FIG. 15C and first and second connectors 76 and 77 for connecting the communications medium to digital signal processor 10 are shown in figures 15D and 15E. Since the main printed circuit board is not isolated from neutral, it is necessary to galvanically isolate the USB communications interface 25. The digital signal processor 10's built-in serial communications feature is used to communicate serially with the media. Signals on the user side of the isolation barrier are applied to an integrated circuit 62, which is a device that takes serial data and translates it to USB data for direct connection to a 16-way computing device. a host USB port 74. The 5V power USB host is used to power the communication medium 46 and negates the need to provide isolated power from the unit. Preferably, there are two active light-emitting diodes 14, which indicate activity on the TX (transmit) and RX (receive) channels. Communications preferably operate at 9600 Baud, which is adequate due to the small amount of past data.

Although the inclusion of a communications medium is not necessary for the performance of the energy saving device and system 1, it is a feature that enables easier use of the device and system 1.

Finally, with reference to figures 16 and 17, screen images of a window interface 40 of the present invention are shown. The window interface 40 is displayed on computing device 16 and allows a user to monitor and configure power saving device and system 1 as desired. A main monitoring screen 41 is provided having a plurality of fields 42 in which an end user may adjust the energy saving device and system 1. For example, field 42 may include an operational mode field 43, a phase field 44, a starting field 45, a calibration field 46 and a working point field 47.

In operational field 43, a user can select the way in which he / she / he wishes to conserve energy. Modes include percentage of voltage reduction where Volts output is adjusted by a fixed percentage, percentage of savings reduction where Volts output is aimed to achieve a percentage of savings and voltage regulation where quadratic root output Average (RMS) is a preset value. Phase field 44 allows a user to select the phase type used in connection with device and energy saving system 1, ie single phase, biphase or three phases. Starting field 45 allows a user to configure system and device 1 to start randomly and / or to have a delayed start or "soft start" in which the user enters the delay time in seconds that the system and device will start. . Calibration field 46 allows a user to enter the desired precise balances and / or rotate the phases. The working point field 47 displays the user-selected fixings and shows the amount of energy saved using the device and power saving system, such as voltage regulation, voltage reduction percentage, or power saving reduction percentage. With respect to voltage percentage reduction, the lower RMS limit is set below the incoming voltage passed through it to allow the incoming voltage to be passed through when it is less than or equal to the lower voltage limit. With respect to savings percentage reduction, the lower RMS limit is set below the incoming voltage passed through it.

Indicators 48 are provided on window interface 40 displaying calculated operating current, operating voltage, line frequency, power saving and phase rotation.

A real time clock 49 may be incorporated into the window interface 40 to allow for additional voltage reduction programming for a predetermined time and a predetermined operating time, for example, by seasons, days of the week, hours of the day, to a predetermined uptime. Also, a user can program the energy saving device and system 1 to operate for various times of the day. Real-time clock 49 is set via a communications port or set to allow selection of set seasonal dates and times when, through experience, they are known to display overloaded power network. During these times , the system allows further reduction of regulated AC voltage, thereby reducing the load on the network.

Each multiple time can be set with its own percentage reduction or additional voltage drop. The digital electricity meter 50 provides a means for recording statistical data on power usage, power factor and surges. The digital electricity meter 50 also provides the ability to include power factor correction capacitors, operates on single phase, two phase and three phase systems, and operates on all voltages used in the world.

Can be used remotely or locally to disable or enable the user's power supply at will from the provider. Also, the digital electricity meter 50 can detect when the device and power saving system 1 have been bridged by a user trying to avoid paying for the power consumption in which the provider is alerted to such abuse. Finally, the use of real-time clock 49 enables a user and / or provider to reduce power consumption at selected times of a day or for a selected period of time, thereby alleviating and / or eliminating blackout conditions. It is to be understood that while a preferred embodiment of the invention is illustrated, it is not to be limited to the specific shape or arrangement of parts described and shown herein. It will be clear to those skilled in the art that various changes may be made without departing from the scope of the invention and the invention is not considered to be limited to what is shown and described in the specification and drawings.

Claims (96)

An energy saving device comprising: at least one phase input connection configured to input a predetermined amount of incoming power having at least one analog signal; at least one zero volt crossing point detector configured to determine at least one zero volt crossing point of at least one analog signal; at least one half-cycle identifier configured to identify at least one positive half-cycle of at least one analog signal and at least one negative half-cycle of at least one analog signal; at least one logic device configured to route at least one half positive cycle of at least one analog signal and at least one half negative cycle of at least one analog signal to at least one digital signal processor configured to process at least one analog signal; at least one drive control configured to reduce the predetermined amount of power by providing pulse width modulation for at least one analog signal to yield a reduced amount of energy, wherein at least one drive control is in electrical connection with at least a digital signal processor; and at least one phase output connection configured to produce the reduced amount of power, wherein at least one drive control comprises a positive half-cycle control transistor configured to provide pulse width modulation for at least one positive half-cycle. of at least one analog signal, a negative half-cycle control transistor configured to provide pulse width modulation for at least one negative half-cycle of at least one digital signal, a first branch control transistor, and a second control transistor. bypass switches configured as routing switches to lock a return electromotive force. An energy saving device according to claim 1 further comprising: at least one detection means for detecting the predetermined amount of energy. An energy saving device according to claim 1 further comprising: at least one analog signal conditioning device configured to condition the at least one analog signal to input at least one half-cycle identifier. An energy saving device according to claim 1 further comprising: at least one phase loss detection device configured to prepare at least one analog signal for inputting at least one half-cycle identifier. An energy saving device according to claim 1 further comprising: at least one phase rotation device configured to prepare at least one analog signal for inputting at least one half-cycle identifier. The energy saving device of claim 1 further comprising: at least one power supply unit in electrical connection with the energy saving device configured to power the energy saving device. An energy saving device according to claim 1 further comprising: at least one floating power supply in electrical connection with at least one drive control. Energy saving device according to claim 1, further comprising: at least one computing device in electrical connection with energy saving device. An energy saving device according to claim 1 further comprising: at least one communications interface in electrical connection with at least one digital signal processor. An energy-saving device according to claim 1 further comprising: at least one reset switch in electrical connection with at least one digital signal processor. Energy saving device according to claim 10, further comprising: at least one LED in electrical connection with at least one reset switch. An energy saving device according to claim 1 further comprising: at least one digital electricity meter in electrical connection with at least one digital signal processor. Energy saving device according to claim 1, wherein the positive half-cycle control transistor and negative half-cycle control transistor are IGBT devices. Energy saving device according to claim 1, wherein the positive half-cycle control transistor and negative half-cycle control transistor are FET devices. Energy saving device according to claim 1, wherein the first branch control transistor and the second branch control transistor are IGBT devices. Energy saving device according to claim 1, wherein the first shunt control transistor and the second shunt control transistor are FET devices. Energy saving device according to claim 1, wherein at least one digital signal processor comprises at least one real time clock. Power-saving device according to claim 1, wherein at least one digital signal processor comprises at least one analog to digital converter. Power-saving device according to claim 1, wherein at least one digital signal processor is in electrical connection with at least one logic device. Energy saving device according to claim 1, wherein at least one logic device is in electrical connection with at least one half-cycle identifier. An energy saving device according to claim 1, wherein at least one logic device is in electrical connection with at least one zero-volt crossing point detector. Energy saving device according to claim 1, wherein at least one logic device is in electrical connection with at least one drive control. Energy saving device according to claim 4, wherein at least one logic device is in electrical connection with at least one phase loss detection device. Energy saving device according to claim 5, wherein at least one logic device is in electrical connection with at least one phase rotation device. An energy-saving device according to claim 2, wherein at least one sensing means measures the predetermined amount of incoming energy through galvanic isolation. An energy-saving device according to claim 1, wherein at least one zero-volt crossing point detector comprises a comparator and a Schmidt buffer. Energy saving device according to claim 26, wherein the comparator has a reference point of approximately half supply voltage. An energy saving device according to claim 3, wherein at least one analog signal conditioning device comprises a first filter for removing and reducing harmonics and transients or interference signals from the at least one analog signal. An energy saving device according to claim 28, wherein at least one analog signal conditioning device comprises a second filter to allow at least one phase change if necessary. Power-saving device according to claim 9, wherein the at least one communications interface is at least one USB communications interface. The power saver device of claim 9, wherein at least one communications interface allows a user to monitor the predetermined amount of power introduced into the power saver device and the reduced amount of energy emitted from the device. energy saving. Energy-saving device according to claim 1, wherein at least one half-cycle identifier identifies an absolute zero crossing of the at least one analog signal. Energy-saving device according to claim 1, wherein at least one logic device is programmable. Energy-saving device according to claim 1, wherein at least one logic device operates in real time. Energy saving device according to claim 1, wherein at least one phase input connection is a single phase input system. Energy-saving device according to claim 1, wherein at least one phase output connection is a single phase output system. Energy-saving device according to claim 1, wherein at least one phase input connection is a two-phase input system. Energy saving device according to claim 1, wherein at least one phase output connection is a two phase output system. Energy saving device according to claim 1, wherein at least one phase input connection is a three phase input system. An energy saving device according to claim 1, wherein at least one phase output connection is a three phase output system. 41. An energy saving system comprising: an energy saving device comprising: at least one phase input connection configured to input a predetermined amount of incoming power having at least one analog signal, at least one crossing point detector at zero volt configured to determine at least one zero-volt crossing point of at least one analog signal, at least one half-cycle identifier configured to identify at least one positive half-cycle of at least one analog signal and at least one negative half-cycle of at least one analog signal, at least one logic device configured to route at least one positive half cycle of at least one analog signal and at least one negative half cycle of at least one analog signal to at least one digital signal processor configured to process at least one analog signal, at least one cone communications interface electrical connection with at least one digital signal processor, at least one drive control configured to reduce the predetermined amount of power by providing pulse width modulation to at least one analog signal to yield a reduced amount of power, wherein at least a drive control is in electrical connection to at least one digital signal processor, and at least one phase output connection configured to produce the smallest amount of power, wherein at least one drive control comprises a medium control transistor. positive cycle configured to provide pulse width modulation for at least one half positive cycle of at least one analog signal, a negative half cycle control transistor configured to provide pulse width modulation for at least one negative half cycle of at least a digital signal, a first branch control transistor, and a second shunt control transistors configured as routing switches to lock a return electromotive force; a power supply unit in electrical connection with the energy saving device configured to power the energy saving device; and a computing device comprising a window interface and a communications interface in electrical connection with at least one power saving device communications interface. Energy saving system according to claim 41, further comprising: at least one detection means for detecting the predetermined amount of energy. The power saving system of claim 41 further comprising: at least one reset switch in electrical connection with at least one digital signal processor of the power saving device. An energy saving system according to claim 43 further comprising: at least one LED in electrical connection with at least one reset switch. An energy-saving system according to claim 41 further comprising: at least one conditioning device configured to condition the at least one analog signal to input at least one half-cycle identifier. The power saving system of claim 41, further comprising: at least one phase loss detection device configured to prepare the at least one analog signal for inputting at least one half-cycle identifier. The power saving system of claim 41 further comprising: at least one phase rotation device configured to prepare the at least one analog signal for inputting at least one half-cycle identifier. An energy-saving system according to claim 41 further comprising: at least one floating power supply in electrical connection with at least one drive control. The energy saving system of claim 41 further comprising: at least one digital electricity meter in electrical connection with at least one digital signal processor. The energy saving system of claim 41, wherein the positive half-cycle control transistor and negative half-cycle control transistor are IGBT devices. Energy saving system according to claim 41, wherein the positive half-cycle control transistor and negative half-cycle control transistor are FET devices. The energy saving system of claim 41, wherein the first branch control transistor and the second branch control transistor are IGBT devices. The power saving system of claim 41, wherein the first branch control transistor and the second branch control transistor are FET devices. The power saving system of claim 41, wherein at least one digital signal processor comprises at least one real time clock. Energy-saving system according to claim 41, wherein at least one digital signal processor comprises at least one analog-digital converter. The power saving system of claim 41, wherein at least one digital signal processor is in electrical connection with at least one logic device. The energy saving system of claim 41, wherein at least one logic device is in electrical connection with at least one half-cycle identifier. Energy saving system according to claim 41, wherein at least one logic device is in electrical connection with at least one zero-volt crossing point detector. Energy saving system according to claim 41, wherein at least one logic device is in electrical connection with at least one drive control. Energy saving system according to claim 46, wherein at least one logic device is in electrical connection with at least one phase loss detection device. Energy saving system according to claim 47, wherein at least one logic device is in electrical connection with at least one phase rotation device. Energy saving system according to claim 42, wherein at least one sensing means measures the predetermined amount of incoming energy through galvanic isolation. An energy-saving system according to claim 41, wherein at least one zero-volt crossing point detector comprises a comparator and a Schmidt buffer. Energy saving system according to claim 63, wherein the comparator has a reference point of approximately half supply voltage. An energy-saving system according to claim 45, wherein at least one signal conditioning device is provided. An analog filter comprises a first filter for removing and reducing harmonics and transients or interference signals from at least one analog signal. A power-saving system according to claim 65, wherein at least one analog signal conditioning device has a second filter to allow at least one phase change if necessary. A power saving system according to claim 41, wherein at least one communications interface is at least one USB communications interface. Energy-saving system according to claim 41, wherein at least one communications interface allows a user to monitor the predetermined amount of energy introduced into the energy-saving system and the reduced amount of energy emitted from the system. energy saving. The power saving system of claim 41, wherein at least one half-cycle identifier identifies an absolute zero crossing of at least one analog signal. The energy saving system of claim 41, wherein at least one logic device is programmable. Energy saving system according to claim 41, wherein at least one logic device operates in real time. Energy saving system according to claim 41, wherein at least one phase input connection is a single phase input system. Energy saving system according to claim 41, wherein at least one phase output connection is a single phase output system. Energy-saving system according to claim 41, wherein at least one phase input connection is a two-phase input system. Energy saving system according to claim 41, wherein at least one phase output connection is a two-phase output system. An energy saving system according to claim 41, wherein at least one phase input connection is a three phase input system. Energy saving system according to claim 41, wherein at least one phase output connection is a three phase output system. Energy saving system comprising: means for inputting a predetermined amount of incoming power having at least one analog signal; means for determining at least one zero-volt crossing point of at least one conditioned analog signal; means for identifying at least one positive half cycle and at least one negative half cycle of at least one analog signal; means for routing at least one positive half cycle of at least one analog signal and at least one negative half cycle of at least one analog signal to at least one processing means for processing at least one analog signal; means for reducing at least one analog signal from the predetermined amount of energy to yield a reduced amount of energy; and a half to emit the reduced energy. Energy saving system according to claim 78, further comprising: means for detecting the predetermined amount of incoming energy. An energy saving system according to claim 78, further comprising: means for conditioning at least one digital signal. Energy saving system according to claim 78, further comprising: means for detecting lost phase of at least one digital signal. Energy saving system according to claim 78, further comprising: means for phase rotating at least one digital signal. Energy saving system according to claim 78, further comprising: means for communicating with at least one computing device. Energy saving system according to claim 78, further comprising: means for resetting the energy saving system. An energy saving system according to claim 78, wherein the reducing means comprises a positive half-cycle control transistor configured to provide pulse width modulation for at least one positive half-cycle of at least one signal. analog, a negative half-cycle control transistor configured to provide pulse width modulation for at least one negative half-cycle of at least one analog signal, and a first branch control transistor and a second branch control transistor configured as routing switches to lock a return electromotive force. Energy-saving system according to claim 85, wherein the positive half-cycle control transistor and negative half-cycle control transistor are IGBT devices. The energy saving system of claim 85, wherein the positive half-cycle control transistor and negative half-cycle control transistor are FET devices. The power saving system of claim 85, wherein the first branch control transistor and the second branch control transistor are IGBT devices. An energy saving system according to claim 85, wherein the first branch control transistor and the second branch control transistor are FET devices. 90. A method for reducing energy consumption by an energy saving device comprising: introducing a predetermined amount of energy having at least one analog signal; determining at least one zero-volt crossing point of at least one analog signal; identifying at least one half positive cycle of at least one analog signal and at least one half negative cycle of at least one analog signal; processing at least one analog signal; reducing the predetermined amount of energy by providing pulse width modulation for at least one analog signal; and emit the reduced amount of energy. 91. The method of claim 90, comprising: detecting the predetermined amount of energy. 92. The method of claim 90, comprising: conditioning at least one analog signal. 93. The method of claim 90, comprising: detecting phase loss of at least one analog signal. 94. The method of claim 90, comprising: determining the phase rotation of at least one analog signal. A method according to claim 90 further comprising: prorating at least one positive half-cycle of at least one analog signal and at least one negative half-cycle of at least one analog signal to processing medium prior to processing. 96. The method of claim 90, wherein reducing comprises: providing pulse width modulation for at least one positive half cycle of at least one analog signal; providing pulse width modulation for at least one negative half cycle of at least one analog signal; and providing a plurality of routing switches for braking a return electromotive force.