BR112022003542A2 - Realização de operações equivalentes a xnor ao ajustar limites de coluna de uma matriz de computação na memória - Google Patents

Realização de operações equivalentes a xnor ao ajustar limites de coluna de uma matriz de computação na memória

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Publication number
BR112022003542A2
BR112022003542A2 BR112022003542A BR112022003542A BR112022003542A2 BR 112022003542 A2 BR112022003542 A2 BR 112022003542A2 BR 112022003542 A BR112022003542 A BR 112022003542A BR 112022003542 A BR112022003542 A BR 112022003542A BR 112022003542 A2 BR112022003542 A2 BR 112022003542A2
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BR
Brazil
Prior art keywords
memory
matrix
xnor
bounds
adjusting column
Prior art date
Application number
BR112022003542A
Other languages
English (en)
Inventor
Edward Teague
Max Welling
Zhongze Wang
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of BR112022003542A2 publication Critical patent/BR112022003542A2/pt

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G06N3/048—Activation functions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
    • G06F15/7821—Tightly coupled to memory, e.g. computational memory, smart memory, processor in memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G06N3/045—Combinations of networks
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • G06N3/065—Analogue means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/08—Learning methods
    • G06N3/084—Backpropagation, e.g. using gradient descent
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G06N3/044—Recurrent networks, e.g. Hopfield networks
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G06N3/047—Probabilistic or stochastic networks
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/08—Learning methods

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Health & Medical Sciences (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Biomedical Technology (AREA)
  • Biophysics (AREA)
  • Software Systems (AREA)
  • General Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • Molecular Biology (AREA)
  • General Health & Medical Sciences (AREA)
  • Evolutionary Computation (AREA)
  • Data Mining & Analysis (AREA)
  • Computational Linguistics (AREA)
  • Mathematical Physics (AREA)
  • Artificial Intelligence (AREA)
  • Computer Hardware Design (AREA)
  • Neurology (AREA)
  • Probability & Statistics with Applications (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Image Analysis (AREA)
  • Image Processing (AREA)

Abstract

realização de operações equivalentes a xnor ao ajustar limites de coluna de uma matriz decomputação na memória. trata-se de um método que realiza operações equivalentes a xnor ao ajustar limites de coluna de uma matriz de computação na memória de uma rede neural artificial. o método inclui ajustar um limite de ativação gerado para cada coluna da matriz de computação na memória com base uma função de um valor de peso e um valor de ativação. o método também inclui calcular uma referência de corrente de polarização de conversão com base em um valor de entrada de um vetor de entrada para a matriz de computação na memória, a matriz de computação na memória sendo programada com um conjunto de pesos. o limite de ativação ajustado e a referência de corrente de polarização de conversão são usados como um limite para determinar os valores de saída da matriz de computação na memória.
BR112022003542A 2019-09-09 2020-09-08 Realização de operações equivalentes a xnor ao ajustar limites de coluna de uma matriz de computação na memória BR112022003542A2 (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US16/565,308 US11562212B2 (en) 2019-09-09 2019-09-09 Performing XNOR equivalent operations by adjusting column thresholds of a compute-in-memory array
PCT/US2020/049754 WO2021050440A1 (en) 2019-09-09 2020-09-08 Performing xnor equivalent operations by adjusting column thresholds of a compute-in-memory array

Publications (1)

Publication Number Publication Date
BR112022003542A2 true BR112022003542A2 (pt) 2022-05-24

Family

ID=72614002

Family Applications (1)

Application Number Title Priority Date Filing Date
BR112022003542A BR112022003542A2 (pt) 2019-09-09 2020-09-08 Realização de operações equivalentes a xnor ao ajustar limites de coluna de uma matriz de computação na memória

Country Status (8)

Country Link
US (1) US11562212B2 (pt)
EP (1) EP4028956A1 (pt)
JP (1) JP2022547460A (pt)
KR (1) KR20220058897A (pt)
CN (1) CN114207628A (pt)
BR (1) BR112022003542A2 (pt)
TW (1) TW202125339A (pt)
WO (1) WO2021050440A1 (pt)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11562212B2 (en) * 2019-09-09 2023-01-24 Qualcomm Incorporated Performing XNOR equivalent operations by adjusting column thresholds of a compute-in-memory array
US11295430B2 (en) * 2020-05-20 2022-04-05 Bank Of America Corporation Image analysis architecture employing logical operations
US11688457B2 (en) * 2020-12-26 2023-06-27 International Business Machines Corporation Using ferroelectric field-effect transistors (FeFETs) as capacitive processing units for in-memory computing
TWI775402B (zh) * 2021-04-22 2022-08-21 臺灣發展軟體科技股份有限公司 資料處理電路及故障減輕方法
US11782642B2 (en) * 2021-06-14 2023-10-10 Western Digital Technologies, Inc. Systems and methods of determining degradation in analog compute-in-memory (ACIM) modules
US20230053294A1 (en) * 2021-08-13 2023-02-16 Taiwan Semiconductor Manufacturing Co., Ltd. Bitwise product-sum accumulations with skip logic
US11373719B1 (en) 2021-08-30 2022-06-28 Texas Instruments Incorporated Contact layer traces to program programmable ROM
CN117271145B (zh) * 2023-11-22 2024-02-27 电子科技大学 一种基于混合计算架构的多任务智能处理器

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0652132A (ja) * 1992-07-28 1994-02-25 Mitsubishi Electric Corp 並列演算半導体集積回路装置およびそれを用いたシステム
US10949736B2 (en) * 2016-11-03 2021-03-16 Intel Corporation Flexible neural network accelerator and methods therefor
US10699778B2 (en) 2017-04-28 2020-06-30 Arizona Board Of Regents On Behalf Of Arizona State University Static random access memory (SRAM) cell and related SRAM array for deep neural network and machine learning applications
US11354562B2 (en) 2018-01-03 2022-06-07 Silicon Storage Technology, Inc. Programmable neuron for analog non-volatile memory in deep learning artificial neural network
US10650806B2 (en) * 2018-04-23 2020-05-12 Cerence Operating Company System and method for discriminative training of regression deep neural networks
US11562212B2 (en) * 2019-09-09 2023-01-24 Qualcomm Incorporated Performing XNOR equivalent operations by adjusting column thresholds of a compute-in-memory array
US11544547B2 (en) * 2020-06-22 2023-01-03 Western Digital Technologies, Inc. Accelerating binary neural networks within latch structure of non-volatile memory devices

Also Published As

Publication number Publication date
KR20220058897A (ko) 2022-05-10
US11562212B2 (en) 2023-01-24
EP4028956A1 (en) 2022-07-20
CN114207628A (zh) 2022-03-18
TW202125339A (zh) 2021-07-01
US20210073619A1 (en) 2021-03-11
JP2022547460A (ja) 2022-11-14
WO2021050440A1 (en) 2021-03-18

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