BR112018005836A2 - método de depuração, processador de múltiplos núcleos e dispositivo de depuração - Google Patents

método de depuração, processador de múltiplos núcleos e dispositivo de depuração

Info

Publication number
BR112018005836A2
BR112018005836A2 BR112018005836-0A BR112018005836A BR112018005836A2 BR 112018005836 A2 BR112018005836 A2 BR 112018005836A2 BR 112018005836 A BR112018005836 A BR 112018005836A BR 112018005836 A2 BR112018005836 A2 BR 112018005836A2
Authority
BR
Brazil
Prior art keywords
execution
present
debugging
interrupt
core processor
Prior art date
Application number
BR112018005836-0A
Other languages
English (en)
Chinese (zh)
Inventor
Wang Mingfa
Yu Gang
Wang Haichuan
Original Assignee
Huawei Technologies Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Huawei Technologies Co., Ltd. filed Critical Huawei Technologies Co., Ltd.
Publication of BR112018005836A2 publication Critical patent/BR112018005836A2/pt

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/36Preventing errors by testing or debugging software
    • G06F11/362Software debugging
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/22Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G06F11/2236Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test CPU or processors
    • G06F11/2242Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test CPU or processors in multi-processor systems, e.g. one processor becoming the test master
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/36Preventing errors by testing or debugging software
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/36Preventing errors by testing or debugging software
    • G06F11/362Software debugging
    • G06F11/3636Software debugging by tracing the execution of the program
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/36Preventing errors by testing or debugging software
    • G06F11/362Software debugging
    • G06F11/3648Software debugging using additional hardware
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/36Preventing errors by testing or debugging software
    • G06F11/3664Environments for testing or debugging software
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46Multiprogramming arrangements
    • G06F9/54Interprogram communication
    • G06F9/545Interprogram communication where tasks reside in different layers, e.g. user- and kernel-space

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Software Systems (AREA)
  • Debugging And Monitoring (AREA)

Abstract

as formas de realização da presente invenção referem-se ao campo das tecnologias de computador. as formas de realização da presente invenção fornecem um método de depuração, incluindo: iniciar, por um núcleo a do processador de múltiplos núcleos após completar a execução de uma rotina de processamento de eventos pré-configurados, para interromper a execução e enviar um sinal de interrupção de execução para outros núcleos em um processo de interromper de correr; depois de receber uma primeira instrução de terminação de interrupção e retomar a execução, executando, pelo núcleo a, uma função de coleta de informações de depuração para coletar informações de depuração do evento predefinido e interromper a execução após concluir a execução da função de coleta de informações de depuração; e depois de receber uma segunda instrução de terminação de interrupção e retomar a execução, enviando, pelo núcleo a, uma instrução de retomada de execução para os outros núcleos. por meio das soluções técnicas fornecidas nas formas de realização da presente invenção, o código do modo kernel e o código do modo de usuário podem ser mascarados em uma mesma plataforma de depuração. além disso, as formas de realização da presente invenção proporcionam ainda um aparelho de depuração correspondente.
BR112018005836-0A 2015-09-25 2016-09-24 método de depuração, processador de múltiplos núcleos e dispositivo de depuração BR112018005836A2 (pt)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
CN201510623211.5A CN105354136B (zh) 2015-09-25 2015-09-25 一种调试方法、多核处理器和调试设备
CN201510623211.5 2015-09-25
PCT/CN2016/099995 WO2017050286A1 (zh) 2015-09-25 2016-09-24 一种调试方法、多核处理器和调试设备

Publications (1)

Publication Number Publication Date
BR112018005836A2 true BR112018005836A2 (pt) 2018-10-09

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
BR112018005836-0A BR112018005836A2 (pt) 2015-09-25 2016-09-24 método de depuração, processador de múltiplos núcleos e dispositivo de depuração

Country Status (6)

Country Link
US (1) US10409709B2 (pt)
EP (1) EP3343377A4 (pt)
KR (1) KR20180057687A (pt)
CN (1) CN105354136B (pt)
BR (1) BR112018005836A2 (pt)
WO (1) WO2017050286A1 (pt)

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JP6981920B2 (ja) * 2018-05-25 2021-12-17 ルネサスエレクトロニクス株式会社 半導体装置、およびデバッグ方法
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Also Published As

Publication number Publication date
KR20180057687A (ko) 2018-05-30
EP3343377A1 (en) 2018-07-04
US20180210811A1 (en) 2018-07-26
US10409709B2 (en) 2019-09-10
WO2017050286A1 (zh) 2017-03-30
CN105354136A (zh) 2016-02-24
EP3343377A4 (en) 2018-09-12
CN105354136B (zh) 2018-06-15

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B06U Preliminary requirement: requests with searches performed by other patent offices: procedure suspended [chapter 6.21 patent gazette]
B11B Dismissal acc. art. 36, par 1 of ipl - no reply within 90 days to fullfil the necessary requirements