BR112018003254A2 - sistemas e métodos para atribuir restrições de grupo em um layout de circuito integrado - Google Patents

sistemas e métodos para atribuir restrições de grupo em um layout de circuito integrado

Info

Publication number
BR112018003254A2
BR112018003254A2 BR112018003254A BR112018003254A BR112018003254A2 BR 112018003254 A2 BR112018003254 A2 BR 112018003254A2 BR 112018003254 A BR112018003254 A BR 112018003254A BR 112018003254 A BR112018003254 A BR 112018003254A BR 112018003254 A2 BR112018003254 A2 BR 112018003254A2
Authority
BR
Brazil
Prior art keywords
cell
group
constraints
circuit layout
restrictions
Prior art date
Application number
BR112018003254A
Other languages
English (en)
Inventor
Riviere-Cazaux Lionel
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of BR112018003254A2 publication Critical patent/BR112018003254A2/pt

Links

Classifications

    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
    • G03F7/70433—Layout for increasing efficiency or for compensating imaging errors, e.g. layout of exposure fields for reducing focus errors; Use of mask features for increasing efficiency or for compensating imaging errors
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
    • G03F7/70466—Multiple exposures, e.g. combination of fine and coarse exposures, double patterning or multiple exposures for printing a single feature
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2111/00—Details relating to CAD techniques
    • G06F2111/04—Constraint-based CAD

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Preparing Plates And Mask In Photomechanical Process (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

métodos e equipamentos para configurar restrições de grupo dos recursos das células para um processo de multi-padronização são fornecidos. o equipamento determina os recursos dentro de um layout de circuito, restrições de distância para pelo menos um dos recursos, restrições de grupo para os recursos com base nas restrições de distância, as restrições de grupo definindo limites em grupos atribuíveis a cada um dos recursos. além disso, o equipamento recebe um layout de circuito integrado que inclui uma pluralidade de células contíguas. o equipamento então determina se as restrições de grupo de uma segunda célula conflitam com as restrições de grupo de uma primeira célula, a segunda célula adjacente à primeira célula e configura um subconjunto das restrições de grupo da segunda célula com base nas restrições de grupo da primeira célula e com base nas restrições de grupo da segunda célula que estão em conflito com as restrições de grupo da primeira célula.
BR112018003254A 2015-08-21 2016-07-01 sistemas e métodos para atribuir restrições de grupo em um layout de circuito integrado BR112018003254A2 (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14/832,669 US9842185B2 (en) 2015-08-21 2015-08-21 Systems and methods for group constraints in an integrated circuit layout
PCT/US2016/040700 WO2017034678A1 (en) 2015-08-21 2016-07-01 Systems and methods for assigning group constraints in an integrated circuit layout

Publications (1)

Publication Number Publication Date
BR112018003254A2 true BR112018003254A2 (pt) 2018-09-25

Family

ID=56618226

Family Applications (1)

Application Number Title Priority Date Filing Date
BR112018003254A BR112018003254A2 (pt) 2015-08-21 2016-07-01 sistemas e métodos para atribuir restrições de grupo em um layout de circuito integrado

Country Status (7)

Country Link
US (1) US9842185B2 (pt)
EP (1) EP3338141A1 (pt)
JP (1) JP2018527616A (pt)
KR (1) KR20180021910A (pt)
CN (1) CN107924135B (pt)
BR (1) BR112018003254A2 (pt)
WO (1) WO2017034678A1 (pt)

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US9971863B2 (en) * 2016-03-01 2018-05-15 Taiwan Semiconductor Manufacturing Co., Ltd. Rule checking for multiple patterning technology
KR102611888B1 (ko) * 2016-11-07 2023-12-11 삼성전자주식회사 스위칭 액티비티에 기초한 반도체 장치의 배치 방법 및 이에 의해 제조된 반도체 장치
US10274829B2 (en) * 2016-12-09 2019-04-30 Taiwan Semiconductor Manufacturing Co., Ltd. Multiple patterning decomposition and manufacturing methods for IC
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Also Published As

Publication number Publication date
CN107924135A (zh) 2018-04-17
KR20180021910A (ko) 2018-03-05
CN107924135B (zh) 2019-08-20
WO2017034678A1 (en) 2017-03-02
US9842185B2 (en) 2017-12-12
JP2018527616A (ja) 2018-09-20
EP3338141A1 (en) 2018-06-27
US20170053057A1 (en) 2017-02-23

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Legal Events

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B11A Dismissal acc. art.33 of ipl - examination not requested within 36 months of filing
B11Y Definitive dismissal acc. article 33 of ipl - extension of time limit for request of examination expired