BR112017014886B1 - RECEIVER SYSTEM THAT RECEIVES A PLURALITY OF CARRIERS AND GENERATES ONE OR A PLURALITY OF FLOWS AND RECEIVING SYSTEM THAT RECEIVES A PLURALITY OF CARRIERS AND GENERATES A FLOW - Google Patents

Abstract

RECEIVER SYSTEM THAT RECEIVES A PLURALITY OF CARRIERS AND GENERATES ONE OR A PLURALITY OF FLOWS, AND, TRANSMISSION SYSTEM THAT DIVIDES AN INPUT SIGNAL AND EMITS A PLURALITY OF TRANSMISSION SIGNALS. A receiver system of the present disclosure includes: a plurality of demodulators (201 to 204); a complement (211) that generates a flow based on an output from each of the demodulators; a selector (212) that selects and outputs one between an output of one of the demodulators, namely the demodulator (201), and a stream of the complement (211); and a back-end processor (300) that generates an output for a monitor based on an output from the selector (212) and the other demodulators, namely the demodulators (202 to 204). The selector (212) selects an output of the demodulator (201) in a single transmission channel mode, and selects the complement stream (211) in a multiple transmission channel mode.

Description

TECHNICAL FIELD OF THE INVENTION

[001] The present disclosure relates to a transmission and receiver system for split data.

HISTORY OF THE TECHNIQUE

[002] Split transmission using multiple carriers (hereinafter “multiple carrier transmission system”) in which a TS (transport stream) that has a capacity exceeding a carrier’s transmission capacity and therefore cannot be transmitted in the Transmission with a single carrier (hereinafter “single carrier transmission”) is divided and multiplexed into structures, and in which data is transmitted using a plurality of carriers, is known in the art (see Patent Document 1; Non-Patent Document 1).

[003] Furthermore, a technique for efficient simultaneous transmission of a TS packet and a VL (variable length) packet is known in the art (see Patent Document 2).

QUOTE LIST PATENT DOCUMENTS

[004] Patent Document 1: Unexamined Japanese Patent Publication No. 2012-209675.

[005] Patent Document 2: Unexamined Japanese Patent Publication No. 2013-175949.

NON-PATENTARY DOCUMENTS

[006] Non-Patent Document 1: MIC: Information and Communications Council/Information and Communications Technology Subcommittee/Broadcasting System Commission Report (Draft), Chapter 6: Technical Prerequisites for Multiple Carrier Transmission (ITU-T J.183), 11.07. 2014, p. 63-92.

SUMMARY OF THE INVENTION TECHNICAL PROBLEM

[007] The present disclosure provides a receiving system that performs multiple carrier transmission by adding a complement that serves as a combiner to an existing receiving system that receives a plurality of carriers.

[008] Furthermore, the present disclosure provides a receiving system that performs multiple carrier transmission by sequential combination in a plurality of demodulators.

[009] Furthermore, the present disclosure provides a transmission system and a receiving system that performs multiple carrier transmission, which can safely absorb a TDOA (time difference of arrival) from a plurality of channels.

[0010] Also, the present disclosure provides a data allocation method and a data acquisition method that can safely convert a VL packet into a transmission packet of a fixed length.

SOLUTION TO THE PROBLEM

[0011] A receiving system in accordance with the present disclosure receives, for example, a plurality of carriers and generates one or a plurality of streams, the system including: a first demodulator that receives and processes a first transmission signal; a second demodulator that receives and processes a second transmission signal different from the first transmission signal; a combiner that generates a stream based on at least one output of the first demodulator and one output of the second demodulator; a selector that receives an output from the first demodulator and a stream from the combiner as inputs, and which selects and outputs one between the output from the first demodulator and a stream from the combiner; and a back-end processor that receives an output of the selector and the output of the second demodulator as inputs, and that generates an output to a monitor, the selector selecting the output of the first demodulator in a single transmit channel receiver mode, and which selects the one stream in one receiver mode in multiple transmission channel.

[0012] Furthermore, a receiving system in accordance with the present disclosure may, for example, receive multiple carriers and generate one or a plurality of streams, the system including: a first demodulator having a first memory that receives and processes a first transmission signal; a second demodulator having a second memory that receives and processes a second transmission signal different from the first transmission signal; one or more additional demodulators; and a back-end processor that generates an output to a monitor, wherein the demodulators including the first demodulator and the second demodulator are all connected in series, the demodulators are sorted into a front-end demodulator, which receives data from a first carrier and which does not input demodulated data into other demodulators, a back-end demodulator, which receives data from a second carrier and which at least partially produces demodulation results to the back-end processor, and intermediate demodulators, which do not include the front-end demodulator and the rear demodulator, and the front demodulator produces an output to one of the intermediate demodulators, and each of the intermediate demodulators both produces demodulation results of data from a carrier corresponding to the respective demodulator and an output from a previous demodulator as part of a flow to a subsequent demodulator.

[0013] A transmission system in accordance with the present disclosure may, for example, divide an input signal and produce a plurality of transmission signals, the system including: a divider that divides an input signal into a plurality of signals and outputs of these signals; an identification data adder, which adds identification data to a predetermined group of signals divided between the signals divided by the divider; a first modulator, which processes a first split signal to which identification data has been added, and produces a first transmission signal; and a second modulator, which processes a second split signal to which the identification data has been added, and produces a second transmission signal.

[0014] A receiving system, in accordance with the present disclosure, may, corresponding to the transmission system, for example, receive a plurality of carriers and generate a stream, the receiving system including: a first demodulator that receives and processes a first signal transmission; a second demodulator that receives and processes a second transmission signal different from the first transmission signal; an identification data detector receiving an output of the first demodulator and an output of the second demodulator as inputs, and identifying predetermined identification data, which is included in the output of the first demodulator and the output of the second demodulator; and a delay correction signal generator which, based on identification results obtained from the identification data detector, uses predetermined processing to determine a subject for adjusting a time difference between an output of the first demodulator and an output of the second demodulator.

[0015] A data allocation method, in accordance with the present disclosure, may include, for example: dividing data from a VL packet; insertion, in a transmission packet 1 of a fixed length, of initial position information indicating a starting position of a VL packet 2, which is later allocated in a case where, in the allocation in a transmission packet of a length fixed, the allocation of a VL packet 1 has been completed somewhere along the transmission packet 1; and subsequent allocation of VL packet 2, wherein, instead of the initial position information 1, the invalid data is allocated to transmit packet 1 in a case where allocation of VL packet 2 to transmit packet 1 is not performed if, after the allocation of VL packet 1 has been completed at some location along transmission packet 1, position 1 start information indicating a starting position of the VL packet 2 that is allocated next is inserted.

[0016] Furthermore, a data acquisition method according to the present disclosure may be, for example, a data acquisition method for acquiring a VL packet allocated to a transmission packet of a fixed length which corresponds to the data allocation method, the processing being carried out interpreting that, in a case where the acquisition of data forming a VL packet 1 has been terminated within a transmission packet 1 of a fixed length, and where no initial information position indicating a starting position of a following VL 2 packet was inserted into the fixed length transmission 1 packet, in addition to the data forming the VL 1 packet, invalid data is included in the fixed length transmission 1 packet.

ADVANTAGES OF THE INVENTION

[0017] According to the present disclosure, a receiving system for multiple carrier transmission can be provided by adding a complement that serves as a combiner to an existing receiving system that receives a plurality of carriers.

[0018] Furthermore, according to the present disclosure, a receiving system for multiple carrier transmission can be provided by performing a sequential combination on a plurality of demodulators.

[0019] Furthermore, according to the present disclosure, a transmission system and a receiving system for multiple carrier transmission can be provided that can safely absorb a TDOA from a plurality of channels.

[0020] Furthermore, in accordance with the present disclosure, a data allocation method and a data acquisition method can be provided that allows the secure conversion of a VL packet into a transmission packet of a fixed length .

BRIEF DESCRIPTION OF THE DRAWINGS

[0021] [FIG. 1] FIG. 1 is a block diagram showing a configuration of a transmission and receiver system in accordance with the present disclosure.

[0022] [FIG. 2] FIG. 2 is a timing diagram showing an example of data configuration in the transmission system and system shown in FIG. 1.

[0023] [FIG. 3] FIG. 3 is a block diagram showing a configuration of a receiving system according to a first embodiment.

[0024] [FIG. 4] FIG. 4 is a block diagram showing a variation of the receiver system shown in FIG. 3.

[0025] [FIG. 5] FIG. 5 is a block diagram showing another variation of the receiver system shown in FIG. 3.

[0026] [FIG. 6] FIG. 6 is a block diagram showing yet another variation of the receiver system shown in FIG. 3.

[0027] [FIG. 7] FIG. 7 is a timed diagram for explaining how the receiver system shown in FIG. operates. 6.

[0028] [FIG. 8] FIG. 8 is a block diagram showing yet another variation of the receiver system shown in FIG. 3.

[0029] [FIG. 9] FIG. 9 is a block diagram showing in detail an example configuration of an add-on shown in FIG. 8.

[0030] [FIG. 10] FIG. 10 is a block diagram showing in detail an example configuration of a TDOA updater shown in FIG. 9.

[0031] [FIG. 11] FIG. 11 is a flowchart for explaining how the TDOA updater shown in FIG. 10.

[0032] [FIG. 12] FIG. 12 is a block diagram showing yet another variation of the receiver system shown in FIG. 3.

[0033] [FIG. 13] FIG. 13 is a block diagram showing yet another variation of the receiver system shown in FIG. 3.

[0034] [FIG. 14] FIG. 14 is a timed diagram for explaining how the receiver system shown in FIG. operates. 13.

[0035] [FIG. 15] FIG. 15 is a block diagram showing yet another variation of the receiver system shown in FIG. 3.

[0036] [FIG. 16] FIG. 16 is a timed diagram for explaining how the receiver system shown in FIG. operates. 15.

[0037] [FIG. 17] FIG. 17 is a timed diagram for explaining in detail how the receiving system shown in FIG. operates. 15.

[0038] [FIG. 18] FIG. 18 is a block diagram showing yet another variation of the receiver system shown in FIG. 3.

[0039] [FIG. 19] FIG. 19 is a block diagram showing yet another variation of the receiver system shown in FIG. 3.

[0040] [FIG. 20] FIG. 20 is a block diagram showing a configuration of a receiver system in accordance with a second embodiment.

[0041] [FIGS. 21A and 21B] FIG. 21A is a block diagram showing a variation of the receiver system shown in FIG. 20, and FIG. 21B is a timed diagram for explaining how the variation of the receiving system shown in FIG. operates. 21A.

[0042] [FIGS. 22A and 22B] FIG. 22A is a block diagram showing another variation of the receiver system shown in FIG. 20, and FIG. 22B is a timed diagram for explaining how this variation of the receiver system shown in FIG. operates. 22A.

[0043] [FIG. 23A and 23B] FIG. 23A is a block diagram showing yet another variation of the receiver system shown in FIG. 20, and FIG. 23B is a timed diagram for explaining how this variation of the receiver system shown in FIG. operates. 23A.

[0044] [FIGS. 24A and 24B] FIG. 24A is a block diagram showing yet another variation of the receiver system shown in FIG. 20, and FIG. 24B is a timed diagram for explaining how this variation of the receiving system shown in FIG. operates. 24A.

[0045] [FIGS. 25A and 25B] FIG. 25A is a block diagram showing yet another variation of the receiver system shown in FIG. 20, and FIG. 25B is a timed diagram for explaining how this variation of the receiver system shown in FIG. operates. 25A.

[0046] [FIG. 26] FIG. 26 is a block diagram showing yet another variation of the receiver system shown in FIG. 20.

[0047] [FIG. 27] FIG. 27 is a block diagram showing a configuration of a transmission system in accordance with a third embodiment.

[0048] [FIG. 28] FIG. 28 is a block diagram showing a configuration of a receiving system in accordance with a third embodiment.

[0049] [FIGS. 29A and 29B] FIGS. 29A and 29B are timed diagrams for explaining how the transmission and receiver systems shown in FIGS. 27 and 28.

[0050] [FIG. 30] FIG. 30 is a block diagram showing a variation of the receiver system shown in FIG. 28.

[0051] [FIG. 31] FIG. 31 is a timed diagram for explaining how the receiver system shown in FIG. operates. 30.

[0052] [FIG. 32] FIG. 32 is a timing diagram showing an example configuration of data received from the receiving system shown in FIG. 30.

[0053] [FIG. 33] FIG. 33 is a timed diagram for explaining how the receiver system shown in FIG. operates alternatively. 30.

[0054] [FIG. 34] FIG. 34 is a timed diagram for explaining how the receiver system shown in FIG. operates. 1.

[0055] [FIG. 35] FIG. 35 is a timing diagram showing an example of data configuration in a transmission and receiver system, in accordance with a fourth embodiment.

[0056] [FIG. 36] FIG. 36 is a timed diagram showing the first exception handling in the data configuration shown in FIG. 35.

[0057] [FIG. 37] FIG. 37 is a timed diagram showing a second exception handling in the data configuration shown in FIG. 35.

[0058] [FIG. 38] FIG. 38 is a timed diagram showing a third exception handling in the data configuration shown in FIG. 35.

[0059] [FIG. 39] FIG. 39 is a timed diagram showing a fourth exception handling in the data configuration shown in FIG. 35.

DESCRIPTION OF ACHIEVEMENTS

[0060] Embodiments of the present disclosure are described below with reference to the drawings.

[0061] FIG. 1 is a block diagram showing a configuration of a transmission and receiver system in accordance with the present disclosure. The transmission and receiver system shown in FIG. 1 is a transmission and receiver system capable of multiple carrier transmission and used for CATV audio and video data transmission. The transmission and receiver system includes a transmitter 100, a CATV transmission line 150, a receiver 200, and a back-end processor 300.

[0062] Transmitter 100 includes a divider 110 and modulators 121, 122, 123 and 124 and divides an input signal and produces a plurality of transmission signals. The divider 110 divides an input signal (a stream that exceeds a transmission capacity of a capacity) into a plurality of signals and outputs these signals. In modulators 121 to 124, both 256-QAM (256-ary Quadrature Amplitude Modulation) and 64-QAM (64-ary Quadrature Amplitude Modulation) are employed in modulation, respectively.

[0063] The receiver 200 includes demodulators 201, 202, 203 and 204, and a combiner 210. Each of the demodulators 201 to 204 demodulates a signal received via a CATV transmission line 150 by demodulation corresponding to the modulation performed by the modulators 121 to 124. Combiner 210 generates a stream based on each output of demodulators 201 to 204. Back-end processor 300 receives an output from combiner 210 as an input, and generates an output to a monitor (not shown). The receiver 200 and the back-end processor 300 act as a receiver system, which receives a plurality of carriers and generates a stream.

[0064] At receiver 200, the following processing is required in multiple carrier transmission: (1) acquiring header information for detecting a header; (2) absorption of a TDOA between each of the channels; (3) adjusting a data rate between each of the channels by inserting a dummy connector; and (4) combining a data stream by parallel/serial conversion.

[0065] FIG. 2 is a timing diagram showing an example of data configuration in the transmission and receiver system shown in FIG. 1. In the example shown in FIG. 2, a connector (a packet) has a length of 188 bytes. The first byte of a connector is a synchronization byte of a fixed value (0 x 47), the next three bytes are TS header bytes that include a PID (packet identifier). Furthermore, a structure is composed of 53 connectors, and the first connector is a TSMF (transport stream multiplexing structure) header (see Patent Document 1). In the multiple carrier transmission system (extended TSMF), in 256-QAM a superstructure consists of four frames, and in 64-QAM a superstructure consists of three frames.

FIRST ACHIEVEMENT

[0066] FIG. 3 is a block diagram showing a configuration of a receiving system, according to a first embodiment. The receiving system shown in FIG. 3 is a combination of an existing receiver system that includes a function for simultaneously processing a plurality of channels (e.g., a simultaneous recording function), and which has a complement 211 added to the existing receiver system. The receiver system includes demodulators 201 to 204, complement 211, a selector 212, and back-end processor 300. Complement 211 serves as the combiner 210 described above and generates a stream based on an output from demodulators 201 to 204 The selector 212 selects and produces one of an output from the demodulator 201 and the one complement stream 211. In doing so, the selector 212 selects the output from the demodulator 201 in a receiver mode on the single transmit channel, and selects the one. complement stream 211 in a receiver mode in the multiple transmission channel. The back-end processor 300 receives an output from the selector 212 outputs of the demodulators 202 to 204 as inputs, and generates an output to a monitor.

[0067] In single transmission channel receiver mode, the back-end processor 300 processes the output of the selector 212 and the outputs of the demodulators 202 to 204 separately. In the receiver mode on the multiple transmit channel, the back-end processor 300 processes the output of the selector 212 and does not process the outputs of the demodulators 202 to 204. The back-end processor 300 can determine whether the receiver mode on the transmit channel single or receiver mode in multi transmission channel is selected. Depending on the specifications of a viewed or listened to channel, the back-end processor 300 may, for example, select receiver mode on the multiple transmission channel when a channel employing multiple carrier transmission has been selected.

[0068] In the configuration shown in FIG. 3, add-on 211 that performs data combining is added to an existing system. A receiving system for multiple carrier transmission may be provided by switching between, and inputting, a conventional stream input by back-end processor 300 and a combined stream.

[0069] Note that demodulators 201 to 204, complement 211, selector 212, and back-end processor 300 are implemented with an LSI (large-scale integrated circuit). Alternatively, only complement 211 and selector 212 may be implemented with an LSI 401. As a further alternative, complement 211, selector 212, and backend processor 300 may be implemented with an LSI 402.

[0070] FIG. 4 is a block diagram showing a variation of the receiver system shown in FIG. 3. In the receiver system shown in FIG. 4, the output timing of the demodulators 201 to 204 is adjusted by using a memory included in the demodulators 201 to 204 to absorb a TDOA and insert a dummy connector. In complement 211 that has been added to serve as combiner 210, data from each output of demodulators 201 to 204 is rearranged and combined.

[0071] In the configuration shown in FIG. 4, TDOA absorption and dummy connector insertion can be performed using an idle memory of demodulators 201 to 204.

[0072] FIG. 5 is a block diagram showing another variation of the receiver system shown in FIG. 3. In the receiver system shown in FIG. 5, a delay correction value is inserted into each of the demodulators 201 to 204. These delay correction values are used to adjust the output timing of each of the demodulators 201 to 204.

[0073] According to the configuration shown in FIG. 5, for example, a fully synchronized operating system is achieved by allowing demodulators 201 to 204 to share a crystal oscillator, a delay correction value is input externally into each of the demodulators 201 to 204, and, after adjusting the delay, a superstructure delay difference causes a TDOA of a transmission signal sent to a receiving system to be set to 0 (a dummy connector is also inserted), and the delay difference is entered into the back-end processor 300 As a result, complement 211 no longer needs to have a memory, and can be miniaturized.

[0074] FIG. 6 is a block diagram showing yet another variation of the receiver system shown in FIG. 3. In the receiver system shown in FIG. 6, complement 211 determines a delay difference between each of the outputs of demodulators 201 to 204. Based on the delay difference, complement 211 determines a delay correction value for each of demodulators 201 to 204.

[0075] According to the configuration shown in FIG. 6, an externally inserted delay correction value in each of the demodulators 201 to 204, as shown in FIG. 5, is determined by measuring a TDOA of each flow in complement 211.

[0076] FIG. 7 is a timed diagram for explaining how the receiver system shown in FIG. operates. 6. Complement 211 uses a common counter to determine a TDOA of a start of a superstructure of each channel relative to an output of each of demodulators 201 to 204.

[0077] FIG. 8 is a block diagram showing yet another variation of the receiver system shown in FIG. 3. In the receiver system shown in FIG. 8, a complement delay correction value 211 is transferred between the chips via a communication circuit, for example, via a CPU (central processing unit) 213, via, for example, an I2C interface. The CPU 213 and the back-end processor 300 may be implemented with an LSI 403.

[0078] FIG. 9 is a block diagram showing in detail an example configuration of the complement 211 (and a portion of each demodulator) shown in FIG. 8. The demodulators 201, 202 shown in FIG. 9 each include a delay adjuster 220. Complement 211 includes a TDOA detector 221, and a TDOA updater 222 for each channel. Complement 211 retains a first delay correction value and a second delay correction value. If a delay difference of continuously inserted outputs of the demodulators 201, 202 is greater than or equal to a previously established value, the complement 211 updates the first delay correction value and the second retained delay correction value.

[0079] FIG. 10 is a block diagram showing in detail an example configuration of a TDOA updater 222 shown in FIG. 9. The TDOA updater 222 shown in FIG. 10 includes an adder 230, a comparator 231, a selector 232, and a D-FF (delay flip-flop) 233.

[0080] FIG. 11 is a flowchart for explaining, in steps 240 to 244, how the TDOA updater 222 shown in FIG. 10. In an initial state, a delay correction value If, at this point, T1 is not 0, the value of X is updated. Then, T becomes 0 as a signal whose delay is adjusted by T1 is input into a TDOA detector 221. If T = 0, the value of X is retained without being updated. Given that oscillation occurs in a transmission line and the TDOA has been changed from T1 to T2, a detected TDOA T value is T3 = T2 - X, because a signal whose delay is adjusted by X = T1 is input into the TDOA detector 221. Consequently, to establish the X delay correction value for T2, the X value can be updated using the equation T2 = T3 + X.

[0081] As described above, according to the configuration shown in FIG. 9, the delay correction values entered into each of the demodulators 201 to 204 are determined by detecting a TDOA of flows in the complement 211. Therefore, although the delay correction values provided to each of the demodulators 201 to 204 are retained, delay value fluctuations are monitored and delay correction values are changed when the TDOA changes.

[0082] FIG. 12 is a block diagram showing yet another variation of the receiver system shown in FIG. 3. In the receiver system shown in FIG. 12, a timing signal is input to each of the demodulators 201 to 204. These timing signals are used to adjust the output timing of each of the demodulators 201 to 204.

[0083] According to the configuration shown in FIG. 12, an external timing signal is provided to each of the demodulators 201 to 204, and delay adjustment is performed in each of the demodulators 201 to 204 based on these timing signals.

[0084] FIG. 13 is a block diagram showing yet another variation of the receiver system shown in FIG. 3. In the receiver system shown in FIG. 13, the same timing signal (e.g., a reset signal) is input to each of the demodulators 201 to 204. This timing signal is used to adjust the output timing of each of the demodulators 201 to 204.

[0085] According to the configuration shown in FIG. 13, a timing signal is provided externally to be shared through each of the demodulators 201 to 204, and delay adjustment is performed in each of the demodulators 201 to 204 based on this timing signal.

[0086] FIG. 14 is a timed diagram for explaining how the receiver system shown in FIG. operates. 13. According to FIG. 14, complement 211 determines, based on a reset completion time, arrival times (tA to tD) of the superstructure starts of each channel, a difference to a previously established arrival time (tE), and establishes this difference as a delay correction value.

[0087] FIG. 15 is a block diagram showing yet another variation of the receiver system shown in FIG. 3. In the receiver system shown in FIG. 15, each of demodulators 201 to 204 is configured to receive a timing signal from another demodulator. That is, demodulators 201 to 204 generate time signals so that the delay adjustment is interconnected with each other.

[0088] FIG. 16 is a timed diagram for explaining how the receiver system shown in FIG. operates. 15. Here, a timing signal from each of the demodulators 201 to 204 may indicate, for example, a 1-bit signal declared at the beginning of the superstructure.

[0089] FIG. 17 is a timed diagram for explaining in detail how the receiving system shown in FIG. operates. 15. For example, demodulator 201 determines a value (tD - tB) + α as the delay correction value. Here, a constant delay time α is added to a difference between the arrival time tD of the most delayed time signal and the arrival time tB of the demodulator 201's own time signal. The value α can be, for example, the time it takes for the demodulator to deliver a valid output after it has started processing.

[0090] FIG. 18 is a block diagram showing yet another variation of the receiver system shown in FIG. 3. In the receiver system shown in FIG. 18, complement 211 generates the timing signal from each of demodulators 201 to 204.

[0091] According to the configuration shown in FIG. 18, the TDOA of each stream is detected in complement 211, complement 211 produces a timing signal for each of demodulators 201 to 204, and a delay difference of a superstructure is set to 0 and input to the back processor. end 300. As a result, complement 211 no longer needs to have a memory, and can be miniaturized.

[0092] FIG. 19 is a block diagram showing yet another variation of the receiver system shown in FIG. 3. In the receiver system shown in FIG. 19, a connection of a memory control signal that allows the complement 211 to access each of the demodulators 201 to 204 is provided between the complement 211 and the demodulators 201 to 204.

[0093] According to the configuration shown in FIG. 19, an idle memory of the demodulators 201 to 204 or the back-end processor 300 is used as a memory required to receive the data. Therefore, complement 211 does not need to have a memory, and can be miniaturized.

SECOND REALIZATION

[0094] FIG. 20 is a block diagram showing a configuration of a receiving system in accordance with a second embodiment. In the receiver system shown in FIG. 20, in each of demodulators 201 to 204, data is combined sequentially to generate a combined stream. In a receiver mode on the single transmission channel, the back-end processor 300 individually processes the data output by the demodulators 201 to 204. In a receiver mode on the multiple transmission channel, the back-end processor 300 processes only the stream combined demodulator 204.

[0095] FIG. 21A is a block diagram showing a variation of the receiver system shown in FIG. 20, and FIG. 21B is a timed diagram for explaining how the variation of the receiving system shown in FIG. operates. 21A. Here, demodulators 201 to 204 increase the data rate gradually for the data to be combined. Note that many variations are possible, depending on the order in which the data is combined and whether there is a dummy connector (D) of a 64-QAM stream.

[0096] FIG. 22A is a block diagram showing another variation of the receiver system shown in FIG. 20. FIG. 22B is a timed diagram for explaining how this variation of the receiver system shown in FIG. operates. 22A. Here, demodulators 201 to 204 increase a data rate from demodulator 201 in the front to achieve a data rate from demodulator 204 in the rear. When data is missing, demodulators 201 to 204 insert a dummy connector (D) as a filler. Demodulators 201 to 204 exchange data in this order. Also note in this example that many variations are possible depending on the matching order and whether there is a dummy connector (D) of a 64-QAM stream.

[0097] FIG. 23A is a block diagram showing yet another variation of the receiver system shown in FIG. 20, and FIG. 23B is a timed diagram for explaining how this variation of the receiver system shown in FIG. operates. 23A. Here, demodulators 201 to 204 each share their processing delay values, which were incorporated during system design. Alternatively, demodulators 201 to 204 may exchange signals to share their processing delay values with each other. In each of the demodulators 201 to 204, deferred processing is performed based on these values. In FIG. 23B, a processing delay value of the demodulator 201 is T1, a processing delay value of the demodulator 202 is T2, and a processing delay value of the demodulator 203 is T3.

[0098] According to the example shown in FIGS. 23A and 23B, processing delay values are shared between demodulators 201 to 204, and deferred processing is performed in demodulators 201 to 204 in accordance with the processing delay values. Note that alternatively, processing delay values can be set externally for each of the demodulators 201 to 204.

[0099] FIG. 24A is a block diagram showing yet another variation of the receiver system shown in FIG. 20, and FIG. 24B is a timed diagram for explaining how this variation of the receiving system shown in FIG. operates. 24A. Here, demodulators 201 to 203 produce a timing signal, which indicates a processing start time to subsequent demodulators 202 to 204.

[00100] According to the example shown in FIGS. 24A and 24B, TDOA absorption is implemented by adding a time signal synchronized to the data.

[00101] FIG. 25A is a block diagram showing yet another variation of the receiver system shown in FIG. 20, and FIG. 25B is a timed diagram for explaining how this variation of the receiver system shown in FIG. operates. 25A. Here, data processing begins when demodulators 202 to 204 observe a predetermined data sequence (e.g., a TSMF header) among the data obtained from previous demodulators 201 to 203.

[00102] According to the example shown in FIGS. 25A and 25B, TDOA absorption can be implemented by inserting a known data sequence into a stream as a reference for time synchronization.

[00103] FIG. 26 is a block diagram showing yet another variation of the receiver system shown in FIG. 20. Here, sequential data processing in demodulators 201, 202 and data processing in demodulator 204 are carried out in parallel, and then in demodulator 203, the data is compressed into a combined stream. That is, the data is combined in demodulators 201 to 204 in a tournament-like manner to generate a combined stream.

THIRD ACHIEVEMENT

[00104] FIG. 27 is a block diagram showing a configuration of a transmission system in accordance with a third embodiment. The transmitter 100 of this transmission system includes the divider 110, an identification data adder 130, and the modulators 131, 132. The divider 110 divides an input signal into a plurality of signals and outputs these signals. The identification data adder 130 adds the identification data (index numbers) to a predetermined group (superstructure) of the signals divided between the signals divided by the divider 110. The modulators 131, 132 process each of the divided signals added by the data identification and produce a transmission signal. The identification data may be data that is identical for each predetermined group, or it may be data that differs in each data split for each predetermined group in accordance with a formula already shared between a sending side and a receiving side. The superstructure index number is contained in the header information.

[00105] FIG. 28 is a block diagram showing a configuration of a receiving system in accordance with the third embodiment. The receiver 200 of this receiving system includes demodulators 201, 202, an identification data detector 250, a delay correction signal generator 253, delay adjusters 261, 262, and a combiner 210. The identification data detector 250 identifies the identification data (index numbers) added to a predetermined group (superstructure) of outputs of the demodulators 201, 202. The delay correction signal generator 253 uses the detection results provided by the identification data detector 250 to generate delay correction signals to the outputs of the demodulators 201, 202. Based on the delay correction signals, the delay adjusters 261, 262 delay the outputs of the demodulators 201, 202 and produce post-delay adjustment signals. The combiner 210 generates at least one stream based on the post-delay adjustment signals.

[00106] FIGS. 29A and 29B are timed diagrams for explaining how the transmission and receiver systems shown in FIGS. 27 and 28. Here, an index number of a superstructure is used for delay adjustment. As shown in FIG. 29A, this allows it to absorb up to a TDOA that exceeds a superstructure duration. Furthermore, as shown in FIG. 29B, a TDOA within a superstructure duration can also, of course, be safely absorbed.

[00107] However, as long as the header information allows the generation of a timing signal of a duration longer than a superstructure (which is a minimum unit of combination), it is not limited to the index number of the superstructure.

[00108] FIG. 30 is a block diagram showing a variation of the receiver system shown in FIG. 28. The receiver 200 of the receiving system shown in FIG. 30 includes demodulators 201, 202, a delay correction signal generator 253, delay adjusters 261, 262, and a combiner 210. The delay correction signal generator 253 uses the outputs of the demodulators 201, 202 to generate delay correction signals to the outputs of the demodulators 201, 202. Based on the delay correction signals, the delay adjusters 261, 262 delay the outputs of the demodulators 201, 202 and produce post-delay adjustment signals. The combiner 210 generates at least one stream based on the post-delay adjustment signals. Furthermore, in the delay correction signal generator 253, a delay difference is determined between the data output by the demodulators 201, 202, and a delay correction signal is only generated if the delay difference is less than a duration predetermined delay time (half a superstructure duration). That is, in the receiver 200, the delay difference is assumed to lie in a superstructure duration, and the TDOA absorption is performed after having the defined pairs of superstructure starts adapted to this condition as pairs that need to be adjusted at time.

[00109] FIG. 31 is a timed diagram for explaining how the receiver system shown in FIG. operates. 30. Here, N is an arbitrary natural number, a superstructure duration is tFRM, a delay difference between an Nth superstructure of channel 1 and an Nth superstructure of channel 2 is tA, and is a delay difference between the Nth superstructure of channel 2 and a (N + 1)th superstructure of channel 1 is tβ. Since tFRM = tA + tβ, the equation tA ^ tFRM/2 is valid when tA < tβ. Accordingly, the delay correction signal generator 253 performs data processing based on the assumption that among the two values tA and tβ determined as delay differences between the two channels, the smaller value is the correct delay difference.

[00110] According to the configuration shown in FIG. 30, a TDOA within half a superstructure life can be absorbed with 100% reliability.

[00111] Now, when interpreting a time and sequence relationship between the outputs of the demodulators 201, 202, the delay correction signal generator 253 shown in FIG. 30 may interpret a combination of split data based on an index (e.g., CC (continuity counter) values within a TS packet header) indicating data continuity.

[00112] FIG. 32 is a timing diagram showing an example configuration of data received from the receiving system shown in FIG. 30. The TS packet header includes a 4-bit CC incremented for each packet by its PID.

[00113] FIG. 33 is a timed diagram for explaining how the receiver system shown in FIG. operates. 30 using CCs. In the example shown in FIG. 33, a #M connector on channel 1 with CC = 1 and a #N connector on channel 2 with CC = 2 have the same PID. Therefore, the continuity of the CCs can be checked. Additionally, a #M + 1 connector on channel 1 with CC = 3 and a #N + 1 connector on channel 2 with CC = 4 have the same PID. Therefore, the continuity of the CCs can be checked. However, a channel 1 #M + 2 connector with CC = 1 and a channel 2 #N + 2 connector with CC = 5 have different PIDs. Therefore, the continuity of the CCs cannot be verified. TDOA absorption can be implemented by implementing delay adjustment based on at least one pair of the first two among the three pairs of connectors mentioned above.

[00114] Note that, when rearranging and combining the data output by demodulators 201 to 204, combiner 210 shown in FIG. 1 performs reorganization and combination based on header information obtained from the output of demodulators 201 to 204, and information used to interpret the header information and stored in an updatable store (register) in combiner 210. As a result, the order of combination can be established arbitrarily in the register. Here, the information available from a carrier sequence is information to identify a carrier, e.g., 8-bit information obtained from outputs resulting from demodulation of a plurality of carriers in receiver 200 and which is included in the header information of an extension. . The order of combination can be determined by the size of the carrier sequence information. Alternatively, the information that converts the carrier sequence information into order can be stored in the register, and the combination order can be determined based on the carrier sequence information and the information in the register. Note that the method for determining the matching order can be shared in advance by both the sending side and the receiving side.

[00115] Furthermore, the combiner 210 shown in FIG. 1 reorganizes and combines the data output by demodulators 201 to 204 based on an index (e.g., CC values within a TS packet header) indicating data continuity. The combiner 210 checks a CC, and automatically discriminates the combination order.

[00116] FIG. 34 is a timed diagram for explaining how the receiver system shown in FIG. operates. 1 using CCs. In the example shown in FIG. 34, on the first connector (#X - 1, #Y - 1, #Z - 1, #W - 1) of each of the channels, only the PID of channel 2 is different, which is why the continuity of the CCs cannot be checked and the order of combination cannot be discriminated. However, on the following connectors (#X, #Y, #Z, #W) of each channel, the PIDs of all channels are the same, which is why the continuity of the CCs can be checked. As a result, it is discriminated that the carrier order follows channel 3, channel 1, channel 4 and channel 2.

FOURTH ACHIEVEMENT

[00117] FIG. 35 is a timing diagram showing an example of data configuration in a transmission and receiver system, in accordance with a fourth embodiment. Here, data is sent and received after a TVL (value of length types) VL packet has been converted into a transmission packet of a fixed length.

[00118] The transmission packet has a fixed length of 188 bytes. The first three bytes constitute a header (that is, a split TLV header), while the remaining 185 bytes constitute a payload. A TLV packet start indicator in the split TLV header being “1” indicates that a TLV packet start is included in the split TLV packet payload. The first byte of the payload used when the TLV packet start indicator is “1” is defined as a start TLV index. A start TLV index value indicates in which byte of the payload the start of the TLV packet is located. When the TLV packet start indicator is “0”, the start TLV index is not inserted into the payload.

[00119] Within the scope of a data allocation method which, as described above, includes (i) splitting the TLV packet, (ii) inserting starting position information (the starting TLV index) indicating a starting position of a VL 2 packet that is next allocated in a case where, in the allocation in a transmission packet of a fixed length, the allocation of a packet 1 which is a VL packet has been completed somewhere along the transmission packet. transmission, and (iii) subsequent allocation of packet 2, a case may occur where allocation of packet 2 cannot be performed if the initial position information (the start TLV index) indicating the starting position of VL packet 2 which is allocated next are inserted after the allocation of packet 1 has been completed somewhere along the transmission packet. Exception handling in this case will be described in the scope of the fourth realization.

[00120] FIG. 36 is a timed diagram showing a first exception handling of the data configuration shown in FIG. 35. Within the scope of the transmitter data allocation method 100 involving the first exception handling, in a case where packet 2 allocation cannot be performed if the initial position information (the start TLV index) indicating the position of packet 2, which is allocated next, is inserted after the allocation of packet 1 has finished somewhere along the transmission packet, invalid data is inserted instead of the initial position information (TLV index of start). That is, the remaining one byte is filled with a random value. As a result, the starting TLV index goes into the next transmission packet.

[00121] In the scope of a receiver data acquisition method 200 corresponding to such a transmitter data allocation method 100, in a case where data acquisition forming a VL packet 1 was completed within a transmission packet 1 of a fixed length such that the VL TLV packet allocated to a transmission packet of a fixed length is acquired, and where the initial position information (the start TLV index) indicating the starting position of the VL packet 2 are not inserted into the fixed-length transmission packet 1, data other than the data forming VL packet 1 within the fixed-length transmission packet 1 are treated as invalid data.

[00122] FIG. 37 is a timed diagram showing a second exception handling of the data configuration shown in FIG. 35. Within the scope of a transmitter data allocation method 100 involving second exception handling, in a case where allocation of packet 2 cannot be performed if the initial position information (start TLV index) indicating the position of packet 2 that is allocated next are inserted after the allocation of packet 1 has finished somewhere along transmission packet 1, an invalid value is assigned instead of the initial position information (start TLV index ). That is, the beginning TLV index designates a field of more than 184 bytes that does not actually exist.

[00123] Within the scope of a receiver data acquisition method 200 that corresponds to such transmitter data allocation method 100, the processing is carried out based on the presumption that, in a case where the acquisition of the data forming the VL packet 1 has been terminated within transmission packet 1 of the fixed length so that the VL TLV packet that is allocated to a transmission packet of a fixed length is acquired, and where within transmission packet 1 of the length fixed an invalid value is assigned as the starting position information (start TLV index) to the starting position information (start TLV index) indicating the starting position of the next VL Packet 2, no data forming the VL packet 2 is present within transmission packet 1 of the fixed length.

[00124] FIG. 38 is a timed diagram showing a third exception handling of the data configuration shown in FIG. 35. According to a transmitter data allocation method 100 involving the third exception handling, the initial position information (start TLV index) is inserted when the start of the VL TLV packet is included in a transmission, and invalid data is inserted instead of the initial position information (start TLV index) when the start of the VL TLV packet is not included in the transmission packet. That is, when the TLV packet start indicator is “0”, a byte at an arbitrary location is stuffed so that an actual payload length becomes 184 bytes.

[00125] Within the scope of a receiver data acquisition method 200 that corresponds to such a transmitter data allocation method 100, the processing is carried out based on the presumption that, in a case where the initial position information (index starting TLV) that indicate a starting position 2 of the next VL 2 packet are not included in the fixed-length transmission packet 1 when a VL 1 packet acquisition process is performed, so that the starting TLV packet VL allocated to a transmission packet of a fixed length is acquired, unlike the data forming VL packet 1, invalid data is included in transmission packet 1 of the fixed length.

[00126] FIG. 39 is a timed diagram showing a fourth exception handling in the data configuration shown in FIG. 35. According to a transmitter data allocation method 100 involving the fourth exception handling, a value indicating the starting position of packet 2 that is allocated next is assigned to the starting position information (start TLV index ) when the beginning of the VL TLV packet is included in the transmission packet, and an invalid value is assigned to the initial position information (start TLV index) when the beginning of the VL TLV packet is not included in the transmission packet streaming. That is, the payload length of the split TLV packet is fixed as 184 bytes, and the start TLV index is inserted continuously. In a case where the start of the TLV packet is not included in the transmission packet, an invalid pointer position (for example, an invalid Z value) is assigned to the start TLV index.

[00127] Within the scope of a receiver data acquisition method 200 corresponding to such a transmitter data allocation method 100, processing is carried out based on the presumption that in a case where in transmission packet 1 of the fixed length an invalid value is assigned as the initial position information (the start TLV index) to the initial position information (the start TLV index) indicating the start position 2 of the next VL packet 2 when an acquisition process of the VL packet 1 is carried out so that the VL TLV packet allocated to a transmission packet of a fixed length is acquired, all data allocated with the data forming the VL packet in transmission packet 1 of the fixed length is given forming the VL 1 package.

[00128] Within the scope of transmitter data allocation method 100 involving the fourth exception handling shown in FIG. 39, a starting TLV index area is retained in the payload separately from the split TLV packet header. Taking into account the process occurring at the receiver 200, however, when allocating the area of the start TLV index present in the payload within the split TLV packet header, alternatively, both the TLV packet start indicator and the starting TLV index area may be present in the header of the split TLV packet. In particular, the allocation of the starting TLV index area at the beginning of the split TLV packet header has the effect that, in processing occurring at receiver 200 or back-end processor 300, the latency between reception and processing of data becomes shorter. In these cases, the split TLV packet header can be assumed to be four bytes, and the split TLV packet header can be kept as three bytes by deleting the remaining one byte from a portion other than the TLV packet start indicator. and the start TLV index area.

[00129] Furthermore, the data allocation described above can be performed only between the receiver 200 and the back-end processor 300. More specifically, the receiver 200 can perform processing within the scope of which, after reconfiguring a sequence of VL data from a data sequence of a fixed length, both the TLV packet start indicator and the start TLV index area are allocated in the header of the split TLV packet, and in particular the area of the starting TLV index is allocated at the beginning of the split TLV packet header.

OTHER ACHIEVEMENTS

[00130] In the description mentioned above, the first to fourth embodiments serve as examples of the technique disclosed in the present application. However, the technique, according to the present disclosure, is not limited to these embodiments and is also applicable to embodiments where modifications, substitutions, additions, omissions or sequential changes are suitably carried out. Furthermore, each of the elements described in the realizations can be combined, and defined as a new realization.

[00131] For example, as long as it is a system in which the transmitter 100 and the receiver 200 can share information generated by combining data from a split stream on a plurality of carriers, the system is not limited to TSMF. Furthermore, the modulation mode is not limited to QAM. The flow form is not limited to a TS packet or a TLV packet. The number of carriers is not limited to 4 or 2.

[00132] Furthermore, the input of each of the demodulators 201 to 204 is not limited to an IF (intermediate frequency) signal, but may be an RF (radio frequency) signal, or may be given after AD (analog to analog) conversion. digital). Each of demodulators 201 to 204 can produce a plurality of streams in the form of TS packets. Information passing from complement 211 to demodulators 201 to 204 is not limited to delay correction values and timing signals.

[00133] Furthermore, the data transmission line is not limited to the CATV transmission line 150 shown in FIG. 1. Transmitted data is not limited to visual and audio data. A transmission system in which a flow exceeding the transmission capacity of a carrier that is divided into a plurality of carriers is not limited to multiple carrier transmission. The modulation format is not limited to 64-QAM and 256-QAM. Package configuration is not limited to the described configuration.

[00134] Finally, within the scope of the first embodiment, an example is described where complement 211 is added to an existing system that has a function for simultaneous recording of a plurality of channels. However, as long as it is a system that can simultaneously receive a plurality of different channels, the present disclosure is not limited to this embodiment.

INDUSTRIAL APPLICABILITY

[00135] As can be seen from the above description, the transmission and receiver system according to the present disclosure is useful for a transmission and receiver system that employs multiple carrier transmission.

DESCRIPTION OF REFERENCE CHARACTERS

[00136] 100 Transmitter

[00137] 110 Divider

[00138] 121 to 124 Modulator

[00139] 130 Identification data adder

[00140] 131, 132 Modulator

[00141] 200 Receiver

[00142] 201 to 204 Demodulator

[00143] 210 Combinator

[00144] 211 Complement

[00145] 212 Selector

[00146] 213 CPU

[00147] 220 Delay Adjuster

[00148] 221 TDOA Detector

[00149] 222 TDOA Updater

[00150] 250 Identification data detector

[00151] 253 Correction signal generator

[00152] 261, 262 Delay Adjuster

[00153] 300 Back-End

[00154] 401 to 403 LSI

Claims (14)

1. RECEIVING SYSTEM THAT RECEIVES A PLURALITY OF CARRIERS AND THAT GENERATES ONE OR A PLURALITY OF FLOWS, the system characterized by comprising: first demodulator that receives and processes a first transmission signal; second demodulator that receives and processes a second transmission signal different from the first transmission signal; combiner that generates a stream based on at least one output of the first demodulator and one output of the second demodulator; selector that receives an output from the first demodulator and a stream from the combiner as inputs, and which selects and outputs one between the output from the first demodulator and a stream from the combiner; and back-end processor that receives an output from the selector and an output from the second demodulator as inputs, and that generates an output to a monitor, wherein the selector selects the output of the first demodulator in a single transmit channel receiver mode, and selects the one stream in one receiver mode in multiple transmission channel. 2. RECEIVING SYSTEM according to claim 1, characterized in that the first demodulator, the second demodulator, the combiner, the selector and the back-end processor are implemented with an LSI. 3. RECEIVING SYSTEM, according to claim 1, characterized in that the combiner, the selector and the back-end processor are implemented with an LSI. 4. RECEIVING SYSTEM, according to claim 1, characterized in that the combiner and the selector are implemented with an LSI. 5. RECEIVING SYSTEM according to claim 1, characterized in that the back-end processor processes an output of the selector and the output of the second demodulator separately in the receiver mode on the single transmission channel, and processes the output of the selector while not processing the output of the second demodulator in receiver mode on the multiple transmission channel. 6. RECEIVING SYSTEM, according to claim 1, characterized by the back-end processor determining whether the receiver mode in the single transmission channel or the receiver mode in the multiple transmission channel is selected. 7. RECEIVING SYSTEM THAT RECEIVES A PLURALITY OF CARRIERS AND GENERATES A FLOW, the system characterized by comprising: first demodulator that receives and processes a first transmission signal; second demodulator that receives and processes a second transmission signal different from the first transmission signal; and combiner that generates a stream based on at least one output of the first demodulator and one output of the second demodulator, wherein in the combiner, the reorganization and combination of the data output by the first demodulator and the data output by the second demodulator are performed with based on the header information obtained from the first and second demodulators, and the first identification data and second identification data, which are respectively linked to the target data to be reorganized; second identification data indicates the order of organization in a group of data, of the first identification data having an identical value; and header information includes information for specifying each carrier of the plurality of carriers. 8. RECEIVING SYSTEM according to claim 7, characterized in that the reorganization and combination is carried out based on the first identification data, the second identification data and predetermined data corresponding to the second identification data, which are defined as information within an upgradeable storage in the combiner. 9. RECEIVING SYSTEM, according to claim 7, the flow being characterized by comprising a plurality of packets in which the indices indicating data continuity in the packets are present, the second identification data are the indices indicating data continuity . 10. RECEIVING SYSTEM THAT RECEIVES A PLURALITY OF CARRIERS AND GENERATES A FLOW, the system characterized by comprising: first demodulator that receives and processes a first transmission signal; second demodulator that receives and processes a second transmission signal different from the first transmission signal; and combiner that generates a stream based on at least one output of the first demodulator and one output of the second demodulator, wherein in the combiner, the reorganization and combination of data output by the first demodulator and data output by the second demodulator are performed with based on header information obtained from the first and second demodulators, and the header information includes information for specifying each carrier of the plurality of carriers. 11. RECEIVING SYSTEM, according to claim 10, characterized in that the information for identifying the plurality of carriers is 8-bit information. 12. RECEIVING SYSTEM, according to claim 11, characterized in that 8-bit information is included in the header information of an extension. 13. RECEIVING SYSTEM according to claim 10, characterized in that the first demodulator and the second demodulator perform different demodulation techniques, and each of the first demodulator and the second demodulator receives a signal in a different modulation and demodulates the signal. 14. RECEIVING SYSTEM according to claim 7, characterized in that the first demodulator and the second demodulator perform different demodulation techniques, and each of the first demodulator and the second demodulator receives a signal in a different modulation and demodulates the signal.